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Diffstat (limited to 'target/linux/brcm47xx/patches-3.0/0007-bcma-get-CPU-clock.patch')
-rw-r--r--target/linux/brcm47xx/patches-3.0/0007-bcma-get-CPU-clock.patch179
1 files changed, 102 insertions, 77 deletions
diff --git a/target/linux/brcm47xx/patches-3.0/0007-bcma-get-CPU-clock.patch b/target/linux/brcm47xx/patches-3.0/0007-bcma-get-CPU-clock.patch
index 7acdb74..aa65dc8 100644
--- a/target/linux/brcm47xx/patches-3.0/0007-bcma-get-CPU-clock.patch
+++ b/target/linux/brcm47xx/patches-3.0/0007-bcma-get-CPU-clock.patch
@@ -1,32 +1,30 @@
-From 257d5fe12600f08df764cac0abc17bef7b6fae9b Mon Sep 17 00:00:00 2001
+From e993e8342e660f29a048be872522eedabaa177e1 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sun, 19 Jun 2011 17:51:30 +0200
-Subject: [PATCH 07/14] bcma: get CPU clock
+Date: Sat, 16 Jul 2011 15:19:38 +0200
+Subject: [PATCH 07/22] bcma: get CPU clock
Add method to return the clock of the CPU. This is needed by the arch
code to calculate the mips_hpt_frequency.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
- drivers/bcma/bcma_private.h | 3 +
- drivers/bcma/driver_chipcommon_pmu.c | 87 +++++++++++++++++++++++++++
- drivers/bcma/driver_mips.c | 12 ++++
- include/linux/bcma/bcma_driver_chipcommon.h | 35 +++++++++++
- include/linux/bcma/bcma_driver_mips.h | 1 +
- 5 files changed, 138 insertions(+), 0 deletions(-)
+ drivers/bcma/bcma_private.h | 1 +
+ drivers/bcma/driver_chipcommon_pmu.c | 107 +++++++++++++++++++++++++++
+ drivers/bcma/driver_mips.c | 12 +++
+ include/linux/bcma/bcma_driver_chipcommon.h | 39 ++++++++++
+ include/linux/bcma/bcma_driver_mips.h | 2 +
+ 5 files changed, 161 insertions(+), 0 deletions(-)
--- a/drivers/bcma/bcma_private.h
+++ b/drivers/bcma/bcma_private.h
-@@ -29,6 +29,9 @@ void bcma_init_bus(struct bcma_bus *bus)
- /* sprom.c */
- int bcma_sprom_get(struct bcma_bus *bus);
+@@ -36,6 +36,7 @@ void bcma_chipco_serial_init(struct bcma
-+/* driver_chipcommon_pmu.c */
-+extern u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
-+
- /* driver_chipcommon.c */
- #ifdef CONFIG_BCMA_DRIVER_MIPS
- extern int bcma_chipco_serial_init(struct bcma_drv_cc *cc,
+ /* driver_chipcommon_pmu.c */
+ u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
++u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
+
+ #ifdef CONFIG_BCMA_HOST_PCI
+ /* host_pci.c */
--- a/drivers/bcma/driver_chipcommon_pmu.c
+++ b/drivers/bcma/driver_chipcommon_pmu.c
@@ -11,6 +11,13 @@
@@ -43,39 +41,29 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
static void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
u32 offset, u32 mask, u32 set)
{
-@@ -136,3 +143,83 @@ void bcma_pmu_init(struct bcma_drv_cc *c
- bcma_pmu_swreg_init(cc);
- bcma_pmu_workarounds(cc);
+@@ -162,3 +169,103 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
+ }
+ return BCMA_CC_PMU_ALP_CLOCK;
}
+
-+static u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
-+{
-+ struct bcma_bus *bus = cc->core->bus;
-+
-+ switch (bus->chipinfo.id) {
-+ case 0x4716:
-+ case 0x4748:
-+ case 47162:
-+ /* always 20Mhz */
-+ return 20000 * 1000;
-+ default:
-+ pr_warn("No ALP clock specified for %04X device, "
-+ "pmu rev. %d, using default %d Hz\n",
-+ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
-+ }
-+ return BCMA_CC_PMU_ALP_CLOCK;
-+}
-+
+/* Find the output of the "m" pll divider given pll controls that start with
+ * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
+ */
+static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
+{
+ u32 tmp, div, ndiv, p1, p2, fc;
++ struct bcma_bus *bus = cc->core->bus;
++
++ BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
+
+ BUG_ON(!m || m > 4);
+
-+ BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
++ if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
++ /* Detect failure in clock setting */
++ tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
++ if (tmp & 0x40000)
++ return 133 * 1000000;
++ }
+
+ tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
+ p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
@@ -107,6 +95,18 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+ case 47162:
+ return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
+ BCMA_CC_PMU5_MAINPLL_SSB);
++ case 0x5356:
++ return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
++ case 0x5357:
++ case 0x4749:
++ return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
++ case 0x5300:
++ return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
++ BCMA_CC_PMU5_MAINPLL_SSB);
++ case 53572:
++ return 75000000;
+ default:
+ pr_warn("No backplane clock specified for %04X device, "
+ "pmu rev. %d, using default %d Hz\n",
@@ -120,16 +120,34 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+{
+ struct bcma_bus *bus = cc->core->bus;
+
-+ if ((cc->pmu.rev == 5 || cc->pmu.rev == 6 || cc->pmu.rev == 7) &&
-+ (bus->chipinfo.id != 0x4319))
-+ return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
-+ BCMA_CC_PMU5_MAINPLL_CPU);
++ if (bus->chipinfo.id == 53572)
++ return 300000000;
++
++ if (cc->pmu.rev >= 5) {
++ u32 pll;
++ switch (bus->chipinfo.id) {
++ case 0x5356:
++ pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
++ break;
++ case 0x5357:
++ case 0x4749:
++ pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
++ break;
++ default:
++ pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
++ break;
++ }
++
++ /* TODO: if (bus->chipinfo.id == 0x5300)
++ return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
++ return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
++ }
+
+ return bcma_pmu_get_clockcontrol(cc);
+}
--- a/drivers/bcma/driver_mips.c
+++ b/drivers/bcma/driver_mips.c
-@@ -157,6 +157,18 @@ static void bcma_core_mips_dump_irq(stru
+@@ -166,6 +166,18 @@ static void bcma_core_mips_dump_irq(stru
}
}
@@ -145,14 +163,14 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+}
+EXPORT_SYMBOL(bcma_cpu_clock);
+
- static void bcma_core_mips_serial_init(struct bcma_drv_mips *mcore)
+ static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
{
struct bcma_bus *bus = mcore->core->bus;
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -246,6 +246,41 @@
- #define BCMA_CC_PLLCTL_DATA 0x0664
- #define BCMA_CC_SPROM 0x0830 /* SPROM beginning */
+@@ -241,8 +241,47 @@
+ #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
+ #define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
+/* Divider allocation in 4716/47162/5356 */
+#define BCMA_CC_PMU5_MAINPLL_CPU 1
@@ -162,43 +180,50 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+/* PLL usage in 4716/47162 */
+#define BCMA_CC_PMU4716_MAINPLL_PLL0 12
+
-+/* ALP clock on pre-PMU chips */
-+#define BCMA_CC_PMU_ALP_CLOCK 20000000
++/* PLL usage in 5356/5357 */
++#define BCMA_CC_PMU5356_MAINPLL_PLL0 0
++#define BCMA_CC_PMU5357_MAINPLL_PLL0 0
++
++/* 4706 PMU */
++#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
++
+ /* ALP clock on pre-PMU chips */
+ #define BCMA_CC_PMU_ALP_CLOCK 20000000
+/* HT clock for systems with PMU-enabled chipcommon */
+#define BCMA_CC_PMU_HT_CLOCK 80000000
+
+/* PMU rev 5 (& 6) */
-+#define BCMA_CC_PPL_P1P2_OFF 0
-+#define BCMA_CC_PPL_P1_MASK 0x0f000000
-+#define BCMA_CC_PPL_P1_SHIFT 24
-+#define BCMA_CC_PPL_P2_MASK 0x00f00000
-+#define BCMA_CC_PPL_P2_SHIFT 20
-+#define BCMA_CC_PPL_M14_OFF 1
-+#define BCMA_CC_PPL_MDIV_MASK 0x000000ff
-+#define BCMA_CC_PPL_MDIV_WIDTH 8
-+#define BCMA_CC_PPL_NM5_OFF 2
-+#define BCMA_CC_PPL_NDIV_MASK 0xfff00000
-+#define BCMA_CC_PPL_NDIV_SHIFT 20
-+#define BCMA_CC_PPL_FMAB_OFF 3
-+#define BCMA_CC_PPL_MRAT_MASK 0xf0000000
-+#define BCMA_CC_PPL_MRAT_SHIFT 28
-+#define BCMA_CC_PPL_ABRAT_MASK 0x08000000
-+#define BCMA_CC_PPL_ABRAT_SHIFT 27
-+#define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
-+#define BCMA_CC_PPL_PLLCTL_OFF 4
-+#define BCMA_CC_PPL_PCHI_OFF 5
-+#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
-+
++#define BCMA_CC_PPL_P1P2_OFF 0
++#define BCMA_CC_PPL_P1_MASK 0x0f000000
++#define BCMA_CC_PPL_P1_SHIFT 24
++#define BCMA_CC_PPL_P2_MASK 0x00f00000
++#define BCMA_CC_PPL_P2_SHIFT 20
++#define BCMA_CC_PPL_M14_OFF 1
++#define BCMA_CC_PPL_MDIV_MASK 0x000000ff
++#define BCMA_CC_PPL_MDIV_WIDTH 8
++#define BCMA_CC_PPL_NM5_OFF 2
++#define BCMA_CC_PPL_NDIV_MASK 0xfff00000
++#define BCMA_CC_PPL_NDIV_SHIFT 20
++#define BCMA_CC_PPL_FMAB_OFF 3
++#define BCMA_CC_PPL_MRAT_MASK 0xf0000000
++#define BCMA_CC_PPL_MRAT_SHIFT 28
++#define BCMA_CC_PPL_ABRAT_MASK 0x08000000
++#define BCMA_CC_PPL_ABRAT_SHIFT 27
++#define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
++#define BCMA_CC_PPL_PLLCTL_OFF 4
++#define BCMA_CC_PPL_PCHI_OFF 5
++#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
+
/* Data for the PMU, if available.
* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
- */
--- a/include/linux/bcma/bcma_driver_mips.h
+++ b/include/linux/bcma/bcma_driver_mips.h
-@@ -54,6 +54,7 @@ struct bcma_drv_mips {
- };
+@@ -44,6 +44,8 @@ extern void bcma_core_mips_init(struct b
+ static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
+ #endif
- extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
+extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
-
++
extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
+ #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
generated by cgit v1.1 at 2024-11-30 16:34:57 +0000