diff options
Diffstat (limited to 'target/linux/cns3xxx/patches-3.10')
21 files changed, 994 insertions, 0 deletions
diff --git a/target/linux/cns3xxx/patches-3.10/000-cns3xxx_arch_include.patch b/target/linux/cns3xxx/patches-3.10/000-cns3xxx_arch_include.patch new file mode 100644 index 0000000..f98fe0c --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/000-cns3xxx_arch_include.patch @@ -0,0 +1,8 @@ +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -1,3 +1,5 @@ ++ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include ++ + obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o + cns3xxx-y += core.o pm.o + cns3xxx-$(CONFIG_ATAGS) += devices.o diff --git a/target/linux/cns3xxx/patches-3.10/001-cns3xxx_section_fix.patch b/target/linux/cns3xxx/patches-3.10/001-cns3xxx_section_fix.patch new file mode 100644 index 0000000..3191726 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/001-cns3xxx_section_fix.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -307,7 +307,7 @@ static struct usb_ohci_pdata cns3xxx_usb + .power_off = csn3xxx_usb_power_off, + }; + +-static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { ++static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { + { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata }, + { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata }, + { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL }, diff --git a/target/linux/cns3xxx/patches-3.10/010-arm_introduce-dma-fiq-irq-broadcast.patch b/target/linux/cns3xxx/patches-3.10/010-arm_introduce-dma-fiq-irq-broadcast.patch new file mode 100644 index 0000000..a666e17 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/010-arm_introduce-dma-fiq-irq-broadcast.patch @@ -0,0 +1,56 @@ +--- a/arch/arm/include/asm/glue-cache.h ++++ b/arch/arm/include/asm/glue-cache.h +@@ -129,11 +129,19 @@ + #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) + #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) + #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) ++#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST + #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) + + #define dmac_map_area __glue(_CACHE,_dma_map_area) + #define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) + #define dmac_flush_range __glue(_CACHE,_dma_flush_range) ++#else ++#define __cpuc_flush_dcache_area __glue(fiq,_flush_kern_dcache_area) ++ ++#define dmac_map_area __glue(fiq,_dma_map_area) ++#define dmac_unmap_area __glue(fiq,_dma_unmap_area) ++#define dmac_flush_range __glue(fiq,_dma_flush_range) ++#endif /* CONFIG_DMA_CACHE_FIQ_BROADCAST */ + #endif + + #endif +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -823,6 +823,17 @@ config DMA_CACHE_RWFO + in hardware, other workarounds are needed (e.g. cache + maintenance broadcasting in software via FIQ). + ++config DMA_CACHE_FIQ_BROADCAST ++ bool "Enable fiq broadcast DMA cache maintenance" ++ depends on CPU_V6K && SMP ++ select FIQ ++ help ++ The Snoop Control Unit on ARM11MPCore does not detect the ++ cache maintenance operations and the dma_{map,unmap}_area() ++ functions may leave stale cache entries on other CPUs. By ++ enabling this option, fiq broadcast in the ARMv6 ++ DMA cache maintenance functions is performed. ++ + config OUTER_CACHE + bool + +--- a/arch/arm/mm/flush.c ++++ b/arch/arm/mm/flush.c +@@ -286,7 +286,10 @@ void flush_dcache_page(struct page *page + + mapping = page_mapping(page); + +- if (!cache_ops_need_broadcast() && ++ if ( ++#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST ++ !cache_ops_need_broadcast() && ++#endif + mapping && !mapping_mapped(mapping)) + clear_bit(PG_dcache_clean, &page->flags); + else { diff --git a/target/linux/cns3xxx/patches-3.10/020-watchdog_support.patch b/target/linux/cns3xxx/patches-3.10/020-watchdog_support.patch new file mode 100644 index 0000000..74ffcc3 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/020-watchdog_support.patch @@ -0,0 +1,59 @@ +1. Made the connection between CNS3xxx SOCs(ARCH_CNS3xxx) and MPcore watchdog + since the CNS3xxx SOCs have ARM11 MPcore CPU. +2. Enable mpcore_watchdog option as module to default configuration at + arch/arm/configs/cns3420vb_defconfig. + +Signed-off-by: Tommy Lin <tommy.lin@caviumnetworks.com> + +--- +arch/arm/Kconfig | 1 + + arch/arm/configs/cns3420vb_defconfig | 2 ++ + arch/arm/mach-cns3xxx/cns3420vb.c | 22 ++++++++++++++++++++++ + 3 files changed, 25 insertions(+), 0 deletions(-) + +--- a/arch/arm/configs/cns3420vb_defconfig ++++ b/arch/arm/configs/cns3420vb_defconfig +@@ -56,6 +56,8 @@ CONFIG_LEGACY_PTY_COUNT=16 + # CONFIG_HW_RANDOM is not set + # CONFIG_HWMON is not set + # CONFIG_VGA_CONSOLE is not set ++CONFIG_WATCHDOG=y ++CONFIG_MPCORE_WATCHDOG=m + # CONFIG_HID_SUPPORT is not set + # CONFIG_USB_SUPPORT is not set + CONFIG_MMC=y +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -206,10 +206,32 @@ static struct platform_device cns3xxx_us + }, + }; + ++/* Watchdog */ ++static struct resource cns3xxx_watchdog_resources[] = { ++ [0] = { ++ .start = CNS3XXX_TC11MP_TWD_BASE, ++ .end = CNS3XXX_TC11MP_TWD_BASE + PAGE_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_LOCALWDOG, ++ .end = IRQ_LOCALWDOG, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device cns3xxx_watchdog_device = { ++ .name = "mpcore_wdt", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(cns3xxx_watchdog_resources), ++ .resource = cns3xxx_watchdog_resources, ++}; ++ + /* + * Initialization + */ + static struct platform_device *cns3420_pdevs[] __initdata = { ++ &cns3xxx_watchdog_device, + &cns3420_nor_pdev, + &cns3xxx_usb_ehci_device, + &cns3xxx_usb_ohci_device, diff --git a/target/linux/cns3xxx/patches-3.10/025-smp_support.patch b/target/linux/cns3xxx/patches-3.10/025-smp_support.patch new file mode 100644 index 0000000..4d6e0cd --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/025-smp_support.patch @@ -0,0 +1,30 @@ +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -5,3 +5,5 @@ cns3xxx-y += core.o pm.o + cns3xxx-$(CONFIG_ATAGS) += devices.o + cns3xxx-$(CONFIG_PCI) += pcie.o + cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o ++cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o ++cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o +--- a/arch/arm/mach-cns3xxx/Kconfig ++++ b/arch/arm/mach-cns3xxx/Kconfig +@@ -6,6 +6,9 @@ config ARCH_CNS3XXX + select MIGHT_HAVE_CACHE_L2X0 + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI ++ select HAVE_ARM_SCU if SMP ++ select HAVE_ARM_TWD if LOCAL_TIMERS ++ select HAVE_SMP + help + Support for Cavium Networks CNS3XXX platform. + +--- a/arch/arm/mach-cns3xxx/core.h ++++ b/arch/arm/mach-cns3xxx/core.h +@@ -11,6 +11,7 @@ + #ifndef __CNS3XXX_CORE_H + #define __CNS3XXX_CORE_H + ++extern struct smp_operations cns3xxx_smp_ops; + extern void cns3xxx_timer_init(void); + + #ifdef CONFIG_CACHE_L2X0 diff --git a/target/linux/cns3xxx/patches-3.10/030-pcie_clock.patch b/target/linux/cns3xxx/patches-3.10/030-pcie_clock.patch new file mode 100644 index 0000000..3734daf --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/030-pcie_clock.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -370,8 +370,6 @@ static int __init cns3xxx_pcie_init(void + for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { + iotable_init(cns3xxx_pcie[i].cfg_bases, + ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases)); +- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i)); +- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); + cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); + cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); + pci_common_init(&cns3xxx_pcie[i].hw_pci); diff --git a/target/linux/cns3xxx/patches-3.10/040-fiq_support.patch b/target/linux/cns3xxx/patches-3.10/040-fiq_support.patch new file mode 100644 index 0000000..25a59c1 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/040-fiq_support.patch @@ -0,0 +1,40 @@ +--- a/arch/arm/mach-cns3xxx/Kconfig ++++ b/arch/arm/mach-cns3xxx/Kconfig +@@ -9,6 +9,7 @@ config ARCH_CNS3XXX + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_SMP ++ select FIQ + help + Support for Cavium Networks CNS3XXX platform. + +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -5,5 +5,5 @@ cns3xxx-y += core.o pm.o + cns3xxx-$(CONFIG_ATAGS) += devices.o + cns3xxx-$(CONFIG_PCI) += pcie.o + cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o +-cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o ++cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o + cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o +--- a/arch/arm/mach-cns3xxx/cns3xxx.h ++++ b/arch/arm/mach-cns3xxx/cns3xxx.h +@@ -267,6 +267,7 @@ + #define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) + #define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) + ++#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4) + /* + * Power management and clock control + */ +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -806,7 +806,7 @@ config KUSER_HELPERS + + config DMA_CACHE_RWFO + bool "Enable read/write for ownership DMA cache maintenance" +- depends on CPU_V6K && SMP ++ depends on CPU_V6K && SMP && !ARCH_CNS3XXX + default y + help + The Snoop Control Unit on ARM11MPCore does not detect the diff --git a/target/linux/cns3xxx/patches-3.10/045-twd_base.patch b/target/linux/cns3xxx/patches-3.10/045-twd_base.patch new file mode 100644 index 0000000..b93a7f1 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/045-twd_base.patch @@ -0,0 +1,45 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -17,6 +17,7 @@ + #include <linux/platform_device.h> + #include <linux/usb/ehci_pdriver.h> + #include <linux/usb/ohci_pdriver.h> ++#include <asm/smp_twd.h> + #include <asm/mach/arch.h> + #include <asm/mach/map.h> + #include <asm/mach/time.h> +@@ -26,6 +27,8 @@ + #include "core.h" + #include "pm.h" + ++#define IRQ_LOCALTIMER 29 ++ + static struct map_desc cns3xxx_io_desc[] __initdata = { + { + .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT, +@@ -159,6 +162,17 @@ static struct irqaction cns3xxx_timer_ir + .handler = cns3xxx_timer_interrupt, + }; + ++static void __init cns3xxx_init_twd(void) ++{ ++#ifdef CONFIG_LOCAL_TIMERS ++ static DEFINE_TWD_LOCAL_TIMER(cns3xx_twd_local_timer, ++ CNS3XXX_TC11MP_TWD_BASE, ++ IRQ_LOCALTIMER); ++ ++ twd_local_timer_register(&cns3xx_twd_local_timer); ++#endif ++} ++ + /* + * Set up the clock source and clock events devices + */ +@@ -212,6 +226,7 @@ static void __init __cns3xxx_timer_init( + setup_irq(timer_irq, &cns3xxx_timer_irq); + + cns3xxx_clockevents_init(timer_irq); ++ cns3xxx_init_twd(); + } + + void __init cns3xxx_timer_init(void) diff --git a/target/linux/cns3xxx/patches-3.10/055-pcie_io.patch b/target/linux/cns3xxx/patches-3.10/055-pcie_io.patch new file mode 100644 index 0000000..b4f2768 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/055-pcie_io.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[] + .pfn = __phys_to_pfn(CNS3XXX_PM_BASE), + .length = SZ_4K, + .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_PCIE0_IO_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE), ++ .length = SZ_16M, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_PCIE1_IO_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE), ++ .length = SZ_16M, ++ .type = MT_DEVICE, + }, + }; + diff --git a/target/linux/cns3xxx/patches-3.10/060-pcie_abort.patch b/target/linux/cns3xxx/patches-3.10/060-pcie_abort.patch new file mode 100644 index 0000000..e1edf05 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/060-pcie_abort.patch @@ -0,0 +1,129 @@ +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -92,6 +92,79 @@ static void __iomem *cns3xxx_pci_cfg_bas + return base + offset; + } + ++static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where) ++{ ++ struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); ++ ++ /* check PCI-compatible status register after access */ ++ if (cnspci->linked) { ++ void __iomem *host_base; ++ u32 sreg, ereg; ++ ++ host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual; ++ sreg = __raw_readw(host_base + 0x6) & 0xF900; ++ ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg ++ ++ if (sreg | ereg) { ++ /* SREG: ++ * BIT15 - Detected Parity Error ++ * BIT14 - Signaled System Error ++ * BIT13 - Received Master Abort ++ * BIT12 - Received Target Abort ++ * BIT11 - Signaled Target Abort ++ * BIT08 - Master Data Parity Error ++ * ++ * EREG: ++ * BIT20 - Unsupported Request ++ * BIT19 - ECRC ++ * BIT18 - Malformed TLP ++ * BIT17 - Receiver Overflow ++ * BIT16 - Unexpected Completion ++ * BIT15 - Completer Abort ++ * BIT14 - Completion Timeout ++ * BIT13 - Flow Control Protocol Error ++ * BIT12 - Poisoned TLP ++ * BIT04 - Data Link Protocol Error ++ * ++ * TODO: see Documentation/pci-error-recovery.txt ++ * implement error_detected handler ++ */ ++/* ++ printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg); ++ if (sreg & BIT(15)) printk(" <PERR"); ++ if (sreg & BIT(14)) printk(" >SERR"); ++ if (sreg & BIT(13)) printk(" <MABRT"); ++ if (sreg & BIT(12)) printk(" <TABRT"); ++ if (sreg & BIT(11)) printk(" >TABRT"); ++ if (sreg & BIT( 8)) printk(" MPERR"); ++ ++ if (ereg & BIT(20)) printk(" Unsup"); ++ if (ereg & BIT(19)) printk(" ECRC"); ++ if (ereg & BIT(18)) printk(" MTLP"); ++ if (ereg & BIT(17)) printk(" OFLOW"); ++ if (ereg & BIT(16)) printk(" Unex"); ++ if (ereg & BIT(15)) printk(" ABRT"); ++ if (ereg & BIT(14)) printk(" COMPTO"); ++ if (ereg & BIT(13)) printk(" FLOW"); ++ if (ereg & BIT(12)) printk(" PTLP"); ++ if (ereg & BIT( 4)) printk(" DLINK"); ++ printk("\n"); ++*/ ++ pr_debug("%s failed port%d sreg=0x%04x\n", __func__, ++ cnspci->hw_pci.domain, sreg); ++ ++ /* make sure the status bits are reset */ ++ __raw_writew(sreg, host_base + 6); ++ __raw_writel(ereg, host_base + 0x104); ++ return 1; ++ } ++ } ++ else ++ return 1; ++ ++ return 0; ++} ++ + static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) + { +@@ -108,6 +181,11 @@ static int cns3xxx_pci_read_config(struc + + v = __raw_readl(base); + ++ if (check_master_abort(bus, devfn, where)) { ++ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } ++ + if (bus->number == 0 && devfn == 0 && + (where & 0xffc) == PCI_CLASS_REVISION) { + /* +@@ -137,11 +215,19 @@ static int cns3xxx_pci_write_config(stru + return PCIBIOS_SUCCESSFUL; + + v = __raw_readl(base); ++ if (check_master_abort(bus, devfn, where)) { ++ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } + + v &= ~(mask << shift); + v |= (val & mask) << shift; + + __raw_writel(v, base); ++ if (check_master_abort(bus, devfn, where)) { ++ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on write\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } + + return PCIBIOS_SUCCESSFUL; + } +@@ -352,8 +438,14 @@ static void __init cns3xxx_pcie_hw_init( + static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) + { ++#if 0 ++/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE ++ * ignore imprecise aborts and use PCI-compatible Status register to ++ * determine errors instead ++ */ + if (fsr & (1 << 10)) + regs->ARM_pc += 4; ++#endif + return 0; + } + diff --git a/target/linux/cns3xxx/patches-3.10/065-pcie_early_init.patch b/target/linux/cns3xxx/patches-3.10/065-pcie_early_init.patch new file mode 100644 index 0000000..252c955 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/065-pcie_early_init.patch @@ -0,0 +1,84 @@ +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -261,11 +261,21 @@ static struct map_desc cns3420_io_desc[] + static void __init cns3420_map_io(void) + { + cns3xxx_map_io(); ++ cns3xxx_pcie_iotable_init(); + iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc)); + + cns3420_early_serial_setup(); + } + ++static int __init cns3420vb_pcie_init(void) ++{ ++ if (!machine_is_cns3420vb()) ++ return 0; ++ ++ return cns3xxx_pcie_init(); ++} ++subsys_initcall(cns3420vb_pcie_init); ++ + MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") + .atag_offset = 0x100, + .nr_irqs = NR_IRQS_CNS3XXX, +--- a/arch/arm/mach-cns3xxx/core.h ++++ b/arch/arm/mach-cns3xxx/core.h +@@ -13,6 +13,7 @@ + + extern struct smp_operations cns3xxx_smp_ops; + extern void cns3xxx_timer_init(void); ++extern void cns3xxx_pcie_iotable_init(void); + + #ifdef CONFIG_CACHE_L2X0 + void __init cns3xxx_l2x0_init(void); +@@ -22,6 +23,7 @@ static inline void cns3xxx_l2x0_init(voi + + void __init cns3xxx_map_io(void); + void __init cns3xxx_init_irq(void); ++int __init cns3xxx_pcie_init(void); + void cns3xxx_power_off(void); + void cns3xxx_restart(char, const char *); + +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -449,7 +449,18 @@ static int cns3xxx_pcie_abort_handler(un + return 0; + } + +-static int __init cns3xxx_pcie_init(void) ++ ++void __init cns3xxx_pcie_iotable_init() ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { ++ iotable_init(cns3xxx_pcie[i].cfg_bases, ++ ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases)); ++ } ++} ++ ++int __init cns3xxx_pcie_init(void) + { + int i; + +@@ -460,15 +471,14 @@ static int __init cns3xxx_pcie_init(void + "imprecise external abort"); + + for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { +- iotable_init(cns3xxx_pcie[i].cfg_bases, +- ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases)); + cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); +- cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); +- pci_common_init(&cns3xxx_pcie[i].hw_pci); ++ if (cns3xxx_pcie[i].linked) { ++ cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); ++ pci_common_init(&cns3xxx_pcie[i].hw_pci); ++ } + } + + pci_assign_unassigned_resources(); + + return 0; + } +-device_initcall(cns3xxx_pcie_init); diff --git a/target/linux/cns3xxx/patches-3.10/070-i2c_support.patch b/target/linux/cns3xxx/patches-3.10/070-i2c_support.patch new file mode 100644 index 0000000..adac218 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/070-i2c_support.patch @@ -0,0 +1,31 @@ +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -375,6 +375,18 @@ config I2C_CBUS_GPIO + This driver can also be built as a module. If so, the module + will be called i2c-cbus-gpio. + ++config I2C_CNS3XXX ++ tristate "Cavium CNS3xxx I2C driver" ++ depends on ARCH_CNS3XXX ++ help ++ Support for Cavium CNS3xxx I2C controller driver. ++ ++ This driver can also be built as a module. If so, the module ++ will be called i2c-cns3xxx. ++ ++ Please note that this driver might be needed to bring up other ++ devices such as Cavium CNS3xxx Ethernet. ++ + config I2C_CPM + tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)" + depends on (CPM1 || CPM2) && OF_I2C +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -89,6 +89,7 @@ obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o + obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o + obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o + obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o ++obj-$(CONFIG_I2C_CNS3XXX) += i2c-cns3xxx.o + obj-$(CONFIG_SCx200_ACB) += scx200_acb.o + obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o + diff --git a/target/linux/cns3xxx/patches-3.10/075-spi_support.patch b/target/linux/cns3xxx/patches-3.10/075-spi_support.patch new file mode 100644 index 0000000..6acb2cd --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/075-spi_support.patch @@ -0,0 +1,57 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -142,6 +142,13 @@ config SPI_CLPS711X + This enables dedicated general purpose SPI/Microwire1-compatible + master mode interface (SSI1) for CLPS711X-based CPUs. + ++config SPI_CNS3XXX ++ tristate "CNS3XXX SPI controller" ++ depends on ARCH_CNS3XXX && SPI_MASTER ++ select SPI_BITBANG ++ help ++ This enables using the CNS3XXX SPI controller in master mode. ++ + config SPI_COLDFIRE_QSPI + tristate "Freescale Coldfire QSPI controller" + depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x) +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5x + obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o + obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o + obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o ++obj-$(CONFIG_SPI_CNS3XXX) += spi-cns3xxx.o + obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o + obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o + obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o +--- a/drivers/spi/spi-bitbang.c ++++ b/drivers/spi/spi-bitbang.c +@@ -328,6 +328,12 @@ static void bitbang_work(struct work_str + */ + if (!m->is_dma_mapped) + t->rx_dma = t->tx_dma = 0; ++ ++ if (t->transfer_list.next == &m->transfers) ++ t->last_in_message_list = 1; ++ else ++ t->last_in_message_list = 0; ++ + status = bitbang->txrx_bufs(spi, t); + } + if (status > 0) +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -524,6 +524,13 @@ struct spi_transfer { + u32 speed_hz; + + struct list_head transfer_list; ++ ++#ifdef CONFIG_ARCH_CNS3XXX ++ unsigned last_in_message_list; ++#ifdef CONFIG_SPI_CNS3XXX_2IOREAD ++ u8 dio_read; ++#endif ++#endif + }; + + /** diff --git a/target/linux/cns3xxx/patches-3.10/080-sata_support.patch b/target/linux/cns3xxx/patches-3.10/080-sata_support.patch new file mode 100644 index 0000000..93d29bf --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/080-sata_support.patch @@ -0,0 +1,44 @@ +--- a/arch/arm/mach-cns3xxx/devices.c ++++ b/arch/arm/mach-cns3xxx/devices.c +@@ -40,7 +40,7 @@ static struct resource cns3xxx_ahci_reso + static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32); + + static struct platform_device cns3xxx_ahci_pdev = { +- .name = "ahci", ++ .name = "cns3xxx-ahci", + .id = 0, + .resource = cns3xxx_ahci_resource, + .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource), +--- a/drivers/ata/ahci_platform.c ++++ b/drivers/ata/ahci_platform.c +@@ -31,6 +31,7 @@ enum ahci_type { + AHCI, /* standard platform ahci */ + IMX53_AHCI, /* ahci on i.mx53 */ + STRICT_AHCI, /* delayed DMA engine start */ ++ CNS3XXX_AHCI, /* AHCI on cns3xxx */ + }; + + static struct platform_device_id ahci_devtype[] = { +@@ -44,6 +45,9 @@ static struct platform_device_id ahci_de + .name = "strict-ahci", + .driver_data = STRICT_AHCI, + }, { ++ .name = "cns3xxx-ahci", ++ .driver_data = CNS3XXX_AHCI, ++ }, { + /* sentinel */ + } + }; +@@ -80,6 +84,12 @@ static const struct ata_port_info ahci_p + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_platform_ops, + }, ++ [CNS3XXX_AHCI] = { ++ .flags = AHCI_FLAG_COMMON, ++ .pio_mask = ATA_PIO4, ++ .udma_mask = ATA_UDMA6, ++ .port_ops = &ahci_platform_retry_srst_ops, ++ } + }; + + static struct scsi_host_template ahci_platform_sht = { diff --git a/target/linux/cns3xxx/patches-3.10/085-ethernet_support.patch b/target/linux/cns3xxx/patches-3.10/085-ethernet_support.patch new file mode 100644 index 0000000..84548a3 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/085-ethernet_support.patch @@ -0,0 +1,20 @@ +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -32,6 +32,7 @@ source "drivers/net/ethernet/calxeda/Kco + source "drivers/net/ethernet/chelsio/Kconfig" + source "drivers/net/ethernet/cirrus/Kconfig" + source "drivers/net/ethernet/cisco/Kconfig" ++source "drivers/net/ethernet/cavium/Kconfig" + source "drivers/net/ethernet/davicom/Kconfig" + + config DNET +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -15,6 +15,7 @@ obj-$(CONFIG_NET_BFIN) += adi/ + obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/ + obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/ + obj-$(CONFIG_NET_CALXEDA_XGMAC) += calxeda/ ++obj-$(CONFIG_NET_VENDOR_CAVIUM) += cavium/ + obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/ + obj-$(CONFIG_NET_VENDOR_CIRRUS) += cirrus/ + obj-$(CONFIG_NET_VENDOR_CISCO) += cisco/ diff --git a/target/linux/cns3xxx/patches-3.10/090-timers.patch b/target/linux/cns3xxx/patches-3.10/090-timers.patch new file mode 100644 index 0000000..46635e1 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/090-timers.patch @@ -0,0 +1,104 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -103,12 +103,13 @@ static void cns3xxx_timer_set_mode(enum + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: +- reload = pclk * 20 / (3 * HZ) * 0x25000; ++ reload = pclk * 1000000 / HZ; + writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); + ctrl |= (1 << 0) | (1 << 2) | (1 << 9); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ ++ writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); + ctrl |= (1 << 2) | (1 << 9); + break; + case CLOCK_EVT_MODE_UNUSED: +@@ -136,7 +137,7 @@ static struct clock_event_device cns3xxx + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = cns3xxx_timer_set_mode, + .set_next_event = cns3xxx_timer_set_next_event, +- .rating = 350, ++ .rating = 300, + .cpumask = cpu_all_mask, + }; + +@@ -183,6 +184,35 @@ static void __init cns3xxx_init_twd(void + #endif + } + ++static cycle_t cns3xxx_get_cycles(struct clocksource *cs) ++{ ++ u64 val; ++ ++ val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); ++ val &= 0xffff; ++ ++ return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET)); ++} ++ ++static struct clocksource clocksource_cns3xxx = { ++ .name = "freerun", ++ .rating = 200, ++ .read = cns3xxx_get_cycles, ++ .mask = CLOCKSOURCE_MASK(48), ++ .shift = 16, ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++}; ++ ++static void __init cns3xxx_clocksource_init(void) ++{ ++ /* Reset the FreeRunning counter */ ++ writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); ++ ++ clocksource_cns3xxx.mult = ++ clocksource_khz2mult(100, clocksource_cns3xxx.shift); ++ clocksource_register(&clocksource_cns3xxx); ++} ++ + /* + * Set up the clock source and clock events devices + */ +@@ -200,13 +230,12 @@ static void __init __cns3xxx_timer_init( + /* stop free running timer3 */ + writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); + +- /* timer1 */ +- writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); +- writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); +- + writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); + writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); + ++ val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ; ++ writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); ++ + /* mask irq, non-mask timer1 overflow */ + irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); + irq_mask &= ~(1 << 2); +@@ -218,23 +247,9 @@ static void __init __cns3xxx_timer_init( + val |= (1 << 9); + writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + +- /* timer2 */ +- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); +- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); +- +- /* mask irq */ +- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); +- irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5)); +- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); +- +- /* down counter */ +- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); +- val |= (1 << 10); +- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); +- +- /* Make irqs happen for the system timer */ + setup_irq(timer_irq, &cns3xxx_timer_irq); + ++ cns3xxx_clocksource_init(); + cns3xxx_clockevents_init(timer_irq); + cns3xxx_init_twd(); + } diff --git a/target/linux/cns3xxx/patches-3.10/095-gpio_support.patch b/target/linux/cns3xxx/patches-3.10/095-gpio_support.patch new file mode 100644 index 0000000..baa16cde --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/095-gpio_support.patch @@ -0,0 +1,82 @@ +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -245,6 +245,10 @@ static void __init cns3420_init(void) + + cns3xxx_ahci_init(); + cns3xxx_sdhci_init(); ++ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA, ++ NR_IRQS_CNS3XXX); ++ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB, ++ NR_IRQS_CNS3XXX + 32); + + pm_power_off = cns3xxx_power_off; + } +--- a/arch/arm/mach-cns3xxx/core.h ++++ b/arch/arm/mach-cns3xxx/core.h +@@ -15,12 +15,6 @@ extern struct smp_operations cns3xxx_smp + extern void cns3xxx_timer_init(void); + extern void cns3xxx_pcie_iotable_init(void); + +-#ifdef CONFIG_CACHE_L2X0 +-void __init cns3xxx_l2x0_init(void); +-#else +-static inline void cns3xxx_l2x0_init(void) {} +-#endif /* CONFIG_CACHE_L2X0 */ +- + void __init cns3xxx_map_io(void); + void __init cns3xxx_init_irq(void); + int __init cns3xxx_pcie_init(void); +--- a/arch/arm/mach-cns3xxx/Kconfig ++++ b/arch/arm/mach-cns3xxx/Kconfig +@@ -2,6 +2,8 @@ config ARCH_CNS3XXX + bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6 + select ARM_GIC + select CPU_V6K ++ select ARCH_REQUIRE_GPIOLIB ++ select GENERIC_IRQ_CHIP + select GENERIC_CLOCKEVENTS + select MIGHT_HAVE_CACHE_L2X0 + select MIGHT_HAVE_PCI +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -1,7 +1,7 @@ + ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include + + obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o +-cns3xxx-y += core.o pm.o ++cns3xxx-y += core.o pm.o gpio.o + cns3xxx-$(CONFIG_ATAGS) += devices.o + cns3xxx-$(CONFIG_PCI) += pcie.o + cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o +--- a/arch/arm/mach-cns3xxx/cns3xxx.h ++++ b/arch/arm/mach-cns3xxx/cns3xxx.h +@@ -68,8 +68,10 @@ + #define SMC_PCELL_ID_3_OFFSET 0xFFC + + #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ ++#define CNS3XXX_GPIOA_BASE_VIRT 0xFB006000 + + #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ ++#define CNS3XXX_GPIOB_BASE_VIRT 0xFB007000 + + #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ + +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -60,6 +60,16 @@ static struct map_desc cns3xxx_io_desc[] + .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE), + .length = SZ_16M, + .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_GPIOA_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_GPIOB_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE, + }, + }; + diff --git a/target/linux/cns3xxx/patches-3.10/097-l2x0_cmdline_disable.patch b/target/linux/cns3xxx/patches-3.10/097-l2x0_cmdline_disable.patch new file mode 100644 index 0000000..73619ba --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/097-l2x0_cmdline_disable.patch @@ -0,0 +1,54 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -273,13 +273,26 @@ void __init cns3xxx_timer_init(void) + + #ifdef CONFIG_CACHE_L2X0 + +-void __init cns3xxx_l2x0_init(void) ++static int cns3xxx_l2x0_enable = 1; ++ ++static int __init cns3xxx_l2x0_disable(char *s) ++{ ++ cns3xxx_l2x0_enable = 0; ++ return 1; ++} ++__setup("nol2x0", cns3xxx_l2x0_disable); ++ ++static int __init cns3xxx_l2x0_init(void) + { +- void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); ++ void __iomem *base; + u32 val; + ++ if (!cns3xxx_l2x0_enable) ++ return 0; ++ ++ base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); + if (WARN_ON(!base)) +- return; ++ return 0; + + /* + * Tag RAM Control register +@@ -309,7 +322,10 @@ void __init cns3xxx_l2x0_init(void) + + /* 32 KiB, 8-way, parity disable */ + l2x0_init(base, 0x00540000, 0xfe000fff); ++ ++ return 0; + } ++arch_initcall(cns3xxx_l2x0_init); + + #endif /* CONFIG_CACHE_L2X0 */ + +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -239,8 +239,6 @@ static struct platform_device *cns3420_p + + static void __init cns3420_init(void) + { +- cns3xxx_l2x0_init(); +- + platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); + + cns3xxx_ahci_init(); diff --git a/target/linux/cns3xxx/patches-3.10/200-dwc_otg_support.patch b/target/linux/cns3xxx/patches-3.10/200-dwc_otg_support.patch new file mode 100644 index 0000000..b8c06c9 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/200-dwc_otg_support.patch @@ -0,0 +1,48 @@ +--- a/drivers/usb/Kconfig ++++ b/drivers/usb/Kconfig +@@ -136,6 +136,8 @@ source "drivers/usb/musb/Kconfig" + + source "drivers/usb/renesas_usbhs/Kconfig" + ++source "drivers/usb/dwc/Kconfig" ++ + source "drivers/usb/class/Kconfig" + + source "drivers/usb/storage/Kconfig" +--- a/drivers/usb/core/urb.c ++++ b/drivers/usb/core/urb.c +@@ -17,7 +17,11 @@ static void urb_destroy(struct kref *kre + + if (urb->transfer_flags & URB_FREE_BUFFER) + kfree(urb->transfer_buffer); +- ++ if (urb->aligned_transfer_buffer) { ++ kfree(urb->aligned_transfer_buffer); ++ urb->aligned_transfer_buffer = 0; ++ urb->aligned_transfer_dma = 0; ++ } + kfree(urb); + } + +--- a/include/linux/usb.h ++++ b/include/linux/usb.h +@@ -1404,6 +1404,9 @@ struct urb { + unsigned int transfer_flags; /* (in) URB_SHORT_NOT_OK | ...*/ + void *transfer_buffer; /* (in) associated data buffer */ + dma_addr_t transfer_dma; /* (in) dma addr for transfer_buffer */ ++ void *aligned_transfer_buffer; /* (in) associeated data buffer */ ++ dma_addr_t aligned_transfer_dma;/* (in) dma addr for transfer_buffer */ ++ u32 aligned_transfer_buffer_length; /* (in) data buffer length */ + struct scatterlist *sg; /* (in) scatter gather buffer list */ + int num_mapped_sgs; /* (internal) mapped sg entries */ + int num_sgs; /* (in) number of entries in the sg list */ +--- a/drivers/usb/Makefile ++++ b/drivers/usb/Makefile +@@ -7,6 +7,7 @@ + obj-$(CONFIG_USB) += core/ + + obj-$(CONFIG_USB_DWC3) += dwc3/ ++obj-$(CONFIG_USB_DWC_OTG) += dwc/ + + obj-$(CONFIG_USB_MON) += mon/ + diff --git a/target/linux/cns3xxx/patches-3.10/300-laguna_support.patch b/target/linux/cns3xxx/patches-3.10/300-laguna_support.patch new file mode 100644 index 0000000..d2338e2 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/300-laguna_support.patch @@ -0,0 +1,46 @@ +--- a/arch/arm/mach-cns3xxx/Kconfig ++++ b/arch/arm/mach-cns3xxx/Kconfig +@@ -27,4 +27,12 @@ config MACH_CNS3420VB + This is a platform with an on-board ARM11 MPCore and has support + for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc. + ++config MACH_GW2388 ++ bool "Support for Gateworks Laguna Platform" ++ help ++ Include support for the Gateworks Laguna Platform ++ ++ This is a platform with an on-board ARM11 MPCore and has support ++ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc. ++ + endmenu +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -7,3 +7,5 @@ cns3xxx-$(CONFIG_PCI) += pcie.o + cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o + cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o + cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o ++cns3xxx-$(CONFIG_MACH_GW2388) += laguna.o ++ +--- a/arch/arm/mach-cns3xxx/devices.c ++++ b/arch/arm/mach-cns3xxx/devices.c +@@ -16,6 +16,7 @@ + #include <linux/compiler.h> + #include <linux/dma-mapping.h> + #include <linux/platform_device.h> ++#include <asm/mach-types.h> + #include "cns3xxx.h" + #include "pm.h" + #include "core.h" +@@ -101,7 +102,11 @@ void __init cns3xxx_sdhci_init(void) + u32 gpioa_pins = __raw_readl(gpioa); + + /* MMC/SD pins share with GPIOA */ +- gpioa_pins |= 0x1fff0004; ++ if (machine_is_gw2388()) { ++ gpioa_pins |= 0x1fff0000; ++ } else { ++ gpioa_pins |= 0x1fff0004; ++ } + __raw_writel(gpioa_pins, gpioa); + + cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); diff --git a/target/linux/cns3xxx/patches-3.10/305-laguna_sdhci_card_detect.patch b/target/linux/cns3xxx/patches-3.10/305-laguna_sdhci_card_detect.patch new file mode 100644 index 0000000..2d28785 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.10/305-laguna_sdhci_card_detect.patch @@ -0,0 +1,16 @@ +--- a/drivers/mmc/host/sdhci-cns3xxx.c ++++ b/drivers/mmc/host/sdhci-cns3xxx.c +@@ -88,10 +88,11 @@ static const struct sdhci_pltfm_data sdh + .ops = &sdhci_cns3xxx_ops, + .quirks = SDHCI_QUIRK_BROKEN_DMA | + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | +- SDHCI_QUIRK_INVERTED_WRITE_PROTECT | ++ //SDHCI_QUIRK_INVERTED_WRITE_PROTECT | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | +- SDHCI_QUIRK_NONSTANDARD_CLOCK, ++ SDHCI_QUIRK_NONSTANDARD_CLOCK | ++ SDHCI_QUIRK_BROKEN_CARD_DETECTION, + }; + + static int sdhci_cns3xxx_probe(struct platform_device *pdev) |