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-rw-r--r--target/linux/generic/patches-3.10/020-ssb_update.patch201
-rw-r--r--target/linux/generic/patches-3.10/025-bcma_backport.patch601
2 files changed, 802 insertions, 0 deletions
diff --git a/target/linux/generic/patches-3.10/020-ssb_update.patch b/target/linux/generic/patches-3.10/020-ssb_update.patch
new file mode 100644
index 0000000..0a75e5e
--- /dev/null
+++ b/target/linux/generic/patches-3.10/020-ssb_update.patch
@@ -0,0 +1,201 @@
+diff --git a/drivers/ssb/Kconfig b/drivers/ssb/Kconfig
+index 5ff3a4f..36171fd 100644
+--- a/drivers/ssb/Kconfig
++++ b/drivers/ssb/Kconfig
+@@ -144,7 +144,7 @@ config SSB_SFLASH
+ # Assumption: We are on embedded, if we compile the MIPS core.
+ config SSB_EMBEDDED
+ bool
+- depends on SSB_DRIVER_MIPS
++ depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
+ default y
+
+ config SSB_DRIVER_EXTIF
+diff --git a/drivers/ssb/driver_chipcommon_sflash.c b/drivers/ssb/driver_chipcommon_sflash.c
+index 720665c..e84cf04 100644
+--- a/drivers/ssb/driver_chipcommon_sflash.c
++++ b/drivers/ssb/driver_chipcommon_sflash.c
+@@ -9,6 +9,19 @@
+
+ #include "ssb_private.h"
+
++static struct resource ssb_sflash_resource = {
++ .name = "ssb_sflash",
++ .start = SSB_FLASH2,
++ .end = 0,
++ .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
++};
++
++struct platform_device ssb_sflash_dev = {
++ .name = "ssb_sflash",
++ .resource = &ssb_sflash_resource,
++ .num_resources = 1,
++};
++
+ struct ssb_sflash_tbl_e {
+ char *name;
+ u32 id;
+@@ -16,7 +29,7 @@ struct ssb_sflash_tbl_e {
+ u16 numblocks;
+ };
+
+-static struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
++static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
+ { "M25P20", 0x11, 0x10000, 4, },
+ { "M25P40", 0x12, 0x10000, 8, },
+
+@@ -27,7 +40,7 @@ static struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
+ { 0 },
+ };
+
+-static struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
++static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
+ { "SST25WF512", 1, 0x1000, 16, },
+ { "SST25VF512", 0x48, 0x1000, 16, },
+ { "SST25WF010", 2, 0x1000, 32, },
+@@ -45,7 +58,7 @@ static struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
+ { 0 },
+ };
+
+-static struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
++static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
+ { "AT45DB011", 0xc, 256, 512, },
+ { "AT45DB021", 0x14, 256, 1024, },
+ { "AT45DB041", 0x1c, 256, 2048, },
+@@ -73,7 +86,8 @@ static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
+ /* Initialize serial flash access */
+ int ssb_sflash_init(struct ssb_chipcommon *cc)
+ {
+- struct ssb_sflash_tbl_e *e;
++ struct ssb_sflash *sflash = &cc->dev->bus->mipscore.sflash;
++ const struct ssb_sflash_tbl_e *e;
+ u32 id, id2;
+
+ switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
+@@ -131,9 +145,21 @@ int ssb_sflash_init(struct ssb_chipcommon *cc)
+ return -ENOTSUPP;
+ }
+
++ sflash->window = SSB_FLASH2;
++ sflash->blocksize = e->blocksize;
++ sflash->numblocks = e->numblocks;
++ sflash->size = sflash->blocksize * sflash->numblocks;
++ sflash->present = true;
++
+ pr_info("Found %s serial flash (blocksize: 0x%X, blocks: %d)\n",
+ e->name, e->blocksize, e->numblocks);
+
++ /* Prepare platform device, but don't register it yet. It's too early,
++ * malloc (required by device_private_init) is not available yet. */
++ ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
++ sflash->size;
++ ssb_sflash_dev.dev.platform_data = sflash;
++
+ pr_err("Serial flash support is not implemented yet!\n");
+
+ return -ENOTSUPP;
+diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
+index 812775a..e55ddf7 100644
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -553,6 +553,14 @@ static int ssb_devices_register(struct ssb_bus *bus)
+ }
+ #endif
+
++#ifdef CONFIG_SSB_SFLASH
++ if (bus->mipscore.sflash.present) {
++ err = platform_device_register(&ssb_sflash_dev);
++ if (err)
++ pr_err("Error registering serial flash\n");
++ }
++#endif
++
+ return 0;
+ error:
+ /* Unwind the already registered devices. */
+diff --git a/drivers/ssb/pcihost_wrapper.c b/drivers/ssb/pcihost_wrapper.c
+index 32ed1fa..69161bb 100644
+--- a/drivers/ssb/pcihost_wrapper.c
++++ b/drivers/ssb/pcihost_wrapper.c
+@@ -38,7 +38,7 @@ static int ssb_pcihost_resume(struct pci_dev *dev)
+ struct ssb_bus *ssb = pci_get_drvdata(dev);
+ int err;
+
+- pci_set_power_state(dev, 0);
++ pci_set_power_state(dev, PCI_D0);
+ err = pci_enable_device(dev);
+ if (err)
+ return err;
+diff --git a/drivers/ssb/sprom.c b/drivers/ssb/sprom.c
+index a3b2364..e753fbe 100644
+--- a/drivers/ssb/sprom.c
++++ b/drivers/ssb/sprom.c
+@@ -54,7 +54,7 @@ static int hex2sprom(u16 *sprom, const char *dump, size_t len,
+ while (cnt < sprom_size_words) {
+ memcpy(tmp, dump, 4);
+ dump += 4;
+- err = strict_strtoul(tmp, 16, &parsed);
++ err = kstrtoul(tmp, 16, &parsed);
+ if (err)
+ return err;
+ sprom[cnt++] = swab16((u16)parsed);
+diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h
+index 4671f17..eb507a5 100644
+--- a/drivers/ssb/ssb_private.h
++++ b/drivers/ssb/ssb_private.h
+@@ -243,6 +243,10 @@ static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
+ extern struct platform_device ssb_pflash_dev;
+ #endif
+
++#ifdef CONFIG_SSB_SFLASH
++extern struct platform_device ssb_sflash_dev;
++#endif
++
+ #ifdef CONFIG_SSB_DRIVER_EXTIF
+ extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
+ extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
+diff --git a/include/linux/ssb/ssb_driver_mips.h b/include/linux/ssb/ssb_driver_mips.h
+index afe79d4..6535e47 100644
+--- a/include/linux/ssb/ssb_driver_mips.h
++++ b/include/linux/ssb/ssb_driver_mips.h
+@@ -20,6 +20,18 @@ struct ssb_pflash {
+ u32 window_size;
+ };
+
++#ifdef CONFIG_SSB_SFLASH
++struct ssb_sflash {
++ bool present;
++ u32 window;
++ u32 blocksize;
++ u16 numblocks;
++ u32 size;
++
++ void *priv;
++};
++#endif
++
+ struct ssb_mipscore {
+ struct ssb_device *dev;
+
+@@ -27,6 +39,9 @@ struct ssb_mipscore {
+ struct ssb_serial_port serial_ports[4];
+
+ struct ssb_pflash pflash;
++#ifdef CONFIG_SSB_SFLASH
++ struct ssb_sflash sflash;
++#endif
+ };
+
+ extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
+diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
+index 3a72569..f9f931c 100644
+--- a/include/linux/ssb/ssb_regs.h
++++ b/include/linux/ssb/ssb_regs.h
+@@ -172,6 +172,7 @@
+ #define SSB_SPROMSIZE_WORDS_R4 220
+ #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
+ #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
++#define SSB_SPROMSIZE_WORDS_R10 230
+ #define SSB_SPROM_BASE1 0x1000
+ #define SSB_SPROM_BASE31 0x0800
+ #define SSB_SPROM_REVISION 0x007E
diff --git a/target/linux/generic/patches-3.10/025-bcma_backport.patch b/target/linux/generic/patches-3.10/025-bcma_backport.patch
new file mode 100644
index 0000000..a6e3b01
--- /dev/null
+++ b/target/linux/generic/patches-3.10/025-bcma_backport.patch
@@ -0,0 +1,601 @@
+diff --git a/drivers/bcma/Kconfig b/drivers/bcma/Kconfig
+index 8b4221c..380a200 100644
+--- a/drivers/bcma/Kconfig
++++ b/drivers/bcma/Kconfig
+@@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
+ config BCMA_HOST_PCI
+ bool "Support for BCMA on PCI-host bus"
+ depends on BCMA_HOST_PCI_POSSIBLE
++ default y
+
+ config BCMA_DRIVER_PCI_HOSTMODE
+ bool "Driver for PCI core working in hostmode"
+diff --git a/drivers/bcma/bcma_private.h b/drivers/bcma/bcma_private.h
+index 79595a0..0215f9a 100644
+--- a/drivers/bcma/bcma_private.h
++++ b/drivers/bcma/bcma_private.h
+@@ -22,6 +22,8 @@
+ struct bcma_bus;
+
+ /* main.c */
++bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
++ int timeout);
+ int bcma_bus_register(struct bcma_bus *bus);
+ void bcma_bus_unregister(struct bcma_bus *bus);
+ int __init bcma_bus_early_register(struct bcma_bus *bus,
+diff --git a/drivers/bcma/core.c b/drivers/bcma/core.c
+index 17b26ce..37a5ffe 100644
+--- a/drivers/bcma/core.c
++++ b/drivers/bcma/core.c
+@@ -9,6 +9,25 @@
+ #include <linux/export.h>
+ #include <linux/bcma/bcma.h>
+
++static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
++ u32 value, int timeout)
++{
++ unsigned long deadline = jiffies + timeout;
++ u32 val;
++
++ do {
++ val = bcma_aread32(core, reg);
++ if ((val & mask) == value)
++ return true;
++ cpu_relax();
++ udelay(10);
++ } while (!time_after_eq(jiffies, deadline));
++
++ bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
++
++ return false;
++}
++
+ bool bcma_core_is_enabled(struct bcma_device *core)
+ {
+ if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
+@@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_device *core, u32 flags)
+ if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
+ return;
+
+- bcma_awrite32(core, BCMA_IOCTL, flags);
+- bcma_aread32(core, BCMA_IOCTL);
+- udelay(10);
++ bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
+
+ bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
+ bcma_aread32(core, BCMA_RESET_CTL);
+ udelay(1);
++
++ bcma_awrite32(core, BCMA_IOCTL, flags);
++ bcma_aread32(core, BCMA_IOCTL);
++ udelay(10);
+ }
+ EXPORT_SYMBOL_GPL(bcma_core_disable);
+
+@@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device *core, u32 flags)
+ bcma_aread32(core, BCMA_IOCTL);
+
+ bcma_awrite32(core, BCMA_RESET_CTL, 0);
++ bcma_aread32(core, BCMA_RESET_CTL);
+ udelay(1);
+
+ bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
+diff --git a/drivers/bcma/driver_chipcommon.c b/drivers/bcma/driver_chipcommon.c
+index 036c674..b068f98 100644
+--- a/drivers/bcma/driver_chipcommon.c
++++ b/drivers/bcma/driver_chipcommon.c
+@@ -140,8 +140,15 @@ void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
+ bcma_core_chipcommon_early_init(cc);
+
+ if (cc->core->id.rev >= 20) {
+- bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
+- bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
++ u32 pullup = 0, pulldown = 0;
++
++ if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
++ pullup = 0x402e0;
++ pulldown = 0x20500;
++ }
++
++ bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
++ bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
+ }
+
+ if (cc->capabilities & BCMA_CC_CAP_PMU)
+diff --git a/drivers/bcma/driver_chipcommon_pmu.c b/drivers/bcma/driver_chipcommon_pmu.c
+index edca73a..5081a8c 100644
+--- a/drivers/bcma/driver_chipcommon_pmu.c
++++ b/drivers/bcma/driver_chipcommon_pmu.c
+@@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
+ }
+ EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
+
++static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
++{
++ u32 ilp_ctl, alp_hz;
++
++ if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
++ BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
++ return 0;
++
++ bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
++ BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
++ usleep_range(1000, 2000);
++
++ ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
++ ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
++
++ bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
++
++ alp_hz = ilp_ctl * 32768 / 4;
++ return (alp_hz + 50000) / 100000 * 100;
++}
++
++static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
++{
++ struct bcma_bus *bus = cc->core->bus;
++ u32 freq_tgt_target = 0, freq_tgt_current;
++ u32 pll0, mask;
++
++ switch (bus->chipinfo.id) {
++ case BCMA_CHIP_ID_BCM43142:
++ /* pmu2_xtaltab0_adfll_485 */
++ switch (xtalfreq) {
++ case 12000:
++ freq_tgt_target = 0x50D52;
++ break;
++ case 20000:
++ freq_tgt_target = 0x307FE;
++ break;
++ case 26000:
++ freq_tgt_target = 0x254EA;
++ break;
++ case 37400:
++ freq_tgt_target = 0x19EF8;
++ break;
++ case 52000:
++ freq_tgt_target = 0x12A75;
++ break;
++ }
++ break;
++ }
++
++ if (!freq_tgt_target) {
++ bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
++ xtalfreq);
++ return;
++ }
++
++ pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
++ freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
++ BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
++
++ if (freq_tgt_current == freq_tgt_target) {
++ bcma_debug(bus, "Target TGT frequency already set\n");
++ return;
++ }
++
++ /* Turn off PLL */
++ switch (bus->chipinfo.id) {
++ case BCMA_CHIP_ID_BCM43142:
++ mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
++ BCMA_RES_4314_MACPHY_CLK_AVAIL);
++
++ bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
++ bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
++ bcma_wait_value(cc->core, BCMA_CLKCTLST,
++ BCMA_CLKCTLST_HAVEHT, 0, 20000);
++ break;
++ }
++
++ pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
++ pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
++ bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
++
++ /* Flush */
++ if (cc->pmu.rev >= 2)
++ bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
++
++ /* TODO: Do we need to update OTP? */
++}
++
++static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
++{
++ struct bcma_bus *bus = cc->core->bus;
++ u32 xtalfreq = bcma_pmu_xtalfreq(cc);
++
++ switch (bus->chipinfo.id) {
++ case BCMA_CHIP_ID_BCM43142:
++ if (xtalfreq == 0)
++ xtalfreq = 20000;
++ bcma_pmu2_pll_init0(cc, xtalfreq);
++ break;
++ }
++}
++
+ static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
+ {
+ struct bcma_bus *bus = cc->core->bus;
+@@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
+ min_msk = 0x200D;
+ max_msk = 0xFFFF;
+ break;
++ case BCMA_CHIP_ID_BCM43142:
++ min_msk = BCMA_RES_4314_LPLDO_PU |
++ BCMA_RES_4314_PMU_SLEEP_DIS |
++ BCMA_RES_4314_PMU_BG_PU |
++ BCMA_RES_4314_CBUCK_LPOM_PU |
++ BCMA_RES_4314_CBUCK_PFM_PU |
++ BCMA_RES_4314_CLDO_PU |
++ BCMA_RES_4314_LPLDO2_LVM |
++ BCMA_RES_4314_WL_PMU_PU |
++ BCMA_RES_4314_LDO3P3_PU |
++ BCMA_RES_4314_OTP_PU |
++ BCMA_RES_4314_WL_PWRSW_PU |
++ BCMA_RES_4314_LQ_AVAIL |
++ BCMA_RES_4314_LOGIC_RET |
++ BCMA_RES_4314_MEM_SLEEP |
++ BCMA_RES_4314_MACPHY_RET |
++ BCMA_RES_4314_WL_CORE_READY;
++ max_msk = 0x3FFFFFFF;
++ break;
+ default:
+ bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
+ bus->chipinfo.id);
+@@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *cc)
+ bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
+ BCMA_CC_PMU_CTL_NOILPONW);
+
++ bcma_pmu_pll_init(cc);
+ bcma_pmu_resources_init(cc);
+ bcma_pmu_workarounds(cc);
+ }
+diff --git a/drivers/bcma/driver_chipcommon_sflash.c b/drivers/bcma/driver_chipcommon_sflash.c
+index e6ed4fe..4d07cce 100644
+--- a/drivers/bcma/driver_chipcommon_sflash.c
++++ b/drivers/bcma/driver_chipcommon_sflash.c
+@@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
+ u16 numblocks;
+ };
+
+-static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
++static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
+ { "M25P20", 0x11, 0x10000, 4, },
+ { "M25P40", 0x12, 0x10000, 8, },
+
+@@ -41,7 +41,7 @@ static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
+ { 0 },
+ };
+
+-static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
++static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
+ { "SST25WF512", 1, 0x1000, 16, },
+ { "SST25VF512", 0x48, 0x1000, 16, },
+ { "SST25WF010", 2, 0x1000, 32, },
+@@ -59,7 +59,7 @@ static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
+ { 0 },
+ };
+
+-static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
++static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
+ { "AT45DB011", 0xc, 256, 512, },
+ { "AT45DB021", 0x14, 256, 1024, },
+ { "AT45DB041", 0x1c, 256, 2048, },
+@@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc *cc)
+ {
+ struct bcma_bus *bus = cc->core->bus;
+ struct bcma_sflash *sflash = &cc->sflash;
+- struct bcma_sflash_tbl_e *e;
++ const struct bcma_sflash_tbl_e *e;
+ u32 id, id2;
+
+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
+diff --git a/drivers/bcma/host_pci.c b/drivers/bcma/host_pci.c
+index fbf2759..a355e63 100644
+--- a/drivers/bcma/host_pci.c
++++ b/drivers/bcma/host_pci.c
+@@ -275,6 +275,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
+ { 0, },
+ };
+diff --git a/drivers/bcma/main.c b/drivers/bcma/main.c
+index f72f52b..0067422 100644
+--- a/drivers/bcma/main.c
++++ b/drivers/bcma/main.c
+@@ -93,6 +93,25 @@ struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
+ return NULL;
+ }
+
++bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
++ int timeout)
++{
++ unsigned long deadline = jiffies + timeout;
++ u32 val;
++
++ do {
++ val = bcma_read32(core, reg);
++ if ((val & mask) == value)
++ return true;
++ cpu_relax();
++ udelay(10);
++ } while (!time_after_eq(jiffies, deadline));
++
++ bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
++
++ return false;
++}
++
+ static void bcma_release_core_dev(struct device *dev)
+ {
+ struct bcma_device *core = container_of(dev, struct bcma_device, dev);
+diff --git a/drivers/bcma/sprom.c b/drivers/bcma/sprom.c
+index 8934298..72bf454 100644
+--- a/drivers/bcma/sprom.c
++++ b/drivers/bcma/sprom.c
+@@ -72,12 +72,12 @@ fail:
+ * R/W ops.
+ **************************************************/
+
+-static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
++static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
++ size_t words)
+ {
+ int i;
+- for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
+- sprom[i] = bcma_read16(bus->drv_cc.core,
+- offset + (i * 2));
++ for (i = 0; i < words; i++)
++ sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
+ }
+
+ /**************************************************
+@@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 data)
+ return t[crc ^ data];
+ }
+
+-static u8 bcma_sprom_crc(const u16 *sprom)
++static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
+ {
+ int word;
+ u8 crc = 0xFF;
+
+- for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
++ for (word = 0; word < words - 1; word++) {
+ crc = bcma_crc8(crc, sprom[word] & 0x00FF);
+ crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
+ }
+- crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
++ crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
+ crc ^= 0xFF;
+
+ return crc;
+ }
+
+-static int bcma_sprom_check_crc(const u16 *sprom)
++static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
+ {
+ u8 crc;
+ u8 expected_crc;
+ u16 tmp;
+
+- crc = bcma_sprom_crc(sprom);
+- tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
++ crc = bcma_sprom_crc(sprom, words);
++ tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
+ expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
+ if (crc != expected_crc)
+ return -EPROTO;
+@@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u16 *sprom)
+ return 0;
+ }
+
+-static int bcma_sprom_valid(const u16 *sprom)
++static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
++ size_t words)
+ {
+ u16 revision;
+ int err;
+
+- err = bcma_sprom_check_crc(sprom);
++ err = bcma_sprom_check_crc(sprom, words);
+ if (err)
+ return err;
+
+- revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
+- if (revision != 8 && revision != 9) {
++ revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
++ if (revision != 8 && revision != 9 && revision != 10) {
+ pr_err("Unsupported SPROM revision: %d\n", revision);
+ return -ENOENT;
+ }
+
++ bus->sprom.revision = revision;
++ bcma_debug(bus, "Found SPROM revision %d\n", revision);
++
+ return 0;
+ }
+
+@@ -208,9 +212,6 @@ static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
+ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
+ ARRAY_SIZE(bus->sprom.core_pwr_info));
+
+- bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
+- SSB_SPROM_REVISION_REV;
+-
+ for (i = 0; i < 3; i++) {
+ v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
+ *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
+@@ -502,7 +503,7 @@ static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
+ case BCMA_CHIP_ID_BCM4331:
+ present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
+ break;
+-
++ case BCMA_CHIP_ID_BCM43142:
+ case BCMA_CHIP_ID_BCM43224:
+ case BCMA_CHIP_ID_BCM43225:
+ /* for these chips OTP is always available */
+@@ -550,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
+ {
+ u16 offset = BCMA_CC_SPROM;
+ u16 *sprom;
+- int err = 0;
++ size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
++ SSB_SPROMSIZE_WORDS_R10, };
++ int i, err = 0;
+
+ if (!bus->drv_cc.core)
+ return -EOPNOTSUPP;
+@@ -579,32 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
+ }
+ }
+
+- sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
+- GFP_KERNEL);
+- if (!sprom)
+- return -ENOMEM;
+-
+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
+ bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
+ bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
+
+ bcma_debug(bus, "SPROM offset 0x%x\n", offset);
+- bcma_sprom_read(bus, offset, sprom);
++ for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
++ size_t words = sprom_sizes[i];
++
++ sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
++ if (!sprom)
++ return -ENOMEM;
++
++ bcma_sprom_read(bus, offset, sprom, words);
++ err = bcma_sprom_valid(bus, sprom, words);
++ if (!err)
++ break;
++
++ kfree(sprom);
++ }
+
+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
+ bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
+ bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
+
+- err = bcma_sprom_valid(sprom);
+ if (err) {
+- bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
++ bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
+ err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
+- goto out;
++ } else {
++ bcma_sprom_extract_r8(bus, sprom);
++ kfree(sprom);
+ }
+
+- bcma_sprom_extract_r8(bus, sprom);
+-
+-out:
+- kfree(sprom);
+ return err;
+ }
+diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
+index 2e34db8..622fc50 100644
+--- a/include/linux/bcma/bcma.h
++++ b/include/linux/bcma/bcma.h
+@@ -144,6 +144,7 @@ struct bcma_host_ops {
+
+ /* Chip IDs of PCIe devices */
+ #define BCMA_CHIP_ID_BCM4313 0x4313
++#define BCMA_CHIP_ID_BCM43142 43142
+ #define BCMA_CHIP_ID_BCM43224 43224
+ #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
+ #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
+diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
+index b8b09ea..c49e1a1 100644
+--- a/include/linux/bcma/bcma_driver_chipcommon.h
++++ b/include/linux/bcma/bcma_driver_chipcommon.h
+@@ -330,6 +330,8 @@
+ #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
+ #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
+ #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
++#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
++#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
+ #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
+ #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
+ #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
+@@ -355,6 +357,11 @@
+ #define BCMA_CC_REGCTL_DATA 0x065C
+ #define BCMA_CC_PLLCTL_ADDR 0x0660
+ #define BCMA_CC_PLLCTL_DATA 0x0664
++#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
++#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
++#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
++#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
++#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
+ #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
+ /* NAND flash MLC controller registers (corerev >= 38) */
+ #define BCMA_CC_NAND_REVISION 0x0C00
+@@ -435,6 +442,23 @@
+ #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
+ #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
+
++/* PMU rev 15 */
++#define BCMA_CC_PMU15_PLL_PLLCTL0 0
++#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
++#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
++#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
++#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
++#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
++#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
++#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
++#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
++#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
++#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
++#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
++#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
++#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
++#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
++
+ /* ALP clock on pre-PMU chips */
+ #define BCMA_CC_PMU_ALP_CLOCK 20000000
+ /* HT clock for systems with PMU-enabled chipcommon */
+@@ -507,6 +531,37 @@
+ #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
+ #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
+
++#define BCMA_RES_4314_LPLDO_PU BIT(0)
++#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
++#define BCMA_RES_4314_PMU_BG_PU BIT(2)
++#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
++#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
++#define BCMA_RES_4314_CLDO_PU BIT(5)
++#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
++#define BCMA_RES_4314_WL_PMU_PU BIT(7)
++#define BCMA_RES_4314_LNLDO_PU BIT(8)
++#define BCMA_RES_4314_LDO3P3_PU BIT(9)
++#define BCMA_RES_4314_OTP_PU BIT(10)
++#define BCMA_RES_4314_XTAL_PU BIT(11)
++#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
++#define BCMA_RES_4314_LQ_AVAIL BIT(13)
++#define BCMA_RES_4314_LOGIC_RET BIT(14)
++#define BCMA_RES_4314_MEM_SLEEP BIT(15)
++#define BCMA_RES_4314_MACPHY_RET BIT(16)
++#define BCMA_RES_4314_WL_CORE_READY BIT(17)
++#define BCMA_RES_4314_ILP_REQ BIT(18)
++#define BCMA_RES_4314_ALP_AVAIL BIT(19)
++#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
++#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
++#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
++#define BCMA_RES_4314_RADIO_PU BIT(23)
++#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
++#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
++#define BCMA_RES_4314_RX_LDO_PU BIT(26)
++#define BCMA_RES_4314_TX_LDO_PU BIT(27)
++#define BCMA_RES_4314_HT_AVAIL BIT(28)
++#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
++
+ /* Data for the PMU, if available.
+ * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
+ */
generated by cgit v1.1 at 2024-12-29 00:50:06 +0000