diff options
Diffstat (limited to 'target/linux/imx6/patches-3.14/0060-pci_imx6_fix-link-failure.patch')
| -rw-r--r-- | target/linux/imx6/patches-3.14/0060-pci_imx6_fix-link-failure.patch | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/target/linux/imx6/patches-3.14/0060-pci_imx6_fix-link-failure.patch b/target/linux/imx6/patches-3.14/0060-pci_imx6_fix-link-failure.patch deleted file mode 100644 index e416d83..0000000 --- a/target/linux/imx6/patches-3.14/0060-pci_imx6_fix-link-failure.patch +++ /dev/null @@ -1,38 +0,0 @@ -PCI: imx6: fix occasional link failure - -According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable -for SS function) must remain deasserted until the reference clock is running -at the appropriate frequency. - -Without this patch we find a high link failure rate (>5%) on certain -IMX6 boards at various temperatures. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> - ---- a/drivers/pci/host/pci-imx6.c -+++ b/drivers/pci/host/pci-imx6.c -@@ -262,11 +262,6 @@ static int imx6_pcie_deassert_core_reset - if (gpio_is_valid(imx6_pcie->power_on_gpio)) - gpio_set_value(imx6_pcie->power_on_gpio, 1); - -- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, -- IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); -- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, -- IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); -- - ret = clk_prepare_enable(imx6_pcie->sata_ref_100m); - if (ret) { - dev_err(pp->dev, "unable to enable sata_ref_100m\n"); -@@ -294,6 +289,12 @@ static int imx6_pcie_deassert_core_reset - /* allow the clocks to stabilize */ - usleep_range(200, 500); - -+ /* power up core phy and enable ref clock */ -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, -+ IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, -+ IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); -+ - /* Some boards don't have PCIe reset GPIO. */ - if (gpio_is_valid(imx6_pcie->reset_gpio)) { - gpio_set_value(imx6_pcie->reset_gpio, 0); |