diff options
Diffstat (limited to 'target/linux/imx6/patches-3.18')
6 files changed, 337 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-3.18/100-bootargs.patch b/target/linux/imx6/patches-3.18/100-bootargs.patch new file mode 100644 index 0000000..0954391 --- /dev/null +++ b/target/linux/imx6/patches-3.18/100-bootargs.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/imx6dl-wandboard.dts ++++ b/arch/arm/boot/dts/imx6dl-wandboard.dts +@@ -19,4 +19,8 @@ + memory { + reg = <0x10000000 0x40000000>; + }; ++ ++ chosen { ++ bootargs = "console=ttymxc0,115200"; ++ }; + }; diff --git a/target/linux/imx6/patches-3.18/200-pci_designware_add-ability-for-custom-swizzle.patch b/target/linux/imx6/patches-3.18/200-pci_designware_add-ability-for-custom-swizzle.patch new file mode 100644 index 0000000..38e5123 --- /dev/null +++ b/target/linux/imx6/patches-3.18/200-pci_designware_add-ability-for-custom-swizzle.patch @@ -0,0 +1,33 @@ +commit e84634dc6c7f3f6af9b8ef1fb36f0d85c476ab95 +Author: Tim Harvey <tharvey@gateworks.com> +Date: Thu Feb 27 01:02:23 2014 -0800 + + PCI: designware: add ability for custom swizzle + + Add the ability for a platform driver to provide a platform-specific + swizzle function. + + Signed-off-by: Tim Harvey <tharvey@gateworks.com> + +--- a/drivers/pci/host/pcie-designware.c ++++ b/drivers/pci/host/pcie-designware.c +@@ -492,6 +492,9 @@ int __init dw_pcie_host_init(struct pcie + if (pp->ops->host_init) + pp->ops->host_init(pp); + ++ if (pp->swizzle) ++ dw_pci.swizzle = pp->swizzle; ++ + dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); + + /* program correct class for RC */ +--- a/drivers/pci/host/pcie-designware.h ++++ b/drivers/pci/host/pcie-designware.h +@@ -53,6 +53,7 @@ struct pcie_port { + struct irq_domain *irq_domain; + unsigned long msi_data; + DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); ++ u8 (*swizzle)(struct pci_dev *, u8 *); + }; + + struct pcie_host_ops { diff --git a/target/linux/imx6/patches-3.18/201-pci_imx6_ventana_fixup-for-IRQ-mismapping.patch b/target/linux/imx6/patches-3.18/201-pci_imx6_ventana_fixup-for-IRQ-mismapping.patch new file mode 100644 index 0000000..4db1569 --- /dev/null +++ b/target/linux/imx6/patches-3.18/201-pci_imx6_ventana_fixup-for-IRQ-mismapping.patch @@ -0,0 +1,81 @@ +commit 2c0d0491438433a1f327f2e754c7b6b55fec51c4 +Author: Tim Harvey <tharvey@gateworks.com> +Date: Thu Feb 27 00:59:53 2014 -0800 + + PCI: imx6: ventana: fixup for IRQ mismapping + + The TI XIO2001 PCIe-to-PCI bridge used on several Ventana expansion boards + has its slot-to-bridge IRQ mapping reversed from the PCI specification: + + INTA->INTD + INTB->INTC + INTC->INTB + INTD->INTA + + Implement a custom swizzle function that does a fixup on the interrupt for + devices on a TI XIO2001 bridge. + + Signed-off-by: Tim Harvey <tharvey@gateworks.com> + +--- a/drivers/pci/host/pci-imx6.c ++++ b/drivers/pci/host/pci-imx6.c +@@ -553,6 +553,39 @@ static int __init imx6_add_pcie_port(str + return 0; + } + ++/* TI XIO2001 PCIe-to-PCI bridge on GW16082 exp card has IRQs reversed */ ++u8 ventana_swizzle(struct pci_dev *dev, u8 *pin) ++{ ++ u8 i = 0; ++ struct pci_dev *pdev = dev; ++ ++ /* count number of TI XIO2001 bridges on bus */ ++ while (!pci_is_root_bus(pdev->bus)) { ++ if (pdev->bus && pdev->bus->self && ++ (pdev->bus->self->vendor == PCI_VENDOR_ID_TI) && ++ (pdev->bus->self->device == PCI_DEVICE_ID_TI_XIO2001)) { ++ i++; ++ } ++ pdev = pdev->bus->self; ++ } ++ while (!pci_is_root_bus(dev->bus)) { ++ /* if we are directly downstream from 1st TI XIO2001 bridge */ ++ if (dev->bus && dev->bus->self && ++ (dev->bus->self->vendor == PCI_VENDOR_ID_TI) && ++ (dev->bus->self->device == PCI_DEVICE_ID_TI_XIO2001)) { ++ if (--i == 0) { ++ /* swap IRQs and swizzle backwards */ ++ *pin = (15 - PCI_SLOT(dev->devfn)) + 1; ++ dev = dev->bus->self; ++ continue; ++ } ++ } ++ *pin = pci_swizzle_interrupt_pin(dev, *pin); ++ dev = dev->bus->self; ++ } ++ return PCI_SLOT(dev->devfn); ++} ++ + static int __init imx6_pcie_probe(struct platform_device *pdev) + { + struct imx6_pcie *imx6_pcie; +@@ -618,6 +651,9 @@ static int __init imx6_pcie_probe(struct + return PTR_ERR(imx6_pcie->iomuxc_gpr); + } + ++ if (of_machine_is_compatible("gw,ventana")) ++ pp->swizzle = ventana_swizzle; ++ + ret = imx6_add_pcie_port(pp, pdev); + if (ret < 0) + return ret; +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -827,6 +827,7 @@ + #define PCI_DEVICE_ID_TI_XX12 0x8039 + #define PCI_DEVICE_ID_TI_XX12_FM 0x803b + #define PCI_DEVICE_ID_TI_XIO2000A 0x8231 ++#define PCI_DEVICE_ID_TI_XIO2001 0x8240 + #define PCI_DEVICE_ID_TI_1130 0xac12 + #define PCI_DEVICE_ID_TI_1031 0xac13 + #define PCI_DEVICE_ID_TI_1131 0xac15 diff --git a/target/linux/imx6/patches-3.18/202-net-igb-add-i210-i211-support-for-phy-read-write.patch b/target/linux/imx6/patches-3.18/202-net-igb-add-i210-i211-support-for-phy-read-write.patch new file mode 100644 index 0000000..fb4b722 --- /dev/null +++ b/target/linux/imx6/patches-3.18/202-net-igb-add-i210-i211-support-for-phy-read-write.patch @@ -0,0 +1,129 @@ +Author: Tim Harvey <tharvey@gateworks.com> +Date: Thu May 15 00:12:26 2014 -0700 + + net: igb: add i210/i211 support for phy read/write + + The i210/i211 uses the MDICNFG register for the phy address instead of the + MDIC register. + + Signed-off-by: Tim Harvey <tharvey@gateworks.com> + +--- a/drivers/net/ethernet/intel/igb/e1000_phy.c ++++ b/drivers/net/ethernet/intel/igb/e1000_phy.c +@@ -135,7 +135,7 @@ out: + s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) + { + struct e1000_phy_info *phy = &hw->phy; +- u32 i, mdic = 0; ++ u32 i, mdicnfg, mdic = 0; + s32 ret_val = 0; + + if (offset > MAX_PHY_REG_ADDRESS) { +@@ -148,11 +148,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h + * Control register. The MAC will take care of interfacing with the + * PHY to retrieve the desired data. + */ +- mdic = ((offset << E1000_MDIC_REG_SHIFT) | +- (phy->addr << E1000_MDIC_PHY_SHIFT) | +- (E1000_MDIC_OP_READ)); ++ switch (hw->mac.type) { ++ case e1000_i210: ++ case e1000_i211: ++ mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); ++ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); ++ wr32(E1000_MDICNFG, mdicnfg); ++ mdic = ((offset << E1000_MDIC_REG_SHIFT) | ++ (E1000_MDIC_OP_READ)); ++ break; ++ default: ++ mdic = ((offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_READ)); ++ break; ++ } + + wr32(E1000_MDIC, mdic); ++ wrfl(); + + /* Poll the ready bit to see if the MDI read completed + * Increasing the time out as testing showed failures with +@@ -177,6 +191,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h + *data = (u16) mdic; + + out: ++ switch (hw->mac.type) { ++ /* restore MDICNFG to have phy's addr */ ++ case e1000_i210: ++ case e1000_i211: ++ mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); ++ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); ++ wr32(E1000_MDICNFG, mdicnfg); ++ break; ++ default: ++ break; ++ } + return ret_val; + } + +@@ -191,7 +217,7 @@ out: + s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) + { + struct e1000_phy_info *phy = &hw->phy; +- u32 i, mdic = 0; ++ u32 i, mdicnfg, mdic = 0; + s32 ret_val = 0; + + if (offset > MAX_PHY_REG_ADDRESS) { +@@ -204,12 +230,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_ + * Control register. The MAC will take care of interfacing with the + * PHY to retrieve the desired data. + */ +- mdic = (((u32)data) | +- (offset << E1000_MDIC_REG_SHIFT) | +- (phy->addr << E1000_MDIC_PHY_SHIFT) | +- (E1000_MDIC_OP_WRITE)); ++ switch (hw->mac.type) { ++ case e1000_i210: ++ case e1000_i211: ++ mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); ++ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); ++ wr32(E1000_MDICNFG, mdicnfg); ++ mdic = (((u32)data) | ++ (offset << E1000_MDIC_REG_SHIFT) | ++ (E1000_MDIC_OP_WRITE)); ++ break; ++ default: ++ mdic = (((u32)data) | ++ (offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_WRITE)); ++ break; ++ } + + wr32(E1000_MDIC, mdic); ++ wrfl(); + + /* Poll the ready bit to see if the MDI read completed + * Increasing the time out as testing showed failures with +@@ -233,6 +274,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_ + } + + out: ++ switch (hw->mac.type) { ++ /* restore MDICNFG to have phy's addr */ ++ case e1000_i210: ++ case e1000_i211: ++ mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); ++ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); ++ wr32(E1000_MDICNFG, mdicnfg); ++ break; ++ default: ++ break; ++ } + return ret_val; + } + diff --git a/target/linux/imx6/patches-3.18/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch b/target/linux/imx6/patches-3.18/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch new file mode 100644 index 0000000..e991fad --- /dev/null +++ b/target/linux/imx6/patches-3.18/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch @@ -0,0 +1,27 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -292,6 +292,14 @@ endif # RTL8366_SMI + + source "drivers/net/phy/b53/Kconfig" + ++config GATEWORKS_GW16083 ++ tristate "Gateworks GW16083 Ethernet Expansion Mezzanine" ++ ---help--- ++ The Gateworks GW16083 Ethernet Expansion Mezzanine connects to a ++ Gateworks Ventana baseboard and provides a 7-port GbE managed ++ Ethernet switch with 4 dedicated GbE RJ45 ports, and 2 Gbe/SFP ++ ports" ++ + endif # PHYLIB + + config MICREL_KS8995MA +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -40,6 +40,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o + obj-$(CONFIG_DP83640_PHY) += dp83640.o + obj-$(CONFIG_STE10XP) += ste10Xp.o + obj-$(CONFIG_MICREL_PHY) += micrel.o ++obj-$(CONFIG_GATEWORKS_GW16083) += gw16083.o + obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o + obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o + obj-$(CONFIG_AT803X_PHY) += at803x.o diff --git a/target/linux/imx6/patches-3.18/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch b/target/linux/imx6/patches-3.18/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch new file mode 100644 index 0000000..6f31f95 --- /dev/null +++ b/target/linux/imx6/patches-3.18/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch @@ -0,0 +1,56 @@ +--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +@@ -89,6 +89,11 @@ + enable-active-high; + }; + }; ++ ++ gw16083: gw16083@52 { ++ compatible = "gateworks,gw16083"; ++ reg = <0x52>; ++ }; + }; + + &fec { +--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +@@ -266,6 +266,11 @@ + }; + }; + }; ++ ++ gw16083: gw16083@52 { ++ compatible = "gateworks,gw16083"; ++ reg = <0x52>; ++ }; + }; + + &pcie { +--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +@@ -267,6 +267,11 @@ + }; + }; + }; ++ ++ gw16083: gw16083@52 { ++ compatible = "gateworks,gw16083"; ++ reg = <0x52>; ++ }; + }; + + &pcie { +--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +@@ -308,6 +308,11 @@ + }; + }; + }; ++ ++ gw16083: gw16083@52 { ++ compatible = "gateworks,gw16083"; ++ reg = <0x52>; ++ }; + }; + + &i2c3 { |