diff options
Diffstat (limited to 'target/linux/mediatek/patches/0073-clk.patch')
| -rw-r--r-- | target/linux/mediatek/patches/0073-clk.patch | 200 |
1 files changed, 200 insertions, 0 deletions
diff --git a/target/linux/mediatek/patches/0073-clk.patch b/target/linux/mediatek/patches/0073-clk.patch new file mode 100644 index 0000000..a3b36a5 --- /dev/null +++ b/target/linux/mediatek/patches/0073-clk.patch @@ -0,0 +1,200 @@ +From a4df453fbfa6199ad33435cee6ce2dfcc65321b0 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Fri, 3 Jul 2015 05:45:58 +0200 +Subject: [PATCH 73/76] clk + +--- + include/dt-bindings/clock/mt7623-clk.h | 158 +++++++++++++++----------------- + 1 file changed, 73 insertions(+), 85 deletions(-) + +diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h +index cb1e8a9..410ef31 100644 +--- a/include/dt-bindings/clock/mt7623-clk.h ++++ b/include/dt-bindings/clock/mt7623-clk.h +@@ -17,96 +17,76 @@ + + /* TOPCKGEN */ + +-#define CLK_TOP_AUDPLL_24 1 +-#define CLK_TOP_AUDPLL_D16 2 +-#define CLK_TOP_AUDPLL_D4 3 +-#define CLK_TOP_AUDPLL_D8 4 +-#define CLK_TOP_CLKPH_MCK 5 +-#define CLK_TOP_CPUM_TCK_IN 6 +-#define CLK_TOP_DSI0_LNTC_DSICLK 7 +-#define CLK_TOP_HDMITX_CLKDIG_CTS 8 +-#define CLK_TOP_LVDS_ETH 9 +-#define CLK_TOP_LVDSPLL_D2 10 +-#define CLK_TOP_LVDSPLL_D4 11 +-#define CLK_TOP_LVDSPLL_D8 12 +-#define CLK_TOP_MAINPLL_230P3M 13 +-#define CLK_TOP_MAINPLL_322P4M 14 +-#define CLK_TOP_MAINPLL_537P3M 15 +-#define CLK_TOP_MAINPLL_806M 16 +-#define CLK_TOP_MEMPLL_MCK_D4 17 +-#define CLK_TOP_MMPLL_D2 18 +-#define CLK_TOP_MSDCPLL_D2 19 +-#define CLK_TOP_SYSPLL1_D16 20 +-#define CLK_TOP_SYSPLL1_D2 21 +-#define CLK_TOP_SYSPLL1_D4 22 +-#define CLK_TOP_SYSPLL1_D8 23 +-#define CLK_TOP_SYSPLL2_D2 24 +-#define CLK_TOP_SYSPLL2_D4 25 +-#define CLK_TOP_SYSPLL2_D8 26 +-#define CLK_TOP_SYSPLL3_D2 27 +-#define CLK_TOP_SYSPLL3_D4 28 +-#define CLK_TOP_SYSPLL4_D2 29 +-#define CLK_TOP_SYSPLL4_D4 30 +-#define CLK_TOP_SYSPLL_D3 31 +-#define CLK_TOP_SYSPLL_D5 32 +-#define CLK_TOP_SYSPLL_D7 33 +-#define CLK_TOP_TVDPLL_d2 34 +-#define CLK_TOP_TVDPLL_D4 35 +-#define CLK_TOP_UNIVPLL_178P3M 36 +-#define CLK_TOP_UNIVPLL1_D10 37 +-#define CLK_TOP_UNIVPLL1_D2 38 +-#define CLK_TOP_UNIVPLL1_D4 39 +-#define CLK_TOP_UNIVPLL1_D6 40 +-#define CLK_TOP_UNIVPLL1_D8 41 +-#define CLK_TOP_UNIVPLL_249P6M 42 +-#define CLK_TOP_UNIVPLL2_D2 43 +-#define CLK_TOP_UNIVPLL2_D4 44 +-#define CLK_TOP_UNIVPLL2_D6 45 +-#define CLK_TOP_UNIVPLL2_D8 46 +-#define CLK_TOP_UNIVPLL_416M 47 +-#define CLK_TOP_UNIVPLL_48M 48 +-#define CLK_TOP_UNIVPLL_624M 49 +-#define CLK_TOP_UNIVPLL_D26 50 +-#define CLK_TOP_UNIVPLL_D5 51 +-#define CLK_TOP_APLL_SEL 52 ++#define CLK_TOP_MAINPLL_650M 1 ++#define CLK_TOP_MAINPLL_433P3M 2 ++#define CLK_TOP_MAINPLL_260M 3 ++#define CLK_TOP_MAINPLL_185P6M 4 ++#define CLK_TOP_UNIVPLL_624M 5 ++#define CLK_TOP_UNIVPLL_416M 6 ++#define CLK_TOP_UNIVPLL_249P6M 7 ++#define CLK_TOP_UNIVPLL_178P3M 8 ++#define CLK_TOP_UNIVPLL_48M 9 ++#define CLK_TOP_AUDPLL_D4 10 ++#define CLK_TOP_AUDPLL_D8 11 ++#define CLK_TOP_AUDPLL_D16 12 ++#define CLK_TOP_AUDPLL_24 13 ++#define CLK_TOP_MSDCPLL_D2 14 ++#define CLK_TOP_SYSPLL1_D2 15 ++#define CLK_TOP_SYSPLL1_D4 16 ++#define CLK_TOP_SYSPLL1_D8 17 ++#define CLK_TOP_SYSPLL1_D16 18 ++#define CLK_TOP_SYSPLL2_D2 19 ++#define CLK_TOP_SYSPLL2_D4 20 ++#define CLK_TOP_SYSPLL2_D8 21 ++#define CLK_TOP_SYSPLL3_D2 22 ++#define CLK_TOP_SYSPLL3_D4 23 ++#define CLK_TOP_SYSPLL4_D2 24 ++#define CLK_TOP_SYSPLL4_D4 25 ++#define CLK_TOP_SYSPLL_D3 26 ++#define CLK_TOP_SYSPLL_D5 27 ++#define CLK_TOP_SYSPLL_D7 28 ++#define CLK_TOP_UNIVPLL1_D2 29 ++#define CLK_TOP_UNIVPLL1_D4 30 ++#define CLK_TOP_UNIVPLL1_D6 31 ++#define CLK_TOP_UNIVPLL1_D8 32 ++#define CLK_TOP_UNIVPLL1_D10 33 ++#define CLK_TOP_UNIVPLL2_D2 34 ++#define CLK_TOP_UNIVPLL2_D4 35 ++#define CLK_TOP_UNIVPLL2_D6 36 ++#define CLK_TOP_UNIVPLL2_D8 37 ++#define CLK_TOP_UNIVPLL_D5 38 ++#define CLK_TOP_UNIVPLL_D26 39 ++#define CLK_TOP_AXI_SEL 40 ++#define CLK_TOP_MEM_SEL 41 ++#define CLK_TOP_DDR_SEL 42 ++#define CLK_TOP_MM_SEL 43 ++#define CLK_TOP_PWM_SEL 44 ++#define CLK_TOP_MFG_SEL 45 ++#define CLK_TOP_UART_SEL 46 ++#define CLK_TOP_SPI_SEL 47 ++#define CLK_TOP_USB20_SEL 48 ++#define CLK_TOP_MSDC30_0_SEL 49 ++#define CLK_TOP_MSDC30_1_SEL 50 ++#define CLK_TOP_MSDC30_2_SEL 51 ++#define CLK_TOP_AUDIO_SEL 52 + #define CLK_TOP_AUDIO_INTBUS_SEL 53 +-#define CLK_TOP_AUDIO_SEL 54 +-#define CLK_TOP_AXI_SEL 55 +-#define CLK_TOP_CAM_SEL 56 +-#define CLK_TOP_DDR_SEL 57 +-#define CLK_TOP_DPI0_SEL 58 +-#define CLK_TOP_DPI1_SEL 59 +-#define CLK_TOP_DPILVDS_SEL 60 +-#define CLK_TOP_ETH_SEL 61 +-#define CLK_TOP_MEM_SEL 62 +-#define CLK_TOP_MFG_SEL 63 +-#define CLK_TOP_MM_SEL 64 +-#define CLK_TOP_MSDC30_0_SEL 65 +-#define CLK_TOP_MSDC30_1_SEL 66 +-#define CLK_TOP_MSDC30_2_SEL 67 +-#define CLK_TOP_NFI2X_SEL 68 +-#define CLK_TOP_PMICSPI_SEL 69 +-#define CLK_TOP_PWM_SEL 70 +-#define CLK_TOP_RTC_SEL 71 +-#define CLK_TOP_SCP_SEL 72 +-#define CLK_TOP_SPI_SEL 73 +-#define CLK_TOP_TVE_SEL 74 +-#define CLK_TOP_UART_SEL 75 +-#define CLK_TOP_USB20_SEL 76 +-#define CLK_TOP_VDEC_SEL 77 +-#define CLK_TOP_NR_CLK 78 ++#define CLK_TOP_PMICSPI_SEL 54 ++#define CLK_TOP_SCP_SEL 55 ++#define CLK_TOP_APLL_SEL 56 ++#define CLK_TOP_RTC_SEL 57 ++#define CLK_TOP_NFI2X_SEL 58 ++#define CLK_TOP_ETH_SEL 59 ++#define CLK_TOP_NR_CLK 60 + + /* APMIXED_SYS */ + + #define CLK_APMIXED_ARMPLL 1 + #define CLK_APMIXED_MAINPLL 2 +-#define CLK_APMIXED_MSDCPLL 3 +-#define CLK_APMIXED_UNIVPLL 4 +-#define CLK_APMIXED_MMPLL 5 +-#define CLK_APMIXED_VENCPLL 6 +-#define CLK_APMIXED_TVDPLL 7 +-#define CLK_APMIXED_LVDSPLL 8 +-#define CLK_APMIXED_AUDPLL 9 ++#define CLK_APMIXED_UNIVPLL 3 ++#define CLK_APMIXED_MSDCPLL 4 ++#define CLK_APMIXED_AUDPLL 5 ++#define CLK_APMIXED_TRGPLL 6 ++#define CLK_APMIXED_ETHPLL 7 + + /* INFRA_SYS */ + +@@ -124,7 +104,8 @@ + #define CLK_INFRA_IRRX 19 + #define CLK_INFRA_PMICSPI 22 + #define CLK_INFRA_PMIC_WRAP 23 +-#define CLK_INFRA_NR_CLK 24 ++#define CLK_INFRA_CA7SEL 24 ++#define CLK_INFRA_NR_CLK 25 + + /* PERI_SYS */ + +@@ -169,5 +150,12 @@ + #define CLK_PERI_UART3_SEL 38 + #define CLK_PERI_NR_CLK 39 + ++#define CLK_HIFSYS_USB0_PHY 1 ++#define CLK_HIFSYS_USB1_PHY 2 ++#define CLK_HIFSYS_PCIE0 3 ++#define CLK_HIFSYS_PCIE1 4 ++#define CLK_HIFSYS_PCIE2 5 ++#define CLK_HIFSYS_NR_CLK 6 ++ + #endif /* _DT_BINDINGS_CLK_MT7623_H */ + +-- +1.7.10.4 + |