diff options
Diffstat (limited to 'target/linux/mvebu/patches-3.10/0157-mtd-nand-pxa3xx-Consolidate-ECC-initialization.patch')
| -rw-r--r-- | target/linux/mvebu/patches-3.10/0157-mtd-nand-pxa3xx-Consolidate-ECC-initialization.patch | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-3.10/0157-mtd-nand-pxa3xx-Consolidate-ECC-initialization.patch b/target/linux/mvebu/patches-3.10/0157-mtd-nand-pxa3xx-Consolidate-ECC-initialization.patch new file mode 100644 index 0000000..28ec7d8 --- /dev/null +++ b/target/linux/mvebu/patches-3.10/0157-mtd-nand-pxa3xx-Consolidate-ECC-initialization.patch @@ -0,0 +1,100 @@ +From 70c36de37f357f38b5a56292534133d75e7d8870 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> +Date: Mon, 25 Nov 2013 12:36:18 -0300 +Subject: [PATCH 157/203] mtd: nand: pxa3xx: Consolidate ECC initialization + +In order to avoid code duplication, let's consolidate the ECC setting +for all SoC variants. Such decision is based on page size and ECC +strength requirements. + +Also, provide a default value for the case where such ECC information +is not provided (non-ONFI devices). + +Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> +--- + drivers/mtd/nand/pxa3xx_nand.c | 40 ++++++++++++++++------------------------ + 1 file changed, 16 insertions(+), 24 deletions(-) + +--- a/drivers/mtd/nand/pxa3xx_nand.c ++++ b/drivers/mtd/nand/pxa3xx_nand.c +@@ -1335,13 +1335,9 @@ static int pxa3xx_nand_sensing(struct px + + static int pxa_ecc_init(struct pxa3xx_nand_info *info, + struct nand_ecc_ctrl *ecc, +- int strength, int page_size) ++ int strength, int ecc_stepsize, int page_size) + { +- /* +- * We don't use strength here as the PXA variant +- * is used with non-ONFI compliant devices. +- */ +- if (page_size == 2048) { ++ if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) { + info->chunk_size = 2048; + info->spare_size = 40; + info->ecc_size = 24; +@@ -1350,7 +1346,7 @@ static int pxa_ecc_init(struct pxa3xx_na + ecc->strength = 1; + return 1; + +- } else if (page_size == 512) { ++ } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) { + info->chunk_size = 512; + info->spare_size = 8; + info->ecc_size = 8; +@@ -1358,19 +1354,12 @@ static int pxa_ecc_init(struct pxa3xx_na + ecc->size = 512; + ecc->strength = 1; + return 1; +- } +- return 0; +-} + +-static int armada370_ecc_init(struct pxa3xx_nand_info *info, +- struct nand_ecc_ctrl *ecc, +- int strength, int ecc_stepsize, int page_size) +-{ + /* + * Required ECC: 4-bit correction per 512 bytes + * Select: 16-bit correction per 2048 bytes + */ +- if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) { ++ } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) { + info->ecc_bch = 1; + info->chunk_size = 2048; + info->spare_size = 32; +@@ -1411,6 +1400,7 @@ static int pxa3xx_nand_scan(struct mtd_i + uint32_t id = -1; + uint64_t chipsize; + int i, ret, num; ++ uint16_t ecc_strength, ecc_step; + + if (pdata->keep_config && !pxa3xx_nand_detect_config(info)) + goto KEEP_CONFIG; +@@ -1505,15 +1495,17 @@ KEEP_CONFIG: + } + } + +- if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) +- ret = armada370_ecc_init(info, &chip->ecc, +- chip->ecc_strength_ds, +- chip->ecc_step_ds, +- mtd->writesize); +- else +- ret = pxa_ecc_init(info, &chip->ecc, +- chip->ecc_strength_ds, +- mtd->writesize); ++ ecc_strength = chip->ecc_strength_ds; ++ ecc_step = chip->ecc_step_ds; ++ ++ /* Set default ECC strength requirements on non-ONFI devices */ ++ if (ecc_strength < 1 && ecc_step < 1) { ++ ecc_strength = 1; ++ ecc_step = 512; ++ } ++ ++ ret = pxa_ecc_init(info, &chip->ecc, ecc_strength, ++ ecc_step, mtd->writesize); + if (!ret) { + dev_err(&info->pdev->dev, + "ECC strength %d at page size %d is not supported\n", |