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-rw-r--r--target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch34
1 files changed, 34 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch b/target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch
new file mode 100644
index 0000000..3c4a111
--- /dev/null
+++ b/target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch
@@ -0,0 +1,34 @@
+From 7eb1f09ec8e25aa2fc3f6fc5fc9405d9f917d503 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Thu, 11 Dec 2014 14:14:58 +0100
+Subject: [PATCH 1/2] ARM: mvebu: A385-AP: Enable the NAND controller
+
+The A385 AP has a 1GB NAND chip. Enable it.
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ arch/arm/boot/dts/armada-385-db-ap.dts | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/arch/arm/boot/dts/armada-385-db-ap.dts
++++ b/arch/arm/boot/dts/armada-385-db-ap.dts
+@@ -150,6 +150,19 @@
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
++
++ nfc: flash@d0000 {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ num-cs = <1>;
++ nand-ecc-strength = <4>;
++ nand-ecc-step-size = <512>;
++ marvell,nand-keep-config;
++ marvell,nand-enable-arbiter;
++ nand-on-flash-bbt;
++ };
+ };
+
+ pcie-controller {