diff options
Diffstat (limited to 'target/linux/omap35xx')
34 files changed, 0 insertions, 35336 deletions
diff --git a/target/linux/omap35xx/Makefile b/target/linux/omap35xx/Makefile deleted file mode 100644 index aecbd28..0000000 --- a/target/linux/omap35xx/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright (C) 2006-2011 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=arm -BOARD:=omap35xx -BOARDNAME:=TI OMAP35xx -FEATURES:=ubifs targz broken -SUBTARGETS=beagleboard gumstix - -LINUX_VERSION:=2.6.32.33 -KERNELNAME:="uImage" - -DEVICE_TYPE=developerboard - -define Target/Description - omap35xx arm -endef - -include $(INCLUDE_DIR)/target.mk - -$(eval $(call BuildTarget)) diff --git a/target/linux/omap35xx/beagleboard/base-files/etc/config/network b/target/linux/omap35xx/beagleboard/base-files/etc/config/network deleted file mode 100644 index 2ea5a4b..0000000 --- a/target/linux/omap35xx/beagleboard/base-files/etc/config/network +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (C) 2006 OpenWrt.org - -config interface loopback - option ifname lo - option proto static - option ipaddr 127.0.0.1 - option netmask 255.0.0.0 - -config interface lan - option ifname usb0 - option type bridge - option proto static - option ipaddr 192.168.1.1 - option netmask 255.255.255.0 diff --git a/target/linux/omap35xx/beagleboard/base-files/etc/inittab b/target/linux/omap35xx/beagleboard/base-files/etc/inittab deleted file mode 100644 index 88567b2..0000000 --- a/target/linux/omap35xx/beagleboard/base-files/etc/inittab +++ /dev/null @@ -1,7 +0,0 @@ -::sysinit:/etc/init.d/rcS S boot -::shutdown:/etc/init.d/rcS K shutdown -tts/0::askfirst:/bin/ash --login -ttyS0::askfirst:/bin/ash --login -ttyS1::askfirst:/bin/ash --login -ttyS2::askfirst:/bin/ash --login -tty1::askfirst:/bin/ash --login diff --git a/target/linux/omap35xx/beagleboard/profiles/beagleboard.mk b/target/linux/omap35xx/beagleboard/profiles/beagleboard.mk deleted file mode 100644 index 59c40f4..0000000 --- a/target/linux/omap35xx/beagleboard/profiles/beagleboard.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (C) 2006-2010 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Beagleboard - NAME:=beagleboard - FEATURES:=ext4 usb -endef - -define Profile/Beagleboard/Description - Beagleboard - www.beagleboard.org -endef -$(eval $(call Profile,Beagleboard)) diff --git a/target/linux/omap35xx/beagleboard/target.mk b/target/linux/omap35xx/beagleboard/target.mk deleted file mode 100644 index 4716d47..0000000 --- a/target/linux/omap35xx/beagleboard/target.mk +++ /dev/null @@ -1,6 +0,0 @@ -BOARDNAME:=Beagleboard - -define Target/Description - Build firmware images for Beagleboard -endef - diff --git a/target/linux/omap35xx/config-2.6.32 b/target/linux/omap35xx/config-2.6.32 deleted file mode 100644 index 717949a..0000000 --- a/target/linux/omap35xx/config-2.6.32 +++ /dev/null @@ -1,1573 +0,0 @@ -# CONFIG_AB3100_CORE is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_ACORN_PARTITION is not set -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_AF_RXRPC is not set -CONFIG_AIO=y -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ANDROID is not set -CONFIG_ANON_INODES=y -# CONFIG_APM_EMULATION is not set -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_H720X is not set -CONFIG_ARCH_HAS_CPUFREQ=y -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_NS9XXX is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -CONFIG_ARCH_OMAP3430=y -CONFIG_ARCH_OMAP34XX=y -# CONFIG_ARCH_OMAP4 is not set -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_REALVIEW is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_STMP3XXX is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_W90X900 is not set -CONFIG_ARM=y -# CONFIG_ARM_ERRATA_430973 is not set -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -# CONFIG_ARM_UNWIND is not set -# CONFIG_ARPD is not set -# CONFIG_ASUS_OLED is not set -# CONFIG_ATA is not set -# CONFIG_ATALK is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_ATM is not set -# CONFIG_AUDIT is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUXDISPLAY is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_BACKTRACE_SELF_TEST is not set -CONFIG_BASE_FULL=y -CONFIG_BASE_SMALL=0 -# CONFIG_BATTERY_BQ27x00 is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_MAX17040 is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_BINARY_PRINTF is not set -# CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_ELF=y -CONFIG_BINFMT_MISC=y -CONFIG_BITREVERSE=y -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -CONFIG_BLK_DEV_INITRD=y -# CONFIG_BLK_DEV_INTEGRITY is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_BLK_DEV_SD=y -# CONFIG_BLK_DEV_SR is not set -# CONFIG_BLK_DEV_UB is not set -# CONFIG_BLK_DEV_XIP is not set -CONFIG_BLOCK=y -# CONFIG_BONDING is not set -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_BRIDGE is not set -CONFIG_BROKEN_ON_SMP=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_BT is not set -# CONFIG_BTRFS_FS is not set -CONFIG_BUG=y -# CONFIG_CAN is not set -# CONFIG_CBUS is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_CFG80211 is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -# CONFIG_CGROUPS is not set -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_ST is not set -CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -# CONFIG_COMEDI is not set -CONFIG_COMMON_CLKDEV=y -CONFIG_COMPAT_BRK=y -# CONFIG_CONFIGFS_FS is not set -# CONFIG_CONNECTOR is not set -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONSTRUCTORS=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_FREQ is not set -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_IDLE is not set -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -# CONFIG_CRAMFS is not set -CONFIG_CRC32=y -CONFIG_CRC7=y -CONFIG_CRC_CCITT=y -CONFIG_CRC_ITU_T=y -# CONFIG_CRC_T10DIF is not set -CONFIG_CRYPTO=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=m -# CONFIG_CRYPTO_AUTHENC is not set -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CCM is not set -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_ECB=m -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_GHASH is not set -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_HW=y -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_LZO is not set -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_PCOMP=y -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_RNG is not set -CONFIG_CRYPTO_RNG2=y -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SEQIV is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TEST is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_VMAC is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_XTS is not set -CONFIG_CRYPTO_ZLIB=y -# CONFIG_CUSE is not set -# CONFIG_DAB is not set -# CONFIG_DCB is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_DEBUG_DEVRES is not set -CONFIG_DEBUG_DRIVER=y -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_DEBUG_GPIO is not set -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_LL is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_SHIRQ is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DECNET is not set -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_LZMA_NEEDED=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DETECT_SOFTLOCKUP=y -CONFIG_DEVKMEM=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -CONFIG_DISPLAY_SUPPORT=y -# CONFIG_DLM is not set -# CONFIG_DMADEVICES is not set -CONFIG_DNOTIFY=y -# CONFIG_DS1682 is not set -# CONFIG_DST is not set -# CONFIG_DUMMY is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_DVB_CORE is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_ECHO is not set -# CONFIG_ECONET is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_EFS_FS is not set -CONFIG_ELF_CORE=y -CONFIG_EMBEDDED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_EPOLL=y -# CONFIG_EQUALIZER is not set -CONFIG_EVENTFD=y -CONFIG_EXPERIMENTAL=y -CONFIG_EXPORTFS=m -CONFIG_EXT4_FS=y -# CONFIG_EZX_PCAP is not set -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -CONFIG_FAT_FS=y -# CONFIG_FAULT_INJECTION is not set -CONFIG_FB=y -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -# CONFIG_FB_BROADSHEET is not set -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MODE_HELPERS is not set -CONFIG_FB_OMAP2=y -CONFIG_FB_OMAP2_DEBUG_SUPPORT=y -CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE=y -CONFIG_FB_OMAP2_NUM_FBS=3 -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_TILEBLITTING is not set -# CONFIG_FB_UDL is not set -# CONFIG_FB_VIRTUAL is not set -CONFIG_FILE_LOCKING=y -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FLATMEM=y -CONFIG_FLATMEM_MANUAL=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_FONTS=y -# CONFIG_FONT_10x18 is not set -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_SUN8x16 is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FRAME_POINTER=y -CONFIG_FRAME_WARN=1024 -CONFIG_FREEZER=y -# CONFIG_FSCACHE is not set -CONFIG_FSNOTIFY=y -CONFIG_FS_MBCACHE=m -CONFIG_FS_POSIX_ACL=y -# CONFIG_FTL is not set -# CONFIG_FTRACE is not set -CONFIG_FUSE_FS=m -CONFIG_FUTEX=y -# CONFIG_FW_LOADER is not set -# CONFIG_GAMEPORT is not set -# CONFIG_GCOV_KERNEL is not set -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_TIME=y -CONFIG_GPIOLIB=y -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_MC33880 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set -# CONFIG_GPIO_SYSFS is not set -CONFIG_GPIO_TWL4030=y -CONFIG_GROUP_SCHED=y -# CONFIG_HAMRADIO is not set -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_TLS_REG=y -CONFIG_HAVE_AOUT=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_HAVE_KERNEL_LZO=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -CONFIG_HAVE_OPROFILE=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_HFSPLUS_FS=m -# CONFIG_HFS_FS is not set -CONFIG_HID=m -# CONFIG_HIDRAW is not set -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_PID is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SUNPLUS is not set -CONFIG_HID_SUPPORT=y -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_ZEROPLUS is not set -# CONFIG_HIGHMEM is not set -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HOTPLUG=y -# CONFIG_HPFS_FS is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -CONFIG_HZ=128 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_COMPAT is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DESIGNWARE is not set -CONFIG_I2C_GPIO=y -CONFIG_I2C_HELPER_AUTO=y -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_SIMTEC is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set -# CONFIG_IDE is not set -# CONFIG_IEEE802154 is not set -# CONFIG_IIO is not set -# CONFIG_IKCONFIG is not set -CONFIG_INET=y -# CONFIG_INET_AH is not set -CONFIG_INET_DIAG=y -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_LRO is not set -CONFIG_INET_TCP_DIAG=y -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INFTL is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_INPUT=y -# CONFIG_INPUT_EVBUG is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_GPIO is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_JOYSTICK is not set -CONFIG_INPUT_KEYBOARD=y -# CONFIG_INPUT_MIMIO is not set -# CONFIG_INPUT_MISC is not set -CONFIG_INPUT_MOUSE=y -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_CFQ=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_NOOP=y -# CONFIG_IPMI_HANDLER is not set -# CONFIG_IPV6 is not set -# CONFIG_IPX is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_DCCP is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_MULTICAST is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_IP_SCTP is not set -# CONFIG_IRDA is not set -# CONFIG_ISCSI_TCP is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_ISP1301_OMAP is not set -CONFIG_JBD=y -CONFIG_JBD2=m -# CONFIG_JBD2_DEBUG is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_JFFS2_SUMMARY is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFS_FS is not set -# CONFIG_KALLSYMS is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_KERNEL_LZO is not set -# CONFIG_KEXEC is not set -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_TWL4030 is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYS is not set -# CONFIG_KGDB is not set -# CONFIG_KSM is not set -# CONFIG_LAPB is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_LBDAF is not set -CONFIG_LCD_CLASS_DEVICE=y -# CONFIG_LCD_ILI9320 is not set -# CONFIG_LCD_LMS283GF05 is not set -# CONFIG_LCD_LTV350QV is not set -CONFIG_LCD_PLATFORM=y -# CONFIG_LCD_TDO24M is not set -# CONFIG_LCD_VGG2432A4 is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_LEDS is not set -# CONFIG_LEDS_BD2802 is not set -CONFIG_LEDS_CLASS=y -# CONFIG_LEDS_DAC124S085 is not set -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_PCA9532 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_TRIGGERS is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_LIB80211 is not set -# CONFIG_LIB80211_CRYPT_CCMP is not set -# CONFIG_LIB80211_CRYPT_TKIP is not set -# CONFIG_LIB80211_CRYPT_WEP is not set -CONFIG_LIBCRC32C=y -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_LINE6_USB is not set -# CONFIG_LLC2 is not set -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCKDEP_SUPPORT=y -# CONFIG_LOCK_STAT is not set -# CONFIG_LOGO is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP3EVM is not set -CONFIG_MACH_OMAP3_BEAGLE=y -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OVERO is not set -# CONFIG_MACVLAN is not set -# CONFIG_MAC_PARTITION is not set -# CONFIG_MD is not set -# CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_TUNER=y -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_MC44S803=y -CONFIG_MEDIA_TUNER_MT20XX=y -CONFIG_MEDIA_TUNER_SIMPLE=y -CONFIG_MEDIA_TUNER_TDA8290=y -CONFIG_MEDIA_TUNER_TDA9887=y -CONFIG_MEDIA_TUNER_TEA5761=y -CONFIG_MEDIA_TUNER_TEA5767=y -CONFIG_MEDIA_TUNER_XC2028=y -CONFIG_MEDIA_TUNER_XC5000=y -# CONFIG_MEMSTICK is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MG_DISK is not set -# CONFIG_MINIX_FS is not set -# CONFIG_MINIX_SUBPARTITION is not set -CONFIG_MINI_FO=y -# CONFIG_MISC_DEVICES is not set -CONFIG_MISC_FILESYSTEMS=y -CONFIG_MMC=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_MMC_DEBUG is not set -CONFIG_MMC_OMAP=y -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_SDHCI is not set -CONFIG_MMC_SPI=y -# CONFIG_MMC_TEST is not set -# CONFIG_MMC_UNSAFE_RESUME is not set -CONFIG_MMU=y -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_GPIO is not set -CONFIG_MOUSE_PS2=y -# CONFIG_MOUSE_PS2_ALPS is not set -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_LOGIPS2PP is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_SYNAPTICS is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -# CONFIG_MOUSE_PS2_TRACKPOINT is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_MOUSE_VSXXXAA is not set -CONFIG_MSDOS_FS=y -CONFIG_MSDOS_PARTITION=y -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_ALAUDA is not set -CONFIG_MTD_AR7_PARTS=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_BLOCK2MTD=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CHAR=y -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_DATAFLASH is not set -CONFIG_MTD_DEBUG=y -CONFIG_MTD_DEBUG_VERBOSE=2 -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -# CONFIG_MTD_JEDECPROBE is not set -# CONFIG_MTD_LPDDR is not set -# CONFIG_MTD_M25P80 is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MTDRAM is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -CONFIG_MTD_NAND_GPIO=y -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_NANDSIM is not set -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_OMAP_PREFETCH=y -# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set -CONFIG_MTD_NAND_PLATFORM=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_ONENAND is not set -# CONFIG_MTD_OOPS is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_ROM is not set -CONFIG_MTD_ROOTFS_ROOT_DEV=y -CONFIG_MTD_ROOTFS_SPLIT=y -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_UBI is not set -# CONFIG_MUSB_PIO_ONLY is not set -# CONFIG_NAMESPACES is not set -# CONFIG_NEON is not set -CONFIG_NET=y -# CONFIG_NETCONSOLE is not set -CONFIG_NETDEVICES=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_NETFILTER is not set -# CONFIG_NETPOLL is not set -# CONFIG_NETWORK_FILESYSTEMS is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NET_9P is not set -# CONFIG_NET_DSA is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_NET_IPIP is not set -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_NET_SCHED is not set -CONFIG_NEW_LEDS=y -# CONFIG_NFTL is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NLATTR=y -CONFIG_NLS=y -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=m -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_NO_HZ=y -# CONFIG_NTFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_OCF_OCF is not set -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_FAKE_VSYNC=y -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -CONFIG_OMAP2_DSS_RFBI=y -# CONFIG_OMAP2_DSS_SDI is not set -# CONFIG_OMAP2_DSS_USE_DSI_PLL is not set -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRAM_SIZE=12 -CONFIG_OMAP2_VRFB=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_32K_TIMER_HZ=128 -# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set -# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -# CONFIG_OMAP_MBOX_FWK is not set -CONFIG_OMAP_MCBSP=y -# CONFIG_OMAP_MPU_TIMER is not set -# CONFIG_OMAP_MUX is not set -# CONFIG_OMAP_PM_NONE is not set -CONFIG_OMAP_PM_NOOP=y -# CONFIG_OMAP_RESET_CLOCKS is not set -CONFIG_OMAP_WATCHDOG=y -# CONFIG_OMFS_FS is not set -# CONFIG_OSF_PARTITION is not set -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PAGE_POISONING is not set -CONFIG_PANEL_GENERIC=y -CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C=y -CONFIG_PANEL_SHARP_LS037V7DW01=y -CONFIG_PANEL_TAAL=y -# CONFIG_PARPORT is not set -CONFIG_PARTITION_ADVANCED=y -# CONFIG_PCCARD is not set -# CONFIG_PCI_SYSCALL is not set -# CONFIG_PDA_POWER is not set -# CONFIG_PHONE is not set -# CONFIG_PHONET is not set -# CONFIG_PHYS_ADDR_T_64BIT is not set -# CONFIG_PLAN9AUTH is not set -CONFIG_PM=y -# CONFIG_PMIC_DA903X is not set -# CONFIG_PM_DEBUG is not set -CONFIG_PM_RUNTIME=y -CONFIG_PM_SLEEP=y -# CONFIG_POHMELFS is not set -# CONFIG_POSIX_MQUEUE is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_PPP is not set -# CONFIG_PPS is not set -# CONFIG_PREEMPT is not set -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_PRINTK=y -# CONFIG_PRINTK_TIME is not set -CONFIG_PROC_FS=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_SYSCTL=y -# CONFIG_PROFILING is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_QUOTA is not set -# CONFIG_R3964 is not set -# CONFIG_RADIO_ADAPTERS is not set -# CONFIG_RAID_ATTRS is not set -# CONFIG_RAR_REGISTER is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_TRACE is not set -# CONFIG_RDS is not set -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_GZIP is not set -CONFIG_RD_LZMA=y -# CONFIG_RD_LZO is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_RELAY is not set -# CONFIG_RFD_FTL is not set -# CONFIG_RFKILL is not set -# CONFIG_ROMFS_FS is not set -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DEBUG is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_PCF2123 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_RTC7301 is not set -# CONFIG_RTC_DRV_RX8025 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_TEST is not set -CONFIG_RTC_DRV_TWL4030=y -# CONFIG_RTC_DRV_V3020 is not set -# CONFIG_RTC_DRV_X1205 is not set -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_LIB=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_RT_MUTEXES=y -# CONFIG_RT_MUTEX_TESTER is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_SAMPLES is not set -# CONFIG_SCHEDSTATS is not set -CONFIG_SCHED_DEBUG=y -CONFIG_SCSI=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_LOGGING is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -CONFIG_SCSI_PROC_FS=y -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_TGT is not set -CONFIG_SCSI_WAIT_SCAN=m -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LIS3_SPI is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_MAX3100 is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_SERIO=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SGI_PARTITION is not set -CONFIG_SHMEM=y -CONFIG_SIGNALFD=y -CONFIG_SLAB=y -CONFIG_SLABINFO=y -# CONFIG_SLIP is not set -# CONFIG_SLOB is not set -# CONFIG_SLOW_WORK is not set -# CONFIG_SLUB is not set -CONFIG_SND=y -# CONFIG_SND_ARM is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_HWDEP is not set -CONFIG_SND_JACK=y -# CONFIG_SND_MIXER_OSS is not set -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_MCBSP=y -CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_PCM=y -# CONFIG_SND_PCM_OSS is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -CONFIG_SND_SEQUENCER=y -CONFIG_SND_SEQUENCER_OSS=y -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_SOC=y -CONFIG_SND_SOC_AD1836=y -CONFIG_SND_SOC_AD1938=y -CONFIG_SND_SOC_AD73311=y -CONFIG_SND_SOC_AK4104=y -CONFIG_SND_SOC_AK4535=y -CONFIG_SND_SOC_AK4642=y -CONFIG_SND_SOC_ALL_CODECS=y -CONFIG_SND_SOC_CS4270=y -CONFIG_SND_SOC_I2C_AND_SPI=y -CONFIG_SND_SOC_L3=y -CONFIG_SND_SOC_MAX9877=y -CONFIG_SND_SOC_PCM3008=y -CONFIG_SND_SOC_SPDIF=y -CONFIG_SND_SOC_SSM2602=y -CONFIG_SND_SOC_TLV320AIC23=y -CONFIG_SND_SOC_TLV320AIC26=y -CONFIG_SND_SOC_TLV320AIC3X=y -CONFIG_SND_SOC_TWL4030=y -CONFIG_SND_SOC_UDA134X=y -CONFIG_SND_SOC_UDA1380=y -CONFIG_SND_SOC_WM8510=y -CONFIG_SND_SOC_WM8523=y -CONFIG_SND_SOC_WM8580=y -CONFIG_SND_SOC_WM8728=y -CONFIG_SND_SOC_WM8731=y -CONFIG_SND_SOC_WM8750=y -CONFIG_SND_SOC_WM8753=y -CONFIG_SND_SOC_WM8776=y -CONFIG_SND_SOC_WM8900=y -CONFIG_SND_SOC_WM8903=y -CONFIG_SND_SOC_WM8940=y -CONFIG_SND_SOC_WM8960=y -CONFIG_SND_SOC_WM8961=y -CONFIG_SND_SOC_WM8971=y -CONFIG_SND_SOC_WM8974=y -CONFIG_SND_SOC_WM8988=y -CONFIG_SND_SOC_WM8990=y -CONFIG_SND_SOC_WM8993=y -CONFIG_SND_SOC_WM9081=y -CONFIG_SND_SOC_WM_HUBS=y -# CONFIG_SND_SPI is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -CONFIG_SND_TIMER=y -CONFIG_SND_USB=y -# CONFIG_SND_USB_AUDIO is not set -# CONFIG_SND_USB_CAIAQ is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SOC_CAMERA is not set -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -# CONFIG_SOUND_PRIME is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -# CONFIG_SPI_GPIO_OLD is not set -CONFIG_SPI_MASTER=y -CONFIG_SPI_OMAP24XX=y -CONFIG_SPI_SPIDEV=y -# CONFIG_SPI_TLE62X0 is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_SQUASHFS=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -CONFIG_SQUASHFS_LZMA=y -# CONFIG_SSB is not set -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSFDC is not set -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -CONFIG_STANDALONE=y -CONFIG_STRIP_ASM_SYMS=y -# CONFIG_SUN_PARTITION is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWAP=y -# CONFIG_SYN_COOKIES is not set -CONFIG_SYSCTL=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_SYSFS=y -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_SYSV68_PARTITION is not set -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_SYSV_FS is not set -# CONFIG_SYS_HYPERVISOR is not set -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_TASKSTATS is not set -# CONFIG_TCG_TPM is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -# CONFIG_TCP_MD5SIG is not set -CONFIG_TEXTSEARCH=y -# CONFIG_TEXTSEARCH_BM is not set -# CONFIG_TEXTSEARCH_FSM is not set -# CONFIG_TEXTSEARCH_KMP is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_HWMON=y -# CONFIG_THUMB2_KERNEL is not set -CONFIG_TICK_ONESHOT=y -CONFIG_TIMERFD=y -# CONFIG_TIMER_STATS is not set -# CONFIG_TIPC is not set -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_TPS65010 is not set -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_TRANZPORT is not set -# CONFIG_TREE_PREEMPT_RCU is not set -CONFIG_TREE_RCU=y -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_TUN is not set -CONFIG_TWL4030_CORE=y -# CONFIG_TWL4030_POWER is not set -CONFIG_TWL4030_USB=y -CONFIG_TWL4030_WATCHDOG=y -# CONFIG_UACCESS_WITH_MEMCPY is not set -# CONFIG_UDF_FS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_UFS_FS is not set -CONFIG_UID16=y -# CONFIG_UIO is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_UNION_MOUNT is not set -CONFIG_UNIX=y -CONFIG_UNIX98_PTYS=y -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_USB=y -# CONFIG_USBPCWATCHDOG is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_ADUTUX is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -# CONFIG_USB_APPLEDISPLAY is not set -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDC_COMPOSITE is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -CONFIG_USB_DEBUG=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -# CONFIG_USB_EHCI_TT_NEWSCHED is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_USB_ETH is not set -CONFIG_USB_EZUSB=y -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_FTDI_ELAN is not set -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_CI13XXX is not set -CONFIG_USB_GADGET_DEBUG=y -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_GADGET_DUMMY_HCD is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_M66592 is not set -CONFIG_USB_GADGET_MUSB_HDRC=y -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -CONFIG_USB_GADGET_SELECTED=y -CONFIG_USB_GADGET_VBUS_DRAW=500 -# CONFIG_USB_GL860 is not set -# CONFIG_USB_GPIO_VBUS is not set -CONFIG_USB_GSPCA=m -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_JEILINJ is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_ZC3XX is not set -# CONFIG_USB_G_PRINTER is not set -CONFIG_USB_G_SERIAL=y -CONFIG_USB_HID=m -# CONFIG_USB_HIDDEV is not set -# CONFIG_USB_HWA_HCD is not set -# CONFIG_USB_IDMOUSE is not set -CONFIG_USB_INVENTRA_DMA=y -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_IP_COMMON is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_KBD is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LIBUSUAL is not set -# CONFIG_USB_M5602 is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_MOUSE is not set -# CONFIG_USB_MUSB_DEBUG is not set -CONFIG_USB_MUSB_HDRC=y -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_OTG is not set -CONFIG_USB_MUSB_PERIPHERAL=y -CONFIG_USB_MUSB_SOC=y -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -CONFIG_USB_OHCI_HCD=m -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_PWC_INPUT_EVDEV is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_S2255 is not set -CONFIG_USB_SERIAL=y -# CONFIG_USB_SERIAL_AIRCABLE is not set -# CONFIG_USB_SERIAL_ARK3116 is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_CH341 is not set -# CONFIG_USB_SERIAL_CONSOLE is not set -# CONFIG_USB_SERIAL_CP210X is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -# CONFIG_USB_SERIAL_DEBUG is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_EMPEG is not set -CONFIG_USB_SERIAL_FTDI_SIO=y -# CONFIG_USB_SERIAL_FUNSOFT is not set -# CONFIG_USB_SERIAL_GARMIN is not set -CONFIG_USB_SERIAL_GENERIC=y -# CONFIG_USB_SERIAL_HP4X is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_IUU is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_MOS7720 is not set -# CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_MOTOROLA is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -# CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_OPTICON is not set -# CONFIG_USB_SERIAL_OPTION is not set -# CONFIG_USB_SERIAL_OTI6858 is not set -CONFIG_USB_SERIAL_PL2303=y -# CONFIG_USB_SERIAL_QUALCOMM is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_SPCP8X5 is not set -# CONFIG_USB_SERIAL_SYMBOL is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_STKWEBCAM is not set -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_ALAUDA=y -CONFIG_USB_STORAGE_DATAFAB=y -# CONFIG_USB_STORAGE_DEBUG is not set -CONFIG_USB_STORAGE_FREECOM=y -CONFIG_USB_STORAGE_JUMPSHOT=y -CONFIG_USB_STORAGE_KARMA=y -CONFIG_USB_STORAGE_SDDR09=y -CONFIG_USB_STORAGE_SDDR55=y -CONFIG_USB_STORAGE_USBAT=y -# CONFIG_USB_STV06XX is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_SUSPEND=y -# CONFIG_USB_TEST is not set -# CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_TMC is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_USBNET is not set -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -# CONFIG_USB_VST is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set -# CONFIG_USB_ZC0301 is not set -# CONFIG_USB_ZERO is not set -# CONFIG_USB_ZR364XX is not set -CONFIG_USER_SCHED=y -CONFIG_V4L_USB_DRIVERS=y -CONFIG_VECTORS_BASE=0xffff0000 -# CONFIG_VETH is not set -CONFIG_VFAT_FS=y -CONFIG_VFP=y -CONFIG_VFPv3=y -# CONFIG_VGASTATE is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_ADV7180 is not set -# CONFIG_VIDEO_ADV7343 is not set -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_ALLOW_V4L1 is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_CS5345 is not set -# CONFIG_VIDEO_CS53L32A is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_CX2341X is not set -# CONFIG_VIDEO_CX25840 is not set -CONFIG_VIDEO_DEV=y -# CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -# CONFIG_VIDEO_HDPVR is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_M52790 is not set -CONFIG_VIDEO_MEDIA=y -# CONFIG_VIDEO_MSP3400 is not set -# CONFIG_VIDEO_MT9V011 is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_VIDEO_OV7670 is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_VIDEO_SAA6588 is not set -# CONFIG_VIDEO_SAA7110 is not set -# CONFIG_VIDEO_SAA711X is not set -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_TCM825X is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TDA9875 is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_TLV320AIC23B is not set -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TVP514X is not set -# CONFIG_VIDEO_TVP5150 is not set -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set -# CONFIG_VIDEO_USBVISION is not set -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L2_COMMON=y -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_VP27SMPX is not set -# CONFIG_VIDEO_VPX3220 is not set -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_WM8775 is not set -CONFIG_VIRT_TO_BUS=y -# CONFIG_VLAN_8021Q is not set -# CONFIG_VMSPLIT_1G is not set -# CONFIG_VMSPLIT_2G is not set -CONFIG_VMSPLIT_3G=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -# CONFIG_VXFS_FS is not set -# CONFIG_W1 is not set -# CONFIG_WAN is not set -# CONFIG_WAN_ROUTER is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set -# CONFIG_WIMAX is not set -CONFIG_WIRELESS=y -# CONFIG_WIRELESS_EXT is not set -CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_WLAN=y -# CONFIG_WLAN_80211 is not set -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_X25 is not set -CONFIG_XFRM=y -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_USER is not set -# CONFIG_XFS_DEBUG is not set -CONFIG_XFS_FS=m -# CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_RT is not set -# CONFIG_XIP_KERNEL is not set -# CONFIG_YAFFS_FS is not set -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/omap35xx/files/boot-mmc.cmd b/target/linux/omap35xx/files/boot-mmc.cmd deleted file mode 100644 index 6e3f238..0000000 --- a/target/linux/omap35xx/files/boot-mmc.cmd +++ /dev/null @@ -1,12 +0,0 @@ -echo ----------------------------- -echo u-boot.cmd -echo Kernel: MMC0P1:uImage -echo RootFS: MMC0P2 -echo VideoMode: 640x480@60 -echo VideoSpec: omapfb:vram:2M,vram:4M -echo ----------------------------- -setenv mmcargs setenv bootargs earlyprintk=ttyO2,115200n8 console=ttyO2,115200n8 console=tty0 root=/dev/mmcblk0p2 rw rootwait init=/etc/preinit nohz=off video=omapfb:vram:1M,vxres:640,vyres:480 -printenv -fatload mmc 0 83000000 uImage -run mmcargs -bootm 83000000 diff --git a/target/linux/omap35xx/gumstix/base-files/etc/config/network b/target/linux/omap35xx/gumstix/base-files/etc/config/network deleted file mode 100644 index bcb4c4b..0000000 --- a/target/linux/omap35xx/gumstix/base-files/etc/config/network +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (C) 2006 OpenWrt.org - -config interface loopback - option ifname lo - option proto static - option ipaddr 127.0.0.1 - option netmask 255.0.0.0 - -config interface lan - option ifname wlan0 - option proto dhcp - -config interface wan - option ifname eth0 - option proto dhcp diff --git a/target/linux/omap35xx/gumstix/base-files/etc/fw_env.config b/target/linux/omap35xx/gumstix/base-files/etc/fw_env.config deleted file mode 100644 index bb47368..0000000 --- a/target/linux/omap35xx/gumstix/base-files/etc/fw_env.config +++ /dev/null @@ -1,2 +0,0 @@ -# MTD device name Device offset Env. size Flash sector size -/dev/mtd2 0x0000 0x20000 0x20000 diff --git a/target/linux/omap35xx/gumstix/base-files/etc/inittab b/target/linux/omap35xx/gumstix/base-files/etc/inittab deleted file mode 100644 index be8fba1..0000000 --- a/target/linux/omap35xx/gumstix/base-files/etc/inittab +++ /dev/null @@ -1,5 +0,0 @@ -# inittab for Gumstix board -::sysinit:/etc/init.d/rcS S boot -::shutdown:/etc/init.d/rcS K stop -ttyO2::askfirst:/bin/ash --login -tty1::askfirst:/bin/ash --login diff --git a/target/linux/omap35xx/gumstix/base-files/lib/preinit/95_ttyS1_noecho b/target/linux/omap35xx/gumstix/base-files/lib/preinit/95_ttyS1_noecho deleted file mode 100644 index 319f513..0000000 --- a/target/linux/omap35xx/gumstix/base-files/lib/preinit/95_ttyS1_noecho +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/sh -# Copyright (C) 2010 OpenWrt.org - -ttyS1_noecho() { - stty -echo < /dev/ttyO1 -} - -boot_hook_add preinit_main ttyS1_noecho - diff --git a/target/linux/omap35xx/gumstix/config-2.6.36 b/target/linux/omap35xx/gumstix/config-2.6.36 deleted file mode 100644 index 23d0fe3..0000000 --- a/target/linux/omap35xx/gumstix/config-2.6.36 +++ /dev/null @@ -1,418 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_APM_EMULATION is not set -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_ARCH_OMAP2PLUS_TYPICAL=y -CONFIG_ARCH_OMAP3=y -CONFIG_ARCH_OMAP3430=y -# CONFIG_ARCH_OMAP4 is not set -CONFIG_ARCH_OMAP_OTG=y -CONFIG_ARCH_REQUIRE_GPIOLIB=y -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_ARCH_USES_GETTIMEOFFSET is not set -CONFIG_ARM=y -CONFIG_ARM_DMA_MEM_BUFFERABLE=y -# CONFIG_ARM_ERRATA_430973 is not set -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -# CONFIG_ARM_ERRATA_743622 is not set -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -# CONFIG_ARPD is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_BLK_DEV_SD=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CMDLINE=" debug " -CONFIG_COMMON_CLKDEV=y -CONFIG_COMPAT_BRK=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRC7=y -CONFIG_CRC_CCITT=y -CONFIG_CRC_ITU_T=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_DEV_OMAP_SHAM is not set -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_INFO_REDUCED is not set -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_USER is not set -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEVKMEM=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_DISPLAY_SUPPORT=y -CONFIG_DNOTIFY=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EARLY_PRINTK=y -CONFIG_ELF_CORE=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_EXPORTFS=m -CONFIG_EXT4_FS=y -CONFIG_FAT_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_OMAP2=y -CONFIG_FB_OMAP2_DEBUG_SUPPORT=y -CONFIG_FB_OMAP2_NUM_FBS=3 -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FONTS=y -# CONFIG_FONT_10x18 is not set -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_SUN8x16 is not set -CONFIG_FORCE_MAX_ZONEORDER=11 -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FRAME_POINTER=y -CONFIG_FREEZER=y -CONFIG_FUSE_FS=m -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_TWL4030=y -# CONFIG_HAMRADIO is not set -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAVE_AOUT=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_HAVE_KERNEL_LZO=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HFSPLUS_FS=m -CONFIG_HID=y -CONFIG_HID_SUPPORT=y -CONFIG_HWMON=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HZ=128 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_GPIO=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_OMAP=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INOTIFY_USER=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYBOARD=y -# CONFIG_INPUT_MISC is not set -CONFIG_INPUT_MOUSE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_MULTICAST is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_ISDN is not set -# CONFIG_ISP1301_OMAP is not set -CONFIG_JBD2=y -# CONFIG_JFFS2_FS is not set -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_LZMA is not set -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_TWL4030 is not set -# CONFIG_LBDAF is not set -# CONFIG_LEDS is not set -# CONFIG_LEDS_REGULATOR is not set -# CONFIG_LEDS_TRIGGERS is not set -CONFIG_LIBCRC32C=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_DEVKIT8000 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP3517EVM is not set -# CONFIG_MACH_OMAP3EVM is not set -# CONFIG_MACH_OMAP3_BEAGLE is not set -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -CONFIG_MACH_OVERO=y -CONFIG_MACH_SBC3530=y -CONFIG_MAGIC_SYSRQ=y -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_OMAP=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MMC_SPI=y -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_GPIO is not set -CONFIG_MOUSE_PS2=y -# CONFIG_MOUSE_PS2_ALPS is not set -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_LOGIPS2PP is not set -# CONFIG_MOUSE_PS2_SYNAPTICS is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -# CONFIG_MOUSE_PS2_TRACKPOINT is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -CONFIG_MSDOS_FS=y -# CONFIG_MTD_BLKDEVS is not set -# CONFIG_MTD_BLOCK is not set -# CONFIG_MTD_BLOCK_RO is not set -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_OMAP_PREFETCH=y -# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set -CONFIG_MTD_NAND_PLATFORM=y -# CONFIG_MTD_ROOTFS_ROOT_DEV is not set -# CONFIG_MTD_ROOTFS_SPLIT is not set -# CONFIG_MTD_SM_COMMON is not set -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_RESERVE=1 -# CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_NET_KEY=y -# CONFIG_NET_SCHED is not set -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_UTF8=m -CONFIG_NO_HZ=y -CONFIG_OMAP2_DSS=y -# CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set -CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y -CONFIG_OMAP2_DSS_DPI=y -# CONFIG_OMAP2_DSS_DSI is not set -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -# CONFIG_OMAP2_DSS_RFBI is not set -# CONFIG_OMAP2_DSS_SDI is not set -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRAM_SIZE=12 -CONFIG_OMAP2_VRFB=y -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_MBOX_FWK is not set -CONFIG_OMAP_MCBSP=y -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_MUX=y -# CONFIG_OMAP_MUX_DEBUG is not set -CONFIG_OMAP_MUX_WARNINGS=y -CONFIG_OMAP_PACKAGE_CBB=y -CONFIG_OMAP_PACKAGE_CUS=y -# CONFIG_OMAP_PM_NONE is not set -CONFIG_OMAP_PM_NOOP=y -# CONFIG_OMAP_RESET_CLOCKS is not set -CONFIG_OMAP_WATCHDOG=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PANEL_GENERIC=y -# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set -# CONFIG_PANEL_SHARP_LS037V7DW01 is not set -# CONFIG_PANEL_TOPPOLY_TDO35S is not set -# CONFIG_PANEL_TPO_TD043MTEA1 is not set -# CONFIG_PCI_SYSCALL is not set -# CONFIG_PDA_POWER is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PHYLIB=y -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_OPS=y -CONFIG_PM_RUNTIME=y -CONFIG_PM_SLEEP=y -CONFIG_POWER_SUPPLY=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_AD5398 is not set -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_DUMMY is not set -# CONFIG_REGULATOR_ISL6271A is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_MAX8649 is not set -# CONFIG_REGULATOR_MAX8660 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_CMOS is not set -CONFIG_RTC_DRV_TWL4030=y -CONFIG_SCHED_DEBUG=y -CONFIG_SCSI=y -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIO=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_SERPORT=y -CONFIG_SMSC911X=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_OMAP24XX=y -CONFIG_SPI_SPIDEV=y -# CONFIG_STAGING is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SUSPEND_NVS=y -# CONFIG_SYN_COOKIES is not set -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_THERMAL=y -CONFIG_THERMAL_HWMON=y -# CONFIG_THUMB2_KERNEL is not set -# CONFIG_TINY_RCU is not set -# CONFIG_TI_DAVINCI_EMAC is not set -CONFIG_TREE_RCU=y -# CONFIG_TWL4030_CODEC is not set -CONFIG_TWL4030_CORE=y -CONFIG_TWL4030_POWER=y -CONFIG_TWL4030_USB=y -CONFIG_TWL4030_WATCHDOG=y -# CONFIG_TWL6030_PWM is not set -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -# CONFIG_UBIFS_FS_DEBUG is not set -CONFIG_UBIFS_FS_LZO=y -# CONFIG_UBIFS_FS_XATTR is not set -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_UID16=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEBUG=y -CONFIG_USB_DEVICE_CLASS=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_HID=y -CONFIG_USB_INVENTRA_DMA=y -# CONFIG_USB_MUSB_DEBUG is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_MUSB_SOC=y -CONFIG_USB_OTG_UTILS=y -CONFIG_USB_SUPPORT=y -# CONFIG_USB_TI_CPPI_DMA is not set -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_VFAT_FS=y -CONFIG_VFP=y -CONFIG_VFPv3=y -# CONFIG_VLAN_8021Q is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_XFS_FS=m -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/omap35xx/gumstix/config-default b/target/linux/omap35xx/gumstix/config-default deleted file mode 100644 index e88aae5..0000000 --- a/target/linux/omap35xx/gumstix/config-default +++ /dev/null @@ -1,334 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_APM_EMULATION is not set -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -CONFIG_ARCH_HAS_OPP=y -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_ARCH_OMAP2PLUS_TYPICAL=y -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set -CONFIG_ARCH_OMAP_OTG=y -CONFIG_ARCH_REQUIRE_GPIOLIB=y -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_ARCH_USES_GETTIMEOFFSET is not set -CONFIG_ARM=y -# CONFIG_ARM_ERRATA_430973 is not set -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -# CONFIG_ARM_ERRATA_743622 is not set -# CONFIG_ARM_ERRATA_754322 is not set -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -CONFIG_BCMA_POSSIBLE=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRC7=y -CONFIG_CRC_ITU_T=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_DEV_OMAP_AES is not set -# CONFIG_CRYPTO_DEV_OMAP_SHAM is not set -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_PCOMP2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_USER is not set -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DNOTIFY=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EXPORTFS=m -CONFIG_EXT4_FS=y -# CONFIG_EXT4_FS_XATTR is not set -CONFIG_FB=y -# CONFIG_FB_OMAP2 is not set -# CONFIG_FB_WMT_GE_ROPS is not set -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FRAME_POINTER=y -CONFIG_FUSE_FS=m -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_TWL4030=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAVE_AOUT=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_GENERIC_HARDIRQS=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_WORK=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_HAVE_KERNEL_LZO=y -CONFIG_HAVE_KERNEL_XZ=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SCHED_CLOCK=y -CONFIG_HAVE_SPARSE_IRQ=y -CONFIG_HID=y -CONFIG_HID_SUPPORT=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HZ=128 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_GPIO=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_OMAP=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -# CONFIG_INPUT_GPIO_BUTTONS is not set -# CONFIG_INPUT_TWL4030_PWRBUTTON is not set -# CONFIG_INPUT_TWL4030_VIBRA is not set -# CONFIG_ISDN is not set -# CONFIG_ISP1301_OMAP is not set -CONFIG_JBD2=y -# CONFIG_JFFS2_FS is not set -CONFIG_KERNEL_LZMA=y -# CONFIG_KERNEL_XZ is not set -CONFIG_KTIME_SCALAR=y -# CONFIG_LEDS is not set -# CONFIG_LEDS_REGULATOR is not set -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_CM_T3517 is not set -# CONFIG_MACH_CRANEBOARD is not set -# CONFIG_MACH_DEVKIT8000 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_IGEP0030 is not set -# CONFIG_MACH_NOKIA_RM680 is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP3517EVM is not set -# CONFIG_MACH_OMAP3530_LV_SOM is not set -# CONFIG_MACH_OMAP3EVM is not set -CONFIG_MACH_OMAP3_BEAGLE=y -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP3_TORPEDO is not set -# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -CONFIG_MACH_OVERO=y -# CONFIG_MACH_SBC3530 is not set -# CONFIG_MACH_TI8168EVM is not set -CONFIG_MFD_OMAP_USB_HOST=y -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_OMAP=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MMC_SPI=y -# CONFIG_MTD_BLKDEVS is not set -# CONFIG_MTD_BLOCK is not set -# CONFIG_MTD_BLOCK_RO is not set -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_PLATFORM=y -# CONFIG_MTD_ROOTFS_ROOT_DEV is not set -# CONFIG_MTD_ROOTFS_SPLIT is not set -# CONFIG_MTD_SM_COMMON is not set -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_RESERVE=1 -# CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NEON=y -# CONFIG_NETDEV_1000 is not set -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_UTF8=m -CONFIG_OMAP2_DSS=y -# CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set -CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y -CONFIG_OMAP2_DSS_DPI=y -# CONFIG_OMAP2_DSS_DSI is not set -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -# CONFIG_OMAP2_DSS_RFBI is not set -# CONFIG_OMAP2_DSS_SDI is not set -CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y -CONFIG_OMAP2_DSS_SLEEP_BEFORE_RESET=y -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VRAM_SIZE=0 -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_MBOX_FWK is not set -CONFIG_OMAP_MCBSP=y -CONFIG_OMAP_MUX=y -# CONFIG_OMAP_MUX_DEBUG is not set -CONFIG_OMAP_MUX_WARNINGS=y -CONFIG_OMAP_PACKAGE_CBB=y -# CONFIG_OMAP_PM_NONE is not set -CONFIG_OMAP_PM_NOOP=y -# CONFIG_OMAP_RESET_CLOCKS is not set -# CONFIG_OMAP_SMARTREFLEX is not set -CONFIG_OMAP_WATCHDOG=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PANEL_GENERIC_DPI is not set -# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -# CONFIG_PANEL_NEC_NL8048HL11_01B is not set -# CONFIG_PANEL_SHARP_LS037V7DW01 is not set -# CONFIG_PANEL_TPO_TD043MTEA1 is not set -# CONFIG_PCI_SYSCALL is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PHYLIB=y -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_OPP=y -CONFIG_PM_RUNTIME=y -CONFIG_PM_RUNTIME_CLK=y -# CONFIG_PREEMPT_RCU is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_AD5398 is not set -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_DUMMY is not set -# CONFIG_REGULATOR_ISL6271A is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_LP3972 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_MAX8649 is not set -# CONFIG_REGULATOR_MAX8660 is not set -# CONFIG_REGULATOR_MAX8952 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -# CONFIG_REGULATOR_TPS6524X is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_RFKILL_REGULATOR is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_TWL4030=y -# CONFIG_SCSI_DMA is not set -CONFIG_SERIAL_OMAP=y -CONFIG_SERIAL_OMAP_CONSOLE=y -CONFIG_SMSC911X=y -# CONFIG_SMSC911X_ARCH_HOOKS is not set -CONFIG_SOC_OMAP3430=y -CONFIG_SOC_OMAPTI816X=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_OMAP24XX=y -CONFIG_SPI_SPIDEV=y -# CONFIG_STAGING is not set -# CONFIG_SWP_EMULATE is not set -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_THUMB2_KERNEL is not set -# CONFIG_TI_DAVINCI_CPDMA is not set -# CONFIG_TI_DAVINCI_EMAC is not set -# CONFIG_TI_DAVINCI_MDIO is not set -# CONFIG_TWL4030_CODEC is not set -CONFIG_TWL4030_CORE=y -# CONFIG_TWL4030_MADC is not set -CONFIG_TWL4030_POWER=y -CONFIG_TWL4030_USB=y -CONFIG_TWL4030_WATCHDOG=y -# CONFIG_TWL6030_PWM is not set -# CONFIG_TWL6030_USB is not set -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -# CONFIG_UBIFS_FS_DEBUG is not set -CONFIG_UBIFS_FS_LZO=y -# CONFIG_UBIFS_FS_XATTR is not set -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_UID16=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEBUG=y -CONFIG_USB_DEVICE_CLASS=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_OMAP=y -CONFIG_USB_OTG_UTILS=y -CONFIG_USB_SUPPORT=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_XFS_FS=m -CONFIG_XZ_DEC=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/omap35xx/gumstix/defconfig.es b/target/linux/omap35xx/gumstix/defconfig.es deleted file mode 100644 index 80b2ae7..0000000 --- a/target/linux/omap35xx/gumstix/defconfig.es +++ /dev/null @@ -1,24 +0,0 @@ -# defconfig for energy station - -CONFIG_TARGET_omap35xx=y -CONFIG_TARGET_omap35xx_gumstix=y -CONFIG_TARGET_omap35xx_gumstix_Es=y -CONFIG_DEVEL=y -CONFIG_BROKEN=y -CONFIG_TOOLCHAINOPTS=y -CONFIG_GCC_VERSION_4_4_5=y -CONFIG_INSTALL_LIBSTDCPP=y -CONFIG_TARGET_OPTIONS=y -CONFIG_TARGET_OPTIMIZATION="-O2 -pipe -march=armv7-a -mtune=cortex-a8 -funit-at-a-time" -CONFIG_USE_UCLIBC=y -CONFIG_UCLIBC_VERSION_0_9_30_1=y -CONFIG_TARGET_ROOTFS_PARTSIZE=200 -CONFIG_SOFT_FLOAT=n -CONFIG_TARGET_ROOTFS_EXT4FS=y -CONFIG_UDEV_EXTRA_firmware=y -CONFIG_BUSYBOX_CONFIG_STTY=y -CONFIG_BUSYBOX_CONFIG_TTY=y -CONFIG_PACKAGE_es=y -CONFIG_PACKAGE_es_sentec_real=y -CONFIG_PACKAGE_es_sentec_sim=y -CONFIG_PACKAGE_estest=y diff --git a/target/linux/omap35xx/gumstix/defconfig.gumstix b/target/linux/omap35xx/gumstix/defconfig.gumstix deleted file mode 100644 index f2429ba..0000000 --- a/target/linux/omap35xx/gumstix/defconfig.gumstix +++ /dev/null @@ -1,20 +0,0 @@ -# defconfig for gumstix - -CONFIG_TARGET_omap35xx=y -CONFIG_TARGET_omap35xx_gumstix=y -CONFIG_DEVEL=y -CONFIG_BROKEN=y -CONFIG_TOOLCHAINOPTS=y -CONFIG_GCC_VERSION_4_4_5=y -CONFIG_INSTALL_LIBSTDCPP=y -CONFIG_TARGET_OPTIONS=y -CONFIG_TARGET_OPTIMIZATION="-O2 -pipe -march=armv7-a -mtune=cortex-a8 -funit-at-a-time" -CONFIG_USE_UCLIBC=y -CONFIG_UCLIBC_VERSION_0_9_30_1=y -CONFIG_TARGET_ROOTFS_PARTSIZE=200 -CONFIG_SOFT_FLOAT=n -CONFIG_TARGET_ROOTFS_EXT4FS=y -CONFIG_UDEV_EXTRA_firmware=y -CONFIG_BUSYBOX_CONFIG_STTY=y -CONFIG_BUSYBOX_CONFIG_TTY=y - diff --git a/target/linux/omap35xx/gumstix/defconfig.vpp b/target/linux/omap35xx/gumstix/defconfig.vpp deleted file mode 100644 index c6ed288..0000000 --- a/target/linux/omap35xx/gumstix/defconfig.vpp +++ /dev/null @@ -1,26 +0,0 @@ -# defconfig for vpp - -CONFIG_TARGET_omap35xx=y -CONFIG_TARGET_omap35xx_gumstix=y -CONFIG_TARGET_omap35xx_gumstix_Vpp=y -CONFIG_DEVEL=y -CONFIG_BROKEN=y -CONFIG_TOOLCHAINOPTS=y -CONFIG_GCC_VERSION_4_4_5=y -CONFIG_INSTALL_LIBSTDCPP=y -CONFIG_TARGET_OPTIONS=y -CONFIG_TARGET_OPTIMIZATION="-O2 -pipe -march=armv7-a -mtune=cortex-a8 -funit-at-a-time" -CONFIG_USE_EGLIBC=y -CONFIG_EGLIBC_VERSION_2_12=y -CONFIG_EGLIBC_REVISION="10454" -CONFIG_EGLIBC_VERSION="2.12" -CONFIG_LIBC="eglibc" -CONFIG_LIBC_VERSION="2.12" -CONFIG_TARGET_SUFFIX="gnueabi" -CONFIG_TARGET_ROOTFS_PARTSIZE=200 -CONFIG_SOFT_FLOAT=n -CONFIG_TARGET_ROOTFS_EXT4FS=y -CONFIG_UDEV_EXTRA_firmware=y -CONFIG_BUSYBOX_CONFIG_STTY=y -CONFIG_BUSYBOX_CONFIG_TTY=y -CONFIG_TARGET_omap35xx_vpp=y diff --git a/target/linux/omap35xx/gumstix/profiles/000-hegw.mk b/target/linux/omap35xx/gumstix/profiles/000-hegw.mk deleted file mode 100644 index ee312b5..0000000 --- a/target/linux/omap35xx/gumstix/profiles/000-hegw.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (C) 2006 - 2009 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Gumstix - NAME:=hegw - PACKAGES:=-iptables -ppp -ppp-mod-pppoe -kmod-ipt-nathelper \ - -firewall -mtd -hotplug2 -udevtrigger -dropbear \ - usb udev kmod-bluetooth ntpclient wpa-supplicant \ - wpa-cli \ - bluez-utils bluez-hcidump usbutils \ - kmod-usb-serial kmod-usb-serial-cp210x kmod-usb-serial-ftdi \ - kmod-usb-serial-pl2303 kmod-usb-uhci kmod-cfg80211 \ - kmod-lib80211 kmod-libertas-sd kmod-mac80211 libnl-tiny \ - crda iw kmod-usb-hid \ - kmod-usb-storage kmod-usb-storage-extras kmod-fs-vfat \ - uboot-omap35xx-omap3_overo \ - hegw hegwtest mtd-utils uboot-envtools -endef - -define Profile/Gumstix/Description - Gumstix www.gumstix.com -endef -$(eval $(call Profile,Gumstix)) diff --git a/target/linux/omap35xx/gumstix/profiles/001-vpp.mk b/target/linux/omap35xx/gumstix/profiles/001-vpp.mk deleted file mode 100644 index 7361ce9..0000000 --- a/target/linux/omap35xx/gumstix/profiles/001-vpp.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (C) 2011 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Vpp - NAME:=vpp - PACKAGES:=-iptables -ppp -ppp-mod-pppoe -kmod-ipt-nathelper \ - -firewall -mtd -hotplug2 -udevtrigger -dropbear \ - usb udev kmod-bluetooth ntpclient wpa-supplicant \ - wpa-cli \ - bluez-utils bluez-hcidump usbutils \ - kmod-usb-serial kmod-usb-serial-cp210x kmod-usb-serial-ftdi \ - kmod-usb-serial-pl2303 kmod-usb-uhci kmod-cfg80211 \ - kmod-lib80211 kmod-libertas-sd kmod-mac80211 libnl-tiny \ - crda iw kmod-usb-hid \ - kmod-usb-storage kmod-usb-storage-extras kmod-fs-vfat \ - uboot-omap35xx-omap3_overo \ - vpp vpptest mtd-utils ejre uboot-envtools -endef - -define Profile/Vpp/Description - Gumstix www.gumstix.com -endef -$(eval $(call Profile,Vpp)) diff --git a/target/linux/omap35xx/gumstix/profiles/002-es.mk b/target/linux/omap35xx/gumstix/profiles/002-es.mk deleted file mode 100644 index cd8c464..0000000 --- a/target/linux/omap35xx/gumstix/profiles/002-es.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (C) 2006 - 2009 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Es - NAME:=es - PACKAGES:=-iptables -ppp -ppp-mod-pppoe -kmod-ipt-nathelper \ - -firewall -mtd -hotplug2 -udevtrigger -dropbear \ - usb udev kmod-bluetooth ntpclient wpa-supplicant \ - wpa-cli \ - bluez-utils bluez-hcidump usbutils \ - kmod-usb-serial kmod-usb-serial-cp210x kmod-usb-serial-ftdi \ - kmod-usb-serial-pl2303 kmod-usb-uhci kmod-cfg80211 \ - kmod-lib80211 kmod-libertas-sd kmod-mac80211 libnl-tiny \ - crda iw kmod-usb-hid \ - kmod-usb-storage kmod-usb-storage-extras kmod-fs-vfat \ - uboot-omap35xx-omap3_overo \ - es estest mtd-utils uboot-envtools -endef - -define Profile/Es/Description - Gumstix www.gumstix.com -endef -$(eval $(call Profile,Es)) diff --git a/target/linux/omap35xx/gumstix/target.mk b/target/linux/omap35xx/gumstix/target.mk deleted file mode 100644 index 3e3d783..0000000 --- a/target/linux/omap35xx/gumstix/target.mk +++ /dev/null @@ -1,7 +0,0 @@ -BOARDNAME:=Gumstix Overo -LINUX_VERSION:=3.0.3 - -define Target/Description - Build firmware images for Gumstix Overo Boards -endef - diff --git a/target/linux/omap35xx/image/Makefile b/target/linux/omap35xx/image/Makefile deleted file mode 100644 index e742b75..0000000 --- a/target/linux/omap35xx/image/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright (C) 2006-2010 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -JFFS2_BLOCKSIZE=128k -JFFS2OPTS += --little-endian --pagesize=0x800 --no-cleanmarkers --pad - -UBIFS_OPTS = -m 2048 -e 126KiB -c 1996 -U -UBINIZE_OPTS = -m 2048 -p 128KiB -s 512 - -define Image/BuildKernel - $(TARGET_CROSS)objcopy -O binary -R .note -R .comment -S $(LINUX_DIR)/arch/arm/boot/compressed/vmlinux linux.bin - mkimage -A arm -O linux -T kernel -C none -a 80008000 -e 80008000 -n "OpenWRT Kernel Image gumstix" -d linux.bin uImage - mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n 'uImage.bin+mmc2' -d ../files/boot-mmc.cmd boot.scr - - mv uImage $(BIN_DIR)/$(IMG_PREFIX)-$(KERNEL)-uImage - mv boot.scr $(BIN_DIR)/boot.scr - rm linux.bin -endef - -define Image/Build - $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(KERNEL)-root.$(1) -# PADDING="true" PATH="$(TARGET_PATH)" ./gen_image.sh $(BIN_DIR)/$(IMG_PREFIX)-$(1).image 4 $(KDIR)/root.bootscript 240 $(KDIR)/root.$(1) - $(call Image/Build/$(1),$(1)) -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/omap35xx/image/gen_image.sh b/target/linux/omap35xx/image/gen_image.sh deleted file mode 100755 index 4fd6e37..0000000 --- a/target/linux/omap35xx/image/gen_image.sh +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env bash -# Copyright (C) 2006 - 2007 OpenWrt.org -set -x -[ $# == 5 ] || { - echo "SYNTAX: $0 <file> <kernel size> <kernel directory> <rootfs size> <rootfs image>" - exit 1 -} - -OUTPUT="$1" -KERNELSIZE="$2" -KERNELDIR="$3" -ROOTFSSIZE="$4" -ROOTFSIMAGE="$5" - -rm -f "$OUTPUT" - -head=16 -sect=63 -cyl=$(( ($KERNELSIZE + $ROOTFSSIZE) * 1024 * 1024 / ($head * $sect * 512))) - -# create partition table -set `ptgen -o "$OUTPUT" -h $head -s $sect -p ${KERNELSIZE}m -p ${ROOTFSSIZE}m` - -KERNELOFFSET="$(($1 / 512))" -KERNELSIZE="$(($2 / 512))" -ROOTFSOFFSET="$(($3 / 512))" -ROOTFSSIZE="$(($4 / 512))" - -BLOCKS="$((($KERNELSIZE / 2) - 1))" - -genext2fs -d "$KERNELDIR" -b "$BLOCKS" "$OUTPUT.kernel" -dd if="$OUTPUT.kernel" of="$OUTPUT" bs=512 seek="$KERNELOFFSET" conv=notrunc -[ -n "$PADDING" ] && dd if=/dev/zero of="$OUTPUT" bs=512 seek="$ROOTFSOFFSET" conv=notrunc count="$ROOTFSSIZE" -dd if="$ROOTFSIMAGE" of="$OUTPUT" bs=512 seek="$ROOTFSOFFSET" conv=notrunc -#rm -f "$OUTPUT.kernel" diff --git a/target/linux/omap35xx/image/ubinize.cfg b/target/linux/omap35xx/image/ubinize.cfg deleted file mode 100644 index 49d55b9..0000000 --- a/target/linux/omap35xx/image/ubinize.cfg +++ /dev/null @@ -1,14 +0,0 @@ -[rootfs] -# Volume mode (other option is static) -mode=ubi -# Source image -image=root.ubifs -# Volume ID in UBI image -vol_id=0 -# Allow for dynamic resize -vol_type=dynamic -# Volume name -vol_name=rootfs -# Autoresize volume at first mount -vol_flags=autoresize - diff --git a/target/linux/omap35xx/patches-2.6.32/001-DSS2.patch b/target/linux/omap35xx/patches-2.6.32/001-DSS2.patch deleted file mode 100644 index be32519..0000000 --- a/target/linux/omap35xx/patches-2.6.32/001-DSS2.patch +++ /dev/null @@ -1,22645 +0,0 @@ ---- /dev/null -+++ b/Documentation/arm/OMAP/DSS -@@ -0,0 +1,317 @@ -+OMAP2/3 Display Subsystem -+------------------------- -+ -+This is an almost total rewrite of the OMAP FB driver in drivers/video/omap -+(let's call it DSS1). The main differences between DSS1 and DSS2 are DSI, -+TV-out and multiple display support, but there are lots of small improvements -+also. -+ -+The DSS2 driver (omapdss module) is in arch/arm/plat-omap/dss/, and the FB, -+panel and controller drivers are in drivers/video/omap2/. DSS1 and DSS2 live -+currently side by side, you can choose which one to use. -+ -+Features -+-------- -+ -+Working and tested features include: -+ -+- MIPI DPI (parallel) output -+- MIPI DSI output in command mode -+- MIPI DBI (RFBI) output -+- SDI output -+- TV output -+- All pieces can be compiled as a module or inside kernel -+- Use DISPC to update any of the outputs -+- Use CPU to update RFBI or DSI output -+- OMAP DISPC planes -+- RGB16, RGB24 packed, RGB24 unpacked -+- YUV2, UYVY -+- Scaling -+- Adjusting DSS FCK to find a good pixel clock -+- Use DSI DPLL to create DSS FCK -+ -+Tested boards include: -+- OMAP3 SDP board -+- Beagle board -+- N810 -+ -+omapdss driver -+-------------- -+ -+The DSS driver does not itself have any support for Linux framebuffer, V4L or -+such like the current ones, but it has an internal kernel API that upper level -+drivers can use. -+ -+The DSS driver models OMAP's overlays, overlay managers and displays in a -+flexible way to enable non-common multi-display configuration. In addition to -+modelling the hardware overlays, omapdss supports virtual overlays and overlay -+managers. These can be used when updating a display with CPU or system DMA. -+ -+Panel and controller drivers -+---------------------------- -+ -+The drivers implement panel or controller specific functionality and are not -+usually visible to users except through omapfb driver. They register -+themselves to the DSS driver. -+ -+omapfb driver -+------------- -+ -+The omapfb driver implements arbitrary number of standard linux framebuffers. -+These framebuffers can be routed flexibly to any overlays, thus allowing very -+dynamic display architecture. -+ -+The driver exports some omapfb specific ioctls, which are compatible with the -+ioctls in the old driver. -+ -+The rest of the non standard features are exported via sysfs. Whether the final -+implementation will use sysfs, or ioctls, is still open. -+ -+V4L2 drivers -+------------ -+ -+V4L2 is being implemented in TI. -+ -+From omapdss point of view the V4L2 drivers should be similar to framebuffer -+driver. -+ -+Architecture -+-------------------- -+ -+Some clarification what the different components do: -+ -+ - Framebuffer is a memory area inside OMAP's SRAM/SDRAM that contains the -+ pixel data for the image. Framebuffer has width and height and color -+ depth. -+ - Overlay defines where the pixels are read from and where they go on the -+ screen. The overlay may be smaller than framebuffer, thus displaying only -+ part of the framebuffer. The position of the overlay may be changed if -+ the overlay is smaller than the display. -+ - Overlay manager combines the overlays in to one image and feeds them to -+ display. -+ - Display is the actual physical display device. -+ -+A framebuffer can be connected to multiple overlays to show the same pixel data -+on all of the overlays. Note that in this case the overlay input sizes must be -+the same, but, in case of video overlays, the output size can be different. Any -+framebuffer can be connected to any overlay. -+ -+An overlay can be connected to one overlay manager. Also DISPC overlays can be -+connected only to DISPC overlay managers, and virtual overlays can be only -+connected to virtual overlays. -+ -+An overlay manager can be connected to one display. There are certain -+restrictions which kinds of displays an overlay manager can be connected: -+ -+ - DISPC TV overlay manager can be only connected to TV display. -+ - Virtual overlay managers can only be connected to DBI or DSI displays. -+ - DISPC LCD overlay manager can be connected to all displays, except TV -+ display. -+ -+Sysfs -+----- -+The sysfs interface is mainly used for testing. I don't think sysfs -+interface is the best for this in the final version, but I don't quite know -+what would be the best interfaces for these things. -+ -+The sysfs interface is divided to two parts: DSS and FB. -+ -+/sys/class/graphics/fb? directory: -+mirror 0=off, 1=on -+rotate Rotation 0-3 for 0, 90, 180, 270 degrees -+rotate_type 0 = DMA rotation, 1 = VRFB rotation -+overlays List of overlay numbers to which framebuffer pixels go -+phys_addr Physical address of the framebuffer -+virt_addr Virtual address of the framebuffer -+size Size of the framebuffer -+ -+/sys/devices/platform/omapdss/overlay? directory: -+enabled 0=off, 1=on -+input_size width,height (ie. the framebuffer size) -+manager Destination overlay manager name -+name -+output_size width,height -+position x,y -+screen_width width -+global_alpha global alpha 0-255 0=transparent 255=opaque -+ -+/sys/devices/platform/omapdss/manager? directory: -+display Destination display -+name -+alpha_blending_enabled 0=off, 1=on -+trans_key_enabled 0=off, 1=on -+trans_key_type gfx-destination, video-source -+trans_key_value transparency color key (RGB24) -+default_color default background color (RGB24) -+ -+/sys/devices/platform/omapdss/display? directory: -+ctrl_name Controller name -+mirror 0=off, 1=on -+update_mode 0=off, 1=auto, 2=manual -+enabled 0=off, 1=on -+name -+rotate Rotation 0-3 for 0, 90, 180, 270 degrees -+timings Display timings (pixclock,xres/hfp/hbp/hsw,yres/vfp/vbp/vsw) -+ When writing, two special timings are accepted for tv-out: -+ "pal" and "ntsc" -+panel_name -+tear_elim Tearing elimination 0=off, 1=on -+ -+There are also some debugfs files at <debugfs>/omapdss/ which show information -+about clocks and registers. -+ -+Examples -+-------- -+ -+The following definitions have been made for the examples below: -+ -+ovl0=/sys/devices/platform/omapdss/overlay0 -+ovl1=/sys/devices/platform/omapdss/overlay1 -+ovl2=/sys/devices/platform/omapdss/overlay2 -+ -+mgr0=/sys/devices/platform/omapdss/manager0 -+mgr1=/sys/devices/platform/omapdss/manager1 -+ -+lcd=/sys/devices/platform/omapdss/display0 -+dvi=/sys/devices/platform/omapdss/display1 -+tv=/sys/devices/platform/omapdss/display2 -+ -+fb0=/sys/class/graphics/fb0 -+fb1=/sys/class/graphics/fb1 -+fb2=/sys/class/graphics/fb2 -+ -+Default setup on OMAP3 SDP -+-------------------------- -+ -+Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI -+and TV-out are not in use. The columns from left to right are: -+framebuffers, overlays, overlay managers, displays. Framebuffers are -+handled by omapfb, and the rest by the DSS. -+ -+FB0 --- GFX -\ DVI -+FB1 --- VID1 --+- LCD ---- LCD -+FB2 --- VID2 -/ TV ----- TV -+ -+Example: Switch from LCD to DVI -+---------------------- -+ -+w=`cat $dvi/timings | cut -d "," -f 2 | cut -d "/" -f 1` -+h=`cat $dvi/timings | cut -d "," -f 3 | cut -d "/" -f 1` -+ -+echo "0" > $lcd/enabled -+echo "" > $mgr0/display -+fbset -fb /dev/fb0 -xres $w -yres $h -vxres $w -vyres $h -+# at this point you have to switch the dvi/lcd dip-switch from the omap board -+echo "dvi" > $mgr0/display -+echo "1" > $dvi/enabled -+ -+After this the configuration looks like: -+ -+FB0 --- GFX -\ -- DVI -+FB1 --- VID1 --+- LCD -/ LCD -+FB2 --- VID2 -/ TV ----- TV -+ -+Example: Clone GFX overlay to LCD and TV -+------------------------------- -+ -+w=`cat $tv/timings | cut -d "," -f 2 | cut -d "/" -f 1` -+h=`cat $tv/timings | cut -d "," -f 3 | cut -d "/" -f 1` -+ -+echo "0" > $ovl0/enabled -+echo "0" > $ovl1/enabled -+ -+echo "" > $fb1/overlays -+echo "0,1" > $fb0/overlays -+ -+echo "$w,$h" > $ovl1/output_size -+echo "tv" > $ovl1/manager -+ -+echo "1" > $ovl0/enabled -+echo "1" > $ovl1/enabled -+ -+echo "1" > $tv/enabled -+ -+After this the configuration looks like (only relevant parts shown): -+ -+FB0 +-- GFX ---- LCD ---- LCD -+ \- VID1 ---- TV ---- TV -+ -+Misc notes -+---------- -+ -+OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator. -+ -+Using DSI DPLL to generate pixel clock it is possible produce the pixel clock -+of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI. -+ -+Rotation and mirroring currently only supports RGB565 and RGB8888 modes. VRFB -+does not support mirroring. -+ -+VRFB rotation requires much more memory than non-rotated framebuffer, so you -+probably need to increase your vram setting before using VRFB rotation. Also, -+many applications may not work with VRFB if they do not pay attention to all -+framebuffer parameters. -+ -+Kernel boot arguments -+--------------------- -+ -+vram=<size> -+ - Amount of total VRAM to preallocate. For example, "10M". omapfb -+ allocates memory for framebuffers from VRAM. -+ -+omapfb.mode=<display>:<mode>[,...] -+ - Default video mode for specified displays. For example, -+ "dvi:800x400MR-24@60". See drivers/video/modedb.c. -+ There are also two special modes: "pal" and "ntsc" that -+ can be used to tv out. -+ -+omapfb.vram=<fbnum>:<size>[@<physaddr>][,...] -+ - VRAM allocated for a framebuffer. Normally omapfb allocates vram -+ depending on the display size. With this you can manually allocate -+ more or define the physical address of each framebuffer. For example, -+ "1:4M" to allocate 4M for fb1. -+ -+omapfb.debug=<y|n> -+ - Enable debug printing. You have to have OMAPFB debug support enabled -+ in kernel config. -+ -+omapfb.test=<y|n> -+ - Draw test pattern to framebuffer whenever framebuffer settings change. -+ You need to have OMAPFB debug support enabled in kernel config. -+ -+omapfb.vrfb=<y|n> -+ - Use VRFB rotation for all framebuffers. -+ -+omapfb.rotate=<angle> -+ - Default rotation applied to all framebuffers. -+ 0 - 0 degree rotation -+ 1 - 90 degree rotation -+ 2 - 180 degree rotation -+ 3 - 270 degree rotation -+ -+omapfb.mirror=<y|n> -+ - Default mirror for all framebuffers. Only works with DMA rotation. -+ -+omapdss.def_disp=<display> -+ - Name of default display, to which all overlays will be connected. -+ Common examples are "lcd" or "tv". -+ -+omapdss.debug=<y|n> -+ - Enable debug printing. You have to have DSS debug support enabled in -+ kernel config. -+ -+TODO -+---- -+ -+DSS locking -+ -+Error checking -+- Lots of checks are missing or implemented just as BUG() -+ -+System DMA update for DSI -+- Can be used for RGB16 and RGB24P modes. Probably not for RGB24U (how -+ to skip the empty byte?) -+ -+OMAP1 support -+- Not sure if needed -+ ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -3848,6 +3848,23 @@ L: linux-omap@vger.kernel.org - S: Maintained - F: drivers/video/omap/ - -+OMAP DISPLAY SUBSYSTEM SUPPORT (DSS2) -+M: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+L: linux-fbdev-devel@lists.sourceforge.net (moderated for non-subscribers) -+L: linux-omap@vger.kernel.org -+S: Maintained -+F: drivers/video/omap2/dss/ -+F: drivers/video/omap2/vrfb.c -+F: drivers/video/omap2/vram.c -+F: Documentation/arm/OMAP/DSS -+ -+OMAP FRAMEBUFFER SUPPORT (FOR DSS2) -+M: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+L: linux-fbdev-devel@lists.sourceforge.net (moderated for non-subscribers) -+L: linux-omap@vger.kernel.org -+S: Maintained -+F: drivers/video/omap2/omapfb/ -+ - OMAP MMC SUPPORT - M: Jarkko Lavinen <jarkko.lavinen@nokia.com> - L: linux-omap@vger.kernel.org ---- a/arch/arm/configs/omap_3430sdp_defconfig -+++ b/arch/arm/configs/omap_3430sdp_defconfig -@@ -1336,10 +1336,33 @@ CONFIG_FB_CFB_IMAGEBLIT=y - # - # CONFIG_FB_S1D13XXX is not set - # CONFIG_FB_VIRTUAL is not set --CONFIG_FB_OMAP=y --# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set -+# CONFIG_FB_METRONOME is not set -+# CONFIG_FB_MB862XX is not set -+# CONFIG_FB_BROADSHEET is not set -+# CONFIG_FB_OMAP_LCD_VGA is not set - # CONFIG_FB_OMAP_BOOTLOADER_INIT is not set --CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2 -+CONFIG_OMAP2_VRAM=y -+CONFIG_OMAP2_VRFB=y -+CONFIG_OMAP2_DSS=y -+CONFIG_OMAP2_VRAM_SIZE=4 -+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y -+# CONFIG_OMAP2_DSS_RFBI is not set -+CONFIG_OMAP2_DSS_VENC=y -+# CONFIG_OMAP2_DSS_SDI is not set -+# CONFIG_OMAP2_DSS_DSI is not set -+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -+CONFIG_FB_OMAP2=y -+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y -+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -+CONFIG_FB_OMAP2_NUM_FBS=3 -+ -+# -+# OMAP2/3 Display Device Drivers -+# -+CONFIG_PANEL_GENERIC=y -+# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -+CONFIG_PANEL_SHARP_LS037V7DW01=y - # CONFIG_BACKLIGHT_LCD_SUPPORT is not set - - # ---- a/arch/arm/mach-omap1/board-nokia770.c -+++ b/arch/arm/mach-omap1/board-nokia770.c -@@ -14,6 +14,7 @@ - #include <linux/platform_device.h> - #include <linux/input.h> - #include <linux/clk.h> -+#include <linux/omapfb.h> - - #include <linux/spi/spi.h> - #include <linux/spi/ads7846.h> -@@ -32,7 +33,6 @@ - #include <mach/keypad.h> - #include <mach/common.h> - #include <mach/dsp_common.h> --#include <mach/omapfb.h> - #include <mach/hwa742.h> - #include <mach/lcd_mipid.h> - #include <mach/mmc.h> ---- a/arch/arm/mach-omap2/board-3430sdp.c -+++ b/arch/arm/mach-omap2/board-3430sdp.c -@@ -37,6 +37,7 @@ - #include <mach/common.h> - #include <mach/dma.h> - #include <mach/gpmc.h> -+#include <mach/display.h> - - #include <mach/control.h> - #include <mach/gpmc-smc91x.h> -@@ -152,31 +153,152 @@ static struct spi_board_info sdp3430_spi - }, - }; - --static struct platform_device sdp3430_lcd_device = { -- .name = "sdp2430_lcd", -- .id = -1, -+ -+#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8 -+#define SDP3430_LCD_PANEL_ENABLE_GPIO 5 -+ -+static unsigned backlight_gpio; -+static unsigned enable_gpio; -+static int lcd_enabled; -+static int dvi_enabled; -+ -+static void __init sdp3430_display_init(void) -+{ -+ int r; -+ -+ enable_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO; -+ backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO; -+ -+ r = gpio_request(enable_gpio, "LCD reset"); -+ if (r) { -+ printk(KERN_ERR "failed to get LCD reset GPIO\n"); -+ goto err0; -+ } -+ -+ r = gpio_request(backlight_gpio, "LCD Backlight"); -+ if (r) { -+ printk(KERN_ERR "failed to get LCD backlight GPIO\n"); -+ goto err1; -+ } -+ -+ gpio_direction_output(enable_gpio, 0); -+ gpio_direction_output(backlight_gpio, 0); -+ -+ return; -+err1: -+ gpio_free(enable_gpio); -+err0: -+ return; -+} -+ -+static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev) -+{ -+ if (dvi_enabled) { -+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); -+ return -EINVAL; -+ } -+ -+ gpio_direction_output(enable_gpio, 1); -+ gpio_direction_output(backlight_gpio, 1); -+ -+ lcd_enabled = 1; -+ -+ return 0; -+} -+ -+static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev) -+{ -+ lcd_enabled = 0; -+ -+ gpio_direction_output(enable_gpio, 0); -+ gpio_direction_output(backlight_gpio, 0); -+} -+ -+static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev) -+{ -+ if (lcd_enabled) { -+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); -+ return -EINVAL; -+ } -+ -+ dvi_enabled = 1; -+ -+ return 0; -+} -+ -+static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev) -+{ -+ dvi_enabled = 0; -+} -+ -+static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev) -+{ -+ return 0; -+} -+ -+static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev) -+{ -+} -+ -+ -+static struct omap_dss_device sdp3430_lcd_device = { -+ .name = "lcd", -+ .driver_name = "sharp_ls_panel", -+ .type = OMAP_DISPLAY_TYPE_DPI, -+ .phy.dpi.data_lines = 16, -+ .platform_enable = sdp3430_panel_enable_lcd, -+ .platform_disable = sdp3430_panel_disable_lcd, -+}; -+ -+static struct omap_dss_device sdp3430_dvi_device = { -+ .name = "dvi", -+ .driver_name = "generic_panel", -+ .type = OMAP_DISPLAY_TYPE_DPI, -+ .phy.dpi.data_lines = 24, -+ .platform_enable = sdp3430_panel_enable_dvi, -+ .platform_disable = sdp3430_panel_disable_dvi, -+}; -+ -+static struct omap_dss_device sdp3430_tv_device = { -+ .name = "tv", -+ .driver_name = "venc", -+ .type = OMAP_DISPLAY_TYPE_VENC, -+ .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, -+ .platform_enable = sdp3430_panel_enable_tv, -+ .platform_disable = sdp3430_panel_disable_tv, -+}; -+ -+ -+static struct omap_dss_device *sdp3430_dss_devices[] = { -+ &sdp3430_lcd_device, -+ &sdp3430_dvi_device, -+ &sdp3430_tv_device, - }; - --static struct regulator_consumer_supply sdp3430_vdac_supply = { -- .supply = "vdac", -- .dev = &sdp3430_lcd_device.dev, -+static struct omap_dss_board_info sdp3430_dss_data = { -+ .num_devices = ARRAY_SIZE(sdp3430_dss_devices), -+ .devices = sdp3430_dss_devices, -+ .default_device = &sdp3430_lcd_device, - }; - --static struct regulator_consumer_supply sdp3430_vdvi_supply = { -- .supply = "vdvi", -- .dev = &sdp3430_lcd_device.dev, -+static struct platform_device sdp3430_dss_device = { -+ .name = "omapdss", -+ .id = -1, -+ .dev = { -+ .platform_data = &sdp3430_dss_data, -+ }, - }; - --static struct platform_device *sdp3430_devices[] __initdata = { -- &sdp3430_lcd_device, -+static struct regulator_consumer_supply sdp3430_vdda_dac_supply = { -+ .supply = "vdda_dac", -+ .dev = &sdp3430_dss_device.dev, - }; - --static struct omap_lcd_config sdp3430_lcd_config __initdata = { -- .ctrl_name = "internal", -+static struct platform_device *sdp3430_devices[] __initdata = { -+ &sdp3430_dss_device, - }; - - static struct omap_board_config_kernel sdp3430_config[] __initdata = { -- { OMAP_TAG_LCD, &sdp3430_lcd_config }, - }; - - static void __init omap_3430sdp_init_irq(void) -@@ -392,22 +514,34 @@ static struct regulator_init_data sdp343 - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, -- .consumer_supplies = &sdp3430_vdac_supply, -+ .consumer_supplies = &sdp3430_vdda_dac_supply, - }; - - /* VPLL2 for digital video outputs */ -+static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = { -+ { -+ .supply = "vdvi", -+ .dev = &sdp3430_lcd_device.dev, -+ }, -+ { -+ .supply = "vdds_dsi", -+ .dev = &sdp3430_dss_device.dev, -+ } -+}; -+ - static struct regulator_init_data sdp3430_vpll2 = { - .constraints = { - .name = "VDVI", - .min_uV = 1800000, - .max_uV = 1800000, -+ .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -- .num_consumer_supplies = 1, -- .consumer_supplies = &sdp3430_vdvi_supply, -+ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vpll2_supplies), -+ .consumer_supplies = sdp3430_vpll2_supplies, - }; - - static struct twl4030_platform_data sdp3430_twldata = { -@@ -499,6 +633,7 @@ static void __init omap_3430sdp_init(voi - omap_serial_init(); - usb_musb_init(); - board_smc91x_init(); -+ sdp3430_display_init(); - enable_board_wakeup_source(); - } - ---- a/arch/arm/mach-omap2/clock24xx.c -+++ b/arch/arm/mach-omap2/clock24xx.c -@@ -116,10 +116,10 @@ static struct omap_clk omap24xx_clks[] = - CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), - CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), - /* DSS domain clocks */ -- CLK("omapfb", "ick", &dss_ick, CK_243X | CK_242X), -- CLK("omapfb", "dss1_fck", &dss1_fck, CK_243X | CK_242X), -- CLK("omapfb", "dss2_fck", &dss2_fck, CK_243X | CK_242X), -- CLK("omapfb", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), -+ CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X), -+ CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X), -+ CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X), -+ CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), - /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), ---- a/arch/arm/mach-omap2/clock34xx.c -+++ b/arch/arm/mach-omap2/clock34xx.c -@@ -236,13 +236,13 @@ static struct omap_clk omap34xx_clks[] = - CLK("omap_rng", "ick", &rng_ick, CK_343X), - CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), - CLK(NULL, "des1_ick", &des1_ick, CK_343X), -- CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), -- CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2), -- CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X), -- CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X), -- CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X), -- CLK("omapfb", "ick", &dss_ick_3430es1, CK_3430ES1), -- CLK("omapfb", "ick", &dss_ick_3430es2, CK_3430ES2), -+ CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), -+ CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2), -+ CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X), -+ CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X), -+ CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X), -+ CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), -+ CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2), - CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), - CLK(NULL, "cam_ick", &cam_ick, CK_343X), - CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), ---- a/arch/arm/mach-omap2/io.c -+++ b/arch/arm/mach-omap2/io.c -@@ -22,17 +22,18 @@ - #include <linux/init.h> - #include <linux/io.h> - #include <linux/clk.h> -+#include <linux/omapfb.h> - - #include <asm/tlb.h> - - #include <asm/mach/map.h> - - #include <mach/mux.h> --#include <mach/omapfb.h> - #include <mach/sram.h> - #include <mach/sdrc.h> - #include <mach/gpmc.h> - #include <mach/serial.h> -+#include <mach/vram.h> - - #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */ - #include "clock.h" -@@ -246,6 +247,7 @@ void __init omap2_map_common_io(void) - omap2_check_revision(); - omap_sram_init(); - omapfb_reserve_sdram(); -+ omap_vram_reserve_sdram(); - } - - /* ---- a/arch/arm/mach-omap2/sdrc.c -+++ b/arch/arm/mach-omap2/sdrc.c -@@ -133,3 +133,19 @@ void __init omap2_sdrc_init(struct omap_ - (1 << SDRC_POWER_PAGEPOLICY_SHIFT); - sdrc_write_reg(l, SDRC_POWER); - } -+ -+void omap2_sms_write_rot_control(u32 val, unsigned ctx) -+{ -+ sms_write_reg(val, SMS_ROT_CONTROL(ctx)); -+} -+ -+void omap2_sms_write_rot_size(u32 val, unsigned ctx) -+{ -+ sms_write_reg(val, SMS_ROT_SIZE(ctx)); -+} -+ -+void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx) -+{ -+ sms_write_reg(val, SMS_ROT_PHYSICAL_BA(ctx)); -+} -+ ---- a/arch/arm/plat-omap/fb.c -+++ b/arch/arm/plat-omap/fb.c -@@ -28,13 +28,13 @@ - #include <linux/platform_device.h> - #include <linux/bootmem.h> - #include <linux/io.h> -+#include <linux/omapfb.h> - - #include <mach/hardware.h> - #include <asm/mach/map.h> - - #include <mach/board.h> - #include <mach/sram.h> --#include <mach/omapfb.h> - - #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) - -@@ -327,7 +327,33 @@ static inline int omap_init_fb(void) - - arch_initcall(omap_init_fb); - --#else -+#elif defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) -+ -+static u64 omap_fb_dma_mask = ~(u32)0; -+static struct omapfb_platform_data omapfb_config; -+ -+static struct platform_device omap_fb_device = { -+ .name = "omapfb", -+ .id = -1, -+ .dev = { -+ .dma_mask = &omap_fb_dma_mask, -+ .coherent_dma_mask = ~(u32)0, -+ .platform_data = &omapfb_config, -+ }, -+ .num_resources = 0, -+}; -+ -+void omapfb_set_platform_data(struct omapfb_platform_data *data) -+{ -+ omapfb_config = *data; -+} -+ -+static inline int omap_init_fb(void) -+{ -+ return platform_device_register(&omap_fb_device); -+} -+ -+arch_initcall(omap_init_fb); - - void omapfb_reserve_sdram(void) {} - unsigned long omapfb_reserve_sram(unsigned long sram_pstart, -@@ -339,5 +365,16 @@ unsigned long omapfb_reserve_sram(unsign - return 0; - } - -+#else -+ -+void omapfb_reserve_sdram(void) {} -+unsigned long omapfb_reserve_sram(unsigned long sram_pstart, -+ unsigned long sram_vstart, -+ unsigned long sram_size, -+ unsigned long start_avail, -+ unsigned long size_avail) -+{ -+ return 0; -+} - - #endif ---- /dev/null -+++ b/arch/arm/plat-omap/include/mach/display.h -@@ -0,0 +1,540 @@ -+/* -+ * linux/include/asm-arm/arch-omap/display.h -+ * -+ * Copyright (C) 2008 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#ifndef __ASM_ARCH_OMAP_DISPLAY_H -+#define __ASM_ARCH_OMAP_DISPLAY_H -+ -+#include <linux/list.h> -+#include <linux/kobject.h> -+#include <linux/device.h> -+#include <asm/atomic.h> -+ -+#define DISPC_IRQ_FRAMEDONE (1 << 0) -+#define DISPC_IRQ_VSYNC (1 << 1) -+#define DISPC_IRQ_EVSYNC_EVEN (1 << 2) -+#define DISPC_IRQ_EVSYNC_ODD (1 << 3) -+#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) -+#define DISPC_IRQ_PROG_LINE_NUM (1 << 5) -+#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) -+#define DISPC_IRQ_GFX_END_WIN (1 << 7) -+#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) -+#define DISPC_IRQ_OCP_ERR (1 << 9) -+#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) -+#define DISPC_IRQ_VID1_END_WIN (1 << 11) -+#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) -+#define DISPC_IRQ_VID2_END_WIN (1 << 13) -+#define DISPC_IRQ_SYNC_LOST (1 << 14) -+#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) -+#define DISPC_IRQ_WAKEUP (1 << 16) -+ -+struct omap_dss_device; -+struct omap_overlay_manager; -+ -+enum omap_display_type { -+ OMAP_DISPLAY_TYPE_NONE = 0, -+ OMAP_DISPLAY_TYPE_DPI = 1 << 0, -+ OMAP_DISPLAY_TYPE_DBI = 1 << 1, -+ OMAP_DISPLAY_TYPE_SDI = 1 << 2, -+ OMAP_DISPLAY_TYPE_DSI = 1 << 3, -+ OMAP_DISPLAY_TYPE_VENC = 1 << 4, -+}; -+ -+enum omap_plane { -+ OMAP_DSS_GFX = 0, -+ OMAP_DSS_VIDEO1 = 1, -+ OMAP_DSS_VIDEO2 = 2 -+}; -+ -+enum omap_channel { -+ OMAP_DSS_CHANNEL_LCD = 0, -+ OMAP_DSS_CHANNEL_DIGIT = 1, -+}; -+ -+enum omap_color_mode { -+ OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ -+ OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ -+ OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ -+ OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ -+ OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */ -+ OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */ -+ OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */ -+ OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */ -+ OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */ -+ OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ -+ OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ -+ OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ -+ OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ -+ OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ -+ -+ OMAP_DSS_COLOR_GFX_OMAP3 = -+ OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 | -+ OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 | -+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 | -+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | -+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 | -+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, -+ -+ OMAP_DSS_COLOR_VID_OMAP3 = -+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 | -+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U | -+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 | -+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 | -+ OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY, -+}; -+ -+enum omap_lcd_display_type { -+ OMAP_DSS_LCD_DISPLAY_STN, -+ OMAP_DSS_LCD_DISPLAY_TFT, -+}; -+ -+enum omap_dss_load_mode { -+ OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, -+ OMAP_DSS_LOAD_CLUT_ONLY = 1, -+ OMAP_DSS_LOAD_FRAME_ONLY = 2, -+ OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, -+}; -+ -+enum omap_dss_trans_key_type { -+ OMAP_DSS_COLOR_KEY_GFX_DST = 0, -+ OMAP_DSS_COLOR_KEY_VID_SRC = 1, -+}; -+ -+enum omap_rfbi_te_mode { -+ OMAP_DSS_RFBI_TE_MODE_1 = 1, -+ OMAP_DSS_RFBI_TE_MODE_2 = 2, -+}; -+ -+enum omap_panel_config { -+ OMAP_DSS_LCD_IVS = 1<<0, -+ OMAP_DSS_LCD_IHS = 1<<1, -+ OMAP_DSS_LCD_IPC = 1<<2, -+ OMAP_DSS_LCD_IEO = 1<<3, -+ OMAP_DSS_LCD_RF = 1<<4, -+ OMAP_DSS_LCD_ONOFF = 1<<5, -+ -+ OMAP_DSS_LCD_TFT = 1<<20, -+}; -+ -+enum omap_dss_venc_type { -+ OMAP_DSS_VENC_TYPE_COMPOSITE, -+ OMAP_DSS_VENC_TYPE_SVIDEO, -+}; -+ -+enum omap_display_caps { -+ OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, -+}; -+ -+enum omap_dss_update_mode { -+ OMAP_DSS_UPDATE_DISABLED = 0, -+ OMAP_DSS_UPDATE_AUTO, -+ OMAP_DSS_UPDATE_MANUAL, -+}; -+ -+enum omap_dss_display_state { -+ OMAP_DSS_DISPLAY_DISABLED = 0, -+ OMAP_DSS_DISPLAY_ACTIVE, -+ OMAP_DSS_DISPLAY_SUSPENDED, -+}; -+ -+/* XXX perhaps this should be removed */ -+enum omap_dss_overlay_managers { -+ OMAP_DSS_OVL_MGR_LCD, -+ OMAP_DSS_OVL_MGR_TV, -+}; -+ -+enum omap_dss_rotation_type { -+ OMAP_DSS_ROT_DMA = 0, -+ OMAP_DSS_ROT_VRFB = 1, -+}; -+ -+enum omap_overlay_caps { -+ OMAP_DSS_OVL_CAP_SCALE = 1 << 0, -+ OMAP_DSS_OVL_CAP_DISPC = 1 << 1, -+}; -+ -+enum omap_overlay_manager_caps { -+ OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0, -+}; -+ -+/* RFBI */ -+ -+struct rfbi_timings { -+ int cs_on_time; -+ int cs_off_time; -+ int we_on_time; -+ int we_off_time; -+ int re_on_time; -+ int re_off_time; -+ int we_cycle_time; -+ int re_cycle_time; -+ int cs_pulse_width; -+ int access_time; -+ -+ int clk_div; -+ -+ u32 tim[5]; /* set by rfbi_convert_timings() */ -+ -+ int converted; -+}; -+ -+void omap_rfbi_write_command(const void *buf, u32 len); -+void omap_rfbi_read_data(void *buf, u32 len); -+void omap_rfbi_write_data(const void *buf, u32 len); -+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, -+ u16 x, u16 y, -+ u16 w, u16 h); -+int omap_rfbi_enable_te(bool enable, unsigned line); -+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, -+ unsigned hs_pulse_time, unsigned vs_pulse_time, -+ int hs_pol_inv, int vs_pol_inv, int extif_div); -+ -+/* DSI */ -+void dsi_bus_lock(void); -+void dsi_bus_unlock(void); -+int dsi_vc_dcs_write(int channel, u8 *data, int len); -+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len); -+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen); -+int dsi_vc_set_max_rx_packet_size(int channel, u16 len); -+int dsi_vc_send_null(int channel); -+int dsi_vc_send_bta_sync(int channel); -+ -+/* Board specific data */ -+struct omap_dss_board_info { -+ int (*get_last_off_on_transaction_id)(struct device *dev); -+ int num_devices; -+ struct omap_dss_device **devices; -+ struct omap_dss_device *default_device; -+}; -+ -+struct omap_video_timings { -+ /* Unit: pixels */ -+ u16 x_res; -+ /* Unit: pixels */ -+ u16 y_res; -+ /* Unit: KHz */ -+ u32 pixel_clock; -+ /* Unit: pixel clocks */ -+ u16 hsw; /* Horizontal synchronization pulse width */ -+ /* Unit: pixel clocks */ -+ u16 hfp; /* Horizontal front porch */ -+ /* Unit: pixel clocks */ -+ u16 hbp; /* Horizontal back porch */ -+ /* Unit: line clocks */ -+ u16 vsw; /* Vertical synchronization pulse width */ -+ /* Unit: line clocks */ -+ u16 vfp; /* Vertical front porch */ -+ /* Unit: line clocks */ -+ u16 vbp; /* Vertical back porch */ -+}; -+ -+#ifdef CONFIG_OMAP2_DSS_VENC -+/* Hardcoded timings for tv modes. Venc only uses these to -+ * identify the mode, and does not actually use the configs -+ * itself. However, the configs should be something that -+ * a normal monitor can also show */ -+const extern struct omap_video_timings omap_dss_pal_timings; -+const extern struct omap_video_timings omap_dss_ntsc_timings; -+#endif -+ -+struct omap_overlay_info { -+ bool enabled; -+ -+ u32 paddr; -+ void __iomem *vaddr; -+ u16 screen_width; -+ u16 width; -+ u16 height; -+ enum omap_color_mode color_mode; -+ u8 rotation; -+ enum omap_dss_rotation_type rotation_type; -+ bool mirror; -+ -+ u16 pos_x; -+ u16 pos_y; -+ u16 out_width; /* if 0, out_width == width */ -+ u16 out_height; /* if 0, out_height == height */ -+ u8 global_alpha; -+}; -+ -+struct omap_overlay { -+ struct kobject kobj; -+ struct list_head list; -+ -+ /* static fields */ -+ const char *name; -+ int id; -+ enum omap_color_mode supported_modes; -+ enum omap_overlay_caps caps; -+ -+ /* dynamic fields */ -+ struct omap_overlay_manager *manager; -+ struct omap_overlay_info info; -+ -+ /* if true, info has been changed, but not applied() yet */ -+ bool info_dirty; -+ -+ int (*set_manager)(struct omap_overlay *ovl, -+ struct omap_overlay_manager *mgr); -+ int (*unset_manager)(struct omap_overlay *ovl); -+ -+ int (*set_overlay_info)(struct omap_overlay *ovl, -+ struct omap_overlay_info *info); -+ void (*get_overlay_info)(struct omap_overlay *ovl, -+ struct omap_overlay_info *info); -+ -+ int (*wait_for_go)(struct omap_overlay *ovl); -+}; -+ -+struct omap_overlay_manager_info { -+ u32 default_color; -+ -+ enum omap_dss_trans_key_type trans_key_type; -+ u32 trans_key; -+ bool trans_enabled; -+ -+ bool alpha_enabled; -+}; -+ -+struct omap_overlay_manager { -+ struct kobject kobj; -+ struct list_head list; -+ -+ /* static fields */ -+ const char *name; -+ int id; -+ enum omap_overlay_manager_caps caps; -+ int num_overlays; -+ struct omap_overlay **overlays; -+ enum omap_display_type supported_displays; -+ -+ /* dynamic fields */ -+ struct omap_dss_device *device; -+ struct omap_overlay_manager_info info; -+ -+ bool device_changed; -+ /* if true, info has been changed but not applied() yet */ -+ bool info_dirty; -+ -+ int (*set_device)(struct omap_overlay_manager *mgr, -+ struct omap_dss_device *dssdev); -+ int (*unset_device)(struct omap_overlay_manager *mgr); -+ -+ int (*set_manager_info)(struct omap_overlay_manager *mgr, -+ struct omap_overlay_manager_info *info); -+ void (*get_manager_info)(struct omap_overlay_manager *mgr, -+ struct omap_overlay_manager_info *info); -+ -+ int (*apply)(struct omap_overlay_manager *mgr); -+ int (*wait_for_go)(struct omap_overlay_manager *mgr); -+}; -+ -+struct omap_dss_device { -+ struct device dev; -+ -+ enum omap_display_type type; -+ -+ union { -+ struct { -+ u8 data_lines; -+ } dpi; -+ -+ struct { -+ u8 channel; -+ u8 data_lines; -+ } rfbi; -+ -+ struct { -+ u8 datapairs; -+ } sdi; -+ -+ struct { -+ u8 clk_lane; -+ u8 clk_pol; -+ u8 data1_lane; -+ u8 data1_pol; -+ u8 data2_lane; -+ u8 data2_pol; -+ unsigned long lp_clk_hz; -+ unsigned long ddr_clk_hz; -+ -+ bool ext_te; -+ u8 ext_te_gpio; -+ } dsi; -+ -+ struct { -+ enum omap_dss_venc_type type; -+ bool invert_polarity; -+ } venc; -+ } phy; -+ -+ struct { -+ struct omap_video_timings timings; -+ -+ int acbi; /* ac-bias pin transitions per interrupt */ -+ /* Unit: line clocks */ -+ int acb; /* ac-bias pin frequency */ -+ -+ enum omap_panel_config config; -+ -+ u8 recommended_bpp; -+ -+ struct omap_dss_device *ctrl; -+ } panel; -+ -+ struct { -+ u8 pixel_size; -+ struct rfbi_timings rfbi_timings; -+ struct omap_dss_device *panel; -+ } ctrl; -+ -+ int reset_gpio; -+ -+ int max_backlight_level; -+ -+ const char *name; -+ -+ /* used to match device to driver */ -+ const char *driver_name; -+ -+ void *data; -+ -+ struct omap_dss_driver *driver; -+ -+ /* helper variable for driver suspend/resume */ -+ bool activate_after_resume; -+ -+ enum omap_display_caps caps; -+ -+ struct omap_overlay_manager *manager; -+ -+ enum omap_dss_display_state state; -+ -+ int (*enable)(struct omap_dss_device *dssdev); -+ void (*disable)(struct omap_dss_device *dssdev); -+ -+ int (*suspend)(struct omap_dss_device *dssdev); -+ int (*resume)(struct omap_dss_device *dssdev); -+ -+ void (*get_resolution)(struct omap_dss_device *dssdev, -+ u16 *xres, u16 *yres); -+ int (*get_recommended_bpp)(struct omap_dss_device *dssdev); -+ -+ int (*check_timings)(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings); -+ void (*set_timings)(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings); -+ void (*get_timings)(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings); -+ int (*update)(struct omap_dss_device *dssdev, -+ u16 x, u16 y, u16 w, u16 h); -+ int (*sync)(struct omap_dss_device *dssdev); -+ int (*wait_vsync)(struct omap_dss_device *dssdev); -+ -+ int (*set_update_mode)(struct omap_dss_device *dssdev, -+ enum omap_dss_update_mode); -+ enum omap_dss_update_mode (*get_update_mode) -+ (struct omap_dss_device *dssdev); -+ -+ int (*enable_te)(struct omap_dss_device *dssdev, bool enable); -+ int (*get_te)(struct omap_dss_device *dssdev); -+ -+ u8 (*get_rotate)(struct omap_dss_device *dssdev); -+ int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); -+ -+ bool (*get_mirror)(struct omap_dss_device *dssdev); -+ int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); -+ -+ int (*run_test)(struct omap_dss_device *dssdev, int test); -+ int (*memory_read)(struct omap_dss_device *dssdev, -+ void *buf, size_t size, -+ u16 x, u16 y, u16 w, u16 h); -+ -+ int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); -+ u32 (*get_wss)(struct omap_dss_device *dssdev); -+ -+ /* platform specific */ -+ int (*platform_enable)(struct omap_dss_device *dssdev); -+ void (*platform_disable)(struct omap_dss_device *dssdev); -+ int (*set_backlight)(struct omap_dss_device *dssdev, int level); -+ int (*get_backlight)(struct omap_dss_device *dssdev); -+}; -+ -+struct omap_dss_driver { -+ struct device_driver driver; -+ -+ int (*probe)(struct omap_dss_device *); -+ void (*remove)(struct omap_dss_device *); -+ -+ int (*enable)(struct omap_dss_device *display); -+ void (*disable)(struct omap_dss_device *display); -+ int (*suspend)(struct omap_dss_device *display); -+ int (*resume)(struct omap_dss_device *display); -+ int (*run_test)(struct omap_dss_device *display, int test); -+ -+ void (*setup_update)(struct omap_dss_device *dssdev, -+ u16 x, u16 y, u16 w, u16 h); -+ -+ int (*enable_te)(struct omap_dss_device *dssdev, bool enable); -+ int (*wait_for_te)(struct omap_dss_device *dssdev); -+ -+ u8 (*get_rotate)(struct omap_dss_device *dssdev); -+ int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); -+ -+ bool (*get_mirror)(struct omap_dss_device *dssdev); -+ int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); -+ -+ int (*memory_read)(struct omap_dss_device *dssdev, -+ void *buf, size_t size, -+ u16 x, u16 y, u16 w, u16 h); -+}; -+ -+int omap_dss_register_driver(struct omap_dss_driver *); -+void omap_dss_unregister_driver(struct omap_dss_driver *); -+ -+int omap_dss_register_device(struct omap_dss_device *); -+void omap_dss_unregister_device(struct omap_dss_device *); -+ -+void omap_dss_get_device(struct omap_dss_device *dssdev); -+void omap_dss_put_device(struct omap_dss_device *dssdev); -+#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) -+struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); -+struct omap_dss_device *omap_dss_find_device(void *data, -+ int (*match)(struct omap_dss_device *dssdev, void *data)); -+ -+int omap_dss_start_device(struct omap_dss_device *dssdev); -+void omap_dss_stop_device(struct omap_dss_device *dssdev); -+ -+int omap_dss_get_num_overlay_managers(void); -+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); -+ -+int omap_dss_get_num_overlays(void); -+struct omap_overlay *omap_dss_get_overlay(int num); -+ -+typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); -+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); -+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); -+ -+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout); -+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, -+ unsigned long timeout); -+ -+#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver) -+#define to_dss_device(x) container_of((x), struct omap_dss_device, dev) -+ -+#endif ---- a/arch/arm/plat-omap/include/mach/omapfb.h -+++ /dev/null -@@ -1,398 +0,0 @@ --/* -- * File: arch/arm/plat-omap/include/mach/omapfb.h -- * -- * Framebuffer driver for TI OMAP boards -- * -- * Copyright (C) 2004 Nokia Corporation -- * Author: Imre Deak <imre.deak@nokia.com> -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License as published by the -- * Free Software Foundation; either version 2 of the License, or (at your -- * option) any later version. -- * -- * This program is distributed in the hope that it will be useful, but -- * WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- * General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License along -- * with this program; if not, write to the Free Software Foundation, Inc., -- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -- */ -- --#ifndef __OMAPFB_H --#define __OMAPFB_H -- --#include <asm/ioctl.h> --#include <asm/types.h> -- --/* IOCTL commands. */ -- --#define OMAP_IOW(num, dtype) _IOW('O', num, dtype) --#define OMAP_IOR(num, dtype) _IOR('O', num, dtype) --#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype) --#define OMAP_IO(num) _IO('O', num) -- --#define OMAPFB_MIRROR OMAP_IOW(31, int) --#define OMAPFB_SYNC_GFX OMAP_IO(37) --#define OMAPFB_VSYNC OMAP_IO(38) --#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int) --#define OMAPFB_GET_CAPS OMAP_IOR(42, struct omapfb_caps) --#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int) --#define OMAPFB_LCD_TEST OMAP_IOW(45, int) --#define OMAPFB_CTRL_TEST OMAP_IOW(46, int) --#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old) --#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key) --#define OMAPFB_GET_COLOR_KEY OMAP_IOW(51, struct omapfb_color_key) --#define OMAPFB_SETUP_PLANE OMAP_IOW(52, struct omapfb_plane_info) --#define OMAPFB_QUERY_PLANE OMAP_IOW(53, struct omapfb_plane_info) --#define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window) --#define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info) --#define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info) -- --#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff --#define OMAPFB_CAPS_LCDC_MASK 0x00fff000 --#define OMAPFB_CAPS_PANEL_MASK 0xff000000 -- --#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000 --#define OMAPFB_CAPS_TEARSYNC 0x00002000 --#define OMAPFB_CAPS_PLANE_RELOCATE_MEM 0x00004000 --#define OMAPFB_CAPS_PLANE_SCALE 0x00008000 --#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000 --#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000 --#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000 --#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000 --#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000 -- --/* Values from DSP must map to lower 16-bits */ --#define OMAPFB_FORMAT_MASK 0x00ff --#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100 --#define OMAPFB_FORMAT_FLAG_TEARSYNC 0x0200 --#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC 0x0400 --#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY 0x0800 --#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY 0x1000 -- --#define OMAPFB_EVENT_READY 1 --#define OMAPFB_EVENT_DISABLED 2 -- --#define OMAPFB_MEMTYPE_SDRAM 0 --#define OMAPFB_MEMTYPE_SRAM 1 --#define OMAPFB_MEMTYPE_MAX 1 -- --enum omapfb_color_format { -- OMAPFB_COLOR_RGB565 = 0, -- OMAPFB_COLOR_YUV422, -- OMAPFB_COLOR_YUV420, -- OMAPFB_COLOR_CLUT_8BPP, -- OMAPFB_COLOR_CLUT_4BPP, -- OMAPFB_COLOR_CLUT_2BPP, -- OMAPFB_COLOR_CLUT_1BPP, -- OMAPFB_COLOR_RGB444, -- OMAPFB_COLOR_YUY422, --}; -- --struct omapfb_update_window { -- __u32 x, y; -- __u32 width, height; -- __u32 format; -- __u32 out_x, out_y; -- __u32 out_width, out_height; -- __u32 reserved[8]; --}; -- --struct omapfb_update_window_old { -- __u32 x, y; -- __u32 width, height; -- __u32 format; --}; -- --enum omapfb_plane { -- OMAPFB_PLANE_GFX = 0, -- OMAPFB_PLANE_VID1, -- OMAPFB_PLANE_VID2, --}; -- --enum omapfb_channel_out { -- OMAPFB_CHANNEL_OUT_LCD = 0, -- OMAPFB_CHANNEL_OUT_DIGIT, --}; -- --struct omapfb_plane_info { -- __u32 pos_x; -- __u32 pos_y; -- __u8 enabled; -- __u8 channel_out; -- __u8 mirror; -- __u8 reserved1; -- __u32 out_width; -- __u32 out_height; -- __u32 reserved2[12]; --}; -- --struct omapfb_mem_info { -- __u32 size; -- __u8 type; -- __u8 reserved[3]; --}; -- --struct omapfb_caps { -- __u32 ctrl; -- __u32 plane_color; -- __u32 wnd_color; --}; -- --enum omapfb_color_key_type { -- OMAPFB_COLOR_KEY_DISABLED = 0, -- OMAPFB_COLOR_KEY_GFX_DST, -- OMAPFB_COLOR_KEY_VID_SRC, --}; -- --struct omapfb_color_key { -- __u8 channel_out; -- __u32 background; -- __u32 trans_key; -- __u8 key_type; --}; -- --enum omapfb_update_mode { -- OMAPFB_UPDATE_DISABLED = 0, -- OMAPFB_AUTO_UPDATE, -- OMAPFB_MANUAL_UPDATE --}; -- --#ifdef __KERNEL__ -- --#include <linux/completion.h> --#include <linux/interrupt.h> --#include <linux/fb.h> --#include <linux/mutex.h> -- --#include <mach/board.h> -- --#define OMAP_LCDC_INV_VSYNC 0x0001 --#define OMAP_LCDC_INV_HSYNC 0x0002 --#define OMAP_LCDC_INV_PIX_CLOCK 0x0004 --#define OMAP_LCDC_INV_OUTPUT_EN 0x0008 --#define OMAP_LCDC_HSVS_RISING_EDGE 0x0010 --#define OMAP_LCDC_HSVS_OPPOSITE 0x0020 -- --#define OMAP_LCDC_SIGNAL_MASK 0x003f -- --#define OMAP_LCDC_PANEL_TFT 0x0100 -- --#define OMAPFB_PLANE_XRES_MIN 8 --#define OMAPFB_PLANE_YRES_MIN 8 -- --#ifdef CONFIG_ARCH_OMAP1 --#define OMAPFB_PLANE_NUM 1 --#else --#define OMAPFB_PLANE_NUM 3 --#endif -- --struct omapfb_device; -- --struct lcd_panel { -- const char *name; -- int config; /* TFT/STN, signal inversion */ -- int bpp; /* Pixel format in fb mem */ -- int data_lines; /* Lines on LCD HW interface */ -- -- int x_res, y_res; -- int pixel_clock; /* In kHz */ -- int hsw; /* Horizontal synchronization -- pulse width */ -- int hfp; /* Horizontal front porch */ -- int hbp; /* Horizontal back porch */ -- int vsw; /* Vertical synchronization -- pulse width */ -- int vfp; /* Vertical front porch */ -- int vbp; /* Vertical back porch */ -- int acb; /* ac-bias pin frequency */ -- int pcd; /* pixel clock divider. -- Obsolete use pixel_clock instead */ -- -- int (*init) (struct lcd_panel *panel, -- struct omapfb_device *fbdev); -- void (*cleanup) (struct lcd_panel *panel); -- int (*enable) (struct lcd_panel *panel); -- void (*disable) (struct lcd_panel *panel); -- unsigned long (*get_caps) (struct lcd_panel *panel); -- int (*set_bklight_level)(struct lcd_panel *panel, -- unsigned int level); -- unsigned int (*get_bklight_level)(struct lcd_panel *panel); -- unsigned int (*get_bklight_max) (struct lcd_panel *panel); -- int (*run_test) (struct lcd_panel *panel, int test_num); --}; -- --struct extif_timings { -- int cs_on_time; -- int cs_off_time; -- int we_on_time; -- int we_off_time; -- int re_on_time; -- int re_off_time; -- int we_cycle_time; -- int re_cycle_time; -- int cs_pulse_width; -- int access_time; -- -- int clk_div; -- -- u32 tim[5]; /* set by extif->convert_timings */ -- -- int converted; --}; -- --struct lcd_ctrl_extif { -- int (*init) (struct omapfb_device *fbdev); -- void (*cleanup) (void); -- void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div); -- unsigned long (*get_max_tx_rate)(void); -- int (*convert_timings) (struct extif_timings *timings); -- void (*set_timings) (const struct extif_timings *timings); -- void (*set_bits_per_cycle)(int bpc); -- void (*write_command) (const void *buf, unsigned int len); -- void (*read_data) (void *buf, unsigned int len); -- void (*write_data) (const void *buf, unsigned int len); -- void (*transfer_area) (int width, int height, -- void (callback)(void * data), void *data); -- int (*setup_tearsync) (unsigned pin_cnt, -- unsigned hs_pulse_time, unsigned vs_pulse_time, -- int hs_pol_inv, int vs_pol_inv, int div); -- int (*enable_tearsync) (int enable, unsigned line); -- -- unsigned long max_transmit_size; --}; -- --struct omapfb_notifier_block { -- struct notifier_block nb; -- void *data; -- int plane_idx; --}; -- --typedef int (*omapfb_notifier_callback_t)(struct notifier_block *, -- unsigned long event, -- void *fbi); -- --struct omapfb_mem_region { -- u32 paddr; -- void __iomem *vaddr; -- unsigned long size; -- u8 type; /* OMAPFB_PLANE_MEM_* */ -- unsigned alloc:1; /* allocated by the driver */ -- unsigned map:1; /* kernel mapped by the driver */ --}; -- --struct omapfb_mem_desc { -- int region_cnt; -- struct omapfb_mem_region region[OMAPFB_PLANE_NUM]; --}; -- --struct lcd_ctrl { -- const char *name; -- void *data; -- -- int (*init) (struct omapfb_device *fbdev, -- int ext_mode, -- struct omapfb_mem_desc *req_md); -- void (*cleanup) (void); -- void (*bind_client) (struct omapfb_notifier_block *nb); -- void (*get_caps) (int plane, struct omapfb_caps *caps); -- int (*set_update_mode)(enum omapfb_update_mode mode); -- enum omapfb_update_mode (*get_update_mode)(void); -- int (*setup_plane) (int plane, int channel_out, -- unsigned long offset, -- int screen_width, -- int pos_x, int pos_y, int width, -- int height, int color_mode); -- int (*set_rotate) (int angle); -- int (*setup_mem) (int plane, size_t size, -- int mem_type, unsigned long *paddr); -- int (*mmap) (struct fb_info *info, -- struct vm_area_struct *vma); -- int (*set_scale) (int plane, -- int orig_width, int orig_height, -- int out_width, int out_height); -- int (*enable_plane) (int plane, int enable); -- int (*update_window) (struct fb_info *fbi, -- struct omapfb_update_window *win, -- void (*callback)(void *), -- void *callback_data); -- void (*sync) (void); -- void (*suspend) (void); -- void (*resume) (void); -- int (*run_test) (int test_num); -- int (*setcolreg) (u_int regno, u16 red, u16 green, -- u16 blue, u16 transp, -- int update_hw_mem); -- int (*set_color_key) (struct omapfb_color_key *ck); -- int (*get_color_key) (struct omapfb_color_key *ck); --}; -- --enum omapfb_state { -- OMAPFB_DISABLED = 0, -- OMAPFB_SUSPENDED= 99, -- OMAPFB_ACTIVE = 100 --}; -- --struct omapfb_plane_struct { -- int idx; -- struct omapfb_plane_info info; -- enum omapfb_color_format color_mode; -- struct omapfb_device *fbdev; --}; -- --struct omapfb_device { -- int state; -- int ext_lcdc; /* Using external -- LCD controller */ -- struct mutex rqueue_mutex; -- -- int palette_size; -- u32 pseudo_palette[17]; -- -- struct lcd_panel *panel; /* LCD panel */ -- const struct lcd_ctrl *ctrl; /* LCD controller */ -- const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */ -- struct lcd_ctrl_extif *ext_if; /* LCD ctrl external -- interface */ -- struct device *dev; -- struct fb_var_screeninfo new_var; /* for mode changes */ -- -- struct omapfb_mem_desc mem_desc; -- struct fb_info *fb_info[OMAPFB_PLANE_NUM]; --}; -- --struct omapfb_platform_data { -- struct omap_lcd_config lcd; -- struct omapfb_mem_desc mem_desc; -- void *ctrl_platform_data; --}; -- --#ifdef CONFIG_ARCH_OMAP1 --extern struct lcd_ctrl omap1_lcd_ctrl; --#else --extern struct lcd_ctrl omap2_disp_ctrl; --#endif -- --extern void omapfb_reserve_sdram(void); --extern void omapfb_register_panel(struct lcd_panel *panel); --extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval); --extern void omapfb_notify_clients(struct omapfb_device *fbdev, -- unsigned long event); --extern int omapfb_register_client(struct omapfb_notifier_block *nb, -- omapfb_notifier_callback_t callback, -- void *callback_data); --extern int omapfb_unregister_client(struct omapfb_notifier_block *nb); --extern int omapfb_update_window_async(struct fb_info *fbi, -- struct omapfb_update_window *win, -- void (*callback)(void *), -- void *callback_data); -- --/* in arch/arm/plat-omap/fb.c */ --extern void omapfb_set_ctrl_platform_data(void *pdata); -- --#endif /* __KERNEL__ */ -- --#endif /* __OMAPFB_H */ ---- a/arch/arm/plat-omap/include/mach/sdrc.h -+++ b/arch/arm/plat-omap/include/mach/sdrc.h -@@ -88,7 +88,10 @@ - - /* SMS register offsets - read/write with sms_{read,write}_reg() */ - --#define SMS_SYSCONFIG 0x010 -+#define SMS_SYSCONFIG 0x010 -+#define SMS_ROT_CONTROL(context) (0x180 + 0x10 * context) -+#define SMS_ROT_SIZE(context) (0x184 + 0x10 * context) -+#define SMS_ROT_PHYSICAL_BA(context) (0x188 + 0x10 * context) - /* REVISIT: fill in other SMS registers here */ - - -@@ -121,6 +124,10 @@ int omap2_sdrc_get_params(unsigned long - struct omap_sdrc_params **sdrc_cs0, - struct omap_sdrc_params **sdrc_cs1); - -+void omap2_sms_write_rot_control(u32 val, unsigned ctx); -+void omap2_sms_write_rot_size(u32 val, unsigned ctx); -+void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx); -+ - #ifdef CONFIG_ARCH_OMAP2 - - struct memory_timings { ---- /dev/null -+++ b/arch/arm/plat-omap/include/mach/vram.h -@@ -0,0 +1,63 @@ -+/* -+ * VRAM manager for OMAP -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#ifndef __OMAP_VRAM_H__ -+#define __OMAP_VRAM_H__ -+ -+#include <linux/autoconf.h> -+#include <linux/types.h> -+ -+#define OMAP_VRAM_MEMTYPE_SDRAM 0 -+#define OMAP_VRAM_MEMTYPE_SRAM 1 -+#define OMAP_VRAM_MEMTYPE_MAX 1 -+ -+extern int omap_vram_add_region(unsigned long paddr, size_t size); -+extern int omap_vram_free(unsigned long paddr, size_t size); -+extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr); -+extern int omap_vram_reserve(unsigned long paddr, size_t size); -+extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram, -+ unsigned long *largest_free_block); -+ -+#ifdef CONFIG_OMAP2_VRAM -+extern void omap_vram_set_sdram_vram(u32 size, u32 start); -+extern void omap_vram_set_sram_vram(u32 size, u32 start); -+ -+extern void omap_vram_reserve_sdram(void); -+extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart, -+ unsigned long sram_vstart, -+ unsigned long sram_size, -+ unsigned long pstart_avail, -+ unsigned long size_avail); -+#else -+static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { } -+static inline void omap_vram_set_sram_vram(u32 size, u32 start) { } -+ -+static inline void omap_vram_reserve_sdram(void) { } -+static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart, -+ unsigned long sram_vstart, -+ unsigned long sram_size, -+ unsigned long pstart_avail, -+ unsigned long size_avail) -+{ -+ return 0; -+} -+#endif -+ -+#endif ---- /dev/null -+++ b/arch/arm/plat-omap/include/mach/vrfb.h -@@ -0,0 +1,46 @@ -+/* -+ * VRFB Rotation Engine -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#ifndef __OMAP_VRFB_H__ -+#define __OMAP_VRFB_H__ -+ -+#define OMAP_VRFB_LINE_LEN 2048 -+ -+struct vrfb { -+ u8 context; -+ void __iomem *vaddr[4]; -+ unsigned long paddr[4]; -+ u16 xoffset; -+ u16 yoffset; -+ u8 bytespp; -+}; -+ -+extern int omap_vrfb_request_ctx(struct vrfb *vrfb); -+extern void omap_vrfb_release_ctx(struct vrfb *vrfb); -+extern void omap_vrfb_suspend_ctx(struct vrfb *vrfb); -+extern void omap_vrfb_resume_ctx(struct vrfb *vrfb); -+extern void omap_vrfb_adjust_size(u16 *width, u16 *height, -+ u8 bytespp); -+extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, -+ u16 width, u16 height, -+ unsigned bytespp, bool yuv_mode); -+extern void omap_vrfb_restore_context(void); -+ -+#endif /* __VRFB_H */ ---- a/arch/arm/plat-omap/sram.c -+++ b/arch/arm/plat-omap/sram.c -@@ -28,6 +28,7 @@ - #include <mach/sram.h> - #include <mach/board.h> - #include <mach/cpu.h> -+#include <mach/vram.h> - - #include <mach/control.h> - -@@ -185,6 +186,13 @@ void __init omap_detect_sram(void) - omap_sram_start + SRAM_BOOTLOADER_SZ, - omap_sram_size - SRAM_BOOTLOADER_SZ); - omap_sram_size -= reserved; -+ -+ reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base, -+ omap_sram_size, -+ omap_sram_start + SRAM_BOOTLOADER_SZ, -+ omap_sram_size - SRAM_BOOTLOADER_SZ); -+ omap_sram_size -= reserved; -+ - omap_sram_ceil = omap_sram_base + omap_sram_size; - } - ---- a/drivers/video/Kconfig -+++ b/drivers/video/Kconfig -@@ -2161,6 +2161,7 @@ config FB_BROADSHEET - a bridge adapter. - - source "drivers/video/omap/Kconfig" -+source "drivers/video/omap2/Kconfig" - - source "drivers/video/backlight/Kconfig" - source "drivers/video/display/Kconfig" ---- a/drivers/video/Makefile -+++ b/drivers/video/Makefile -@@ -124,6 +124,7 @@ obj-$(CONFIG_FB_SM501) += sm5 - obj-$(CONFIG_FB_XILINX) += xilinxfb.o - obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o - obj-$(CONFIG_FB_OMAP) += omap/ -+obj-y += omap2/ - obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o - obj-$(CONFIG_FB_CARMINE) += carminefb.o - obj-$(CONFIG_FB_MB862XX) += mb862xx/ ---- a/drivers/video/omap/Kconfig -+++ b/drivers/video/omap/Kconfig -@@ -1,6 +1,7 @@ - config FB_OMAP - tristate "OMAP frame buffer support (EXPERIMENTAL)" -- depends on FB && ARCH_OMAP -+ depends on FB && ARCH_OMAP && (OMAP2_DSS = "n") -+ - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT -@@ -72,7 +73,7 @@ config FB_OMAP_LCD_MIPID - - config FB_OMAP_BOOTLOADER_INIT - bool "Check bootloader initialization" -- depends on FB_OMAP -+ depends on FB_OMAP || FB_OMAP2 - help - Say Y here if you want to enable checking if the bootloader has - already initialized the display controller. In this case the ---- a/drivers/video/omap/blizzard.c -+++ b/drivers/video/omap/blizzard.c -@@ -27,9 +27,9 @@ - #include <linux/clk.h> - - #include <mach/dma.h> --#include <mach/omapfb.h> - #include <mach/blizzard.h> - -+#include "omapfb.h" - #include "dispc.h" - - #define MODULE_NAME "blizzard" ---- a/drivers/video/omap/dispc.c -+++ b/drivers/video/omap/dispc.c -@@ -24,11 +24,12 @@ - #include <linux/vmalloc.h> - #include <linux/clk.h> - #include <linux/io.h> -+#include <linux/platform_device.h> - - #include <mach/sram.h> --#include <mach/omapfb.h> - #include <mach/board.h> - -+#include "omapfb.h" - #include "dispc.h" - - #define MODULE_NAME "dispc" -@@ -188,6 +189,11 @@ static struct { - struct omapfb_color_key color_key; - } dispc; - -+static struct platform_device omapdss_device = { -+ .name = "omapdss", -+ .id = -1, -+}; -+ - static void enable_lcd_clocks(int enable); - - static void inline dispc_write_reg(int idx, u32 val) -@@ -907,20 +913,20 @@ static irqreturn_t omap_dispc_irq_handle - - static int get_dss_clocks(void) - { -- dispc.dss_ick = clk_get(dispc.fbdev->dev, "ick"); -+ dispc.dss_ick = clk_get(&omapdss_device.dev, "ick"); - if (IS_ERR(dispc.dss_ick)) { - dev_err(dispc.fbdev->dev, "can't get ick\n"); - return PTR_ERR(dispc.dss_ick); - } - -- dispc.dss1_fck = clk_get(dispc.fbdev->dev, "dss1_fck"); -+ dispc.dss1_fck = clk_get(&omapdss_device.dev, "dss1_fck"); - if (IS_ERR(dispc.dss1_fck)) { - dev_err(dispc.fbdev->dev, "can't get dss1_fck\n"); - clk_put(dispc.dss_ick); - return PTR_ERR(dispc.dss1_fck); - } - -- dispc.dss_54m_fck = clk_get(dispc.fbdev->dev, "tv_fck"); -+ dispc.dss_54m_fck = clk_get(&omapdss_device.dev, "tv_fck"); - if (IS_ERR(dispc.dss_54m_fck)) { - dev_err(dispc.fbdev->dev, "can't get tv_fck\n"); - clk_put(dispc.dss_ick); -@@ -1371,6 +1377,12 @@ static int omap_dispc_init(struct omapfb - int skip_init = 0; - int i; - -+ r = platform_device_register(&omapdss_device); -+ if (r) { -+ dev_err(fbdev->dev, "can't register omapdss device\n"); -+ return r; -+ } -+ - memset(&dispc, 0, sizeof(dispc)); - - dispc.base = ioremap(DISPC_BASE, SZ_1K); -@@ -1508,6 +1520,7 @@ static void omap_dispc_cleanup(void) - free_irq(INT_24XX_DSS_IRQ, dispc.fbdev); - put_dss_clocks(); - iounmap(dispc.base); -+ platform_device_unregister(&omapdss_device); - } - - const struct lcd_ctrl omap2_int_ctrl = { ---- a/drivers/video/omap/hwa742.c -+++ b/drivers/video/omap/hwa742.c -@@ -27,8 +27,8 @@ - #include <linux/clk.h> - - #include <mach/dma.h> --#include <mach/omapfb.h> - #include <mach/hwa742.h> -+#include "omapfb.h" - - #define HWA742_REV_CODE_REG 0x0 - #define HWA742_CONFIG_REG 0x2 ---- a/drivers/video/omap/lcd_2430sdp.c -+++ b/drivers/video/omap/lcd_2430sdp.c -@@ -28,9 +28,10 @@ - #include <linux/i2c/twl4030.h> - - #include <mach/mux.h> --#include <mach/omapfb.h> - #include <asm/mach-types.h> - -+#include "omapfb.h" -+ - #define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91 - #define SDP2430_LCD_PANEL_ENABLE_GPIO 154 - #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 24 ---- a/drivers/video/omap/lcd_ams_delta.c -+++ b/drivers/video/omap/lcd_ams_delta.c -@@ -27,7 +27,8 @@ - - #include <mach/board-ams-delta.h> - #include <mach/hardware.h> --#include <mach/omapfb.h> -+ -+#include "omapfb.h" - - #define AMS_DELTA_DEFAULT_CONTRAST 112 - ---- a/drivers/video/omap/lcd_apollon.c -+++ b/drivers/video/omap/lcd_apollon.c -@@ -26,7 +26,8 @@ - - #include <mach/gpio.h> - #include <mach/mux.h> --#include <mach/omapfb.h> -+ -+#include "omapfb.h" - - /* #define USE_35INCH_LCD 1 */ - ---- a/drivers/video/omap/lcd_h3.c -+++ b/drivers/video/omap/lcd_h3.c -@@ -24,7 +24,7 @@ - #include <linux/i2c/tps65010.h> - - #include <mach/gpio.h> --#include <mach/omapfb.h> -+#include "omapfb.h" - - #define MODULE_NAME "omapfb-lcd_h3" - ---- a/drivers/video/omap/lcd_h4.c -+++ b/drivers/video/omap/lcd_h4.c -@@ -22,7 +22,7 @@ - #include <linux/module.h> - #include <linux/platform_device.h> - --#include <mach/omapfb.h> -+#include "omapfb.h" - - static int h4_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev) - { ---- a/drivers/video/omap/lcd_inn1510.c -+++ b/drivers/video/omap/lcd_inn1510.c -@@ -24,7 +24,7 @@ - #include <linux/io.h> - - #include <mach/fpga.h> --#include <mach/omapfb.h> -+#include "omapfb.h" - - static int innovator1510_panel_init(struct lcd_panel *panel, - struct omapfb_device *fbdev) ---- a/drivers/video/omap/lcd_inn1610.c -+++ b/drivers/video/omap/lcd_inn1610.c -@@ -23,7 +23,7 @@ - #include <linux/platform_device.h> - - #include <mach/gpio.h> --#include <mach/omapfb.h> -+#include "omapfb.h" - - #define MODULE_NAME "omapfb-lcd_h3" - ---- a/drivers/video/omap/lcd_ldp.c -+++ b/drivers/video/omap/lcd_ldp.c -@@ -28,9 +28,10 @@ - - #include <mach/gpio.h> - #include <mach/mux.h> --#include <mach/omapfb.h> - #include <asm/mach-types.h> - -+#include "omapfb.h" -+ - #define LCD_PANEL_BACKLIGHT_GPIO (15 + OMAP_MAX_GPIO_LINES) - #define LCD_PANEL_ENABLE_GPIO (7 + OMAP_MAX_GPIO_LINES) - ---- a/drivers/video/omap/lcd_mipid.c -+++ b/drivers/video/omap/lcd_mipid.c -@@ -23,9 +23,10 @@ - #include <linux/workqueue.h> - #include <linux/spi/spi.h> - --#include <mach/omapfb.h> - #include <mach/lcd_mipid.h> - -+#include "omapfb.h" -+ - #define MIPID_MODULE_NAME "lcd_mipid" - - #define MIPID_CMD_READ_DISP_ID 0x04 ---- a/drivers/video/omap/lcd_omap2evm.c -+++ b/drivers/video/omap/lcd_omap2evm.c -@@ -27,9 +27,10 @@ - #include <linux/i2c/twl4030.h> - - #include <mach/mux.h> --#include <mach/omapfb.h> - #include <asm/mach-types.h> - -+#include "omapfb.h" -+ - #define LCD_PANEL_ENABLE_GPIO 154 - #define LCD_PANEL_LR 128 - #define LCD_PANEL_UD 129 ---- a/drivers/video/omap/lcd_omap3beagle.c -+++ b/drivers/video/omap/lcd_omap3beagle.c -@@ -26,9 +26,10 @@ - #include <linux/i2c/twl4030.h> - - #include <mach/mux.h> --#include <mach/omapfb.h> - #include <asm/mach-types.h> - -+#include "omapfb.h" -+ - #define LCD_PANEL_ENABLE_GPIO 170 - - static int omap3beagle_panel_init(struct lcd_panel *panel, ---- a/drivers/video/omap/lcd_omap3evm.c -+++ b/drivers/video/omap/lcd_omap3evm.c -@@ -26,9 +26,10 @@ - #include <linux/i2c/twl4030.h> - - #include <mach/mux.h> --#include <mach/omapfb.h> - #include <asm/mach-types.h> - -+#include "omapfb.h" -+ - #define LCD_PANEL_ENABLE_GPIO 153 - #define LCD_PANEL_LR 2 - #define LCD_PANEL_UD 3 ---- a/drivers/video/omap/lcd_osk.c -+++ b/drivers/video/omap/lcd_osk.c -@@ -25,7 +25,7 @@ - - #include <mach/gpio.h> - #include <mach/mux.h> --#include <mach/omapfb.h> -+#include "omapfb.h" - - static int osk_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev) - { ---- a/drivers/video/omap/lcd_overo.c -+++ b/drivers/video/omap/lcd_overo.c -@@ -25,9 +25,10 @@ - - #include <mach/gpio.h> - #include <mach/mux.h> --#include <mach/omapfb.h> - #include <asm/mach-types.h> - -+#include "omapfb.h" -+ - #define LCD_ENABLE 144 - - static int overo_panel_init(struct lcd_panel *panel, ---- a/drivers/video/omap/lcd_palmte.c -+++ b/drivers/video/omap/lcd_palmte.c -@@ -24,7 +24,7 @@ - #include <linux/io.h> - - #include <mach/fpga.h> --#include <mach/omapfb.h> -+#include "omapfb.h" - - static int palmte_panel_init(struct lcd_panel *panel, - struct omapfb_device *fbdev) ---- a/drivers/video/omap/lcd_palmtt.c -+++ b/drivers/video/omap/lcd_palmtt.c -@@ -30,7 +30,7 @@ GPIO13 - screen blanking - #include <linux/io.h> - - #include <mach/gpio.h> --#include <mach/omapfb.h> -+#include "omapfb.h" - - static int palmtt_panel_init(struct lcd_panel *panel, - struct omapfb_device *fbdev) ---- a/drivers/video/omap/lcd_palmz71.c -+++ b/drivers/video/omap/lcd_palmz71.c -@@ -24,7 +24,7 @@ - #include <linux/platform_device.h> - #include <linux/io.h> - --#include <mach/omapfb.h> -+#include "omapfb.h" - - static int palmz71_panel_init(struct lcd_panel *panel, - struct omapfb_device *fbdev) ---- a/drivers/video/omap/lcdc.c -+++ b/drivers/video/omap/lcdc.c -@@ -30,10 +30,11 @@ - #include <linux/clk.h> - - #include <mach/dma.h> --#include <mach/omapfb.h> - - #include <asm/mach-types.h> - -+#include "omapfb.h" -+ - #include "lcdc.h" - - #define MODULE_NAME "lcdc" ---- /dev/null -+++ b/drivers/video/omap/omapfb.h -@@ -0,0 +1,227 @@ -+/* -+ * File: drivers/video/omap/omapfb.h -+ * -+ * Framebuffer driver for TI OMAP boards -+ * -+ * Copyright (C) 2004 Nokia Corporation -+ * Author: Imre Deak <imre.deak@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#ifndef __OMAPFB_H -+#define __OMAPFB_H -+ -+#include <linux/fb.h> -+#include <linux/mutex.h> -+#include <linux/omapfb.h> -+ -+#define OMAPFB_EVENT_READY 1 -+#define OMAPFB_EVENT_DISABLED 2 -+ -+#define OMAP_LCDC_INV_VSYNC 0x0001 -+#define OMAP_LCDC_INV_HSYNC 0x0002 -+#define OMAP_LCDC_INV_PIX_CLOCK 0x0004 -+#define OMAP_LCDC_INV_OUTPUT_EN 0x0008 -+#define OMAP_LCDC_HSVS_RISING_EDGE 0x0010 -+#define OMAP_LCDC_HSVS_OPPOSITE 0x0020 -+ -+#define OMAP_LCDC_SIGNAL_MASK 0x003f -+ -+#define OMAP_LCDC_PANEL_TFT 0x0100 -+ -+#define OMAPFB_PLANE_XRES_MIN 8 -+#define OMAPFB_PLANE_YRES_MIN 8 -+ -+struct omapfb_device; -+ -+struct lcd_panel { -+ const char *name; -+ int config; /* TFT/STN, signal inversion */ -+ int bpp; /* Pixel format in fb mem */ -+ int data_lines; /* Lines on LCD HW interface */ -+ -+ int x_res, y_res; -+ int pixel_clock; /* In kHz */ -+ int hsw; /* Horizontal synchronization -+ pulse width */ -+ int hfp; /* Horizontal front porch */ -+ int hbp; /* Horizontal back porch */ -+ int vsw; /* Vertical synchronization -+ pulse width */ -+ int vfp; /* Vertical front porch */ -+ int vbp; /* Vertical back porch */ -+ int acb; /* ac-bias pin frequency */ -+ int pcd; /* pixel clock divider. -+ Obsolete use pixel_clock instead */ -+ -+ int (*init) (struct lcd_panel *panel, -+ struct omapfb_device *fbdev); -+ void (*cleanup) (struct lcd_panel *panel); -+ int (*enable) (struct lcd_panel *panel); -+ void (*disable) (struct lcd_panel *panel); -+ unsigned long (*get_caps) (struct lcd_panel *panel); -+ int (*set_bklight_level)(struct lcd_panel *panel, -+ unsigned int level); -+ unsigned int (*get_bklight_level)(struct lcd_panel *panel); -+ unsigned int (*get_bklight_max) (struct lcd_panel *panel); -+ int (*run_test) (struct lcd_panel *panel, int test_num); -+}; -+ -+struct extif_timings { -+ int cs_on_time; -+ int cs_off_time; -+ int we_on_time; -+ int we_off_time; -+ int re_on_time; -+ int re_off_time; -+ int we_cycle_time; -+ int re_cycle_time; -+ int cs_pulse_width; -+ int access_time; -+ -+ int clk_div; -+ -+ u32 tim[5]; /* set by extif->convert_timings */ -+ -+ int converted; -+}; -+ -+struct lcd_ctrl_extif { -+ int (*init) (struct omapfb_device *fbdev); -+ void (*cleanup) (void); -+ void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div); -+ unsigned long (*get_max_tx_rate)(void); -+ int (*convert_timings) (struct extif_timings *timings); -+ void (*set_timings) (const struct extif_timings *timings); -+ void (*set_bits_per_cycle)(int bpc); -+ void (*write_command) (const void *buf, unsigned int len); -+ void (*read_data) (void *buf, unsigned int len); -+ void (*write_data) (const void *buf, unsigned int len); -+ void (*transfer_area) (int width, int height, -+ void (callback)(void *data), void *data); -+ int (*setup_tearsync) (unsigned pin_cnt, -+ unsigned hs_pulse_time, unsigned vs_pulse_time, -+ int hs_pol_inv, int vs_pol_inv, int div); -+ int (*enable_tearsync) (int enable, unsigned line); -+ -+ unsigned long max_transmit_size; -+}; -+ -+struct omapfb_notifier_block { -+ struct notifier_block nb; -+ void *data; -+ int plane_idx; -+}; -+ -+typedef int (*omapfb_notifier_callback_t)(struct notifier_block *, -+ unsigned long event, -+ void *fbi); -+ -+struct lcd_ctrl { -+ const char *name; -+ void *data; -+ -+ int (*init) (struct omapfb_device *fbdev, -+ int ext_mode, -+ struct omapfb_mem_desc *req_md); -+ void (*cleanup) (void); -+ void (*bind_client) (struct omapfb_notifier_block *nb); -+ void (*get_caps) (int plane, struct omapfb_caps *caps); -+ int (*set_update_mode)(enum omapfb_update_mode mode); -+ enum omapfb_update_mode (*get_update_mode)(void); -+ int (*setup_plane) (int plane, int channel_out, -+ unsigned long offset, -+ int screen_width, -+ int pos_x, int pos_y, int width, -+ int height, int color_mode); -+ int (*set_rotate) (int angle); -+ int (*setup_mem) (int plane, size_t size, -+ int mem_type, unsigned long *paddr); -+ int (*mmap) (struct fb_info *info, -+ struct vm_area_struct *vma); -+ int (*set_scale) (int plane, -+ int orig_width, int orig_height, -+ int out_width, int out_height); -+ int (*enable_plane) (int plane, int enable); -+ int (*update_window) (struct fb_info *fbi, -+ struct omapfb_update_window *win, -+ void (*callback)(void *), -+ void *callback_data); -+ void (*sync) (void); -+ void (*suspend) (void); -+ void (*resume) (void); -+ int (*run_test) (int test_num); -+ int (*setcolreg) (u_int regno, u16 red, u16 green, -+ u16 blue, u16 transp, -+ int update_hw_mem); -+ int (*set_color_key) (struct omapfb_color_key *ck); -+ int (*get_color_key) (struct omapfb_color_key *ck); -+}; -+ -+enum omapfb_state { -+ OMAPFB_DISABLED = 0, -+ OMAPFB_SUSPENDED = 99, -+ OMAPFB_ACTIVE = 100 -+}; -+ -+struct omapfb_plane_struct { -+ int idx; -+ struct omapfb_plane_info info; -+ enum omapfb_color_format color_mode; -+ struct omapfb_device *fbdev; -+}; -+ -+struct omapfb_device { -+ int state; -+ int ext_lcdc; /* Using external -+ LCD controller */ -+ struct mutex rqueue_mutex; -+ -+ int palette_size; -+ u32 pseudo_palette[17]; -+ -+ struct lcd_panel *panel; /* LCD panel */ -+ const struct lcd_ctrl *ctrl; /* LCD controller */ -+ const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */ -+ struct lcd_ctrl_extif *ext_if; /* LCD ctrl external -+ interface */ -+ struct device *dev; -+ struct fb_var_screeninfo new_var; /* for mode changes */ -+ -+ struct omapfb_mem_desc mem_desc; -+ struct fb_info *fb_info[OMAPFB_PLANE_NUM]; -+}; -+ -+#ifdef CONFIG_ARCH_OMAP1 -+extern struct lcd_ctrl omap1_lcd_ctrl; -+#else -+extern struct lcd_ctrl omap2_disp_ctrl; -+#endif -+ -+extern void omapfb_register_panel(struct lcd_panel *panel); -+extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval); -+extern void omapfb_notify_clients(struct omapfb_device *fbdev, -+ unsigned long event); -+extern int omapfb_register_client(struct omapfb_notifier_block *nb, -+ omapfb_notifier_callback_t callback, -+ void *callback_data); -+extern int omapfb_unregister_client(struct omapfb_notifier_block *nb); -+extern int omapfb_update_window_async(struct fb_info *fbi, -+ struct omapfb_update_window *win, -+ void (*callback)(void *), -+ void *callback_data); -+ -+#endif /* __OMAPFB_H */ ---- a/drivers/video/omap/omapfb_main.c -+++ b/drivers/video/omap/omapfb_main.c -@@ -29,8 +29,8 @@ - #include <linux/uaccess.h> - - #include <mach/dma.h> --#include <mach/omapfb.h> - -+#include "omapfb.h" - #include "lcdc.h" - #include "dispc.h" - ---- a/drivers/video/omap/rfbi.c -+++ b/drivers/video/omap/rfbi.c -@@ -27,8 +27,7 @@ - #include <linux/clk.h> - #include <linux/io.h> - --#include <mach/omapfb.h> -- -+#include "omapfb.h" - #include "dispc.h" - - /* To work around an RFBI transfer rate limitation */ ---- a/drivers/video/omap/sossi.c -+++ b/drivers/video/omap/sossi.c -@@ -25,8 +25,8 @@ - #include <linux/io.h> - - #include <mach/dma.h> --#include <mach/omapfb.h> - -+#include "omapfb.h" - #include "lcdc.h" - - #define MODULE_NAME "omapfb-sossi" ---- /dev/null -+++ b/drivers/video/omap2/Kconfig -@@ -0,0 +1,9 @@ -+config OMAP2_VRAM -+ bool -+ -+config OMAP2_VRFB -+ bool -+ -+source "drivers/video/omap2/dss/Kconfig" -+source "drivers/video/omap2/omapfb/Kconfig" -+source "drivers/video/omap2/displays/Kconfig" ---- /dev/null -+++ b/drivers/video/omap2/Makefile -@@ -0,0 +1,6 @@ -+obj-$(CONFIG_OMAP2_VRAM) += vram.o -+obj-$(CONFIG_OMAP2_VRFB) += vrfb.o -+ -+obj-y += dss/ -+obj-y += omapfb/ -+obj-y += displays/ ---- /dev/null -+++ b/drivers/video/omap2/displays/Kconfig -@@ -0,0 +1,28 @@ -+menu "OMAP2/3 Display Device Drivers" -+ depends on OMAP2_DSS -+ -+config PANEL_GENERIC -+ tristate "Generic Panel" -+ help -+ Generic panel driver. -+ Used for DVI output for Beagle and OMAP3 SDP. -+ -+config PANEL_SAMSUNG_LTE430WQ_F0C -+ tristate "Samsung LTE430WQ-F0C LCD Panel" -+ depends on OMAP2_DSS -+ help -+ LCD Panel used on Overo Palo43 -+ -+config PANEL_SHARP_LS037V7DW01 -+ tristate "Sharp LS037V7DW01 LCD Panel" -+ depends on OMAP2_DSS -+ help -+ LCD Panel used in TI's SDP3430 and EVM boards -+ -+config PANEL_TAAL -+ tristate "Taal DSI Panel" -+ depends on OMAP2_DSS_DSI -+ help -+ Taal DSI command mode panel from TPO. -+ -+endmenu ---- /dev/null -+++ b/drivers/video/omap2/displays/Makefile -@@ -0,0 +1,5 @@ -+obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o -+obj-$(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) += panel-samsung-lte430wq-f0c.o -+obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o -+ -+obj-$(CONFIG_PANEL_TAAL) += panel-taal.o ---- /dev/null -+++ b/drivers/video/omap2/displays/panel-generic.c -@@ -0,0 +1,104 @@ -+/* -+ * Generic panel support -+ * -+ * Copyright (C) 2008 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#include <linux/module.h> -+#include <linux/delay.h> -+ -+#include <mach/display.h> -+ -+static struct omap_video_timings generic_panel_timings = { -+ /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */ -+ .x_res = 640, -+ .y_res = 480, -+ .pixel_clock = 23500, -+ .hfp = 48, -+ .hsw = 32, -+ .hbp = 80, -+ .vfp = 3, -+ .vsw = 4, -+ .vbp = 7, -+}; -+ -+static int generic_panel_probe(struct omap_dss_device *dssdev) -+{ -+ dssdev->panel.config = OMAP_DSS_LCD_TFT; -+ dssdev->panel.timings = generic_panel_timings; -+ -+ return 0; -+} -+ -+static void generic_panel_remove(struct omap_dss_device *dssdev) -+{ -+} -+ -+static int generic_panel_enable(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ if (dssdev->platform_enable) -+ r = dssdev->platform_enable(dssdev); -+ -+ return r; -+} -+ -+static void generic_panel_disable(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->platform_disable) -+ dssdev->platform_disable(dssdev); -+} -+ -+static int generic_panel_suspend(struct omap_dss_device *dssdev) -+{ -+ generic_panel_disable(dssdev); -+ return 0; -+} -+ -+static int generic_panel_resume(struct omap_dss_device *dssdev) -+{ -+ return generic_panel_enable(dssdev); -+} -+ -+static struct omap_dss_driver generic_driver = { -+ .probe = generic_panel_probe, -+ .remove = generic_panel_remove, -+ -+ .enable = generic_panel_enable, -+ .disable = generic_panel_disable, -+ .suspend = generic_panel_suspend, -+ .resume = generic_panel_resume, -+ -+ .driver = { -+ .name = "generic_panel", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init generic_panel_drv_init(void) -+{ -+ return omap_dss_register_driver(&generic_driver); -+} -+ -+static void __exit generic_panel_drv_exit(void) -+{ -+ omap_dss_unregister_driver(&generic_driver); -+} -+ -+module_init(generic_panel_drv_init); -+module_exit(generic_panel_drv_exit); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c -@@ -0,0 +1,113 @@ -+/* -+ * LCD panel driver for Samsung LTE430WQ-F0C -+ * -+ * Author: Steve Sakoman <steve@sakoman.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#include <linux/module.h> -+#include <linux/delay.h> -+ -+#include <mach/display.h> -+ -+static struct omap_video_timings samsung_lte_timings = { -+ .x_res = 480, -+ .y_res = 272, -+ -+ .pixel_clock = 9200, -+ -+ .hsw = 41, -+ .hfp = 8, -+ .hbp = 45-41, -+ -+ .vsw = 10, -+ .vfp = 4, -+ .vbp = 12-10, -+}; -+ -+static int samsung_lte_panel_probe(struct omap_dss_device *dssdev) -+{ -+ dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | -+ OMAP_DSS_LCD_IHS; -+ dssdev->panel.timings = samsung_lte_timings; -+ -+ return 0; -+} -+ -+static void samsung_lte_panel_remove(struct omap_dss_device *dssdev) -+{ -+} -+ -+static int samsung_lte_panel_enable(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ /* wait couple of vsyncs until enabling the LCD */ -+ msleep(50); -+ -+ if (dssdev->platform_enable) -+ r = dssdev->platform_enable(dssdev); -+ -+ return r; -+} -+ -+static void samsung_lte_panel_disable(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->platform_disable) -+ dssdev->platform_disable(dssdev); -+ -+ /* wait at least 5 vsyncs after disabling the LCD */ -+ -+ msleep(100); -+} -+ -+static int samsung_lte_panel_suspend(struct omap_dss_device *dssdev) -+{ -+ samsung_lte_panel_disable(dssdev); -+ return 0; -+} -+ -+static int samsung_lte_panel_resume(struct omap_dss_device *dssdev) -+{ -+ return samsung_lte_panel_enable(dssdev); -+} -+ -+static struct omap_dss_driver samsung_lte_driver = { -+ .probe = samsung_lte_panel_probe, -+ .remove = samsung_lte_panel_remove, -+ -+ .enable = samsung_lte_panel_enable, -+ .disable = samsung_lte_panel_disable, -+ .suspend = samsung_lte_panel_suspend, -+ .resume = samsung_lte_panel_resume, -+ -+ .driver = { -+ .name = "samsung_lte_panel", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init samsung_lte_panel_drv_init(void) -+{ -+ return omap_dss_register_driver(&samsung_lte_driver); -+} -+ -+static void __exit samsung_lte_panel_drv_exit(void) -+{ -+ omap_dss_unregister_driver(&samsung_lte_driver); -+} -+ -+module_init(samsung_lte_panel_drv_init); -+module_exit(samsung_lte_panel_drv_exit); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c -@@ -0,0 +1,153 @@ -+/* -+ * LCD panel driver for Sharp LS037V7DW01 -+ * -+ * Copyright (C) 2008 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#include <linux/module.h> -+#include <linux/delay.h> -+#include <linux/device.h> -+#include <linux/regulator/consumer.h> -+#include <linux/err.h> -+ -+#include <mach/display.h> -+ -+struct sharp_data { -+ /* XXX This regulator should actually be in SDP board file, not here, -+ * as it doesn't actually power the LCD, but something else that -+ * affects the output to LCD (I think. Somebody clarify). It doesn't do -+ * harm here, as SDP is the only board using this currently */ -+ struct regulator *vdvi_reg; -+}; -+ -+static struct omap_video_timings sharp_ls_timings = { -+ .x_res = 480, -+ .y_res = 640, -+ -+ .pixel_clock = 19200, -+ -+ .hsw = 2, -+ .hfp = 1, -+ .hbp = 28, -+ -+ .vsw = 1, -+ .vfp = 1, -+ .vbp = 1, -+}; -+ -+static int sharp_ls_panel_probe(struct omap_dss_device *dssdev) -+{ -+ struct sharp_data *sd; -+ -+ dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | -+ OMAP_DSS_LCD_IHS; -+ dssdev->panel.acb = 0x28; -+ dssdev->panel.timings = sharp_ls_timings; -+ -+ sd = kzalloc(sizeof(*sd), GFP_KERNEL); -+ if (!sd) -+ return -ENOMEM; -+ -+ dev_set_drvdata(&dssdev->dev, sd); -+ -+ sd->vdvi_reg = regulator_get(&dssdev->dev, "vdvi"); -+ if (IS_ERR(sd->vdvi_reg)) { -+ kfree(sd); -+ pr_err("failed to get VDVI regulator\n"); -+ return PTR_ERR(sd->vdvi_reg); -+ } -+ -+ return 0; -+} -+ -+static void sharp_ls_panel_remove(struct omap_dss_device *dssdev) -+{ -+ struct sharp_data *sd = dev_get_drvdata(&dssdev->dev); -+ -+ regulator_put(sd->vdvi_reg); -+ -+ kfree(sd); -+} -+ -+static int sharp_ls_panel_enable(struct omap_dss_device *dssdev) -+{ -+ struct sharp_data *sd = dev_get_drvdata(&dssdev->dev); -+ int r = 0; -+ -+ /* wait couple of vsyncs until enabling the LCD */ -+ msleep(50); -+ -+ regulator_enable(sd->vdvi_reg); -+ -+ if (dssdev->platform_enable) -+ r = dssdev->platform_enable(dssdev); -+ -+ return r; -+} -+ -+static void sharp_ls_panel_disable(struct omap_dss_device *dssdev) -+{ -+ struct sharp_data *sd = dev_get_drvdata(&dssdev->dev); -+ -+ if (dssdev->platform_disable) -+ dssdev->platform_disable(dssdev); -+ -+ regulator_disable(sd->vdvi_reg); -+ -+ /* wait at least 5 vsyncs after disabling the LCD */ -+ -+ msleep(100); -+} -+ -+static int sharp_ls_panel_suspend(struct omap_dss_device *dssdev) -+{ -+ sharp_ls_panel_disable(dssdev); -+ return 0; -+} -+ -+static int sharp_ls_panel_resume(struct omap_dss_device *dssdev) -+{ -+ return sharp_ls_panel_enable(dssdev); -+} -+ -+static struct omap_dss_driver sharp_ls_driver = { -+ .probe = sharp_ls_panel_probe, -+ .remove = sharp_ls_panel_remove, -+ -+ .enable = sharp_ls_panel_enable, -+ .disable = sharp_ls_panel_disable, -+ .suspend = sharp_ls_panel_suspend, -+ .resume = sharp_ls_panel_resume, -+ -+ .driver = { -+ .name = "sharp_ls_panel", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init sharp_ls_panel_drv_init(void) -+{ -+ return omap_dss_register_driver(&sharp_ls_driver); -+} -+ -+static void __exit sharp_ls_panel_drv_exit(void) -+{ -+ omap_dss_unregister_driver(&sharp_ls_driver); -+} -+ -+module_init(sharp_ls_panel_drv_init); -+module_exit(sharp_ls_panel_drv_exit); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/video/omap2/displays/panel-taal.c -@@ -0,0 +1,900 @@ -+/* -+ * Taal DSI command mode panel -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+/*#define DEBUG*/ -+ -+#include <linux/module.h> -+#include <linux/delay.h> -+#include <linux/err.h> -+#include <linux/jiffies.h> -+#include <linux/sched.h> -+#include <linux/backlight.h> -+#include <linux/fb.h> -+#include <linux/interrupt.h> -+#include <linux/gpio.h> -+#include <linux/completion.h> -+ -+#include <mach/display.h> -+ -+/* DSI Virtual channel. Hardcoded for now. */ -+#define TCH 0 -+ -+#define DCS_READ_NUM_ERRORS 0x05 -+#define DCS_READ_POWER_MODE 0x0a -+#define DCS_READ_MADCTL 0x0b -+#define DCS_READ_PIXEL_FORMAT 0x0c -+#define DCS_SLEEP_IN 0x10 -+#define DCS_SLEEP_OUT 0x11 -+#define DCS_DISPLAY_OFF 0x28 -+#define DCS_DISPLAY_ON 0x29 -+#define DCS_COLUMN_ADDR 0x2a -+#define DCS_PAGE_ADDR 0x2b -+#define DCS_MEMORY_WRITE 0x2c -+#define DCS_TEAR_OFF 0x34 -+#define DCS_TEAR_ON 0x35 -+#define DCS_MEM_ACC_CTRL 0x36 -+#define DCS_PIXEL_FORMAT 0x3a -+#define DCS_BRIGHTNESS 0x51 -+#define DCS_CTRL_DISPLAY 0x53 -+#define DCS_WRITE_CABC 0x55 -+#define DCS_READ_CABC 0x56 -+#define DCS_GET_ID1 0xda -+#define DCS_GET_ID2 0xdb -+#define DCS_GET_ID3 0xdc -+ -+struct taal_data { -+ struct backlight_device *bldev; -+ -+ unsigned long hw_guard_end; /* next value of jiffies when we can -+ * issue the next sleep in/out command -+ */ -+ unsigned long hw_guard_wait; /* max guard time in jiffies */ -+ -+ struct omap_dss_device *dssdev; -+ -+ bool enabled; -+ u8 rotate; -+ bool mirror; -+ -+ bool te_enabled; -+ bool use_ext_te; -+ struct completion te_completion; -+ -+ bool use_dsi_bl; -+ -+ bool cabc_broken; -+ unsigned cabc_mode; -+ -+ bool intro_printed; -+}; -+ -+static void hw_guard_start(struct taal_data *td, int guard_msec) -+{ -+ td->hw_guard_wait = msecs_to_jiffies(guard_msec); -+ td->hw_guard_end = jiffies + td->hw_guard_wait; -+} -+ -+static void hw_guard_wait(struct taal_data *td) -+{ -+ unsigned long wait = td->hw_guard_end - jiffies; -+ -+ if ((long)wait > 0 && wait <= td->hw_guard_wait) { -+ set_current_state(TASK_UNINTERRUPTIBLE); -+ schedule_timeout(wait); -+ } -+} -+ -+static int taal_dcs_read_1(u8 dcs_cmd, u8 *data) -+{ -+ int r; -+ u8 buf[1]; -+ -+ r = dsi_vc_dcs_read(TCH, dcs_cmd, buf, 1); -+ -+ if (r < 0) -+ return r; -+ -+ *data = buf[0]; -+ -+ return 0; -+} -+ -+static int taal_dcs_write_0(u8 dcs_cmd) -+{ -+ return dsi_vc_dcs_write(TCH, &dcs_cmd, 1); -+} -+ -+static int taal_dcs_write_1(u8 dcs_cmd, u8 param) -+{ -+ u8 buf[2]; -+ buf[0] = dcs_cmd; -+ buf[1] = param; -+ return dsi_vc_dcs_write(TCH, buf, 2); -+} -+ -+static int taal_sleep_in(struct taal_data *td) -+ -+{ -+ u8 cmd; -+ int r; -+ -+ hw_guard_wait(td); -+ -+ cmd = DCS_SLEEP_IN; -+ r = dsi_vc_dcs_write_nosync(TCH, &cmd, 1); -+ if (r) -+ return r; -+ -+ hw_guard_start(td, 120); -+ -+ msleep(5); -+ -+ return 0; -+} -+ -+static int taal_sleep_out(struct taal_data *td) -+{ -+ int r; -+ -+ hw_guard_wait(td); -+ -+ r = taal_dcs_write_0(DCS_SLEEP_OUT); -+ if (r) -+ return r; -+ -+ hw_guard_start(td, 120); -+ -+ msleep(5); -+ -+ return 0; -+} -+ -+static int taal_get_id(u8 *id1, u8 *id2, u8 *id3) -+{ -+ int r; -+ -+ r = taal_dcs_read_1(DCS_GET_ID1, id1); -+ if (r) -+ return r; -+ r = taal_dcs_read_1(DCS_GET_ID2, id2); -+ if (r) -+ return r; -+ r = taal_dcs_read_1(DCS_GET_ID3, id3); -+ if (r) -+ return r; -+ -+ return 0; -+} -+ -+static int taal_set_addr_mode(u8 rotate, bool mirror) -+{ -+ int r; -+ u8 mode; -+ int b5, b6, b7; -+ -+ r = taal_dcs_read_1(DCS_READ_MADCTL, &mode); -+ if (r) -+ return r; -+ -+ switch (rotate) { -+ default: -+ case 0: -+ b7 = 0; -+ b6 = 0; -+ b5 = 0; -+ break; -+ case 1: -+ b7 = 0; -+ b6 = 1; -+ b5 = 1; -+ break; -+ case 2: -+ b7 = 1; -+ b6 = 1; -+ b5 = 0; -+ break; -+ case 3: -+ b7 = 1; -+ b6 = 0; -+ b5 = 1; -+ break; -+ } -+ -+ if (mirror) -+ b6 = !b6; -+ -+ mode &= ~((1<<7) | (1<<6) | (1<<5)); -+ mode |= (b7 << 7) | (b6 << 6) | (b5 << 5); -+ -+ return taal_dcs_write_1(DCS_MEM_ACC_CTRL, mode); -+} -+ -+static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h) -+{ -+ int r; -+ u16 x1 = x; -+ u16 x2 = x + w - 1; -+ u16 y1 = y; -+ u16 y2 = y + h - 1; -+ -+ u8 buf[5]; -+ buf[0] = DCS_COLUMN_ADDR; -+ buf[1] = (x1 >> 8) & 0xff; -+ buf[2] = (x1 >> 0) & 0xff; -+ buf[3] = (x2 >> 8) & 0xff; -+ buf[4] = (x2 >> 0) & 0xff; -+ -+ r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf)); -+ if (r) -+ return r; -+ -+ buf[0] = DCS_PAGE_ADDR; -+ buf[1] = (y1 >> 8) & 0xff; -+ buf[2] = (y1 >> 0) & 0xff; -+ buf[3] = (y2 >> 8) & 0xff; -+ buf[4] = (y2 >> 0) & 0xff; -+ -+ r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf)); -+ if (r) -+ return r; -+ -+ dsi_vc_send_bta_sync(TCH); -+ -+ return r; -+} -+ -+static int taal_bl_update_status(struct backlight_device *dev) -+{ -+ struct omap_dss_device *dssdev = dev_get_drvdata(&dev->dev); -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ int r; -+ int level; -+ -+ if (dev->props.fb_blank == FB_BLANK_UNBLANK && -+ dev->props.power == FB_BLANK_UNBLANK) -+ level = dev->props.brightness; -+ else -+ level = 0; -+ -+ dev_dbg(&dssdev->dev, "update brightness to %d\n", level); -+ -+ if (td->use_dsi_bl) { -+ if (td->enabled) { -+ dsi_bus_lock(); -+ r = taal_dcs_write_1(DCS_BRIGHTNESS, level); -+ dsi_bus_unlock(); -+ if (r) -+ return r; -+ } -+ } else { -+ if (!dssdev->set_backlight) -+ return -EINVAL; -+ -+ r = dssdev->set_backlight(dssdev, level); -+ if (r) -+ return r; -+ } -+ -+ return 0; -+} -+ -+static int taal_bl_get_intensity(struct backlight_device *dev) -+{ -+ if (dev->props.fb_blank == FB_BLANK_UNBLANK && -+ dev->props.power == FB_BLANK_UNBLANK) -+ return dev->props.brightness; -+ -+ return 0; -+} -+ -+static struct backlight_ops taal_bl_ops = { -+ .get_brightness = taal_bl_get_intensity, -+ .update_status = taal_bl_update_status, -+}; -+ -+static void taal_get_timings(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings) -+{ -+ *timings = dssdev->panel.timings; -+} -+ -+static void taal_get_resolution(struct omap_dss_device *dssdev, -+ u16 *xres, u16 *yres) -+{ -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ -+ if (td->rotate == 0 || td->rotate == 2) { -+ *xres = dssdev->panel.timings.x_res; -+ *yres = dssdev->panel.timings.y_res; -+ } else { -+ *yres = dssdev->panel.timings.x_res; -+ *xres = dssdev->panel.timings.y_res; -+ } -+} -+ -+static irqreturn_t taal_te_isr(int irq, void *data) -+{ -+ struct omap_dss_device *dssdev = data; -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ -+ complete_all(&td->te_completion); -+ -+ return IRQ_HANDLED; -+} -+ -+static ssize_t taal_num_errors_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ u8 errors; -+ int r; -+ -+ if (td->enabled) { -+ dsi_bus_lock(); -+ r = taal_dcs_read_1(DCS_READ_NUM_ERRORS, &errors); -+ dsi_bus_unlock(); -+ } else { -+ r = -ENODEV; -+ } -+ -+ if (r) -+ return r; -+ -+ return snprintf(buf, PAGE_SIZE, "%d\n", errors); -+} -+ -+static ssize_t taal_hw_revision_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ u8 id1, id2, id3; -+ int r; -+ -+ if (td->enabled) { -+ dsi_bus_lock(); -+ r = taal_get_id(&id1, &id2, &id3); -+ dsi_bus_unlock(); -+ } else { -+ r = -ENODEV; -+ } -+ -+ if (r) -+ return r; -+ -+ return snprintf(buf, PAGE_SIZE, "%02x.%02x.%02x\n", id1, id2, id3); -+} -+ -+static const char *cabc_modes[] = { -+ "off", /* used also always when CABC is not supported */ -+ "ui", -+ "still-image", -+ "moving-image", -+}; -+ -+static ssize_t show_cabc_mode(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ const char *mode_str; -+ int mode; -+ int len; -+ -+ mode = td->cabc_mode; -+ -+ mode_str = "unknown"; -+ if (mode >= 0 && mode < ARRAY_SIZE(cabc_modes)) -+ mode_str = cabc_modes[mode]; -+ len = snprintf(buf, PAGE_SIZE, "%s\n", mode_str); -+ -+ return len < PAGE_SIZE - 1 ? len : PAGE_SIZE - 1; -+} -+ -+static ssize_t store_cabc_mode(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(cabc_modes); i++) { -+ if (sysfs_streq(cabc_modes[i], buf)) -+ break; -+ } -+ -+ if (i == ARRAY_SIZE(cabc_modes)) -+ return -EINVAL; -+ -+ if (td->enabled) { -+ dsi_bus_lock(); -+ if (!td->cabc_broken) -+ taal_dcs_write_1(DCS_WRITE_CABC, i); -+ dsi_bus_unlock(); -+ } -+ -+ td->cabc_mode = i; -+ -+ return count; -+} -+ -+static ssize_t show_cabc_available_modes(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ int len; -+ int i; -+ -+ for (i = 0, len = 0; -+ len < PAGE_SIZE && i < ARRAY_SIZE(cabc_modes); i++) -+ len += snprintf(&buf[len], PAGE_SIZE - len, "%s%s%s", -+ i ? " " : "", cabc_modes[i], -+ i == ARRAY_SIZE(cabc_modes) - 1 ? "\n" : ""); -+ -+ return len < PAGE_SIZE ? len : PAGE_SIZE - 1; -+} -+ -+static DEVICE_ATTR(num_dsi_errors, S_IRUGO, taal_num_errors_show, NULL); -+static DEVICE_ATTR(hw_revision, S_IRUGO, taal_hw_revision_show, NULL); -+static DEVICE_ATTR(cabc_mode, S_IRUGO | S_IWUSR, -+ show_cabc_mode, store_cabc_mode); -+static DEVICE_ATTR(cabc_available_modes, S_IRUGO, -+ show_cabc_available_modes, NULL); -+ -+static struct attribute *taal_attrs[] = { -+ &dev_attr_num_dsi_errors.attr, -+ &dev_attr_hw_revision.attr, -+ &dev_attr_cabc_mode.attr, -+ &dev_attr_cabc_available_modes.attr, -+ NULL, -+}; -+ -+static struct attribute_group taal_attr_group = { -+ .attrs = taal_attrs, -+}; -+ -+static int taal_probe(struct omap_dss_device *dssdev) -+{ -+ struct taal_data *td; -+ struct backlight_device *bldev; -+ int r; -+ -+ const struct omap_video_timings taal_panel_timings = { -+ .x_res = 864, -+ .y_res = 480, -+ }; -+ -+ dev_dbg(&dssdev->dev, "probe\n"); -+ -+ dssdev->panel.config = OMAP_DSS_LCD_TFT; -+ dssdev->panel.timings = taal_panel_timings; -+ dssdev->ctrl.pixel_size = 24; -+ -+ td = kzalloc(sizeof(*td), GFP_KERNEL); -+ if (!td) { -+ r = -ENOMEM; -+ goto err0; -+ } -+ -+ dev_set_drvdata(&dssdev->dev, td); -+ -+ dssdev->get_timings = taal_get_timings; -+ dssdev->get_resolution = taal_get_resolution; -+ -+ /* if no platform set_backlight() defined, presume DSI backlight -+ * control */ -+ if (!dssdev->set_backlight) -+ td->use_dsi_bl = true; -+ -+ bldev = backlight_device_register("taal", &dssdev->dev, dssdev, -+ &taal_bl_ops); -+ if (IS_ERR(bldev)) { -+ r = PTR_ERR(bldev); -+ goto err1; -+ } -+ -+ td->bldev = bldev; -+ -+ bldev->props.fb_blank = FB_BLANK_UNBLANK; -+ bldev->props.power = FB_BLANK_UNBLANK; -+ if (td->use_dsi_bl) { -+ bldev->props.max_brightness = 255; -+ bldev->props.brightness = 255; -+ } else { -+ bldev->props.max_brightness = 127; -+ bldev->props.brightness = 127; -+ } -+ -+ taal_bl_update_status(bldev); -+ -+ if (dssdev->phy.dsi.ext_te) { -+ int gpio = dssdev->phy.dsi.ext_te_gpio; -+ -+ r = gpio_request(gpio, "taal irq"); -+ if (r) { -+ dev_err(&dssdev->dev, "GPIO request failed\n"); -+ goto err2; -+ } -+ -+ gpio_direction_input(gpio); -+ -+ r = request_irq(gpio_to_irq(gpio), taal_te_isr, -+ IRQF_DISABLED | IRQF_TRIGGER_RISING, -+ "taal vsync", dssdev); -+ -+ if (r) { -+ dev_err(&dssdev->dev, "IRQ request failed\n"); -+ gpio_free(gpio); -+ goto err2; -+ } -+ -+ init_completion(&td->te_completion); -+ -+ td->use_ext_te = true; -+ } -+ -+ r = sysfs_create_group(&dssdev->dev.kobj, &taal_attr_group); -+ if (r) { -+ dev_err(&dssdev->dev, "failed to create sysfs files\n"); -+ goto err3; -+ } -+ -+ return 0; -+err3: -+ if (td->use_ext_te) { -+ int gpio = dssdev->phy.dsi.ext_te_gpio; -+ free_irq(gpio_to_irq(gpio), dssdev); -+ gpio_free(gpio); -+ } -+err2: -+ backlight_device_unregister(bldev); -+err1: -+ kfree(td); -+err0: -+ return r; -+} -+ -+static void taal_remove(struct omap_dss_device *dssdev) -+{ -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ struct backlight_device *bldev; -+ -+ dev_dbg(&dssdev->dev, "remove\n"); -+ -+ sysfs_remove_group(&dssdev->dev.kobj, &taal_attr_group); -+ -+ if (td->use_ext_te) { -+ int gpio = dssdev->phy.dsi.ext_te_gpio; -+ free_irq(gpio_to_irq(gpio), dssdev); -+ gpio_free(gpio); -+ } -+ -+ bldev = td->bldev; -+ bldev->props.power = FB_BLANK_POWERDOWN; -+ taal_bl_update_status(bldev); -+ backlight_device_unregister(bldev); -+ -+ kfree(td); -+} -+ -+static int taal_enable(struct omap_dss_device *dssdev) -+{ -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ u8 id1, id2, id3; -+ int r; -+ -+ dev_dbg(&dssdev->dev, "enable\n"); -+ -+ if (dssdev->platform_enable) { -+ r = dssdev->platform_enable(dssdev); -+ if (r) -+ return r; -+ } -+ -+ /* it seems we have to wait a bit until taal is ready */ -+ msleep(5); -+ -+ r = taal_sleep_out(td); -+ if (r) -+ return r; -+ -+ r = taal_get_id(&id1, &id2, &id3); -+ if (r) -+ return r; -+ -+ /* on early revisions CABC is broken */ -+ if (id2 == 0x00 || id2 == 0xff || id2 == 0x81) -+ td->cabc_broken = true; -+ -+ taal_dcs_write_1(DCS_BRIGHTNESS, 0xff); -+ taal_dcs_write_1(DCS_CTRL_DISPLAY, (1<<2) | (1<<5)); /* BL | BCTRL */ -+ -+ taal_dcs_write_1(DCS_PIXEL_FORMAT, 0x7); /* 24bit/pixel */ -+ -+ taal_set_addr_mode(td->rotate, td->mirror); -+ if (!td->cabc_broken) -+ taal_dcs_write_1(DCS_WRITE_CABC, td->cabc_mode); -+ -+ taal_dcs_write_0(DCS_DISPLAY_ON); -+ -+ td->enabled = 1; -+ -+ if (!td->intro_printed) { -+ dev_info(&dssdev->dev, "revision %02x.%02x.%02x\n", -+ id1, id2, id3); -+ if (td->cabc_broken) -+ dev_info(&dssdev->dev, -+ "old Taal version, CABC disabled\n"); -+ td->intro_printed = true; -+ } -+ -+ return 0; -+} -+ -+static void taal_disable(struct omap_dss_device *dssdev) -+{ -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ -+ dev_dbg(&dssdev->dev, "disable\n"); -+ -+ taal_dcs_write_0(DCS_DISPLAY_OFF); -+ taal_sleep_in(td); -+ -+ /* wait a bit so that the message goes through */ -+ msleep(10); -+ -+ if (dssdev->platform_disable) -+ dssdev->platform_disable(dssdev); -+ -+ td->enabled = 0; -+} -+ -+static int taal_suspend(struct omap_dss_device *dssdev) -+{ -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ struct backlight_device *bldev = td->bldev; -+ -+ bldev->props.power = FB_BLANK_POWERDOWN; -+ taal_bl_update_status(bldev); -+ -+ return 0; -+} -+ -+static int taal_resume(struct omap_dss_device *dssdev) -+{ -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ struct backlight_device *bldev = td->bldev; -+ -+ bldev->props.power = FB_BLANK_UNBLANK; -+ taal_bl_update_status(bldev); -+ -+ return 0; -+} -+ -+static void taal_setup_update(struct omap_dss_device *dssdev, -+ u16 x, u16 y, u16 w, u16 h) -+{ -+ taal_set_update_window(x, y, w, h); -+} -+ -+static int taal_enable_te(struct omap_dss_device *dssdev, bool enable) -+{ -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ int r; -+ -+ td->te_enabled = enable; -+ -+ if (enable) -+ r = taal_dcs_write_1(DCS_TEAR_ON, 0); -+ else -+ r = taal_dcs_write_0(DCS_TEAR_OFF); -+ -+ return r; -+} -+ -+static int taal_wait_te(struct omap_dss_device *dssdev) -+{ -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ long wait = msecs_to_jiffies(500); -+ -+ if (!td->use_ext_te || !td->te_enabled) -+ return 0; -+ -+ INIT_COMPLETION(td->te_completion); -+ wait = wait_for_completion_timeout(&td->te_completion, wait); -+ if (wait == 0) { -+ dev_err(&dssdev->dev, "timeout waiting TE\n"); -+ return -ETIME; -+ } -+ -+ return 0; -+} -+ -+static int taal_rotate(struct omap_dss_device *dssdev, u8 rotate) -+{ -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ int r; -+ -+ dev_dbg(&dssdev->dev, "rotate %d\n", rotate); -+ -+ if (td->enabled) { -+ r = taal_set_addr_mode(rotate, td->mirror); -+ -+ if (r) -+ return r; -+ } -+ -+ td->rotate = rotate; -+ -+ return 0; -+} -+ -+static u8 taal_get_rotate(struct omap_dss_device *dssdev) -+{ -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ return td->rotate; -+} -+ -+static int taal_mirror(struct omap_dss_device *dssdev, bool enable) -+{ -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ int r; -+ -+ dev_dbg(&dssdev->dev, "mirror %d\n", enable); -+ -+ if (td->enabled) { -+ r = taal_set_addr_mode(td->rotate, enable); -+ -+ if (r) -+ return r; -+ } -+ -+ td->mirror = enable; -+ -+ return 0; -+} -+ -+static bool taal_get_mirror(struct omap_dss_device *dssdev) -+{ -+ struct taal_data *td = dev_get_drvdata(&dssdev->dev); -+ return td->mirror; -+} -+ -+static int taal_run_test(struct omap_dss_device *dssdev, int test_num) -+{ -+ u8 id1, id2, id3; -+ int r; -+ -+ r = taal_dcs_read_1(DCS_GET_ID1, &id1); -+ if (r) -+ return r; -+ r = taal_dcs_read_1(DCS_GET_ID2, &id2); -+ if (r) -+ return r; -+ r = taal_dcs_read_1(DCS_GET_ID3, &id3); -+ if (r) -+ return r; -+ -+ return 0; -+} -+ -+static int taal_memory_read(struct omap_dss_device *dssdev, -+ void *buf, size_t size, -+ u16 x, u16 y, u16 w, u16 h) -+{ -+ int r; -+ int first = 1; -+ int plen; -+ unsigned buf_used = 0; -+ -+ if (size < w * h * 3) -+ return -ENOMEM; -+ -+ size = min(w * h * 3, -+ dssdev->panel.timings.x_res * -+ dssdev->panel.timings.y_res * 3); -+ -+ /* plen 1 or 2 goes into short packet. until checksum error is fixed, -+ * use short packets. plen 32 works, but bigger packets seem to cause -+ * an error. */ -+ if (size % 2) -+ plen = 1; -+ else -+ plen = 2; -+ -+ taal_setup_update(dssdev, x, y, w, h); -+ -+ r = dsi_vc_set_max_rx_packet_size(TCH, plen); -+ if (r) -+ return r; -+ -+ while (buf_used < size) { -+ u8 dcs_cmd = first ? 0x2e : 0x3e; -+ first = 0; -+ -+ r = dsi_vc_dcs_read(TCH, dcs_cmd, -+ buf + buf_used, size - buf_used); -+ -+ if (r < 0) { -+ dev_err(&dssdev->dev, "read error\n"); -+ goto err; -+ } -+ -+ buf_used += r; -+ -+ if (r < plen) { -+ dev_err(&dssdev->dev, "short read\n"); -+ break; -+ } -+ } -+ -+ r = buf_used; -+ -+err: -+ dsi_vc_set_max_rx_packet_size(TCH, 1); -+ -+ return r; -+} -+ -+static struct omap_dss_driver taal_driver = { -+ .probe = taal_probe, -+ .remove = taal_remove, -+ -+ .enable = taal_enable, -+ .disable = taal_disable, -+ .suspend = taal_suspend, -+ .resume = taal_resume, -+ -+ .setup_update = taal_setup_update, -+ .enable_te = taal_enable_te, -+ .wait_for_te = taal_wait_te, -+ .set_rotate = taal_rotate, -+ .get_rotate = taal_get_rotate, -+ .set_mirror = taal_mirror, -+ .get_mirror = taal_get_mirror, -+ .run_test = taal_run_test, -+ .memory_read = taal_memory_read, -+ -+ .driver = { -+ .name = "taal", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init taal_init(void) -+{ -+ omap_dss_register_driver(&taal_driver); -+ -+ return 0; -+} -+ -+static void __exit taal_exit(void) -+{ -+ omap_dss_unregister_driver(&taal_driver); -+} -+ -+module_init(taal_init); -+module_exit(taal_exit); -+ -+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>"); -+MODULE_DESCRIPTION("Taal Driver"); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/video/omap2/dss/Kconfig -@@ -0,0 +1,89 @@ -+menuconfig OMAP2_DSS -+ tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)" -+ depends on ARCH_OMAP2 || ARCH_OMAP3 -+ help -+ OMAP2/3 Display Subsystem support. -+ -+if OMAP2_DSS -+ -+config OMAP2_VRAM_SIZE -+ int "VRAM size (MB)" -+ range 0 32 -+ default 0 -+ help -+ The amount of SDRAM to reserve at boot time for video RAM use. -+ This VRAM will be used by omapfb and other drivers that need -+ large continuous RAM area for video use. -+ -+ You can also set this with "vram=<bytes>" kernel argument, or -+ in the board file. -+ -+config OMAP2_DSS_DEBUG_SUPPORT -+ bool "Debug support" -+ default y -+ help -+ This enables debug messages. You need to enable printing -+ with 'debug' module parameter. -+ -+config OMAP2_DSS_RFBI -+ bool "RFBI support" -+ default n -+ help -+ MIPI DBI, or RFBI (Remote Framebuffer Interface), support. -+ -+config OMAP2_DSS_VENC -+ bool "VENC support" -+ default y -+ help -+ OMAP Video Encoder support. -+ -+config OMAP2_DSS_SDI -+ bool "SDI support" -+ depends on ARCH_OMAP3 -+ default n -+ help -+ SDI (Serial Display Interface) support. -+ -+config OMAP2_DSS_DSI -+ bool "DSI support" -+ depends on ARCH_OMAP3 -+ default n -+ help -+ MIPI DSI support. -+ -+config OMAP2_DSS_USE_DSI_PLL -+ bool "Use DSI PLL for PCLK (EXPERIMENTAL)" -+ default n -+ depends on OMAP2_DSS_DSI -+ help -+ Use DSI PLL to generate pixel clock. Currently only for DPI output. -+ DSI PLL can be used to generate higher and more precise pixel clocks. -+ -+config OMAP2_DSS_FAKE_VSYNC -+ bool "Fake VSYNC irq from manual update displays" -+ default n -+ help -+ If this is selected, DSI will generate a fake DISPC VSYNC interrupt -+ when DSI has sent a frame. This is only needed with DSI or RFBI -+ displays using manual mode, and you want VSYNC to, for example, -+ time animation. -+ -+config OMAP2_DSS_MIN_FCK_PER_PCK -+ int "Minimum FCK/PCK ratio (for scaling)" -+ range 0 32 -+ default 0 -+ help -+ This can be used to adjust the minimum FCK/PCK ratio. -+ -+ With this you can make sure that DISPC FCK is at least -+ n x PCK. Video plane scaling requires higher FCK than -+ normally. -+ -+ If this is set to 0, there's no extra constraint on the -+ DISPC FCK. However, the FCK will at minimum be -+ 2xPCK (if active matrix) or 3xPCK (if passive matrix). -+ -+ Max FCK is 173MHz, so this doesn't work if your PCK -+ is very high. -+ -+endif ---- /dev/null -+++ b/drivers/video/omap2/dss/Makefile -@@ -0,0 +1,6 @@ -+obj-$(CONFIG_OMAP2_DSS) += omapdss.o -+omapdss-y := core.o dss.o dispc.o dpi.o display.o manager.o overlay.o -+omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o -+omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o -+omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o -+omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o ---- /dev/null -+++ b/drivers/video/omap2/dss/core.c -@@ -0,0 +1,917 @@ -+/* -+ * linux/drivers/video/omap2/dss/core.c -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#define DSS_SUBSYS_NAME "CORE" -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/clk.h> -+#include <linux/err.h> -+#include <linux/platform_device.h> -+#include <linux/seq_file.h> -+#include <linux/debugfs.h> -+#include <linux/io.h> -+#include <linux/device.h> -+ -+#include <mach/display.h> -+#include <mach/clock.h> -+ -+#include "dss.h" -+ -+static struct { -+ struct platform_device *pdev; -+ int ctx_id; -+ -+ struct clk *dss_ick; -+ struct clk *dss1_fck; -+ struct clk *dss2_fck; -+ struct clk *dss_54m_fck; -+ struct clk *dss_96m_fck; -+ unsigned num_clks_enabled; -+} core; -+ -+static void dss_clk_enable_all_no_ctx(void); -+static void dss_clk_disable_all_no_ctx(void); -+static void dss_clk_enable_no_ctx(enum dss_clock clks); -+static void dss_clk_disable_no_ctx(enum dss_clock clks); -+ -+static char *def_disp_name; -+module_param_named(def_disp, def_disp_name, charp, 0); -+MODULE_PARM_DESC(def_disp_name, "default display name"); -+ -+#ifdef DEBUG -+unsigned int dss_debug; -+module_param_named(debug, dss_debug, bool, 0644); -+#endif -+ -+/* CONTEXT */ -+static int dss_get_ctx_id(void) -+{ -+ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; -+ int r; -+ -+ if (!pdata->get_last_off_on_transaction_id) -+ return 0; -+ r = pdata->get_last_off_on_transaction_id(&core.pdev->dev); -+ if (r < 0) { -+ dev_err(&core.pdev->dev, "getting transaction ID failed, " -+ "will force context restore\n"); -+ r = -1; -+ } -+ return r; -+} -+ -+int dss_need_ctx_restore(void) -+{ -+ int id = dss_get_ctx_id(); -+ -+ if (id < 0 || id != core.ctx_id) { -+ DSSDBG("ctx id %d -> id %d\n", -+ core.ctx_id, id); -+ core.ctx_id = id; -+ return 1; -+ } else { -+ return 0; -+ } -+} -+ -+static void save_all_ctx(void) -+{ -+ DSSDBG("save context\n"); -+ -+ dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ dss_save_context(); -+ dispc_save_context(); -+#ifdef CONFIG_OMAP2_DSS_DSI -+ dsi_save_context(); -+#endif -+ -+ dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); -+} -+ -+static void restore_all_ctx(void) -+{ -+ DSSDBG("restore context\n"); -+ -+ dss_clk_enable_all_no_ctx(); -+ -+ dss_restore_context(); -+ dispc_restore_context(); -+#ifdef CONFIG_OMAP2_DSS_DSI -+ dsi_restore_context(); -+#endif -+ -+ dss_clk_disable_all_no_ctx(); -+} -+ -+/* CLOCKS */ -+void dss_dump_clocks(struct seq_file *s) -+{ -+ int i; -+ struct clk *clocks[5] = { -+ core.dss_ick, -+ core.dss1_fck, -+ core.dss2_fck, -+ core.dss_54m_fck, -+ core.dss_96m_fck -+ }; -+ -+ seq_printf(s, "- dss -\n"); -+ -+ seq_printf(s, "internal clk count\t%u\n", core.num_clks_enabled); -+ -+ for (i = 0; i < 5; i++) { -+ if (!clocks[i]) -+ continue; -+ seq_printf(s, "%-15s\t%lu\t%d\n", -+ clocks[i]->name, -+ clk_get_rate(clocks[i]), -+ clocks[i]->usecount); -+ } -+} -+ -+static int dss_get_clock(struct clk **clock, const char *clk_name) -+{ -+ struct clk *clk; -+ -+ clk = clk_get(&core.pdev->dev, clk_name); -+ -+ if (IS_ERR(clk)) { -+ DSSERR("can't get clock %s", clk_name); -+ return PTR_ERR(clk); -+ } -+ -+ *clock = clk; -+ -+ DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); -+ -+ return 0; -+} -+ -+static int dss_get_clocks(void) -+{ -+ int r; -+ -+ core.dss_ick = NULL; -+ core.dss1_fck = NULL; -+ core.dss2_fck = NULL; -+ core.dss_54m_fck = NULL; -+ core.dss_96m_fck = NULL; -+ -+ r = dss_get_clock(&core.dss_ick, "ick"); -+ if (r) -+ goto err; -+ -+ r = dss_get_clock(&core.dss1_fck, "dss1_fck"); -+ if (r) -+ goto err; -+ -+ r = dss_get_clock(&core.dss2_fck, "dss2_fck"); -+ if (r) -+ goto err; -+ -+ r = dss_get_clock(&core.dss_54m_fck, "tv_fck"); -+ if (r) -+ goto err; -+ -+ r = dss_get_clock(&core.dss_96m_fck, "video_fck"); -+ if (r) -+ goto err; -+ -+ return 0; -+ -+err: -+ if (core.dss_ick) -+ clk_put(core.dss_ick); -+ if (core.dss1_fck) -+ clk_put(core.dss1_fck); -+ if (core.dss2_fck) -+ clk_put(core.dss2_fck); -+ if (core.dss_54m_fck) -+ clk_put(core.dss_54m_fck); -+ if (core.dss_96m_fck) -+ clk_put(core.dss_96m_fck); -+ -+ return r; -+} -+ -+static void dss_put_clocks(void) -+{ -+ if (core.dss_96m_fck) -+ clk_put(core.dss_96m_fck); -+ clk_put(core.dss_54m_fck); -+ clk_put(core.dss1_fck); -+ clk_put(core.dss2_fck); -+ clk_put(core.dss_ick); -+} -+ -+unsigned long dss_clk_get_rate(enum dss_clock clk) -+{ -+ switch (clk) { -+ case DSS_CLK_ICK: -+ return clk_get_rate(core.dss_ick); -+ case DSS_CLK_FCK1: -+ return clk_get_rate(core.dss1_fck); -+ case DSS_CLK_FCK2: -+ return clk_get_rate(core.dss2_fck); -+ case DSS_CLK_54M: -+ return clk_get_rate(core.dss_54m_fck); -+ case DSS_CLK_96M: -+ return clk_get_rate(core.dss_96m_fck); -+ } -+ -+ BUG(); -+ return 0; -+} -+ -+static unsigned count_clk_bits(enum dss_clock clks) -+{ -+ unsigned num_clks = 0; -+ -+ if (clks & DSS_CLK_ICK) -+ ++num_clks; -+ if (clks & DSS_CLK_FCK1) -+ ++num_clks; -+ if (clks & DSS_CLK_FCK2) -+ ++num_clks; -+ if (clks & DSS_CLK_54M) -+ ++num_clks; -+ if (clks & DSS_CLK_96M) -+ ++num_clks; -+ -+ return num_clks; -+} -+ -+static void dss_clk_enable_no_ctx(enum dss_clock clks) -+{ -+ unsigned num_clks = count_clk_bits(clks); -+ -+ if (clks & DSS_CLK_ICK) -+ clk_enable(core.dss_ick); -+ if (clks & DSS_CLK_FCK1) -+ clk_enable(core.dss1_fck); -+ if (clks & DSS_CLK_FCK2) -+ clk_enable(core.dss2_fck); -+ if (clks & DSS_CLK_54M) -+ clk_enable(core.dss_54m_fck); -+ if (clks & DSS_CLK_96M) -+ clk_enable(core.dss_96m_fck); -+ -+ core.num_clks_enabled += num_clks; -+} -+ -+void dss_clk_enable(enum dss_clock clks) -+{ -+ dss_clk_enable_no_ctx(clks); -+ -+ if (cpu_is_omap34xx() && dss_need_ctx_restore()) -+ restore_all_ctx(); -+} -+ -+static void dss_clk_disable_no_ctx(enum dss_clock clks) -+{ -+ unsigned num_clks = count_clk_bits(clks); -+ -+ if (clks & DSS_CLK_ICK) -+ clk_disable(core.dss_ick); -+ if (clks & DSS_CLK_FCK1) -+ clk_disable(core.dss1_fck); -+ if (clks & DSS_CLK_FCK2) -+ clk_disable(core.dss2_fck); -+ if (clks & DSS_CLK_54M) -+ clk_disable(core.dss_54m_fck); -+ if (clks & DSS_CLK_96M) -+ clk_disable(core.dss_96m_fck); -+ -+ core.num_clks_enabled -= num_clks; -+} -+ -+void dss_clk_disable(enum dss_clock clks) -+{ -+ if (cpu_is_omap34xx()) { -+ unsigned num_clks = count_clk_bits(clks); -+ -+ BUG_ON(core.num_clks_enabled < num_clks); -+ -+ if (core.num_clks_enabled == num_clks) -+ save_all_ctx(); -+ } -+ -+ dss_clk_disable_no_ctx(clks); -+} -+ -+static void dss_clk_enable_all_no_ctx(void) -+{ -+ enum dss_clock clks; -+ -+ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; -+ if (cpu_is_omap34xx()) -+ clks |= DSS_CLK_96M; -+ dss_clk_enable_no_ctx(clks); -+} -+ -+static void dss_clk_disable_all_no_ctx(void) -+{ -+ enum dss_clock clks; -+ -+ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; -+ if (cpu_is_omap34xx()) -+ clks |= DSS_CLK_96M; -+ dss_clk_disable_no_ctx(clks); -+} -+ -+static void dss_clk_disable_all(void) -+{ -+ enum dss_clock clks; -+ -+ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; -+ if (cpu_is_omap34xx()) -+ clks |= DSS_CLK_96M; -+ dss_clk_disable(clks); -+} -+ -+/* DEBUGFS */ -+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) -+static void dss_debug_dump_clocks(struct seq_file *s) -+{ -+ dss_dump_clocks(s); -+ dispc_dump_clocks(s); -+#ifdef CONFIG_OMAP2_DSS_DSI -+ dsi_dump_clocks(s); -+#endif -+} -+ -+static int dss_debug_show(struct seq_file *s, void *unused) -+{ -+ void (*func)(struct seq_file *) = s->private; -+ func(s); -+ return 0; -+} -+ -+static int dss_debug_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, dss_debug_show, inode->i_private); -+} -+ -+static const struct file_operations dss_debug_fops = { -+ .open = dss_debug_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static struct dentry *dss_debugfs_dir; -+ -+static int dss_initialize_debugfs(void) -+{ -+ dss_debugfs_dir = debugfs_create_dir("omapdss", NULL); -+ if (IS_ERR(dss_debugfs_dir)) { -+ int err = PTR_ERR(dss_debugfs_dir); -+ dss_debugfs_dir = NULL; -+ return err; -+ } -+ -+ debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir, -+ &dss_debug_dump_clocks, &dss_debug_fops); -+ -+ debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir, -+ &dss_dump_regs, &dss_debug_fops); -+ debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir, -+ &dispc_dump_regs, &dss_debug_fops); -+#ifdef CONFIG_OMAP2_DSS_RFBI -+ debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir, -+ &rfbi_dump_regs, &dss_debug_fops); -+#endif -+#ifdef CONFIG_OMAP2_DSS_DSI -+ debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir, -+ &dsi_dump_regs, &dss_debug_fops); -+#endif -+#ifdef CONFIG_OMAP2_DSS_VENC -+ debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir, -+ &venc_dump_regs, &dss_debug_fops); -+#endif -+ return 0; -+} -+ -+static void dss_uninitialize_debugfs(void) -+{ -+ if (dss_debugfs_dir) -+ debugfs_remove_recursive(dss_debugfs_dir); -+} -+#endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */ -+ -+/* PLATFORM DEVICE */ -+static int omap_dss_probe(struct platform_device *pdev) -+{ -+ struct omap_dss_board_info *pdata = pdev->dev.platform_data; -+ int skip_init = 0; -+ int r; -+ int i; -+ -+ core.pdev = pdev; -+ -+ dss_init_overlay_managers(pdev); -+ dss_init_overlays(pdev); -+ -+ r = dss_get_clocks(); -+ if (r) -+ goto fail0; -+ -+ dss_clk_enable_all_no_ctx(); -+ -+ core.ctx_id = dss_get_ctx_id(); -+ DSSDBG("initial ctx id %u\n", core.ctx_id); -+ -+#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT -+ /* DISPC_CONTROL */ -+ if (omap_readl(0x48050440) & 1) /* LCD enabled? */ -+ skip_init = 1; -+#endif -+ -+ r = dss_init(skip_init); -+ if (r) { -+ DSSERR("Failed to initialize DSS\n"); -+ goto fail0; -+ } -+ -+#ifdef CONFIG_OMAP2_DSS_RFBI -+ r = rfbi_init(); -+ if (r) { -+ DSSERR("Failed to initialize rfbi\n"); -+ goto fail0; -+ } -+#endif -+ -+ r = dpi_init(); -+ if (r) { -+ DSSERR("Failed to initialize dpi\n"); -+ goto fail0; -+ } -+ -+ r = dispc_init(); -+ if (r) { -+ DSSERR("Failed to initialize dispc\n"); -+ goto fail0; -+ } -+#ifdef CONFIG_OMAP2_DSS_VENC -+ r = venc_init(pdev); -+ if (r) { -+ DSSERR("Failed to initialize venc\n"); -+ goto fail0; -+ } -+#endif -+ if (cpu_is_omap34xx()) { -+#ifdef CONFIG_OMAP2_DSS_SDI -+ r = sdi_init(skip_init); -+ if (r) { -+ DSSERR("Failed to initialize SDI\n"); -+ goto fail0; -+ } -+#endif -+#ifdef CONFIG_OMAP2_DSS_DSI -+ r = dsi_init(pdev); -+ if (r) { -+ DSSERR("Failed to initialize DSI\n"); -+ goto fail0; -+ } -+#endif -+ } -+ -+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) -+ r = dss_initialize_debugfs(); -+ if (r) -+ goto fail0; -+#endif -+ -+ for (i = 0; i < pdata->num_devices; ++i) { -+ struct omap_dss_device *dssdev = pdata->devices[i]; -+ -+ r = omap_dss_register_device(dssdev); -+ if (r) -+ DSSERR("device reg failed %d\n", i); -+ -+ if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0) -+ pdata->default_device = dssdev; -+ } -+ -+ dss_clk_disable_all(); -+ -+ return 0; -+ -+ /* XXX fail correctly */ -+fail0: -+ return r; -+} -+ -+static int omap_dss_remove(struct platform_device *pdev) -+{ -+ struct omap_dss_board_info *pdata = pdev->dev.platform_data; -+ int i; -+ int c; -+ -+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) -+ dss_uninitialize_debugfs(); -+#endif -+ -+#ifdef CONFIG_OMAP2_DSS_VENC -+ venc_exit(); -+#endif -+ dispc_exit(); -+ dpi_exit(); -+#ifdef CONFIG_OMAP2_DSS_RFBI -+ rfbi_exit(); -+#endif -+ if (cpu_is_omap34xx()) { -+#ifdef CONFIG_OMAP2_DSS_DSI -+ dsi_exit(); -+#endif -+#ifdef CONFIG_OMAP2_DSS_SDI -+ sdi_exit(); -+#endif -+ } -+ -+ dss_exit(); -+ -+ /* these should be removed at some point */ -+ c = core.dss_ick->usecount; -+ if (c > 0) { -+ DSSERR("warning: dss_ick usecount %d, disabling\n", c); -+ while (c-- > 0) -+ clk_disable(core.dss_ick); -+ } -+ -+ c = core.dss1_fck->usecount; -+ if (c > 0) { -+ DSSERR("warning: dss1_fck usecount %d, disabling\n", c); -+ while (c-- > 0) -+ clk_disable(core.dss1_fck); -+ } -+ -+ c = core.dss2_fck->usecount; -+ if (c > 0) { -+ DSSERR("warning: dss2_fck usecount %d, disabling\n", c); -+ while (c-- > 0) -+ clk_disable(core.dss2_fck); -+ } -+ -+ c = core.dss_54m_fck->usecount; -+ if (c > 0) { -+ DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c); -+ while (c-- > 0) -+ clk_disable(core.dss_54m_fck); -+ } -+ -+ if (core.dss_96m_fck) { -+ c = core.dss_96m_fck->usecount; -+ if (c > 0) { -+ DSSERR("warning: dss_96m_fck usecount %d, disabling\n", -+ c); -+ while (c-- > 0) -+ clk_disable(core.dss_96m_fck); -+ } -+ } -+ -+ dss_put_clocks(); -+ -+ dss_uninit_overlays(pdev); -+ dss_uninit_overlay_managers(pdev); -+ -+ for (i = 0; i < pdata->num_devices; ++i) -+ omap_dss_unregister_device(pdata->devices[i]); -+ -+ return 0; -+} -+ -+static void omap_dss_shutdown(struct platform_device *pdev) -+{ -+ DSSDBG("shutdown\n"); -+} -+ -+static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state) -+{ -+ DSSDBG("suspend %d\n", state.event); -+ -+ return dss_suspend_all_devices(); -+} -+ -+static int omap_dss_resume(struct platform_device *pdev) -+{ -+ DSSDBG("resume\n"); -+ -+ return dss_resume_all_devices(); -+} -+ -+static struct platform_driver omap_dss_driver = { -+ .probe = omap_dss_probe, -+ .remove = omap_dss_remove, -+ .shutdown = omap_dss_shutdown, -+ .suspend = omap_dss_suspend, -+ .resume = omap_dss_resume, -+ .driver = { -+ .name = "omapdss", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+/* BUS */ -+static int dss_bus_match(struct device *dev, struct device_driver *driver) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ -+ DSSDBG("bus_match. dev %s/%s, drv %s\n", -+ dev_name(dev), dssdev->driver_name, driver->name); -+ -+ return strcmp(dssdev->driver_name, driver->name) == 0; -+} -+ -+static ssize_t device_name_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ return snprintf(buf, PAGE_SIZE, "%s\n", -+ dssdev->name ? -+ dssdev->name : ""); -+} -+ -+static struct device_attribute default_dev_attrs[] = { -+ __ATTR(name, S_IRUGO, device_name_show, NULL), -+ __ATTR_NULL, -+}; -+ -+static ssize_t driver_name_show(struct device_driver *drv, char *buf) -+{ -+ struct omap_dss_driver *dssdrv = to_dss_driver(drv); -+ return snprintf(buf, PAGE_SIZE, "%s\n", -+ dssdrv->driver.name ? -+ dssdrv->driver.name : ""); -+} -+static struct driver_attribute default_drv_attrs[] = { -+ __ATTR(name, S_IRUGO, driver_name_show, NULL), -+ __ATTR_NULL, -+}; -+ -+static struct bus_type dss_bus_type = { -+ .name = "omapdss", -+ .match = dss_bus_match, -+ .dev_attrs = default_dev_attrs, -+ .drv_attrs = default_drv_attrs, -+}; -+ -+static void dss_bus_release(struct device *dev) -+{ -+ DSSDBG("bus_release\n"); -+} -+ -+static struct device dss_bus = { -+ .release = dss_bus_release, -+}; -+ -+struct bus_type *dss_get_bus(void) -+{ -+ return &dss_bus_type; -+} -+ -+/* DRIVER */ -+static int dss_driver_probe(struct device *dev) -+{ -+ int r; -+ struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver); -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; -+ bool force; -+ -+ DSSDBG("driver_probe: dev %s/%s, drv %s\n", -+ dev_name(dev), dssdev->driver_name, -+ dssdrv->driver.name); -+ -+ dss_init_device(core.pdev, dssdev); -+ -+ /* skip this if the device is behind a ctrl */ -+ if (!dssdev->panel.ctrl) { -+ force = pdata->default_device == dssdev; -+ dss_recheck_connections(dssdev, force); -+ } -+ -+ r = dssdrv->probe(dssdev); -+ -+ if (r) { -+ DSSERR("driver probe failed: %d\n", r); -+ return r; -+ } -+ -+ DSSDBG("probe done for device %s\n", dev_name(dev)); -+ -+ dssdev->driver = dssdrv; -+ -+ return 0; -+} -+ -+static int dss_driver_remove(struct device *dev) -+{ -+ struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver); -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ -+ DSSDBG("driver_remove: dev %s/%s\n", dev_name(dev), -+ dssdev->driver_name); -+ -+ dssdrv->remove(dssdev); -+ -+ dss_uninit_device(core.pdev, dssdev); -+ -+ dssdev->driver = NULL; -+ -+ return 0; -+} -+ -+int omap_dss_register_driver(struct omap_dss_driver *dssdriver) -+{ -+ dssdriver->driver.bus = &dss_bus_type; -+ dssdriver->driver.probe = dss_driver_probe; -+ dssdriver->driver.remove = dss_driver_remove; -+ return driver_register(&dssdriver->driver); -+} -+EXPORT_SYMBOL(omap_dss_register_driver); -+ -+void omap_dss_unregister_driver(struct omap_dss_driver *dssdriver) -+{ -+ driver_unregister(&dssdriver->driver); -+} -+EXPORT_SYMBOL(omap_dss_unregister_driver); -+ -+/* DEVICE */ -+static void reset_device(struct device *dev, int check) -+{ -+ u8 *dev_p = (u8 *)dev; -+ u8 *dev_end = dev_p + sizeof(*dev); -+ void *saved_pdata; -+ -+ saved_pdata = dev->platform_data; -+ if (check) { -+ /* -+ * Check if there is any other setting than platform_data -+ * in struct device; warn that these will be reset by our -+ * init. -+ */ -+ dev->platform_data = NULL; -+ while (dev_p < dev_end) { -+ if (*dev_p) { -+ WARN("%s: struct device fields will be " -+ "discarded\n", -+ __func__); -+ break; -+ } -+ dev_p++; -+ } -+ } -+ memset(dev, 0, sizeof(*dev)); -+ dev->platform_data = saved_pdata; -+} -+ -+ -+static void omap_dss_dev_release(struct device *dev) -+{ -+ reset_device(dev, 0); -+} -+ -+int omap_dss_register_device(struct omap_dss_device *dssdev) -+{ -+ static int dev_num; -+ static int panel_num; -+ int r; -+ -+ WARN_ON(!dssdev->driver_name); -+ -+ reset_device(&dssdev->dev, 1); -+ dssdev->dev.bus = &dss_bus_type; -+ dssdev->dev.parent = &dss_bus; -+ dssdev->dev.release = omap_dss_dev_release; -+ dev_set_name(&dssdev->dev, "display%d", dev_num++); -+ r = device_register(&dssdev->dev); -+ if (r) -+ return r; -+ -+ if (dssdev->ctrl.panel) { -+ struct omap_dss_device *panel = dssdev->ctrl.panel; -+ -+ panel->panel.ctrl = dssdev; -+ -+ reset_device(&panel->dev, 1); -+ panel->dev.bus = &dss_bus_type; -+ panel->dev.parent = &dssdev->dev; -+ panel->dev.release = omap_dss_dev_release; -+ dev_set_name(&panel->dev, "panel%d", panel_num++); -+ r = device_register(&panel->dev); -+ if (r) -+ return r; -+ } -+ -+ return 0; -+} -+ -+void omap_dss_unregister_device(struct omap_dss_device *dssdev) -+{ -+ device_unregister(&dssdev->dev); -+ -+ if (dssdev->ctrl.panel) { -+ struct omap_dss_device *panel = dssdev->ctrl.panel; -+ device_unregister(&panel->dev); -+ } -+} -+ -+/* BUS */ -+static int omap_dss_bus_register(void) -+{ -+ int r; -+ -+ r = bus_register(&dss_bus_type); -+ if (r) { -+ DSSERR("bus register failed\n"); -+ return r; -+ } -+ -+ dev_set_name(&dss_bus, "omapdss"); -+ r = device_register(&dss_bus); -+ if (r) { -+ DSSERR("bus driver register failed\n"); -+ bus_unregister(&dss_bus_type); -+ return r; -+ } -+ -+ return 0; -+} -+ -+/* INIT */ -+ -+#ifdef CONFIG_OMAP2_DSS_MODULE -+static void omap_dss_bus_unregister(void) -+{ -+ device_unregister(&dss_bus); -+ -+ bus_unregister(&dss_bus_type); -+} -+ -+static int __init omap_dss_init(void) -+{ -+ int r; -+ -+ r = omap_dss_bus_register(); -+ if (r) -+ return r; -+ -+ r = platform_driver_register(&omap_dss_driver); -+ if (r) { -+ omap_dss_bus_unregister(); -+ return r; -+ } -+ -+ return 0; -+} -+ -+static void __exit omap_dss_exit(void) -+{ -+ platform_driver_unregister(&omap_dss_driver); -+ -+ omap_dss_bus_unregister(); -+} -+ -+module_init(omap_dss_init); -+module_exit(omap_dss_exit); -+#else -+static int __init omap_dss_init(void) -+{ -+ return omap_dss_bus_register(); -+} -+ -+static int __init omap_dss_init2(void) -+{ -+ return platform_driver_register(&omap_dss_driver); -+} -+ -+core_initcall(omap_dss_init); -+device_initcall(omap_dss_init2); -+#endif -+ -+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>"); -+MODULE_DESCRIPTION("OMAP2/3 Display Subsystem"); -+MODULE_LICENSE("GPL v2"); -+ ---- /dev/null -+++ b/drivers/video/omap2/dss/dispc.c -@@ -0,0 +1,3182 @@ -+/* -+ * linux/drivers/video/omap2/dss/dispc.c -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#define DSS_SUBSYS_NAME "DISPC" -+ -+#include <linux/kernel.h> -+#include <linux/dma-mapping.h> -+#include <linux/vmalloc.h> -+#include <linux/clk.h> -+#include <linux/io.h> -+#include <linux/jiffies.h> -+#include <linux/seq_file.h> -+#include <linux/delay.h> -+#include <linux/workqueue.h> -+ -+#include <mach/sram.h> -+#include <mach/board.h> -+#include <mach/clock.h> -+ -+#include <mach/display.h> -+ -+#include "dss.h" -+ -+/* DISPC */ -+#define DISPC_BASE 0x48050400 -+ -+#define DISPC_SZ_REGS SZ_1K -+ -+struct dispc_reg { u16 idx; }; -+ -+#define DISPC_REG(idx) ((const struct dispc_reg) { idx }) -+ -+/* DISPC common */ -+#define DISPC_REVISION DISPC_REG(0x0000) -+#define DISPC_SYSCONFIG DISPC_REG(0x0010) -+#define DISPC_SYSSTATUS DISPC_REG(0x0014) -+#define DISPC_IRQSTATUS DISPC_REG(0x0018) -+#define DISPC_IRQENABLE DISPC_REG(0x001C) -+#define DISPC_CONTROL DISPC_REG(0x0040) -+#define DISPC_CONFIG DISPC_REG(0x0044) -+#define DISPC_CAPABLE DISPC_REG(0x0048) -+#define DISPC_DEFAULT_COLOR0 DISPC_REG(0x004C) -+#define DISPC_DEFAULT_COLOR1 DISPC_REG(0x0050) -+#define DISPC_TRANS_COLOR0 DISPC_REG(0x0054) -+#define DISPC_TRANS_COLOR1 DISPC_REG(0x0058) -+#define DISPC_LINE_STATUS DISPC_REG(0x005C) -+#define DISPC_LINE_NUMBER DISPC_REG(0x0060) -+#define DISPC_TIMING_H DISPC_REG(0x0064) -+#define DISPC_TIMING_V DISPC_REG(0x0068) -+#define DISPC_POL_FREQ DISPC_REG(0x006C) -+#define DISPC_DIVISOR DISPC_REG(0x0070) -+#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074) -+#define DISPC_SIZE_DIG DISPC_REG(0x0078) -+#define DISPC_SIZE_LCD DISPC_REG(0x007C) -+ -+/* DISPC GFX plane */ -+#define DISPC_GFX_BA0 DISPC_REG(0x0080) -+#define DISPC_GFX_BA1 DISPC_REG(0x0084) -+#define DISPC_GFX_POSITION DISPC_REG(0x0088) -+#define DISPC_GFX_SIZE DISPC_REG(0x008C) -+#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0) -+#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4) -+#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8) -+#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC) -+#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0) -+#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4) -+#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8) -+ -+#define DISPC_DATA_CYCLE1 DISPC_REG(0x01D4) -+#define DISPC_DATA_CYCLE2 DISPC_REG(0x01D8) -+#define DISPC_DATA_CYCLE3 DISPC_REG(0x01DC) -+ -+#define DISPC_CPR_COEF_R DISPC_REG(0x0220) -+#define DISPC_CPR_COEF_G DISPC_REG(0x0224) -+#define DISPC_CPR_COEF_B DISPC_REG(0x0228) -+ -+#define DISPC_GFX_PRELOAD DISPC_REG(0x022C) -+ -+/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */ -+#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx) -+ -+#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000) -+#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004) -+#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008) -+#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C) -+#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010) -+#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014) -+#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018) -+#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C) -+#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020) -+#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024) -+#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028) -+#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C) -+#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030) -+ -+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -+#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8) -+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -+#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8) -+/* coef index i = {0, 1, 2, 3, 4} */ -+#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4) -+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -+#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4) -+ -+#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04) -+ -+ -+#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ -+ DISPC_IRQ_OCP_ERR | \ -+ DISPC_IRQ_VID1_FIFO_UNDERFLOW | \ -+ DISPC_IRQ_VID2_FIFO_UNDERFLOW | \ -+ DISPC_IRQ_SYNC_LOST | \ -+ DISPC_IRQ_SYNC_LOST_DIGIT) -+ -+#define DISPC_MAX_NR_ISRS 8 -+ -+struct omap_dispc_isr_data { -+ omap_dispc_isr_t isr; -+ void *arg; -+ u32 mask; -+}; -+ -+#define REG_GET(idx, start, end) \ -+ FLD_GET(dispc_read_reg(idx), start, end) -+ -+#define REG_FLD_MOD(idx, val, start, end) \ -+ dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) -+ -+static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES, -+ DISPC_VID_ATTRIBUTES(0), -+ DISPC_VID_ATTRIBUTES(1) }; -+ -+static struct { -+ void __iomem *base; -+ -+ struct clk *dpll4_m4_ck; -+ -+ unsigned long cache_req_pck; -+ unsigned long cache_prate; -+ struct dispc_clock_info cache_cinfo; -+ -+ u32 fifo_size[3]; -+ -+ spinlock_t irq_lock; -+ u32 irq_error_mask; -+ struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS]; -+ u32 error_irqs; -+ struct work_struct error_work; -+ -+ u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; -+} dispc; -+ -+static void _omap_dispc_set_irqs(void); -+ -+static inline void dispc_write_reg(const struct dispc_reg idx, u32 val) -+{ -+ __raw_writel(val, dispc.base + idx.idx); -+} -+ -+static inline u32 dispc_read_reg(const struct dispc_reg idx) -+{ -+ return __raw_readl(dispc.base + idx.idx); -+} -+ -+#define SR(reg) \ -+ dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg) -+#define RR(reg) \ -+ dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)]) -+ -+void dispc_save_context(void) -+{ -+ if (cpu_is_omap24xx()) -+ return; -+ -+ SR(SYSCONFIG); -+ SR(IRQENABLE); -+ SR(CONTROL); -+ SR(CONFIG); -+ SR(DEFAULT_COLOR0); -+ SR(DEFAULT_COLOR1); -+ SR(TRANS_COLOR0); -+ SR(TRANS_COLOR1); -+ SR(LINE_NUMBER); -+ SR(TIMING_H); -+ SR(TIMING_V); -+ SR(POL_FREQ); -+ SR(DIVISOR); -+ SR(GLOBAL_ALPHA); -+ SR(SIZE_DIG); -+ SR(SIZE_LCD); -+ -+ SR(GFX_BA0); -+ SR(GFX_BA1); -+ SR(GFX_POSITION); -+ SR(GFX_SIZE); -+ SR(GFX_ATTRIBUTES); -+ SR(GFX_FIFO_THRESHOLD); -+ SR(GFX_ROW_INC); -+ SR(GFX_PIXEL_INC); -+ SR(GFX_WINDOW_SKIP); -+ SR(GFX_TABLE_BA); -+ -+ SR(DATA_CYCLE1); -+ SR(DATA_CYCLE2); -+ SR(DATA_CYCLE3); -+ -+ SR(CPR_COEF_R); -+ SR(CPR_COEF_G); -+ SR(CPR_COEF_B); -+ -+ SR(GFX_PRELOAD); -+ -+ /* VID1 */ -+ SR(VID_BA0(0)); -+ SR(VID_BA1(0)); -+ SR(VID_POSITION(0)); -+ SR(VID_SIZE(0)); -+ SR(VID_ATTRIBUTES(0)); -+ SR(VID_FIFO_THRESHOLD(0)); -+ SR(VID_ROW_INC(0)); -+ SR(VID_PIXEL_INC(0)); -+ SR(VID_FIR(0)); -+ SR(VID_PICTURE_SIZE(0)); -+ SR(VID_ACCU0(0)); -+ SR(VID_ACCU1(0)); -+ -+ SR(VID_FIR_COEF_H(0, 0)); -+ SR(VID_FIR_COEF_H(0, 1)); -+ SR(VID_FIR_COEF_H(0, 2)); -+ SR(VID_FIR_COEF_H(0, 3)); -+ SR(VID_FIR_COEF_H(0, 4)); -+ SR(VID_FIR_COEF_H(0, 5)); -+ SR(VID_FIR_COEF_H(0, 6)); -+ SR(VID_FIR_COEF_H(0, 7)); -+ -+ SR(VID_FIR_COEF_HV(0, 0)); -+ SR(VID_FIR_COEF_HV(0, 1)); -+ SR(VID_FIR_COEF_HV(0, 2)); -+ SR(VID_FIR_COEF_HV(0, 3)); -+ SR(VID_FIR_COEF_HV(0, 4)); -+ SR(VID_FIR_COEF_HV(0, 5)); -+ SR(VID_FIR_COEF_HV(0, 6)); -+ SR(VID_FIR_COEF_HV(0, 7)); -+ -+ SR(VID_CONV_COEF(0, 0)); -+ SR(VID_CONV_COEF(0, 1)); -+ SR(VID_CONV_COEF(0, 2)); -+ SR(VID_CONV_COEF(0, 3)); -+ SR(VID_CONV_COEF(0, 4)); -+ -+ SR(VID_FIR_COEF_V(0, 0)); -+ SR(VID_FIR_COEF_V(0, 1)); -+ SR(VID_FIR_COEF_V(0, 2)); -+ SR(VID_FIR_COEF_V(0, 3)); -+ SR(VID_FIR_COEF_V(0, 4)); -+ SR(VID_FIR_COEF_V(0, 5)); -+ SR(VID_FIR_COEF_V(0, 6)); -+ SR(VID_FIR_COEF_V(0, 7)); -+ -+ SR(VID_PRELOAD(0)); -+ -+ /* VID2 */ -+ SR(VID_BA0(1)); -+ SR(VID_BA1(1)); -+ SR(VID_POSITION(1)); -+ SR(VID_SIZE(1)); -+ SR(VID_ATTRIBUTES(1)); -+ SR(VID_FIFO_THRESHOLD(1)); -+ SR(VID_ROW_INC(1)); -+ SR(VID_PIXEL_INC(1)); -+ SR(VID_FIR(1)); -+ SR(VID_PICTURE_SIZE(1)); -+ SR(VID_ACCU0(1)); -+ SR(VID_ACCU1(1)); -+ -+ SR(VID_FIR_COEF_H(1, 0)); -+ SR(VID_FIR_COEF_H(1, 1)); -+ SR(VID_FIR_COEF_H(1, 2)); -+ SR(VID_FIR_COEF_H(1, 3)); -+ SR(VID_FIR_COEF_H(1, 4)); -+ SR(VID_FIR_COEF_H(1, 5)); -+ SR(VID_FIR_COEF_H(1, 6)); -+ SR(VID_FIR_COEF_H(1, 7)); -+ -+ SR(VID_FIR_COEF_HV(1, 0)); -+ SR(VID_FIR_COEF_HV(1, 1)); -+ SR(VID_FIR_COEF_HV(1, 2)); -+ SR(VID_FIR_COEF_HV(1, 3)); -+ SR(VID_FIR_COEF_HV(1, 4)); -+ SR(VID_FIR_COEF_HV(1, 5)); -+ SR(VID_FIR_COEF_HV(1, 6)); -+ SR(VID_FIR_COEF_HV(1, 7)); -+ -+ SR(VID_CONV_COEF(1, 0)); -+ SR(VID_CONV_COEF(1, 1)); -+ SR(VID_CONV_COEF(1, 2)); -+ SR(VID_CONV_COEF(1, 3)); -+ SR(VID_CONV_COEF(1, 4)); -+ -+ SR(VID_FIR_COEF_V(1, 0)); -+ SR(VID_FIR_COEF_V(1, 1)); -+ SR(VID_FIR_COEF_V(1, 2)); -+ SR(VID_FIR_COEF_V(1, 3)); -+ SR(VID_FIR_COEF_V(1, 4)); -+ SR(VID_FIR_COEF_V(1, 5)); -+ SR(VID_FIR_COEF_V(1, 6)); -+ SR(VID_FIR_COEF_V(1, 7)); -+ -+ SR(VID_PRELOAD(1)); -+} -+ -+void dispc_restore_context(void) -+{ -+ RR(SYSCONFIG); -+ RR(IRQENABLE); -+ /*RR(CONTROL);*/ -+ RR(CONFIG); -+ RR(DEFAULT_COLOR0); -+ RR(DEFAULT_COLOR1); -+ RR(TRANS_COLOR0); -+ RR(TRANS_COLOR1); -+ RR(LINE_NUMBER); -+ RR(TIMING_H); -+ RR(TIMING_V); -+ RR(POL_FREQ); -+ RR(DIVISOR); -+ RR(GLOBAL_ALPHA); -+ RR(SIZE_DIG); -+ RR(SIZE_LCD); -+ -+ RR(GFX_BA0); -+ RR(GFX_BA1); -+ RR(GFX_POSITION); -+ RR(GFX_SIZE); -+ RR(GFX_ATTRIBUTES); -+ RR(GFX_FIFO_THRESHOLD); -+ RR(GFX_ROW_INC); -+ RR(GFX_PIXEL_INC); -+ RR(GFX_WINDOW_SKIP); -+ RR(GFX_TABLE_BA); -+ -+ RR(DATA_CYCLE1); -+ RR(DATA_CYCLE2); -+ RR(DATA_CYCLE3); -+ -+ RR(CPR_COEF_R); -+ RR(CPR_COEF_G); -+ RR(CPR_COEF_B); -+ -+ RR(GFX_PRELOAD); -+ -+ /* VID1 */ -+ RR(VID_BA0(0)); -+ RR(VID_BA1(0)); -+ RR(VID_POSITION(0)); -+ RR(VID_SIZE(0)); -+ RR(VID_ATTRIBUTES(0)); -+ RR(VID_FIFO_THRESHOLD(0)); -+ RR(VID_ROW_INC(0)); -+ RR(VID_PIXEL_INC(0)); -+ RR(VID_FIR(0)); -+ RR(VID_PICTURE_SIZE(0)); -+ RR(VID_ACCU0(0)); -+ RR(VID_ACCU1(0)); -+ -+ RR(VID_FIR_COEF_H(0, 0)); -+ RR(VID_FIR_COEF_H(0, 1)); -+ RR(VID_FIR_COEF_H(0, 2)); -+ RR(VID_FIR_COEF_H(0, 3)); -+ RR(VID_FIR_COEF_H(0, 4)); -+ RR(VID_FIR_COEF_H(0, 5)); -+ RR(VID_FIR_COEF_H(0, 6)); -+ RR(VID_FIR_COEF_H(0, 7)); -+ -+ RR(VID_FIR_COEF_HV(0, 0)); -+ RR(VID_FIR_COEF_HV(0, 1)); -+ RR(VID_FIR_COEF_HV(0, 2)); -+ RR(VID_FIR_COEF_HV(0, 3)); -+ RR(VID_FIR_COEF_HV(0, 4)); -+ RR(VID_FIR_COEF_HV(0, 5)); -+ RR(VID_FIR_COEF_HV(0, 6)); -+ RR(VID_FIR_COEF_HV(0, 7)); -+ -+ RR(VID_CONV_COEF(0, 0)); -+ RR(VID_CONV_COEF(0, 1)); -+ RR(VID_CONV_COEF(0, 2)); -+ RR(VID_CONV_COEF(0, 3)); -+ RR(VID_CONV_COEF(0, 4)); -+ -+ RR(VID_FIR_COEF_V(0, 0)); -+ RR(VID_FIR_COEF_V(0, 1)); -+ RR(VID_FIR_COEF_V(0, 2)); -+ RR(VID_FIR_COEF_V(0, 3)); -+ RR(VID_FIR_COEF_V(0, 4)); -+ RR(VID_FIR_COEF_V(0, 5)); -+ RR(VID_FIR_COEF_V(0, 6)); -+ RR(VID_FIR_COEF_V(0, 7)); -+ -+ RR(VID_PRELOAD(0)); -+ -+ /* VID2 */ -+ RR(VID_BA0(1)); -+ RR(VID_BA1(1)); -+ RR(VID_POSITION(1)); -+ RR(VID_SIZE(1)); -+ RR(VID_ATTRIBUTES(1)); -+ RR(VID_FIFO_THRESHOLD(1)); -+ RR(VID_ROW_INC(1)); -+ RR(VID_PIXEL_INC(1)); -+ RR(VID_FIR(1)); -+ RR(VID_PICTURE_SIZE(1)); -+ RR(VID_ACCU0(1)); -+ RR(VID_ACCU1(1)); -+ -+ RR(VID_FIR_COEF_H(1, 0)); -+ RR(VID_FIR_COEF_H(1, 1)); -+ RR(VID_FIR_COEF_H(1, 2)); -+ RR(VID_FIR_COEF_H(1, 3)); -+ RR(VID_FIR_COEF_H(1, 4)); -+ RR(VID_FIR_COEF_H(1, 5)); -+ RR(VID_FIR_COEF_H(1, 6)); -+ RR(VID_FIR_COEF_H(1, 7)); -+ -+ RR(VID_FIR_COEF_HV(1, 0)); -+ RR(VID_FIR_COEF_HV(1, 1)); -+ RR(VID_FIR_COEF_HV(1, 2)); -+ RR(VID_FIR_COEF_HV(1, 3)); -+ RR(VID_FIR_COEF_HV(1, 4)); -+ RR(VID_FIR_COEF_HV(1, 5)); -+ RR(VID_FIR_COEF_HV(1, 6)); -+ RR(VID_FIR_COEF_HV(1, 7)); -+ -+ RR(VID_CONV_COEF(1, 0)); -+ RR(VID_CONV_COEF(1, 1)); -+ RR(VID_CONV_COEF(1, 2)); -+ RR(VID_CONV_COEF(1, 3)); -+ RR(VID_CONV_COEF(1, 4)); -+ -+ RR(VID_FIR_COEF_V(1, 0)); -+ RR(VID_FIR_COEF_V(1, 1)); -+ RR(VID_FIR_COEF_V(1, 2)); -+ RR(VID_FIR_COEF_V(1, 3)); -+ RR(VID_FIR_COEF_V(1, 4)); -+ RR(VID_FIR_COEF_V(1, 5)); -+ RR(VID_FIR_COEF_V(1, 6)); -+ RR(VID_FIR_COEF_V(1, 7)); -+ -+ RR(VID_PRELOAD(1)); -+ -+ /* enable last, because LCD & DIGIT enable are here */ -+ RR(CONTROL); -+} -+ -+#undef SR -+#undef RR -+ -+static inline void enable_clocks(bool enable) -+{ -+ if (enable) -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ else -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+} -+ -+bool dispc_go_busy(enum omap_channel channel) -+{ -+ int bit; -+ -+ if (channel == OMAP_DSS_CHANNEL_LCD) -+ bit = 5; /* GOLCD */ -+ else -+ bit = 6; /* GODIGIT */ -+ -+ return REG_GET(DISPC_CONTROL, bit, bit) == 1; -+} -+ -+void dispc_go(enum omap_channel channel) -+{ -+ int bit; -+ -+ enable_clocks(1); -+ -+ if (channel == OMAP_DSS_CHANNEL_LCD) -+ bit = 0; /* LCDENABLE */ -+ else -+ bit = 1; /* DIGITALENABLE */ -+ -+ /* if the channel is not enabled, we don't need GO */ -+ if (REG_GET(DISPC_CONTROL, bit, bit) == 0) -+ goto end; -+ -+ if (channel == OMAP_DSS_CHANNEL_LCD) -+ bit = 5; /* GOLCD */ -+ else -+ bit = 6; /* GODIGIT */ -+ -+ if (REG_GET(DISPC_CONTROL, bit, bit) == 1) { -+ DSSERR("GO bit not down for channel %d\n", channel); -+ goto end; -+ } -+ -+ DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT"); -+ -+ REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit); -+end: -+ enable_clocks(0); -+} -+ -+static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value) -+{ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value); -+} -+ -+static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value) -+{ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value); -+} -+ -+static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value) -+{ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value); -+} -+ -+static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup, -+ int vscaleup, int five_taps) -+{ -+ /* Coefficients for horizontal up-sampling */ -+ static const u32 coef_hup[8] = { -+ 0x00800000, -+ 0x0D7CF800, -+ 0x1E70F5FF, -+ 0x335FF5FE, -+ 0xF74949F7, -+ 0xF55F33FB, -+ 0xF5701EFE, -+ 0xF87C0DFF, -+ }; -+ -+ /* Coefficients for horizontal down-sampling */ -+ static const u32 coef_hdown[8] = { -+ 0x24382400, -+ 0x28371FFE, -+ 0x2C361BFB, -+ 0x303516F9, -+ 0x11343311, -+ 0x1635300C, -+ 0x1B362C08, -+ 0x1F372804, -+ }; -+ -+ /* Coefficients for horizontal and vertical up-sampling */ -+ static const u32 coef_hvup[2][8] = { -+ { -+ 0x00800000, -+ 0x037B02FF, -+ 0x0C6F05FE, -+ 0x205907FB, -+ 0x00404000, -+ 0x075920FE, -+ 0x056F0CFF, -+ 0x027B0300, -+ }, -+ { -+ 0x00800000, -+ 0x0D7CF8FF, -+ 0x1E70F5FE, -+ 0x335FF5FB, -+ 0xF7404000, -+ 0xF55F33FE, -+ 0xF5701EFF, -+ 0xF87C0D00, -+ }, -+ }; -+ -+ /* Coefficients for horizontal and vertical down-sampling */ -+ static const u32 coef_hvdown[2][8] = { -+ { -+ 0x24382400, -+ 0x28391F04, -+ 0x2D381B08, -+ 0x3237170C, -+ 0x123737F7, -+ 0x173732F9, -+ 0x1B382DFB, -+ 0x1F3928FE, -+ }, -+ { -+ 0x24382400, -+ 0x28371F04, -+ 0x2C361B08, -+ 0x3035160C, -+ 0x113433F7, -+ 0x163530F9, -+ 0x1B362CFB, -+ 0x1F3728FE, -+ }, -+ }; -+ -+ /* Coefficients for vertical up-sampling */ -+ static const u32 coef_vup[8] = { -+ 0x00000000, -+ 0x0000FF00, -+ 0x0000FEFF, -+ 0x0000FBFE, -+ 0x000000F7, -+ 0x0000FEFB, -+ 0x0000FFFE, -+ 0x000000FF, -+ }; -+ -+ -+ /* Coefficients for vertical down-sampling */ -+ static const u32 coef_vdown[8] = { -+ 0x00000000, -+ 0x000004FE, -+ 0x000008FB, -+ 0x00000CF9, -+ 0x0000F711, -+ 0x0000F90C, -+ 0x0000FB08, -+ 0x0000FE04, -+ }; -+ -+ const u32 *h_coef; -+ const u32 *hv_coef; -+ const u32 *hv_coef_mod; -+ const u32 *v_coef; -+ int i; -+ -+ if (hscaleup) -+ h_coef = coef_hup; -+ else -+ h_coef = coef_hdown; -+ -+ if (vscaleup) { -+ hv_coef = coef_hvup[five_taps]; -+ v_coef = coef_vup; -+ -+ if (hscaleup) -+ hv_coef_mod = NULL; -+ else -+ hv_coef_mod = coef_hvdown[five_taps]; -+ } else { -+ hv_coef = coef_hvdown[five_taps]; -+ v_coef = coef_vdown; -+ -+ if (hscaleup) -+ hv_coef_mod = coef_hvup[five_taps]; -+ else -+ hv_coef_mod = NULL; -+ } -+ -+ for (i = 0; i < 8; i++) { -+ u32 h, hv; -+ -+ h = h_coef[i]; -+ -+ hv = hv_coef[i]; -+ -+ if (hv_coef_mod) { -+ hv &= 0xffffff00; -+ hv |= (hv_coef_mod[i] & 0xff); -+ } -+ -+ _dispc_write_firh_reg(plane, i, h); -+ _dispc_write_firhv_reg(plane, i, hv); -+ } -+ -+ if (!five_taps) -+ return; -+ -+ for (i = 0; i < 8; i++) { -+ u32 v; -+ v = v_coef[i]; -+ _dispc_write_firv_reg(plane, i, v); -+ } -+} -+ -+static void _dispc_setup_color_conv_coef(void) -+{ -+ const struct color_conv_coef { -+ int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; -+ int full_range; -+ } ctbl_bt601_5 = { -+ 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, -+ }; -+ -+ const struct color_conv_coef *ct; -+ -+#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) -+ -+ ct = &ctbl_bt601_5; -+ -+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb)); -+ -+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb)); -+ -+#undef CVAL -+ -+ REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11); -+ REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11); -+} -+ -+ -+static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr) -+{ -+ const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0, -+ DISPC_VID_BA0(0), -+ DISPC_VID_BA0(1) }; -+ -+ dispc_write_reg(ba0_reg[plane], paddr); -+} -+ -+static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr) -+{ -+ const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1, -+ DISPC_VID_BA1(0), -+ DISPC_VID_BA1(1) }; -+ -+ dispc_write_reg(ba1_reg[plane], paddr); -+} -+ -+static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y) -+{ -+ const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION, -+ DISPC_VID_POSITION(0), -+ DISPC_VID_POSITION(1) }; -+ -+ u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); -+ dispc_write_reg(pos_reg[plane], val); -+} -+ -+static void _dispc_set_pic_size(enum omap_plane plane, int width, int height) -+{ -+ const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE, -+ DISPC_VID_PICTURE_SIZE(0), -+ DISPC_VID_PICTURE_SIZE(1) }; -+ u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); -+ dispc_write_reg(siz_reg[plane], val); -+} -+ -+static void _dispc_set_vid_size(enum omap_plane plane, int width, int height) -+{ -+ u32 val; -+ const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0), -+ DISPC_VID_SIZE(1) }; -+ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); -+ dispc_write_reg(vsi_reg[plane-1], val); -+} -+ -+static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha) -+{ -+ -+ BUG_ON(plane == OMAP_DSS_VIDEO1); -+ -+ if (plane == OMAP_DSS_GFX) -+ REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0); -+ else if (plane == OMAP_DSS_VIDEO2) -+ REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16); -+} -+ -+static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc) -+{ -+ const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC, -+ DISPC_VID_PIXEL_INC(0), -+ DISPC_VID_PIXEL_INC(1) }; -+ -+ dispc_write_reg(ri_reg[plane], inc); -+} -+ -+static void _dispc_set_row_inc(enum omap_plane plane, s32 inc) -+{ -+ const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC, -+ DISPC_VID_ROW_INC(0), -+ DISPC_VID_ROW_INC(1) }; -+ -+ dispc_write_reg(ri_reg[plane], inc); -+} -+ -+static void _dispc_set_color_mode(enum omap_plane plane, -+ enum omap_color_mode color_mode) -+{ -+ u32 m = 0; -+ -+ switch (color_mode) { -+ case OMAP_DSS_COLOR_CLUT1: -+ m = 0x0; break; -+ case OMAP_DSS_COLOR_CLUT2: -+ m = 0x1; break; -+ case OMAP_DSS_COLOR_CLUT4: -+ m = 0x2; break; -+ case OMAP_DSS_COLOR_CLUT8: -+ m = 0x3; break; -+ case OMAP_DSS_COLOR_RGB12U: -+ m = 0x4; break; -+ case OMAP_DSS_COLOR_ARGB16: -+ m = 0x5; break; -+ case OMAP_DSS_COLOR_RGB16: -+ m = 0x6; break; -+ case OMAP_DSS_COLOR_RGB24U: -+ m = 0x8; break; -+ case OMAP_DSS_COLOR_RGB24P: -+ m = 0x9; break; -+ case OMAP_DSS_COLOR_YUV2: -+ m = 0xa; break; -+ case OMAP_DSS_COLOR_UYVY: -+ m = 0xb; break; -+ case OMAP_DSS_COLOR_ARGB32: -+ m = 0xc; break; -+ case OMAP_DSS_COLOR_RGBA32: -+ m = 0xd; break; -+ case OMAP_DSS_COLOR_RGBX32: -+ m = 0xe; break; -+ default: -+ BUG(); break; -+ } -+ -+ REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1); -+} -+ -+static void _dispc_set_channel_out(enum omap_plane plane, -+ enum omap_channel channel) -+{ -+ int shift; -+ u32 val; -+ -+ switch (plane) { -+ case OMAP_DSS_GFX: -+ shift = 8; -+ break; -+ case OMAP_DSS_VIDEO1: -+ case OMAP_DSS_VIDEO2: -+ shift = 16; -+ break; -+ default: -+ BUG(); -+ return; -+ } -+ -+ val = dispc_read_reg(dispc_reg_att[plane]); -+ val = FLD_MOD(val, channel, shift, shift); -+ dispc_write_reg(dispc_reg_att[plane], val); -+} -+ -+void dispc_set_burst_size(enum omap_plane plane, -+ enum omap_burst_size burst_size) -+{ -+ int shift; -+ u32 val; -+ -+ enable_clocks(1); -+ -+ switch (plane) { -+ case OMAP_DSS_GFX: -+ shift = 6; -+ break; -+ case OMAP_DSS_VIDEO1: -+ case OMAP_DSS_VIDEO2: -+ shift = 14; -+ break; -+ default: -+ BUG(); -+ return; -+ } -+ -+ val = dispc_read_reg(dispc_reg_att[plane]); -+ val = FLD_MOD(val, burst_size, shift+1, shift); -+ dispc_write_reg(dispc_reg_att[plane], val); -+ -+ enable_clocks(0); -+} -+ -+static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable) -+{ -+ u32 val; -+ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ val = dispc_read_reg(dispc_reg_att[plane]); -+ val = FLD_MOD(val, enable, 9, 9); -+ dispc_write_reg(dispc_reg_att[plane], val); -+} -+ -+void dispc_enable_replication(enum omap_plane plane, bool enable) -+{ -+ int bit; -+ -+ if (plane == OMAP_DSS_GFX) -+ bit = 5; -+ else -+ bit = 10; -+ -+ enable_clocks(1); -+ REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit); -+ enable_clocks(0); -+} -+ -+void dispc_set_lcd_size(u16 width, u16 height) -+{ -+ u32 val; -+ BUG_ON((width > (1 << 11)) || (height > (1 << 11))); -+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); -+ enable_clocks(1); -+ dispc_write_reg(DISPC_SIZE_LCD, val); -+ enable_clocks(0); -+} -+ -+void dispc_set_digit_size(u16 width, u16 height) -+{ -+ u32 val; -+ BUG_ON((width > (1 << 11)) || (height > (1 << 11))); -+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); -+ enable_clocks(1); -+ dispc_write_reg(DISPC_SIZE_DIG, val); -+ enable_clocks(0); -+} -+ -+static void dispc_read_plane_fifo_sizes(void) -+{ -+ const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS, -+ DISPC_VID_FIFO_SIZE_STATUS(0), -+ DISPC_VID_FIFO_SIZE_STATUS(1) }; -+ u32 size; -+ int plane; -+ -+ enable_clocks(1); -+ -+ for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) { -+ if (cpu_is_omap24xx()) -+ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0); -+ else if (cpu_is_omap34xx()) -+ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0); -+ else -+ BUG(); -+ -+ dispc.fifo_size[plane] = size; -+ } -+ -+ enable_clocks(0); -+} -+ -+u32 dispc_get_plane_fifo_size(enum omap_plane plane) -+{ -+ return dispc.fifo_size[plane]; -+} -+ -+void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high) -+{ -+ const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD, -+ DISPC_VID_FIFO_THRESHOLD(0), -+ DISPC_VID_FIFO_THRESHOLD(1) }; -+ enable_clocks(1); -+ -+ DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n", -+ plane, -+ REG_GET(ftrs_reg[plane], 11, 0), -+ REG_GET(ftrs_reg[plane], 27, 16), -+ low, high); -+ -+ if (cpu_is_omap24xx()) -+ dispc_write_reg(ftrs_reg[plane], -+ FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0)); -+ else -+ dispc_write_reg(ftrs_reg[plane], -+ FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0)); -+ -+ enable_clocks(0); -+} -+ -+void dispc_enable_fifomerge(bool enable) -+{ -+ enable_clocks(1); -+ -+ DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); -+ REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); -+ -+ enable_clocks(0); -+} -+ -+static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc) -+{ -+ u32 val; -+ const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0), -+ DISPC_VID_FIR(1) }; -+ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ if (cpu_is_omap24xx()) -+ val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0); -+ else -+ val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); -+ dispc_write_reg(fir_reg[plane-1], val); -+} -+ -+static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) -+{ -+ u32 val; -+ const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0), -+ DISPC_VID_ACCU0(1) }; -+ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); -+ dispc_write_reg(ac0_reg[plane-1], val); -+} -+ -+static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) -+{ -+ u32 val; -+ const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0), -+ DISPC_VID_ACCU1(1) }; -+ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); -+ dispc_write_reg(ac1_reg[plane-1], val); -+} -+ -+ -+static void _dispc_set_scaling(enum omap_plane plane, -+ u16 orig_width, u16 orig_height, -+ u16 out_width, u16 out_height, -+ bool ilace, bool five_taps, -+ bool fieldmode) -+{ -+ int fir_hinc; -+ int fir_vinc; -+ int hscaleup, vscaleup; -+ int accu0 = 0; -+ int accu1 = 0; -+ u32 l; -+ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ hscaleup = orig_width <= out_width; -+ vscaleup = orig_height <= out_height; -+ -+ _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps); -+ -+ if (!orig_width || orig_width == out_width) -+ fir_hinc = 0; -+ else -+ fir_hinc = 1024 * orig_width / out_width; -+ -+ if (!orig_height || orig_height == out_height) -+ fir_vinc = 0; -+ else -+ fir_vinc = 1024 * orig_height / out_height; -+ -+ _dispc_set_fir(plane, fir_hinc, fir_vinc); -+ -+ l = dispc_read_reg(dispc_reg_att[plane]); -+ l &= ~((0x0f << 5) | (0x3 << 21)); -+ -+ l |= fir_hinc ? (1 << 5) : 0; -+ l |= fir_vinc ? (1 << 6) : 0; -+ -+ l |= hscaleup ? 0 : (1 << 7); -+ l |= vscaleup ? 0 : (1 << 8); -+ -+ l |= five_taps ? (1 << 21) : 0; -+ l |= five_taps ? (1 << 22) : 0; -+ -+ dispc_write_reg(dispc_reg_att[plane], l); -+ -+ /* -+ * field 0 = even field = bottom field -+ * field 1 = odd field = top field -+ */ -+ if (ilace && !fieldmode) { -+ accu1 = 0; -+ accu0 = (fir_vinc / 2) & 0x3ff; -+ if (accu0 >= 1024/2) { -+ accu1 = 1024/2; -+ accu0 -= accu1; -+ } -+ } -+ -+ _dispc_set_vid_accu0(plane, 0, accu0); -+ _dispc_set_vid_accu1(plane, 0, accu1); -+} -+ -+static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation, -+ bool mirroring, enum omap_color_mode color_mode) -+{ -+ if (color_mode == OMAP_DSS_COLOR_YUV2 || -+ color_mode == OMAP_DSS_COLOR_UYVY) { -+ int vidrot = 0; -+ -+ if (mirroring) { -+ switch (rotation) { -+ case 0: -+ vidrot = 2; -+ break; -+ case 1: -+ vidrot = 1; -+ break; -+ case 2: -+ vidrot = 0; -+ break; -+ case 3: -+ vidrot = 3; -+ break; -+ } -+ } else { -+ switch (rotation) { -+ case 0: -+ vidrot = 0; -+ break; -+ case 1: -+ vidrot = 1; -+ break; -+ case 2: -+ vidrot = 2; -+ break; -+ case 3: -+ vidrot = 3; -+ break; -+ } -+ } -+ -+ REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12); -+ -+ if (rotation == 1 || rotation == 3) -+ REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18); -+ else -+ REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18); -+ } else { -+ REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12); -+ REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18); -+ } -+} -+ -+static s32 pixinc(int pixels, u8 ps) -+{ -+ if (pixels == 1) -+ return 1; -+ else if (pixels > 1) -+ return 1 + (pixels - 1) * ps; -+ else if (pixels < 0) -+ return 1 - (-pixels + 1) * ps; -+ else -+ BUG(); -+} -+ -+static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, -+ u16 screen_width, -+ u16 width, u16 height, -+ enum omap_color_mode color_mode, bool fieldmode, -+ unsigned int field_offset, -+ unsigned *offset0, unsigned *offset1, -+ s32 *row_inc, s32 *pix_inc) -+{ -+ u8 ps; -+ -+ switch (color_mode) { -+ case OMAP_DSS_COLOR_RGB16: -+ case OMAP_DSS_COLOR_ARGB16: -+ ps = 2; -+ break; -+ -+ case OMAP_DSS_COLOR_RGB24P: -+ ps = 3; -+ break; -+ -+ case OMAP_DSS_COLOR_RGB24U: -+ case OMAP_DSS_COLOR_ARGB32: -+ case OMAP_DSS_COLOR_RGBA32: -+ case OMAP_DSS_COLOR_RGBX32: -+ case OMAP_DSS_COLOR_YUV2: -+ case OMAP_DSS_COLOR_UYVY: -+ ps = 4; -+ break; -+ -+ default: -+ BUG(); -+ return; -+ } -+ -+ DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, -+ width, height); -+ -+ /* -+ * field 0 = even field = bottom field -+ * field 1 = odd field = top field -+ */ -+ switch (rotation + mirror * 4) { -+ case 0: -+ case 2: -+ /* -+ * If the pixel format is YUV or UYVY divide the width -+ * of the image by 2 for 0 and 180 degree rotation. -+ */ -+ if (color_mode == OMAP_DSS_COLOR_YUV2 || -+ color_mode == OMAP_DSS_COLOR_UYVY) -+ width = width >> 1; -+ case 1: -+ case 3: -+ *offset1 = 0; -+ if (field_offset) -+ *offset0 = field_offset * screen_width * ps; -+ else -+ *offset0 = 0; -+ -+ *row_inc = pixinc(1 + (screen_width - width) + -+ (fieldmode ? screen_width : 0), -+ ps); -+ *pix_inc = pixinc(1, ps); -+ break; -+ -+ case 4: -+ case 6: -+ /* If the pixel format is YUV or UYVY divide the width -+ * of the image by 2 for 0 degree and 180 degree -+ */ -+ if (color_mode == OMAP_DSS_COLOR_YUV2 || -+ color_mode == OMAP_DSS_COLOR_UYVY) -+ width = width >> 1; -+ case 5: -+ case 7: -+ *offset1 = 0; -+ if (field_offset) -+ *offset0 = field_offset * screen_width * ps; -+ else -+ *offset0 = 0; -+ *row_inc = pixinc(1 - (screen_width + width) - -+ (fieldmode ? screen_width : 0), -+ ps); -+ *pix_inc = pixinc(1, ps); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+ -+static void calc_dma_rotation_offset(u8 rotation, bool mirror, -+ u16 screen_width, -+ u16 width, u16 height, -+ enum omap_color_mode color_mode, bool fieldmode, -+ unsigned int field_offset, -+ unsigned *offset0, unsigned *offset1, -+ s32 *row_inc, s32 *pix_inc) -+{ -+ u8 ps; -+ u16 fbw, fbh; -+ -+ switch (color_mode) { -+ case OMAP_DSS_COLOR_RGB16: -+ case OMAP_DSS_COLOR_ARGB16: -+ ps = 2; -+ break; -+ -+ case OMAP_DSS_COLOR_RGB24P: -+ ps = 3; -+ break; -+ -+ case OMAP_DSS_COLOR_RGB24U: -+ case OMAP_DSS_COLOR_ARGB32: -+ case OMAP_DSS_COLOR_RGBA32: -+ case OMAP_DSS_COLOR_RGBX32: -+ ps = 4; -+ break; -+ -+ case OMAP_DSS_COLOR_YUV2: -+ case OMAP_DSS_COLOR_UYVY: -+ ps = 2; -+ break; -+ default: -+ BUG(); -+ return; -+ } -+ -+ DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, -+ width, height); -+ -+ /* width & height are overlay sizes, convert to fb sizes */ -+ -+ if (rotation == 0 || rotation == 2) { -+ fbw = width; -+ fbh = height; -+ } else { -+ fbw = height; -+ fbh = width; -+ } -+ -+ /* -+ * field 0 = even field = bottom field -+ * field 1 = odd field = top field -+ */ -+ switch (rotation + mirror * 4) { -+ case 0: -+ *offset1 = 0; -+ if (field_offset) -+ *offset0 = *offset1 + field_offset * screen_width * ps; -+ else -+ *offset0 = *offset1; -+ *row_inc = pixinc(1 + (screen_width - fbw) + -+ (fieldmode ? screen_width : 0), -+ ps); -+ *pix_inc = pixinc(1, ps); -+ break; -+ case 1: -+ *offset1 = screen_width * (fbh - 1) * ps; -+ if (field_offset) -+ *offset0 = *offset1 + field_offset * ps; -+ else -+ *offset0 = *offset1; -+ *row_inc = pixinc(screen_width * (fbh - 1) + 1 + -+ (fieldmode ? 1 : 0), ps); -+ *pix_inc = pixinc(-screen_width, ps); -+ break; -+ case 2: -+ *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; -+ if (field_offset) -+ *offset0 = *offset1 - field_offset * screen_width * ps; -+ else -+ *offset0 = *offset1; -+ *row_inc = pixinc(-1 - -+ (screen_width - fbw) - -+ (fieldmode ? screen_width : 0), -+ ps); -+ *pix_inc = pixinc(-1, ps); -+ break; -+ case 3: -+ *offset1 = (fbw - 1) * ps; -+ if (field_offset) -+ *offset0 = *offset1 - field_offset * ps; -+ else -+ *offset0 = *offset1; -+ *row_inc = pixinc(-screen_width * (fbh - 1) - 1 - -+ (fieldmode ? 1 : 0), ps); -+ *pix_inc = pixinc(screen_width, ps); -+ break; -+ -+ /* mirroring */ -+ case 0 + 4: -+ *offset1 = (fbw - 1) * ps; -+ if (field_offset) -+ *offset0 = *offset1 + field_offset * screen_width * ps; -+ else -+ *offset0 = *offset1; -+ *row_inc = pixinc(screen_width * 2 - 1 + -+ (fieldmode ? screen_width : 0), -+ ps); -+ *pix_inc = pixinc(-1, ps); -+ break; -+ -+ case 1 + 4: -+ *offset1 = 0; -+ if (field_offset) -+ *offset0 = *offset1 + field_offset * ps; -+ else -+ *offset0 = *offset1; -+ *row_inc = pixinc(-screen_width * (fbh - 1) + 1 + -+ (fieldmode ? 1 : 0), -+ ps); -+ *pix_inc = pixinc(screen_width, ps); -+ break; -+ -+ case 2 + 4: -+ *offset1 = screen_width * (fbh - 1) * ps; -+ if (field_offset) -+ *offset0 = *offset1 - field_offset * screen_width * ps; -+ else -+ *offset0 = *offset1; -+ *row_inc = pixinc(1 - screen_width * 2 - -+ (fieldmode ? screen_width : 0), -+ ps); -+ *pix_inc = pixinc(1, ps); -+ break; -+ -+ case 3 + 4: -+ *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; -+ if (field_offset) -+ *offset0 = *offset1 - field_offset * ps; -+ else -+ *offset0 = *offset1; -+ *row_inc = pixinc(screen_width * (fbh - 1) - 1 - -+ (fieldmode ? 1 : 0), -+ ps); -+ *pix_inc = pixinc(-screen_width, ps); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+ -+static unsigned long calc_fclk_five_taps(u16 width, u16 height, -+ u16 out_width, u16 out_height, enum omap_color_mode color_mode) -+{ -+ u32 fclk = 0; -+ /* FIXME venc pclk? */ -+ u64 tmp, pclk = dispc_pclk_rate(); -+ -+ if (height > out_height) { -+ /* FIXME get real display PPL */ -+ unsigned int ppl = 800; -+ -+ tmp = pclk * height * out_width; -+ do_div(tmp, 2 * out_height * ppl); -+ fclk = tmp; -+ -+ if (height > 2 * out_height && ppl != out_width) { -+ tmp = pclk * (height - 2 * out_height) * out_width; -+ do_div(tmp, 2 * out_height * (ppl - out_width)); -+ fclk = max(fclk, (u32) tmp); -+ } -+ } -+ -+ if (width > out_width) { -+ tmp = pclk * width; -+ do_div(tmp, out_width); -+ fclk = max(fclk, (u32) tmp); -+ -+ if (color_mode == OMAP_DSS_COLOR_RGB24U) -+ fclk <<= 1; -+ } -+ -+ return fclk; -+} -+ -+static unsigned long calc_fclk(u16 width, u16 height, -+ u16 out_width, u16 out_height) -+{ -+ unsigned int hf, vf; -+ -+ /* -+ * FIXME how to determine the 'A' factor -+ * for the no downscaling case ? -+ */ -+ -+ if (width > 3 * out_width) -+ hf = 4; -+ else if (width > 2 * out_width) -+ hf = 3; -+ else if (width > out_width) -+ hf = 2; -+ else -+ hf = 1; -+ -+ if (height > out_height) -+ vf = 2; -+ else -+ vf = 1; -+ -+ /* FIXME venc pclk? */ -+ return dispc_pclk_rate() * vf * hf; -+} -+ -+void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out) -+{ -+ enable_clocks(1); -+ _dispc_set_channel_out(plane, channel_out); -+ enable_clocks(0); -+} -+ -+static int _dispc_setup_plane(enum omap_plane plane, -+ u32 paddr, u16 screen_width, -+ u16 pos_x, u16 pos_y, -+ u16 width, u16 height, -+ u16 out_width, u16 out_height, -+ enum omap_color_mode color_mode, -+ bool ilace, -+ enum omap_dss_rotation_type rotation_type, -+ u8 rotation, int mirror, -+ u8 global_alpha) -+{ -+ const int maxdownscale = cpu_is_omap34xx() ? 4 : 2; -+ bool five_taps = 0; -+ bool fieldmode = 0; -+ int cconv = 0; -+ unsigned offset0, offset1; -+ s32 row_inc; -+ s32 pix_inc; -+ u16 frame_height = height; -+ unsigned int field_offset = 0; -+ -+ if (paddr == 0) -+ return -EINVAL; -+ -+ if (ilace && height == out_height) -+ fieldmode = 1; -+ -+ if (ilace) { -+ if (fieldmode) -+ height /= 2; -+ pos_y /= 2; -+ out_height /= 2; -+ -+ DSSDBG("adjusting for ilace: height %d, pos_y %d, " -+ "out_height %d\n", -+ height, pos_y, out_height); -+ } -+ -+ if (plane == OMAP_DSS_GFX) { -+ if (width != out_width || height != out_height) -+ return -EINVAL; -+ -+ switch (color_mode) { -+ case OMAP_DSS_COLOR_ARGB16: -+ case OMAP_DSS_COLOR_RGB16: -+ case OMAP_DSS_COLOR_RGB24P: -+ case OMAP_DSS_COLOR_RGB24U: -+ case OMAP_DSS_COLOR_ARGB32: -+ case OMAP_DSS_COLOR_RGBA32: -+ case OMAP_DSS_COLOR_RGBX32: -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ } else { -+ /* video plane */ -+ -+ unsigned long fclk = 0; -+ -+ if (out_width < width / maxdownscale || -+ out_width > width * 8) -+ return -EINVAL; -+ -+ if (out_height < height / maxdownscale || -+ out_height > height * 8) -+ return -EINVAL; -+ -+ switch (color_mode) { -+ case OMAP_DSS_COLOR_RGB16: -+ case OMAP_DSS_COLOR_RGB24P: -+ case OMAP_DSS_COLOR_RGB24U: -+ case OMAP_DSS_COLOR_RGBX32: -+ break; -+ -+ case OMAP_DSS_COLOR_ARGB16: -+ case OMAP_DSS_COLOR_ARGB32: -+ case OMAP_DSS_COLOR_RGBA32: -+ if (plane == OMAP_DSS_VIDEO1) -+ return -EINVAL; -+ break; -+ -+ case OMAP_DSS_COLOR_YUV2: -+ case OMAP_DSS_COLOR_UYVY: -+ cconv = 1; -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ /* Must use 5-tap filter? */ -+ five_taps = height > out_height * 2; -+ -+ if (!five_taps) { -+ fclk = calc_fclk(width, height, -+ out_width, out_height); -+ -+ /* Try 5-tap filter if 3-tap fclk is too high */ -+ if (cpu_is_omap34xx() && height > out_height && -+ fclk > dispc_fclk_rate()) -+ five_taps = true; -+ } -+ -+ if (width > (2048 >> five_taps)) -+ return -EINVAL; -+ -+ if (five_taps) -+ fclk = calc_fclk_five_taps(width, height, -+ out_width, out_height, color_mode); -+ -+ DSSDBG("required fclk rate = %lu Hz\n", fclk); -+ DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate()); -+ -+ if (fclk > dispc_fclk_rate()) { -+ DSSERR("failed to set up scaling, " -+ "required fclk rate = %lu Hz, " -+ "current fclk rate = %lu Hz\n", -+ fclk, dispc_fclk_rate()); -+ return -EINVAL; -+ } -+ } -+ -+ if (ilace && !fieldmode) { -+ /* -+ * when downscaling the bottom field may have to start several -+ * source lines below the top field. Unfortunately ACCUI -+ * registers will only hold the fractional part of the offset -+ * so the integer part must be added to the base address of the -+ * bottom field. -+ */ -+ if (!height || height == out_height) -+ field_offset = 0; -+ else -+ field_offset = height / out_height / 2; -+ } -+ -+ /* Fields are independent but interleaved in memory. */ -+ if (fieldmode) -+ field_offset = 1; -+ -+ if (rotation_type == OMAP_DSS_ROT_DMA) -+ calc_dma_rotation_offset(rotation, mirror, -+ screen_width, width, frame_height, color_mode, -+ fieldmode, field_offset, -+ &offset0, &offset1, &row_inc, &pix_inc); -+ else -+ calc_vrfb_rotation_offset(rotation, mirror, -+ screen_width, width, frame_height, color_mode, -+ fieldmode, field_offset, -+ &offset0, &offset1, &row_inc, &pix_inc); -+ -+ DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", -+ offset0, offset1, row_inc, pix_inc); -+ -+ _dispc_set_color_mode(plane, color_mode); -+ -+ _dispc_set_plane_ba0(plane, paddr + offset0); -+ _dispc_set_plane_ba1(plane, paddr + offset1); -+ -+ _dispc_set_row_inc(plane, row_inc); -+ _dispc_set_pix_inc(plane, pix_inc); -+ -+ DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height, -+ out_width, out_height); -+ -+ _dispc_set_plane_pos(plane, pos_x, pos_y); -+ -+ _dispc_set_pic_size(plane, width, height); -+ -+ if (plane != OMAP_DSS_GFX) { -+ _dispc_set_scaling(plane, width, height, -+ out_width, out_height, -+ ilace, five_taps, fieldmode); -+ _dispc_set_vid_size(plane, out_width, out_height); -+ _dispc_set_vid_color_conv(plane, cconv); -+ } -+ -+ _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode); -+ -+ if (plane != OMAP_DSS_VIDEO1) -+ _dispc_setup_global_alpha(plane, global_alpha); -+ -+ return 0; -+} -+ -+static void _dispc_enable_plane(enum omap_plane plane, bool enable) -+{ -+ REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0); -+} -+ -+static void dispc_disable_isr(void *data, u32 mask) -+{ -+ struct completion *compl = data; -+ complete(compl); -+} -+ -+static void _enable_lcd_out(bool enable) -+{ -+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0); -+} -+ -+void dispc_enable_lcd_out(bool enable) -+{ -+ struct completion frame_done_completion; -+ bool is_on; -+ int r; -+ -+ enable_clocks(1); -+ -+ /* When we disable LCD output, we need to wait until frame is done. -+ * Otherwise the DSS is still working, and turning off the clocks -+ * prevents DSS from going to OFF mode */ -+ is_on = REG_GET(DISPC_CONTROL, 0, 0); -+ -+ if (!enable && is_on) { -+ init_completion(&frame_done_completion); -+ -+ r = omap_dispc_register_isr(dispc_disable_isr, -+ &frame_done_completion, -+ DISPC_IRQ_FRAMEDONE); -+ -+ if (r) -+ DSSERR("failed to register FRAMEDONE isr\n"); -+ } -+ -+ _enable_lcd_out(enable); -+ -+ if (!enable && is_on) { -+ if (!wait_for_completion_timeout(&frame_done_completion, -+ msecs_to_jiffies(100))) -+ DSSERR("timeout waiting for FRAME DONE\n"); -+ -+ r = omap_dispc_unregister_isr(dispc_disable_isr, -+ &frame_done_completion, -+ DISPC_IRQ_FRAMEDONE); -+ -+ if (r) -+ DSSERR("failed to unregister FRAMEDONE isr\n"); -+ } -+ -+ enable_clocks(0); -+} -+ -+static void _enable_digit_out(bool enable) -+{ -+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1); -+} -+ -+void dispc_enable_digit_out(bool enable) -+{ -+ struct completion frame_done_completion; -+ int r; -+ -+ enable_clocks(1); -+ -+ if (REG_GET(DISPC_CONTROL, 1, 1) == enable) { -+ enable_clocks(0); -+ return; -+ } -+ -+ if (enable) { -+ unsigned long flags; -+ /* When we enable digit output, we'll get an extra digit -+ * sync lost interrupt, that we need to ignore */ -+ spin_lock_irqsave(&dispc.irq_lock, flags); -+ dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT; -+ _omap_dispc_set_irqs(); -+ spin_unlock_irqrestore(&dispc.irq_lock, flags); -+ } -+ -+ /* When we disable digit output, we need to wait until fields are done. -+ * Otherwise the DSS is still working, and turning off the clocks -+ * prevents DSS from going to OFF mode. And when enabling, we need to -+ * wait for the extra sync losts */ -+ init_completion(&frame_done_completion); -+ -+ r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion, -+ DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD); -+ if (r) -+ DSSERR("failed to register EVSYNC isr\n"); -+ -+ _enable_digit_out(enable); -+ -+ /* XXX I understand from TRM that we should only wait for the -+ * current field to complete. But it seems we have to wait -+ * for both fields */ -+ if (!wait_for_completion_timeout(&frame_done_completion, -+ msecs_to_jiffies(100))) -+ DSSERR("timeout waiting for EVSYNC\n"); -+ -+ if (!wait_for_completion_timeout(&frame_done_completion, -+ msecs_to_jiffies(100))) -+ DSSERR("timeout waiting for EVSYNC\n"); -+ -+ r = omap_dispc_unregister_isr(dispc_disable_isr, -+ &frame_done_completion, -+ DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD); -+ if (r) -+ DSSERR("failed to unregister EVSYNC isr\n"); -+ -+ if (enable) { -+ unsigned long flags; -+ spin_lock_irqsave(&dispc.irq_lock, flags); -+ dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR; -+ dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT); -+ _omap_dispc_set_irqs(); -+ spin_unlock_irqrestore(&dispc.irq_lock, flags); -+ } -+ -+ enable_clocks(0); -+} -+ -+void dispc_lcd_enable_signal_polarity(bool act_high) -+{ -+ enable_clocks(1); -+ REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); -+ enable_clocks(0); -+} -+ -+void dispc_lcd_enable_signal(bool enable) -+{ -+ enable_clocks(1); -+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); -+ enable_clocks(0); -+} -+ -+void dispc_pck_free_enable(bool enable) -+{ -+ enable_clocks(1); -+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); -+ enable_clocks(0); -+} -+ -+void dispc_enable_fifohandcheck(bool enable) -+{ -+ enable_clocks(1); -+ REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16); -+ enable_clocks(0); -+} -+ -+ -+void dispc_set_lcd_display_type(enum omap_lcd_display_type type) -+{ -+ int mode; -+ -+ switch (type) { -+ case OMAP_DSS_LCD_DISPLAY_STN: -+ mode = 0; -+ break; -+ -+ case OMAP_DSS_LCD_DISPLAY_TFT: -+ mode = 1; -+ break; -+ -+ default: -+ BUG(); -+ return; -+ } -+ -+ enable_clocks(1); -+ REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3); -+ enable_clocks(0); -+} -+ -+void dispc_set_loadmode(enum omap_dss_load_mode mode) -+{ -+ enable_clocks(1); -+ REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); -+ enable_clocks(0); -+} -+ -+ -+void dispc_set_default_color(enum omap_channel channel, u32 color) -+{ -+ const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0, -+ DISPC_DEFAULT_COLOR1 }; -+ -+ enable_clocks(1); -+ dispc_write_reg(def_reg[channel], color); -+ enable_clocks(0); -+} -+ -+u32 dispc_get_default_color(enum omap_channel channel) -+{ -+ const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0, -+ DISPC_DEFAULT_COLOR1 }; -+ u32 l; -+ -+ BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT && -+ channel != OMAP_DSS_CHANNEL_LCD); -+ -+ enable_clocks(1); -+ l = dispc_read_reg(def_reg[channel]); -+ enable_clocks(0); -+ -+ return l; -+} -+ -+void dispc_set_trans_key(enum omap_channel ch, -+ enum omap_dss_trans_key_type type, -+ u32 trans_key) -+{ -+ const struct dispc_reg tr_reg[] = { -+ DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 }; -+ -+ enable_clocks(1); -+ if (ch == OMAP_DSS_CHANNEL_LCD) -+ REG_FLD_MOD(DISPC_CONFIG, type, 11, 11); -+ else /* OMAP_DSS_CHANNEL_DIGIT */ -+ REG_FLD_MOD(DISPC_CONFIG, type, 13, 13); -+ -+ dispc_write_reg(tr_reg[ch], trans_key); -+ enable_clocks(0); -+} -+ -+void dispc_get_trans_key(enum omap_channel ch, -+ enum omap_dss_trans_key_type *type, -+ u32 *trans_key) -+{ -+ const struct dispc_reg tr_reg[] = { -+ DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 }; -+ -+ enable_clocks(1); -+ if (type) { -+ if (ch == OMAP_DSS_CHANNEL_LCD) -+ *type = REG_GET(DISPC_CONFIG, 11, 11); -+ else if (ch == OMAP_DSS_CHANNEL_DIGIT) -+ *type = REG_GET(DISPC_CONFIG, 13, 13); -+ else -+ BUG(); -+ } -+ -+ if (trans_key) -+ *trans_key = dispc_read_reg(tr_reg[ch]); -+ enable_clocks(0); -+} -+ -+void dispc_enable_trans_key(enum omap_channel ch, bool enable) -+{ -+ enable_clocks(1); -+ if (ch == OMAP_DSS_CHANNEL_LCD) -+ REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10); -+ else /* OMAP_DSS_CHANNEL_DIGIT */ -+ REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12); -+ enable_clocks(0); -+} -+void dispc_enable_alpha_blending(enum omap_channel ch, bool enable) -+{ -+ enable_clocks(1); -+ if (ch == OMAP_DSS_CHANNEL_LCD) -+ REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); -+ else /* OMAP_DSS_CHANNEL_DIGIT */ -+ REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); -+ enable_clocks(0); -+} -+bool dispc_alpha_blending_enabled(enum omap_channel ch) -+{ -+ bool enabled; -+ -+ enable_clocks(1); -+ if (ch == OMAP_DSS_CHANNEL_LCD) -+ enabled = REG_GET(DISPC_CONFIG, 18, 18); -+ else if (ch == OMAP_DSS_CHANNEL_DIGIT) -+ enabled = REG_GET(DISPC_CONFIG, 18, 18); -+ else -+ BUG(); -+ enable_clocks(0); -+ -+ return enabled; -+ -+} -+ -+ -+bool dispc_trans_key_enabled(enum omap_channel ch) -+{ -+ bool enabled; -+ -+ enable_clocks(1); -+ if (ch == OMAP_DSS_CHANNEL_LCD) -+ enabled = REG_GET(DISPC_CONFIG, 10, 10); -+ else if (ch == OMAP_DSS_CHANNEL_DIGIT) -+ enabled = REG_GET(DISPC_CONFIG, 12, 12); -+ else -+ BUG(); -+ enable_clocks(0); -+ -+ return enabled; -+} -+ -+ -+void dispc_set_tft_data_lines(u8 data_lines) -+{ -+ int code; -+ -+ switch (data_lines) { -+ case 12: -+ code = 0; -+ break; -+ case 16: -+ code = 1; -+ break; -+ case 18: -+ code = 2; -+ break; -+ case 24: -+ code = 3; -+ break; -+ default: -+ BUG(); -+ return; -+ } -+ -+ enable_clocks(1); -+ REG_FLD_MOD(DISPC_CONTROL, code, 9, 8); -+ enable_clocks(0); -+} -+ -+void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode) -+{ -+ u32 l; -+ int stallmode; -+ int gpout0 = 1; -+ int gpout1; -+ -+ switch (mode) { -+ case OMAP_DSS_PARALLELMODE_BYPASS: -+ stallmode = 0; -+ gpout1 = 1; -+ break; -+ -+ case OMAP_DSS_PARALLELMODE_RFBI: -+ stallmode = 1; -+ gpout1 = 0; -+ break; -+ -+ case OMAP_DSS_PARALLELMODE_DSI: -+ stallmode = 1; -+ gpout1 = 1; -+ break; -+ -+ default: -+ BUG(); -+ return; -+ } -+ -+ enable_clocks(1); -+ -+ l = dispc_read_reg(DISPC_CONTROL); -+ -+ l = FLD_MOD(l, stallmode, 11, 11); -+ l = FLD_MOD(l, gpout0, 15, 15); -+ l = FLD_MOD(l, gpout1, 16, 16); -+ -+ dispc_write_reg(DISPC_CONTROL, l); -+ -+ enable_clocks(0); -+} -+ -+static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, -+ int vsw, int vfp, int vbp) -+{ -+ if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) { -+ if (hsw < 1 || hsw > 64 || -+ hfp < 1 || hfp > 256 || -+ hbp < 1 || hbp > 256 || -+ vsw < 1 || vsw > 64 || -+ vfp < 0 || vfp > 255 || -+ vbp < 0 || vbp > 255) -+ return false; -+ } else { -+ if (hsw < 1 || hsw > 256 || -+ hfp < 1 || hfp > 4096 || -+ hbp < 1 || hbp > 4096 || -+ vsw < 1 || vsw > 256 || -+ vfp < 0 || vfp > 4095 || -+ vbp < 0 || vbp > 4095) -+ return false; -+ } -+ -+ return true; -+} -+ -+bool dispc_lcd_timings_ok(struct omap_video_timings *timings) -+{ -+ return _dispc_lcd_timings_ok(timings->hsw, timings->hfp, -+ timings->hbp, timings->vsw, -+ timings->vfp, timings->vbp); -+} -+ -+static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp, -+ int vsw, int vfp, int vbp) -+{ -+ u32 timing_h, timing_v; -+ -+ if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) { -+ timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) | -+ FLD_VAL(hbp-1, 27, 20); -+ -+ timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) | -+ FLD_VAL(vbp, 27, 20); -+ } else { -+ timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) | -+ FLD_VAL(hbp-1, 31, 20); -+ -+ timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) | -+ FLD_VAL(vbp, 31, 20); -+ } -+ -+ enable_clocks(1); -+ dispc_write_reg(DISPC_TIMING_H, timing_h); -+ dispc_write_reg(DISPC_TIMING_V, timing_v); -+ enable_clocks(0); -+} -+ -+/* change name to mode? */ -+void dispc_set_lcd_timings(struct omap_video_timings *timings) -+{ -+ unsigned xtot, ytot; -+ unsigned long ht, vt; -+ -+ if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, -+ timings->hbp, timings->vsw, -+ timings->vfp, timings->vbp)) -+ BUG(); -+ -+ _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp, -+ timings->vsw, timings->vfp, timings->vbp); -+ -+ dispc_set_lcd_size(timings->x_res, timings->y_res); -+ -+ xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp; -+ ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp; -+ -+ ht = (timings->pixel_clock * 1000) / xtot; -+ vt = (timings->pixel_clock * 1000) / xtot / ytot; -+ -+ DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res); -+ DSSDBG("pck %u\n", timings->pixel_clock); -+ DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", -+ timings->hsw, timings->hfp, timings->hbp, -+ timings->vsw, timings->vfp, timings->vbp); -+ -+ DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); -+} -+ -+void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div) -+{ -+ BUG_ON(lck_div < 1); -+ BUG_ON(pck_div < 2); -+ -+ enable_clocks(1); -+ dispc_write_reg(DISPC_DIVISOR, -+ FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); -+ enable_clocks(0); -+} -+ -+static void dispc_get_lcd_divisor(int *lck_div, int *pck_div) -+{ -+ u32 l; -+ l = dispc_read_reg(DISPC_DIVISOR); -+ *lck_div = FLD_GET(l, 23, 16); -+ *pck_div = FLD_GET(l, 7, 0); -+} -+ -+unsigned long dispc_fclk_rate(void) -+{ -+ unsigned long r = 0; -+ -+ if (dss_get_dispc_clk_source() == 0) -+ r = dss_clk_get_rate(DSS_CLK_FCK1); -+ else -+#ifdef CONFIG_OMAP2_DSS_DSI -+ r = dsi_get_dsi1_pll_rate(); -+#else -+ BUG(); -+#endif -+ return r; -+} -+ -+unsigned long dispc_lclk_rate(void) -+{ -+ int lcd; -+ unsigned long r; -+ u32 l; -+ -+ l = dispc_read_reg(DISPC_DIVISOR); -+ -+ lcd = FLD_GET(l, 23, 16); -+ -+ r = dispc_fclk_rate(); -+ -+ return r / lcd; -+} -+ -+unsigned long dispc_pclk_rate(void) -+{ -+ int lcd, pcd; -+ unsigned long r; -+ u32 l; -+ -+ l = dispc_read_reg(DISPC_DIVISOR); -+ -+ lcd = FLD_GET(l, 23, 16); -+ pcd = FLD_GET(l, 7, 0); -+ -+ r = dispc_fclk_rate(); -+ -+ return r / lcd / pcd; -+} -+ -+void dispc_dump_clocks(struct seq_file *s) -+{ -+ int lcd, pcd; -+ -+ enable_clocks(1); -+ -+ dispc_get_lcd_divisor(&lcd, &pcd); -+ -+ seq_printf(s, "- dispc -\n"); -+ -+ seq_printf(s, "dispc fclk source = %s\n", -+ dss_get_dispc_clk_source() == 0 ? -+ "dss1_alwon_fclk" : "dsi1_pll_fclk"); -+ -+ seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n", -+ dispc_fclk_rate(), -+ lcd, pcd, -+ dispc_pclk_rate()); -+ -+ enable_clocks(0); -+} -+ -+void dispc_dump_regs(struct seq_file *s) -+{ -+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r)) -+ -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ DUMPREG(DISPC_REVISION); -+ DUMPREG(DISPC_SYSCONFIG); -+ DUMPREG(DISPC_SYSSTATUS); -+ DUMPREG(DISPC_IRQSTATUS); -+ DUMPREG(DISPC_IRQENABLE); -+ DUMPREG(DISPC_CONTROL); -+ DUMPREG(DISPC_CONFIG); -+ DUMPREG(DISPC_CAPABLE); -+ DUMPREG(DISPC_DEFAULT_COLOR0); -+ DUMPREG(DISPC_DEFAULT_COLOR1); -+ DUMPREG(DISPC_TRANS_COLOR0); -+ DUMPREG(DISPC_TRANS_COLOR1); -+ DUMPREG(DISPC_LINE_STATUS); -+ DUMPREG(DISPC_LINE_NUMBER); -+ DUMPREG(DISPC_TIMING_H); -+ DUMPREG(DISPC_TIMING_V); -+ DUMPREG(DISPC_POL_FREQ); -+ DUMPREG(DISPC_DIVISOR); -+ DUMPREG(DISPC_GLOBAL_ALPHA); -+ DUMPREG(DISPC_SIZE_DIG); -+ DUMPREG(DISPC_SIZE_LCD); -+ -+ DUMPREG(DISPC_GFX_BA0); -+ DUMPREG(DISPC_GFX_BA1); -+ DUMPREG(DISPC_GFX_POSITION); -+ DUMPREG(DISPC_GFX_SIZE); -+ DUMPREG(DISPC_GFX_ATTRIBUTES); -+ DUMPREG(DISPC_GFX_FIFO_THRESHOLD); -+ DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS); -+ DUMPREG(DISPC_GFX_ROW_INC); -+ DUMPREG(DISPC_GFX_PIXEL_INC); -+ DUMPREG(DISPC_GFX_WINDOW_SKIP); -+ DUMPREG(DISPC_GFX_TABLE_BA); -+ -+ DUMPREG(DISPC_DATA_CYCLE1); -+ DUMPREG(DISPC_DATA_CYCLE2); -+ DUMPREG(DISPC_DATA_CYCLE3); -+ -+ DUMPREG(DISPC_CPR_COEF_R); -+ DUMPREG(DISPC_CPR_COEF_G); -+ DUMPREG(DISPC_CPR_COEF_B); -+ -+ DUMPREG(DISPC_GFX_PRELOAD); -+ -+ DUMPREG(DISPC_VID_BA0(0)); -+ DUMPREG(DISPC_VID_BA1(0)); -+ DUMPREG(DISPC_VID_POSITION(0)); -+ DUMPREG(DISPC_VID_SIZE(0)); -+ DUMPREG(DISPC_VID_ATTRIBUTES(0)); -+ DUMPREG(DISPC_VID_FIFO_THRESHOLD(0)); -+ DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0)); -+ DUMPREG(DISPC_VID_ROW_INC(0)); -+ DUMPREG(DISPC_VID_PIXEL_INC(0)); -+ DUMPREG(DISPC_VID_FIR(0)); -+ DUMPREG(DISPC_VID_PICTURE_SIZE(0)); -+ DUMPREG(DISPC_VID_ACCU0(0)); -+ DUMPREG(DISPC_VID_ACCU1(0)); -+ -+ DUMPREG(DISPC_VID_BA0(1)); -+ DUMPREG(DISPC_VID_BA1(1)); -+ DUMPREG(DISPC_VID_POSITION(1)); -+ DUMPREG(DISPC_VID_SIZE(1)); -+ DUMPREG(DISPC_VID_ATTRIBUTES(1)); -+ DUMPREG(DISPC_VID_FIFO_THRESHOLD(1)); -+ DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1)); -+ DUMPREG(DISPC_VID_ROW_INC(1)); -+ DUMPREG(DISPC_VID_PIXEL_INC(1)); -+ DUMPREG(DISPC_VID_FIR(1)); -+ DUMPREG(DISPC_VID_PICTURE_SIZE(1)); -+ DUMPREG(DISPC_VID_ACCU0(1)); -+ DUMPREG(DISPC_VID_ACCU1(1)); -+ -+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 0)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 1)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 2)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 3)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 4)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 5)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 6)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 7)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7)); -+ DUMPREG(DISPC_VID_CONV_COEF(0, 0)); -+ DUMPREG(DISPC_VID_CONV_COEF(0, 1)); -+ DUMPREG(DISPC_VID_CONV_COEF(0, 2)); -+ DUMPREG(DISPC_VID_CONV_COEF(0, 3)); -+ DUMPREG(DISPC_VID_CONV_COEF(0, 4)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 0)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 1)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 2)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 3)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 4)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 5)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 6)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 7)); -+ -+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 0)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 1)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 2)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 3)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 4)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 5)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 6)); -+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 7)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6)); -+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7)); -+ DUMPREG(DISPC_VID_CONV_COEF(1, 0)); -+ DUMPREG(DISPC_VID_CONV_COEF(1, 1)); -+ DUMPREG(DISPC_VID_CONV_COEF(1, 2)); -+ DUMPREG(DISPC_VID_CONV_COEF(1, 3)); -+ DUMPREG(DISPC_VID_CONV_COEF(1, 4)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 0)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 1)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 2)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 3)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 4)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 5)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 6)); -+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 7)); -+ -+ DUMPREG(DISPC_VID_PRELOAD(0)); -+ DUMPREG(DISPC_VID_PRELOAD(1)); -+ -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+#undef DUMPREG -+} -+ -+static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc, -+ bool ihs, bool ivs, u8 acbi, u8 acb) -+{ -+ u32 l = 0; -+ -+ DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n", -+ onoff, rf, ieo, ipc, ihs, ivs, acbi, acb); -+ -+ l |= FLD_VAL(onoff, 17, 17); -+ l |= FLD_VAL(rf, 16, 16); -+ l |= FLD_VAL(ieo, 15, 15); -+ l |= FLD_VAL(ipc, 14, 14); -+ l |= FLD_VAL(ihs, 13, 13); -+ l |= FLD_VAL(ivs, 12, 12); -+ l |= FLD_VAL(acbi, 11, 8); -+ l |= FLD_VAL(acb, 7, 0); -+ -+ enable_clocks(1); -+ dispc_write_reg(DISPC_POL_FREQ, l); -+ enable_clocks(0); -+} -+ -+void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb) -+{ -+ _dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0, -+ (config & OMAP_DSS_LCD_RF) != 0, -+ (config & OMAP_DSS_LCD_IEO) != 0, -+ (config & OMAP_DSS_LCD_IPC) != 0, -+ (config & OMAP_DSS_LCD_IHS) != 0, -+ (config & OMAP_DSS_LCD_IVS) != 0, -+ acbi, acb); -+} -+ -+void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck, -+ u16 *lck_div, u16 *pck_div) -+{ -+ u16 pcd_min = is_tft ? 2 : 3; -+ unsigned long best_pck; -+ u16 best_ld, cur_ld; -+ u16 best_pd, cur_pd; -+ -+ best_pck = 0; -+ best_ld = 0; -+ best_pd = 0; -+ -+ for (cur_ld = 1; cur_ld <= 255; ++cur_ld) { -+ unsigned long lck = fck / cur_ld; -+ -+ for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) { -+ unsigned long pck = lck / cur_pd; -+ long old_delta = abs(best_pck - req_pck); -+ long new_delta = abs(pck - req_pck); -+ -+ if (best_pck == 0 || new_delta < old_delta) { -+ best_pck = pck; -+ best_ld = cur_ld; -+ best_pd = cur_pd; -+ -+ if (pck == req_pck) -+ goto found; -+ } -+ -+ if (pck < req_pck) -+ break; -+ } -+ -+ if (lck / pcd_min < req_pck) -+ break; -+ } -+ -+found: -+ *lck_div = best_ld; -+ *pck_div = best_pd; -+} -+ -+int dispc_calc_clock_div(bool is_tft, unsigned long req_pck, -+ struct dispc_clock_info *cinfo) -+{ -+ unsigned long prate; -+ struct dispc_clock_info cur, best; -+ int match = 0; -+ int min_fck_per_pck; -+ unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1); -+ -+ if (cpu_is_omap34xx()) -+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck)); -+ else -+ prate = 0; -+ -+ if (req_pck == dispc.cache_req_pck && -+ ((cpu_is_omap34xx() && prate == dispc.cache_prate) || -+ dispc.cache_cinfo.fck == fck_rate)) { -+ DSSDBG("dispc clock info found from cache.\n"); -+ *cinfo = dispc.cache_cinfo; -+ return 0; -+ } -+ -+ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; -+ -+ if (min_fck_per_pck && -+ req_pck * min_fck_per_pck > DISPC_MAX_FCK) { -+ DSSERR("Requested pixel clock not possible with the current " -+ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " -+ "the constraint off.\n"); -+ min_fck_per_pck = 0; -+ } -+ -+retry: -+ memset(&cur, 0, sizeof(cur)); -+ memset(&best, 0, sizeof(best)); -+ -+ if (cpu_is_omap24xx()) { -+ /* XXX can we change the clock on omap2? */ -+ cur.fck = dss_clk_get_rate(DSS_CLK_FCK1); -+ cur.fck_div = 1; -+ -+ match = 1; -+ -+ find_lck_pck_divs(is_tft, req_pck, cur.fck, -+ &cur.lck_div, &cur.pck_div); -+ -+ cur.lck = cur.fck / cur.lck_div; -+ cur.pck = cur.lck / cur.pck_div; -+ -+ best = cur; -+ -+ goto found; -+ } else if (cpu_is_omap34xx()) { -+ for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) { -+ cur.fck = prate / cur.fck_div * 2; -+ -+ if (cur.fck > DISPC_MAX_FCK) -+ continue; -+ -+ if (min_fck_per_pck && -+ cur.fck < req_pck * min_fck_per_pck) -+ continue; -+ -+ match = 1; -+ -+ find_lck_pck_divs(is_tft, req_pck, cur.fck, -+ &cur.lck_div, &cur.pck_div); -+ -+ cur.lck = cur.fck / cur.lck_div; -+ cur.pck = cur.lck / cur.pck_div; -+ -+ if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) { -+ best = cur; -+ -+ if (cur.pck == req_pck) -+ goto found; -+ } -+ } -+ } else { -+ BUG(); -+ } -+ -+found: -+ if (!match) { -+ if (min_fck_per_pck) { -+ DSSERR("Could not find suitable clock settings.\n" -+ "Turning FCK/PCK constraint off and" -+ "trying again.\n"); -+ min_fck_per_pck = 0; -+ goto retry; -+ } -+ -+ DSSERR("Could not find suitable clock settings.\n"); -+ -+ return -EINVAL; -+ } -+ -+ if (cinfo) -+ *cinfo = best; -+ -+ dispc.cache_req_pck = req_pck; -+ dispc.cache_prate = prate; -+ dispc.cache_cinfo = best; -+ -+ return 0; -+} -+ -+int dispc_set_clock_div(struct dispc_clock_info *cinfo) -+{ -+ unsigned long prate; -+ int r; -+ -+ if (cpu_is_omap34xx()) { -+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck)); -+ DSSDBG("dpll4_m4 = %ld\n", prate); -+ } -+ -+ DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); -+ DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div); -+ DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div); -+ -+ if (cpu_is_omap34xx()) { -+ r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div); -+ if (r) -+ return r; -+ } -+ -+ dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div); -+ -+ return 0; -+} -+ -+int dispc_get_clock_div(struct dispc_clock_info *cinfo) -+{ -+ cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1); -+ -+ if (cpu_is_omap34xx()) { -+ unsigned long prate; -+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck)); -+ cinfo->fck_div = prate / (cinfo->fck / 2); -+ } else { -+ cinfo->fck_div = 0; -+ } -+ -+ cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16); -+ cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0); -+ -+ cinfo->lck = cinfo->fck / cinfo->lck_div; -+ cinfo->pck = cinfo->lck / cinfo->pck_div; -+ -+ return 0; -+} -+ -+/* dispc.irq_lock has to be locked by the caller */ -+static void _omap_dispc_set_irqs(void) -+{ -+ u32 mask; -+ u32 old_mask; -+ int i; -+ struct omap_dispc_isr_data *isr_data; -+ -+ mask = dispc.irq_error_mask; -+ -+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { -+ isr_data = &dispc.registered_isr[i]; -+ -+ if (isr_data->isr == NULL) -+ continue; -+ -+ mask |= isr_data->mask; -+ } -+ -+ enable_clocks(1); -+ -+ old_mask = dispc_read_reg(DISPC_IRQENABLE); -+ /* clear the irqstatus for newly enabled irqs */ -+ dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask); -+ -+ dispc_write_reg(DISPC_IRQENABLE, mask); -+ -+ enable_clocks(0); -+} -+ -+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) -+{ -+ int i; -+ int ret; -+ unsigned long flags; -+ struct omap_dispc_isr_data *isr_data; -+ -+ if (isr == NULL) -+ return -EINVAL; -+ -+ spin_lock_irqsave(&dispc.irq_lock, flags); -+ -+ /* check for duplicate entry */ -+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { -+ isr_data = &dispc.registered_isr[i]; -+ if (isr_data->isr == isr && isr_data->arg == arg && -+ isr_data->mask == mask) { -+ ret = -EINVAL; -+ goto err; -+ } -+ } -+ -+ isr_data = NULL; -+ ret = -EBUSY; -+ -+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { -+ isr_data = &dispc.registered_isr[i]; -+ -+ if (isr_data->isr != NULL) -+ continue; -+ -+ isr_data->isr = isr; -+ isr_data->arg = arg; -+ isr_data->mask = mask; -+ ret = 0; -+ -+ break; -+ } -+ -+ _omap_dispc_set_irqs(); -+ -+ spin_unlock_irqrestore(&dispc.irq_lock, flags); -+ -+ return 0; -+err: -+ spin_unlock_irqrestore(&dispc.irq_lock, flags); -+ -+ return ret; -+} -+EXPORT_SYMBOL(omap_dispc_register_isr); -+ -+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask) -+{ -+ int i; -+ unsigned long flags; -+ int ret = -EINVAL; -+ struct omap_dispc_isr_data *isr_data; -+ -+ spin_lock_irqsave(&dispc.irq_lock, flags); -+ -+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { -+ isr_data = &dispc.registered_isr[i]; -+ if (isr_data->isr != isr || isr_data->arg != arg || -+ isr_data->mask != mask) -+ continue; -+ -+ /* found the correct isr */ -+ -+ isr_data->isr = NULL; -+ isr_data->arg = NULL; -+ isr_data->mask = 0; -+ -+ ret = 0; -+ break; -+ } -+ -+ if (ret == 0) -+ _omap_dispc_set_irqs(); -+ -+ spin_unlock_irqrestore(&dispc.irq_lock, flags); -+ -+ return ret; -+} -+EXPORT_SYMBOL(omap_dispc_unregister_isr); -+ -+#ifdef DEBUG -+static void print_irq_status(u32 status) -+{ -+ if ((status & dispc.irq_error_mask) == 0) -+ return; -+ -+ printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status); -+ -+#define PIS(x) \ -+ if (status & DISPC_IRQ_##x) \ -+ printk(#x " "); -+ PIS(GFX_FIFO_UNDERFLOW); -+ PIS(OCP_ERR); -+ PIS(VID1_FIFO_UNDERFLOW); -+ PIS(VID2_FIFO_UNDERFLOW); -+ PIS(SYNC_LOST); -+ PIS(SYNC_LOST_DIGIT); -+#undef PIS -+ -+ printk("\n"); -+} -+#endif -+ -+/* Called from dss.c. Note that we don't touch clocks here, -+ * but we presume they are on because we got an IRQ. However, -+ * an irq handler may turn the clocks off, so we may not have -+ * clock later in the function. */ -+void dispc_irq_handler(void) -+{ -+ int i; -+ u32 irqstatus; -+ u32 handledirqs = 0; -+ u32 unhandled_errors; -+ struct omap_dispc_isr_data *isr_data; -+ struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS]; -+ -+ spin_lock(&dispc.irq_lock); -+ -+ irqstatus = dispc_read_reg(DISPC_IRQSTATUS); -+ -+#ifdef DEBUG -+ if (dss_debug) -+ print_irq_status(irqstatus); -+#endif -+ /* Ack the interrupt. Do it here before clocks are possibly turned -+ * off */ -+ dispc_write_reg(DISPC_IRQSTATUS, irqstatus); -+ -+ /* make a copy and unlock, so that isrs can unregister -+ * themselves */ -+ memcpy(registered_isr, dispc.registered_isr, -+ sizeof(registered_isr)); -+ -+ spin_unlock(&dispc.irq_lock); -+ -+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { -+ isr_data = ®istered_isr[i]; -+ -+ if (!isr_data->isr) -+ continue; -+ -+ if (isr_data->mask & irqstatus) { -+ isr_data->isr(isr_data->arg, irqstatus); -+ handledirqs |= isr_data->mask; -+ } -+ } -+ -+ spin_lock(&dispc.irq_lock); -+ -+ unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask; -+ -+ if (unhandled_errors) { -+ dispc.error_irqs |= unhandled_errors; -+ -+ dispc.irq_error_mask &= ~unhandled_errors; -+ _omap_dispc_set_irqs(); -+ -+ schedule_work(&dispc.error_work); -+ } -+ -+ spin_unlock(&dispc.irq_lock); -+} -+ -+static void dispc_error_worker(struct work_struct *work) -+{ -+ int i; -+ u32 errors; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&dispc.irq_lock, flags); -+ errors = dispc.error_irqs; -+ dispc.error_irqs = 0; -+ spin_unlock_irqrestore(&dispc.irq_lock, flags); -+ -+ if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) { -+ DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n"); -+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) { -+ struct omap_overlay *ovl; -+ ovl = omap_dss_get_overlay(i); -+ -+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) -+ continue; -+ -+ if (ovl->id == 0) { -+ dispc_enable_plane(ovl->id, 0); -+ dispc_go(ovl->manager->id); -+ mdelay(50); -+ break; -+ } -+ } -+ } -+ -+ if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) { -+ DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n"); -+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) { -+ struct omap_overlay *ovl; -+ ovl = omap_dss_get_overlay(i); -+ -+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) -+ continue; -+ -+ if (ovl->id == 1) { -+ dispc_enable_plane(ovl->id, 0); -+ dispc_go(ovl->manager->id); -+ mdelay(50); -+ break; -+ } -+ } -+ } -+ -+ if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) { -+ DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n"); -+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) { -+ struct omap_overlay *ovl; -+ ovl = omap_dss_get_overlay(i); -+ -+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) -+ continue; -+ -+ if (ovl->id == 2) { -+ dispc_enable_plane(ovl->id, 0); -+ dispc_go(ovl->manager->id); -+ mdelay(50); -+ break; -+ } -+ } -+ } -+ -+ if (errors & DISPC_IRQ_SYNC_LOST) { -+ struct omap_overlay_manager *manager = NULL; -+ bool enable = false; -+ -+ DSSERR("SYNC_LOST, disabling LCD\n"); -+ -+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { -+ struct omap_overlay_manager *mgr; -+ mgr = omap_dss_get_overlay_manager(i); -+ -+ if (mgr->id == OMAP_DSS_CHANNEL_LCD) { -+ manager = mgr; -+ enable = mgr->device->state == -+ OMAP_DSS_DISPLAY_ACTIVE; -+ mgr->device->disable(mgr->device); -+ break; -+ } -+ } -+ -+ if (manager) { -+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) { -+ struct omap_overlay *ovl; -+ ovl = omap_dss_get_overlay(i); -+ -+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) -+ continue; -+ -+ if (ovl->id != 0 && ovl->manager == manager) -+ dispc_enable_plane(ovl->id, 0); -+ } -+ -+ dispc_go(manager->id); -+ mdelay(50); -+ if (enable) -+ manager->device->enable(manager->device); -+ } -+ } -+ -+ if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) { -+ struct omap_overlay_manager *manager = NULL; -+ bool enable = false; -+ -+ DSSERR("SYNC_LOST_DIGIT, disabling TV\n"); -+ -+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { -+ struct omap_overlay_manager *mgr; -+ mgr = omap_dss_get_overlay_manager(i); -+ -+ if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) { -+ manager = mgr; -+ enable = mgr->device->state == -+ OMAP_DSS_DISPLAY_ACTIVE; -+ mgr->device->disable(mgr->device); -+ break; -+ } -+ } -+ -+ if (manager) { -+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) { -+ struct omap_overlay *ovl; -+ ovl = omap_dss_get_overlay(i); -+ -+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) -+ continue; -+ -+ if (ovl->id != 0 && ovl->manager == manager) -+ dispc_enable_plane(ovl->id, 0); -+ } -+ -+ dispc_go(manager->id); -+ mdelay(50); -+ if (enable) -+ manager->device->enable(manager->device); -+ } -+ } -+ -+ if (errors & DISPC_IRQ_OCP_ERR) { -+ DSSERR("OCP_ERR\n"); -+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { -+ struct omap_overlay_manager *mgr; -+ mgr = omap_dss_get_overlay_manager(i); -+ -+ if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC) -+ mgr->device->disable(mgr->device); -+ } -+ } -+ -+ spin_lock_irqsave(&dispc.irq_lock, flags); -+ dispc.irq_error_mask |= errors; -+ _omap_dispc_set_irqs(); -+ spin_unlock_irqrestore(&dispc.irq_lock, flags); -+} -+ -+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout) -+{ -+ void dispc_irq_wait_handler(void *data, u32 mask) -+ { -+ complete((struct completion *)data); -+ } -+ -+ int r; -+ DECLARE_COMPLETION_ONSTACK(completion); -+ -+ r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion, -+ irqmask); -+ -+ if (r) -+ return r; -+ -+ timeout = wait_for_completion_timeout(&completion, timeout); -+ -+ omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); -+ -+ if (timeout == 0) -+ return -ETIMEDOUT; -+ -+ if (timeout == -ERESTARTSYS) -+ return -ERESTARTSYS; -+ -+ return 0; -+} -+ -+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, -+ unsigned long timeout) -+{ -+ void dispc_irq_wait_handler(void *data, u32 mask) -+ { -+ complete((struct completion *)data); -+ } -+ -+ int r; -+ DECLARE_COMPLETION_ONSTACK(completion); -+ -+ r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion, -+ irqmask); -+ -+ if (r) -+ return r; -+ -+ timeout = wait_for_completion_interruptible_timeout(&completion, -+ timeout); -+ -+ omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); -+ -+ if (timeout == 0) -+ return -ETIMEDOUT; -+ -+ if (timeout == -ERESTARTSYS) -+ return -ERESTARTSYS; -+ -+ return 0; -+} -+ -+#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC -+void dispc_fake_vsync_irq(void) -+{ -+ u32 irqstatus = DISPC_IRQ_VSYNC; -+ int i; -+ -+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { -+ struct omap_dispc_isr_data *isr_data; -+ isr_data = &dispc.registered_isr[i]; -+ -+ if (!isr_data->isr) -+ continue; -+ -+ if (isr_data->mask & irqstatus) -+ isr_data->isr(isr_data->arg, irqstatus); -+ } -+} -+#endif -+ -+static void _omap_dispc_initialize_irq(void) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&dispc.irq_lock, flags); -+ -+ memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr)); -+ -+ dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR; -+ -+ /* there's SYNC_LOST_DIGIT waiting after enabling the DSS, -+ * so clear it */ -+ dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS)); -+ -+ _omap_dispc_set_irqs(); -+ -+ spin_unlock_irqrestore(&dispc.irq_lock, flags); -+} -+ -+void dispc_enable_sidle(void) -+{ -+ REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ -+} -+ -+void dispc_disable_sidle(void) -+{ -+ REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ -+} -+ -+static void _omap_dispc_initial_config(void) -+{ -+ u32 l; -+ -+ l = dispc_read_reg(DISPC_SYSCONFIG); -+ l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */ -+ l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */ -+ l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */ -+ l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */ -+ dispc_write_reg(DISPC_SYSCONFIG, l); -+ -+ /* FUNCGATED */ -+ REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); -+ -+ /* L3 firewall setting: enable access to OCM RAM */ -+ if (cpu_is_omap24xx()) -+ __raw_writel(0x402000b0, OMAP2_IO_ADDRESS(0x680050a0)); -+ -+ _dispc_setup_color_conv_coef(); -+ -+ dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); -+ -+ dispc_read_plane_fifo_sizes(); -+} -+ -+int dispc_init(void) -+{ -+ u32 rev; -+ -+ spin_lock_init(&dispc.irq_lock); -+ -+ INIT_WORK(&dispc.error_work, dispc_error_worker); -+ -+ dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS); -+ if (!dispc.base) { -+ DSSERR("can't ioremap DISPC\n"); -+ return -ENOMEM; -+ } -+ -+ if (cpu_is_omap34xx()) { -+ dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); -+ if (IS_ERR(dispc.dpll4_m4_ck)) { -+ DSSERR("Failed to get dpll4_m4_ck\n"); -+ return -ENODEV; -+ } -+ } -+ -+ enable_clocks(1); -+ -+ _omap_dispc_initial_config(); -+ -+ _omap_dispc_initialize_irq(); -+ -+ dispc_save_context(); -+ -+ rev = dispc_read_reg(DISPC_REVISION); -+ printk(KERN_INFO "OMAP DISPC rev %d.%d\n", -+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); -+ -+ enable_clocks(0); -+ -+ return 0; -+} -+ -+void dispc_exit(void) -+{ -+ if (cpu_is_omap34xx()) -+ clk_put(dispc.dpll4_m4_ck); -+ iounmap(dispc.base); -+} -+ -+int dispc_enable_plane(enum omap_plane plane, bool enable) -+{ -+ DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); -+ -+ enable_clocks(1); -+ _dispc_enable_plane(plane, enable); -+ enable_clocks(0); -+ -+ return 0; -+} -+ -+int dispc_setup_plane(enum omap_plane plane, -+ u32 paddr, u16 screen_width, -+ u16 pos_x, u16 pos_y, -+ u16 width, u16 height, -+ u16 out_width, u16 out_height, -+ enum omap_color_mode color_mode, -+ bool ilace, -+ enum omap_dss_rotation_type rotation_type, -+ u8 rotation, bool mirror, u8 global_alpha) -+{ -+ int r = 0; -+ -+ DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> " -+ "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n", -+ plane, paddr, screen_width, pos_x, pos_y, -+ width, height, -+ out_width, out_height, -+ ilace, color_mode, -+ rotation, mirror); -+ -+ enable_clocks(1); -+ -+ r = _dispc_setup_plane(plane, -+ paddr, screen_width, -+ pos_x, pos_y, -+ width, height, -+ out_width, out_height, -+ color_mode, ilace, -+ rotation_type, -+ rotation, mirror, -+ global_alpha); -+ -+ enable_clocks(0); -+ -+ return r; -+} ---- /dev/null -+++ b/drivers/video/omap2/dss/display.c -@@ -0,0 +1,658 @@ -+/* -+ * linux/drivers/video/omap2/dss/display.c -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#define DSS_SUBSYS_NAME "DISPLAY" -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/jiffies.h> -+#include <linux/list.h> -+#include <linux/platform_device.h> -+ -+#include <mach/display.h> -+#include "dss.h" -+ -+static LIST_HEAD(display_list); -+ -+static ssize_t display_enabled_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ bool enabled = dssdev->state != OMAP_DSS_DISPLAY_DISABLED; -+ -+ return snprintf(buf, PAGE_SIZE, "%d\n", enabled); -+} -+ -+static ssize_t display_enabled_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t size) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ bool enabled, r; -+ -+ enabled = simple_strtoul(buf, NULL, 10); -+ -+ if (enabled != (dssdev->state != OMAP_DSS_DISPLAY_DISABLED)) { -+ if (enabled) { -+ r = dssdev->enable(dssdev); -+ if (r) -+ return r; -+ } else { -+ dssdev->disable(dssdev); -+ } -+ } -+ -+ return size; -+} -+ -+static ssize_t display_upd_mode_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ enum omap_dss_update_mode mode = OMAP_DSS_UPDATE_AUTO; -+ if (dssdev->get_update_mode) -+ mode = dssdev->get_update_mode(dssdev); -+ return snprintf(buf, PAGE_SIZE, "%d\n", mode); -+} -+ -+static ssize_t display_upd_mode_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t size) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ int val, r; -+ enum omap_dss_update_mode mode; -+ -+ val = simple_strtoul(buf, NULL, 10); -+ -+ switch (val) { -+ case OMAP_DSS_UPDATE_DISABLED: -+ case OMAP_DSS_UPDATE_AUTO: -+ case OMAP_DSS_UPDATE_MANUAL: -+ mode = (enum omap_dss_update_mode)val; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ r = dssdev->set_update_mode(dssdev, mode); -+ if (r) -+ return r; -+ -+ return size; -+} -+ -+static ssize_t display_tear_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ return snprintf(buf, PAGE_SIZE, "%d\n", -+ dssdev->get_te ? dssdev->get_te(dssdev) : 0); -+} -+ -+static ssize_t display_tear_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t size) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ unsigned long te; -+ int r; -+ -+ if (!dssdev->enable_te || !dssdev->get_te) -+ return -ENOENT; -+ -+ te = simple_strtoul(buf, NULL, 0); -+ -+ r = dssdev->enable_te(dssdev, te); -+ if (r) -+ return r; -+ -+ return size; -+} -+ -+static ssize_t display_timings_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ struct omap_video_timings t; -+ -+ if (!dssdev->get_timings) -+ return -ENOENT; -+ -+ dssdev->get_timings(dssdev, &t); -+ -+ return snprintf(buf, PAGE_SIZE, "%u,%u/%u/%u/%u,%u/%u/%u/%u\n", -+ t.pixel_clock, -+ t.x_res, t.hfp, t.hbp, t.hsw, -+ t.y_res, t.vfp, t.vbp, t.vsw); -+} -+ -+static ssize_t display_timings_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t size) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ struct omap_video_timings t; -+ int r, found; -+ -+ if (!dssdev->set_timings || !dssdev->check_timings) -+ return -ENOENT; -+ -+ found = 0; -+#ifdef CONFIG_OMAP2_DSS_VENC -+ if (strncmp("pal", buf, 3) == 0) { -+ t = omap_dss_pal_timings; -+ found = 1; -+ } else if (strncmp("ntsc", buf, 4) == 0) { -+ t = omap_dss_ntsc_timings; -+ found = 1; -+ } -+#endif -+ if (!found && sscanf(buf, "%u,%hu/%hu/%hu/%hu,%hu/%hu/%hu/%hu", -+ &t.pixel_clock, -+ &t.x_res, &t.hfp, &t.hbp, &t.hsw, -+ &t.y_res, &t.vfp, &t.vbp, &t.vsw) != 9) -+ return -EINVAL; -+ -+ r = dssdev->check_timings(dssdev, &t); -+ if (r) -+ return r; -+ -+ dssdev->set_timings(dssdev, &t); -+ -+ return size; -+} -+ -+static ssize_t display_rotate_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ int rotate; -+ if (!dssdev->get_rotate) -+ return -ENOENT; -+ rotate = dssdev->get_rotate(dssdev); -+ return snprintf(buf, PAGE_SIZE, "%u\n", rotate); -+} -+ -+static ssize_t display_rotate_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t size) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ unsigned long rot; -+ int r; -+ -+ if (!dssdev->set_rotate || !dssdev->get_rotate) -+ return -ENOENT; -+ -+ rot = simple_strtoul(buf, NULL, 0); -+ -+ r = dssdev->set_rotate(dssdev, rot); -+ if (r) -+ return r; -+ -+ return size; -+} -+ -+static ssize_t display_mirror_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ int mirror; -+ if (!dssdev->get_mirror) -+ return -ENOENT; -+ mirror = dssdev->get_mirror(dssdev); -+ return snprintf(buf, PAGE_SIZE, "%u\n", mirror); -+} -+ -+static ssize_t display_mirror_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t size) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ unsigned long mirror; -+ int r; -+ -+ if (!dssdev->set_mirror || !dssdev->get_mirror) -+ return -ENOENT; -+ -+ mirror = simple_strtoul(buf, NULL, 0); -+ -+ r = dssdev->set_mirror(dssdev, mirror); -+ if (r) -+ return r; -+ -+ return size; -+} -+ -+static ssize_t display_wss_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ unsigned int wss; -+ -+ if (!dssdev->get_wss) -+ return -ENOENT; -+ -+ wss = dssdev->get_wss(dssdev); -+ -+ return snprintf(buf, PAGE_SIZE, "0x%05x\n", wss); -+} -+ -+static ssize_t display_wss_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t size) -+{ -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ unsigned long wss; -+ int r; -+ -+ if (!dssdev->get_wss || !dssdev->set_wss) -+ return -ENOENT; -+ -+ if (strict_strtoul(buf, 0, &wss)) -+ return -EINVAL; -+ -+ if (wss > 0xfffff) -+ return -EINVAL; -+ -+ r = dssdev->set_wss(dssdev, wss); -+ if (r) -+ return r; -+ -+ return size; -+} -+ -+static DEVICE_ATTR(enabled, S_IRUGO|S_IWUSR, -+ display_enabled_show, display_enabled_store); -+static DEVICE_ATTR(update_mode, S_IRUGO|S_IWUSR, -+ display_upd_mode_show, display_upd_mode_store); -+static DEVICE_ATTR(tear_elim, S_IRUGO|S_IWUSR, -+ display_tear_show, display_tear_store); -+static DEVICE_ATTR(timings, S_IRUGO|S_IWUSR, -+ display_timings_show, display_timings_store); -+static DEVICE_ATTR(rotate, S_IRUGO|S_IWUSR, -+ display_rotate_show, display_rotate_store); -+static DEVICE_ATTR(mirror, S_IRUGO|S_IWUSR, -+ display_mirror_show, display_mirror_store); -+static DEVICE_ATTR(wss, S_IRUGO|S_IWUSR, -+ display_wss_show, display_wss_store); -+ -+static struct device_attribute *display_sysfs_attrs[] = { -+ &dev_attr_enabled, -+ &dev_attr_update_mode, -+ &dev_attr_tear_elim, -+ &dev_attr_timings, -+ &dev_attr_rotate, -+ &dev_attr_mirror, -+ &dev_attr_wss, -+ NULL -+}; -+ -+static void default_get_resolution(struct omap_dss_device *dssdev, -+ u16 *xres, u16 *yres) -+{ -+ *xres = dssdev->panel.timings.x_res; -+ *yres = dssdev->panel.timings.y_res; -+} -+ -+void default_get_overlay_fifo_thresholds(enum omap_plane plane, -+ u32 fifo_size, enum omap_burst_size *burst_size, -+ u32 *fifo_low, u32 *fifo_high) -+{ -+ unsigned burst_size_bytes; -+ -+ *burst_size = OMAP_DSS_BURST_16x32; -+ burst_size_bytes = 16 * 32 / 8; -+ -+ *fifo_high = fifo_size - 1; -+ *fifo_low = fifo_size - burst_size_bytes; -+} -+ -+static int default_wait_vsync(struct omap_dss_device *dssdev) -+{ -+ unsigned long timeout = msecs_to_jiffies(500); -+ u32 irq; -+ -+ if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) -+ irq = DISPC_IRQ_EVSYNC_ODD; -+ else -+ irq = DISPC_IRQ_VSYNC; -+ -+ return omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout); -+} -+ -+static int default_get_recommended_bpp(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->panel.recommended_bpp) -+ return dssdev->panel.recommended_bpp; -+ -+ switch (dssdev->type) { -+ case OMAP_DISPLAY_TYPE_DPI: -+ if (dssdev->phy.dpi.data_lines == 24) -+ return 24; -+ else -+ return 16; -+ -+ case OMAP_DISPLAY_TYPE_DBI: -+ case OMAP_DISPLAY_TYPE_DSI: -+ if (dssdev->ctrl.pixel_size == 24) -+ return 24; -+ else -+ return 16; -+ case OMAP_DISPLAY_TYPE_VENC: -+ case OMAP_DISPLAY_TYPE_SDI: -+ return 24; -+ return 24; -+ default: -+ BUG(); -+ } -+} -+ -+/* Checks if replication logic should be used. Only use for active matrix, -+ * when overlay is in RGB12U or RGB16 mode, and LCD interface is -+ * 18bpp or 24bpp */ -+bool dss_use_replication(struct omap_dss_device *dssdev, -+ enum omap_color_mode mode) -+{ -+ int bpp; -+ -+ if (mode != OMAP_DSS_COLOR_RGB12U && mode != OMAP_DSS_COLOR_RGB16) -+ return false; -+ -+ if (dssdev->type == OMAP_DISPLAY_TYPE_DPI && -+ (dssdev->panel.config & OMAP_DSS_LCD_TFT) == 0) -+ return false; -+ -+ switch (dssdev->type) { -+ case OMAP_DISPLAY_TYPE_DPI: -+ bpp = dssdev->phy.dpi.data_lines; -+ break; -+ case OMAP_DISPLAY_TYPE_VENC: -+ case OMAP_DISPLAY_TYPE_SDI: -+ bpp = 24; -+ break; -+ case OMAP_DISPLAY_TYPE_DBI: -+ case OMAP_DISPLAY_TYPE_DSI: -+ bpp = dssdev->ctrl.pixel_size; -+ break; -+ default: -+ BUG(); -+ } -+ -+ return bpp > 16; -+} -+ -+void dss_init_device(struct platform_device *pdev, -+ struct omap_dss_device *dssdev) -+{ -+ struct device_attribute *attr; -+ int i; -+ int r; -+ -+ switch (dssdev->type) { -+ case OMAP_DISPLAY_TYPE_DPI: -+#ifdef CONFIG_OMAP2_DSS_RFBI -+ case OMAP_DISPLAY_TYPE_DBI: -+#endif -+#ifdef CONFIG_OMAP2_DSS_SDI -+ case OMAP_DISPLAY_TYPE_SDI: -+#endif -+#ifdef CONFIG_OMAP2_DSS_DSI -+ case OMAP_DISPLAY_TYPE_DSI: -+#endif -+#ifdef CONFIG_OMAP2_DSS_VENC -+ case OMAP_DISPLAY_TYPE_VENC: -+#endif -+ break; -+ default: -+ DSSERR("Support for display '%s' not compiled in.\n", -+ dssdev->name); -+ return; -+ } -+ -+ dssdev->get_resolution = default_get_resolution; -+ dssdev->get_recommended_bpp = default_get_recommended_bpp; -+ dssdev->wait_vsync = default_wait_vsync; -+ -+ switch (dssdev->type) { -+ case OMAP_DISPLAY_TYPE_DPI: -+ r = dpi_init_display(dssdev); -+ break; -+#ifdef CONFIG_OMAP2_DSS_RFBI -+ case OMAP_DISPLAY_TYPE_DBI: -+ r = rfbi_init_display(dssdev); -+ break; -+#endif -+#ifdef CONFIG_OMAP2_DSS_VENC -+ case OMAP_DISPLAY_TYPE_VENC: -+ r = venc_init_display(dssdev); -+ break; -+#endif -+#ifdef CONFIG_OMAP2_DSS_SDI -+ case OMAP_DISPLAY_TYPE_SDI: -+ r = sdi_init_display(dssdev); -+ break; -+#endif -+#ifdef CONFIG_OMAP2_DSS_DSI -+ case OMAP_DISPLAY_TYPE_DSI: -+ r = dsi_init_display(dssdev); -+ break; -+#endif -+ default: -+ BUG(); -+ } -+ -+ if (r) { -+ DSSERR("failed to init display %s\n", dssdev->name); -+ return; -+ } -+ -+ /* create device sysfs files */ -+ i = 0; -+ while ((attr = display_sysfs_attrs[i++]) != NULL) { -+ r = device_create_file(&dssdev->dev, attr); -+ if (r) -+ DSSERR("failed to create sysfs file\n"); -+ } -+ -+ /* create display? sysfs links */ -+ r = sysfs_create_link(&pdev->dev.kobj, &dssdev->dev.kobj, -+ dev_name(&dssdev->dev)); -+ if (r) -+ DSSERR("failed to create sysfs display link\n"); -+} -+ -+void dss_uninit_device(struct platform_device *pdev, -+ struct omap_dss_device *dssdev) -+{ -+ struct device_attribute *attr; -+ int i = 0; -+ -+ sysfs_remove_link(&pdev->dev.kobj, dev_name(&dssdev->dev)); -+ -+ while ((attr = display_sysfs_attrs[i++]) != NULL) -+ device_remove_file(&dssdev->dev, attr); -+ -+ if (dssdev->manager) -+ dssdev->manager->unset_device(dssdev->manager); -+} -+ -+static int dss_suspend_device(struct device *dev, void *data) -+{ -+ int r; -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) { -+ dssdev->activate_after_resume = false; -+ return 0; -+ } -+ -+ if (!dssdev->suspend) { -+ DSSERR("display '%s' doesn't implement suspend\n", -+ dssdev->name); -+ return -ENOSYS; -+ } -+ -+ r = dssdev->suspend(dssdev); -+ if (r) -+ return r; -+ -+ dssdev->activate_after_resume = true; -+ -+ return 0; -+} -+ -+int dss_suspend_all_devices(void) -+{ -+ int r; -+ struct bus_type *bus = dss_get_bus(); -+ -+ r = bus_for_each_dev(bus, NULL, NULL, dss_suspend_device); -+ if (r) { -+ /* resume all displays that were suspended */ -+ dss_resume_all_devices(); -+ return r; -+ } -+ -+ return 0; -+} -+ -+static int dss_resume_device(struct device *dev, void *data) -+{ -+ int r; -+ struct omap_dss_device *dssdev = to_dss_device(dev); -+ -+ if (dssdev->activate_after_resume && dssdev->resume) { -+ r = dssdev->resume(dssdev); -+ if (r) -+ return r; -+ } -+ -+ dssdev->activate_after_resume = false; -+ -+ return 0; -+} -+ -+int dss_resume_all_devices(void) -+{ -+ struct bus_type *bus = dss_get_bus(); -+ -+ return bus_for_each_dev(bus, NULL, NULL, dss_resume_device); -+} -+ -+ -+void omap_dss_get_device(struct omap_dss_device *dssdev) -+{ -+ get_device(&dssdev->dev); -+} -+EXPORT_SYMBOL(omap_dss_get_device); -+ -+void omap_dss_put_device(struct omap_dss_device *dssdev) -+{ -+ put_device(&dssdev->dev); -+} -+EXPORT_SYMBOL(omap_dss_put_device); -+ -+/* ref count of the found device is incremented. ref count -+ * of from-device is decremented. */ -+struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from) -+{ -+ struct device *dev; -+ struct device *dev_start = NULL; -+ struct omap_dss_device *dssdev = NULL; -+ -+ int match(struct device *dev, void *data) -+ { -+ /* skip panels connected to controllers */ -+ if (to_dss_device(dev)->panel.ctrl) -+ return 0; -+ -+ return 1; -+ } -+ -+ if (from) -+ dev_start = &from->dev; -+ dev = bus_find_device(dss_get_bus(), dev_start, NULL, match); -+ if (dev) -+ dssdev = to_dss_device(dev); -+ if (from) -+ put_device(&from->dev); -+ -+ return dssdev; -+} -+EXPORT_SYMBOL(omap_dss_get_next_device); -+ -+struct omap_dss_device *omap_dss_find_device(void *data, -+ int (*match)(struct omap_dss_device *dssdev, void *data)) -+{ -+ struct omap_dss_device *dssdev = NULL; -+ -+ while ((dssdev = omap_dss_get_next_device(dssdev)) != NULL) { -+ if (match(dssdev, data)) -+ return dssdev; -+ } -+ -+ return NULL; -+} -+EXPORT_SYMBOL(omap_dss_find_device); -+ -+int omap_dss_start_device(struct omap_dss_device *dssdev) -+{ -+ int r; -+ -+ if (!dssdev->driver) { -+ DSSDBG("no driver\n"); -+ r = -ENODEV; -+ goto err0; -+ } -+ -+ if (dssdev->ctrl.panel && !dssdev->ctrl.panel->driver) { -+ DSSDBG("no panel driver\n"); -+ r = -ENODEV; -+ goto err0; -+ } -+ -+ if (!try_module_get(dssdev->dev.driver->owner)) { -+ r = -ENODEV; -+ goto err0; -+ } -+ -+ if (dssdev->ctrl.panel) { -+ if (!try_module_get(dssdev->ctrl.panel->dev.driver->owner)) { -+ r = -ENODEV; -+ goto err1; -+ } -+ } -+ -+ return 0; -+err1: -+ module_put(dssdev->dev.driver->owner); -+err0: -+ return r; -+} -+EXPORT_SYMBOL(omap_dss_start_device); -+ -+void omap_dss_stop_device(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->ctrl.panel) -+ module_put(dssdev->ctrl.panel->dev.driver->owner); -+ -+ module_put(dssdev->dev.driver->owner); -+} -+EXPORT_SYMBOL(omap_dss_stop_device); -+ ---- /dev/null -+++ b/drivers/video/omap2/dss/dpi.c -@@ -0,0 +1,388 @@ -+/* -+ * linux/drivers/video/omap2/dss/dpi.c -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#define DSS_SUBSYS_NAME "DPI" -+ -+#include <linux/kernel.h> -+#include <linux/clk.h> -+#include <linux/delay.h> -+#include <linux/errno.h> -+ -+#include <mach/board.h> -+#include <mach/display.h> -+#include <mach/cpu.h> -+ -+#include "dss.h" -+ -+static struct { -+ int update_enabled; -+} dpi; -+ -+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL -+static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req, -+ unsigned long *fck, int *lck_div, int *pck_div) -+{ -+ struct dsi_clock_info cinfo; -+ int r; -+ -+ r = dsi_pll_calc_pck(is_tft, pck_req, &cinfo); -+ if (r) -+ return r; -+ -+ r = dsi_pll_program(&cinfo); -+ if (r) -+ return r; -+ -+ dss_select_clk_source(0, 1); -+ -+ dispc_set_lcd_divisor(cinfo.lck_div, cinfo.pck_div); -+ -+ *fck = cinfo.dsi1_pll_fclk; -+ *lck_div = cinfo.lck_div; -+ *pck_div = cinfo.pck_div; -+ -+ return 0; -+} -+#else -+static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req, -+ unsigned long *fck, int *lck_div, int *pck_div) -+{ -+ struct dispc_clock_info cinfo; -+ int r; -+ -+ r = dispc_calc_clock_div(is_tft, pck_req, &cinfo); -+ if (r) -+ return r; -+ -+ r = dispc_set_clock_div(&cinfo); -+ if (r) -+ return r; -+ -+ *fck = cinfo.fck; -+ *lck_div = cinfo.lck_div; -+ *pck_div = cinfo.pck_div; -+ -+ return 0; -+} -+#endif -+ -+static int dpi_set_mode(struct omap_dss_device *dssdev) -+{ -+ struct omap_video_timings *t = &dssdev->panel.timings; -+ int lck_div, pck_div; -+ unsigned long fck; -+ unsigned long pck; -+ bool is_tft; -+ int r = 0; -+ -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi, -+ dssdev->panel.acb); -+ -+ is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0; -+ -+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL -+ r = dpi_set_dsi_clk(is_tft, t->pixel_clock * 1000, -+ &fck, &lck_div, &pck_div); -+#else -+ r = dpi_set_dispc_clk(is_tft, t->pixel_clock * 1000, -+ &fck, &lck_div, &pck_div); -+#endif -+ if (r) -+ goto err0; -+ -+ pck = fck / lck_div / pck_div / 1000; -+ -+ if (pck != t->pixel_clock) { -+ DSSWARN("Could not find exact pixel clock. " -+ "Requested %d kHz, got %lu kHz\n", -+ t->pixel_clock, pck); -+ -+ t->pixel_clock = pck; -+ } -+ -+ dispc_set_lcd_timings(t); -+ -+err0: -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ return r; -+} -+ -+static int dpi_basic_init(struct omap_dss_device *dssdev) -+{ -+ bool is_tft; -+ -+ is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0; -+ -+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS); -+ dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT : -+ OMAP_DSS_LCD_DISPLAY_STN); -+ dispc_set_tft_data_lines(dssdev->phy.dpi.data_lines); -+ -+ return 0; -+} -+ -+static int dpi_display_enable(struct omap_dss_device *dssdev) -+{ -+ int r; -+ -+ r = omap_dss_start_device(dssdev); -+ if (r) { -+ DSSERR("failed to start device\n"); -+ goto err0; -+ } -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { -+ DSSERR("display already enabled\n"); -+ r = -EINVAL; -+ goto err1; -+ } -+ -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ r = dpi_basic_init(dssdev); -+ if (r) -+ goto err2; -+ -+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL -+ dss_clk_enable(DSS_CLK_FCK2); -+ r = dsi_pll_init(0, 1); -+ if (r) -+ goto err3; -+#endif -+ r = dpi_set_mode(dssdev); -+ if (r) -+ goto err4; -+ -+ mdelay(2); -+ -+ dispc_enable_lcd_out(1); -+ -+ r = dssdev->driver->enable(dssdev); -+ if (r) -+ goto err5; -+ -+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -+ -+ return 0; -+ -+err5: -+ dispc_enable_lcd_out(0); -+err4: -+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL -+ dsi_pll_uninit(); -+err3: -+ dss_clk_disable(DSS_CLK_FCK2); -+#endif -+err2: -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+err1: -+ omap_dss_stop_device(dssdev); -+err0: -+ return r; -+} -+ -+static int dpi_display_resume(struct omap_dss_device *dssdev); -+ -+static void dpi_display_disable(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED) -+ return; -+ -+ if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) -+ dpi_display_resume(dssdev); -+ -+ dssdev->driver->disable(dssdev); -+ -+ dispc_enable_lcd_out(0); -+ -+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL -+ dss_select_clk_source(0, 0); -+ dsi_pll_uninit(); -+ dss_clk_disable(DSS_CLK_FCK2); -+#endif -+ -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ dssdev->state = OMAP_DSS_DISPLAY_DISABLED; -+ -+ omap_dss_stop_device(dssdev); -+} -+ -+static int dpi_display_suspend(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) -+ return -EINVAL; -+ -+ DSSDBG("dpi_display_suspend\n"); -+ -+ if (dssdev->driver->suspend) -+ dssdev->driver->suspend(dssdev); -+ -+ dispc_enable_lcd_out(0); -+ -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; -+ -+ return 0; -+} -+ -+static int dpi_display_resume(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) -+ return -EINVAL; -+ -+ DSSDBG("dpi_display_resume\n"); -+ -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ dispc_enable_lcd_out(1); -+ -+ if (dssdev->driver->resume) -+ dssdev->driver->resume(dssdev); -+ -+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -+ -+ return 0; -+} -+ -+static void dpi_set_timings(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings) -+{ -+ DSSDBG("dpi_set_timings\n"); -+ dssdev->panel.timings = *timings; -+ if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { -+ dpi_set_mode(dssdev); -+ dispc_go(OMAP_DSS_CHANNEL_LCD); -+ } -+} -+ -+static int dpi_check_timings(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings) -+{ -+ bool is_tft; -+ int r; -+ int lck_div, pck_div; -+ unsigned long fck; -+ unsigned long pck; -+ -+ if (!dispc_lcd_timings_ok(timings)) -+ return -EINVAL; -+ -+ if (timings->pixel_clock == 0) -+ return -EINVAL; -+ -+ is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0; -+ -+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL -+ { -+ struct dsi_clock_info cinfo; -+ r = dsi_pll_calc_pck(is_tft, timings->pixel_clock * 1000, -+ &cinfo); -+ -+ if (r) -+ return r; -+ -+ fck = cinfo.dsi1_pll_fclk; -+ lck_div = cinfo.lck_div; -+ pck_div = cinfo.pck_div; -+ } -+#else -+ { -+ struct dispc_clock_info cinfo; -+ r = dispc_calc_clock_div(is_tft, timings->pixel_clock * 1000, -+ &cinfo); -+ -+ if (r) -+ return r; -+ -+ fck = cinfo.fck; -+ lck_div = cinfo.lck_div; -+ pck_div = cinfo.pck_div; -+ } -+#endif -+ -+ pck = fck / lck_div / pck_div / 1000; -+ -+ timings->pixel_clock = pck; -+ -+ return 0; -+} -+ -+static void dpi_get_timings(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings) -+{ -+ *timings = dssdev->panel.timings; -+} -+ -+static int dpi_display_set_update_mode(struct omap_dss_device *dssdev, -+ enum omap_dss_update_mode mode) -+{ -+ if (mode == OMAP_DSS_UPDATE_MANUAL) -+ return -EINVAL; -+ -+ if (mode == OMAP_DSS_UPDATE_DISABLED) { -+ dispc_enable_lcd_out(0); -+ dpi.update_enabled = 0; -+ } else { -+ dispc_enable_lcd_out(1); -+ dpi.update_enabled = 1; -+ } -+ -+ return 0; -+} -+ -+static enum omap_dss_update_mode dpi_display_get_update_mode( -+ struct omap_dss_device *dssdev) -+{ -+ return dpi.update_enabled ? OMAP_DSS_UPDATE_AUTO : -+ OMAP_DSS_UPDATE_DISABLED; -+} -+ -+int dpi_init_display(struct omap_dss_device *dssdev) -+{ -+ DSSDBG("init_display\n"); -+ -+ dssdev->enable = dpi_display_enable; -+ dssdev->disable = dpi_display_disable; -+ dssdev->suspend = dpi_display_suspend; -+ dssdev->resume = dpi_display_resume; -+ dssdev->set_timings = dpi_set_timings; -+ dssdev->check_timings = dpi_check_timings; -+ dssdev->get_timings = dpi_get_timings; -+ dssdev->set_update_mode = dpi_display_set_update_mode; -+ dssdev->get_update_mode = dpi_display_get_update_mode; -+ -+ return 0; -+} -+ -+int dpi_init(void) -+{ -+ return 0; -+} -+ -+void dpi_exit(void) -+{ -+} -+ ---- /dev/null -+++ b/drivers/video/omap2/dss/dsi.c -@@ -0,0 +1,3509 @@ -+/* -+ * linux/drivers/video/omap2/dss/dsi.c -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#define DSS_SUBSYS_NAME "DSI" -+ -+#include <linux/kernel.h> -+#include <linux/io.h> -+#include <linux/clk.h> -+#include <linux/device.h> -+#include <linux/err.h> -+#include <linux/interrupt.h> -+#include <linux/delay.h> -+#include <linux/mutex.h> -+#include <linux/seq_file.h> -+#include <linux/platform_device.h> -+#include <linux/regulator/consumer.h> -+#include <linux/kthread.h> -+#include <linux/wait.h> -+ -+#include <mach/board.h> -+#include <mach/display.h> -+#include <mach/clock.h> -+ -+#include "dss.h" -+ -+/*#define VERBOSE_IRQ*/ -+ -+#define DSI_BASE 0x4804FC00 -+ -+struct dsi_reg { u16 idx; }; -+ -+#define DSI_REG(idx) ((const struct dsi_reg) { idx }) -+ -+#define DSI_SZ_REGS SZ_1K -+/* DSI Protocol Engine */ -+ -+#define DSI_REVISION DSI_REG(0x0000) -+#define DSI_SYSCONFIG DSI_REG(0x0010) -+#define DSI_SYSSTATUS DSI_REG(0x0014) -+#define DSI_IRQSTATUS DSI_REG(0x0018) -+#define DSI_IRQENABLE DSI_REG(0x001C) -+#define DSI_CTRL DSI_REG(0x0040) -+#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) -+#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) -+#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) -+#define DSI_CLK_CTRL DSI_REG(0x0054) -+#define DSI_TIMING1 DSI_REG(0x0058) -+#define DSI_TIMING2 DSI_REG(0x005C) -+#define DSI_VM_TIMING1 DSI_REG(0x0060) -+#define DSI_VM_TIMING2 DSI_REG(0x0064) -+#define DSI_VM_TIMING3 DSI_REG(0x0068) -+#define DSI_CLK_TIMING DSI_REG(0x006C) -+#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) -+#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) -+#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) -+#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) -+#define DSI_VM_TIMING4 DSI_REG(0x0080) -+#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) -+#define DSI_VM_TIMING5 DSI_REG(0x0088) -+#define DSI_VM_TIMING6 DSI_REG(0x008C) -+#define DSI_VM_TIMING7 DSI_REG(0x0090) -+#define DSI_STOPCLK_TIMING DSI_REG(0x0094) -+#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) -+#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) -+#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) -+#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) -+#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) -+#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) -+#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) -+ -+/* DSIPHY_SCP */ -+ -+#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) -+#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) -+#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) -+#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) -+ -+/* DSI_PLL_CTRL_SCP */ -+ -+#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) -+#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) -+#define DSI_PLL_GO DSI_REG(0x300 + 0x0008) -+#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) -+#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) -+ -+#define REG_GET(idx, start, end) \ -+ FLD_GET(dsi_read_reg(idx), start, end) -+ -+#define REG_FLD_MOD(idx, val, start, end) \ -+ dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end)) -+ -+/* Global interrupts */ -+#define DSI_IRQ_VC0 (1 << 0) -+#define DSI_IRQ_VC1 (1 << 1) -+#define DSI_IRQ_VC2 (1 << 2) -+#define DSI_IRQ_VC3 (1 << 3) -+#define DSI_IRQ_WAKEUP (1 << 4) -+#define DSI_IRQ_RESYNC (1 << 5) -+#define DSI_IRQ_PLL_LOCK (1 << 7) -+#define DSI_IRQ_PLL_UNLOCK (1 << 8) -+#define DSI_IRQ_PLL_RECALL (1 << 9) -+#define DSI_IRQ_COMPLEXIO_ERR (1 << 10) -+#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) -+#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) -+#define DSI_IRQ_TE_TRIGGER (1 << 16) -+#define DSI_IRQ_ACK_TRIGGER (1 << 17) -+#define DSI_IRQ_SYNC_LOST (1 << 18) -+#define DSI_IRQ_LDO_POWER_GOOD (1 << 19) -+#define DSI_IRQ_TA_TIMEOUT (1 << 20) -+#define DSI_IRQ_ERROR_MASK \ -+ (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ -+ DSI_IRQ_TA_TIMEOUT) -+#define DSI_IRQ_CHANNEL_MASK 0xf -+ -+/* Virtual channel interrupts */ -+#define DSI_VC_IRQ_CS (1 << 0) -+#define DSI_VC_IRQ_ECC_CORR (1 << 1) -+#define DSI_VC_IRQ_PACKET_SENT (1 << 2) -+#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) -+#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) -+#define DSI_VC_IRQ_BTA (1 << 5) -+#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) -+#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) -+#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) -+#define DSI_VC_IRQ_ERROR_MASK \ -+ (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ -+ DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ -+ DSI_VC_IRQ_FIFO_TX_UDF) -+ -+/* ComplexIO interrupts */ -+#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) -+#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) -+#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) -+#define DSI_CIO_IRQ_ERRESC1 (1 << 5) -+#define DSI_CIO_IRQ_ERRESC2 (1 << 6) -+#define DSI_CIO_IRQ_ERRESC3 (1 << 7) -+#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) -+#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) -+#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) -+#define DSI_CIO_IRQ_STATEULPS1 (1 << 15) -+#define DSI_CIO_IRQ_STATEULPS2 (1 << 16) -+#define DSI_CIO_IRQ_STATEULPS3 (1 << 17) -+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) -+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) -+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) -+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) -+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) -+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) -+#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) -+#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) -+ -+#define DSI_DT_DCS_SHORT_WRITE_0 0x05 -+#define DSI_DT_DCS_SHORT_WRITE_1 0x15 -+#define DSI_DT_DCS_READ 0x06 -+#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37 -+#define DSI_DT_NULL_PACKET 0x09 -+#define DSI_DT_DCS_LONG_WRITE 0x39 -+ -+#define DSI_DT_RX_ACK_WITH_ERR 0x02 -+#define DSI_DT_RX_DCS_LONG_READ 0x1c -+#define DSI_DT_RX_SHORT_READ_1 0x21 -+#define DSI_DT_RX_SHORT_READ_2 0x22 -+ -+#define FINT_MAX 2100000 -+#define FINT_MIN 750000 -+#define REGN_MAX (1 << 7) -+#define REGM_MAX ((1 << 11) - 1) -+#define REGM3_MAX (1 << 4) -+#define REGM4_MAX (1 << 4) -+ -+enum fifo_size { -+ DSI_FIFO_SIZE_0 = 0, -+ DSI_FIFO_SIZE_32 = 1, -+ DSI_FIFO_SIZE_64 = 2, -+ DSI_FIFO_SIZE_96 = 3, -+ DSI_FIFO_SIZE_128 = 4, -+}; -+ -+enum dsi_vc_mode { -+ DSI_VC_MODE_L4 = 0, -+ DSI_VC_MODE_VP, -+}; -+ -+struct dsi_update_region { -+ bool dirty; -+ u16 x, y, w, h; -+ struct omap_dss_device *device; -+}; -+ -+static struct -+{ -+ void __iomem *base; -+ -+ unsigned long dsi1_pll_fclk; /* Hz */ -+ unsigned long dsi2_pll_fclk; /* Hz */ -+ unsigned long dsiphy; /* Hz */ -+ unsigned long ddr_clk; /* Hz */ -+ -+ struct regulator *vdds_dsi_reg; -+ -+ struct { -+ enum dsi_vc_mode mode; -+ struct omap_dss_device *dssdev; -+ enum fifo_size fifo_size; -+ int dest_per; /* destination peripheral 0-3 */ -+ } vc[4]; -+ -+ struct mutex lock; -+ struct mutex bus_lock; -+ -+ unsigned pll_locked; -+ -+ struct completion bta_completion; -+ -+ struct task_struct *thread; -+ wait_queue_head_t waitqueue; -+ -+ spinlock_t update_lock; -+ bool framedone_received; -+ struct dsi_update_region update_region; -+ struct dsi_update_region active_update_region; -+ struct completion update_completion; -+ -+ enum omap_dss_update_mode user_update_mode; -+ enum omap_dss_update_mode update_mode; -+ bool te_enabled; -+ bool use_ext_te; -+ -+ unsigned long cache_req_pck; -+ unsigned long cache_clk_freq; -+ struct dsi_clock_info cache_cinfo; -+ -+ u32 errors; -+ spinlock_t errors_lock; -+#ifdef DEBUG -+ ktime_t perf_setup_time; -+ ktime_t perf_start_time; -+ ktime_t perf_start_time_auto; -+ int perf_measure_frames; -+#endif -+ int debug_read; -+ int debug_write; -+} dsi; -+ -+#ifdef DEBUG -+static unsigned int dsi_perf; -+module_param_named(dsi_perf, dsi_perf, bool, 0644); -+#endif -+ -+static inline void dsi_write_reg(const struct dsi_reg idx, u32 val) -+{ -+ __raw_writel(val, dsi.base + idx.idx); -+} -+ -+static inline u32 dsi_read_reg(const struct dsi_reg idx) -+{ -+ return __raw_readl(dsi.base + idx.idx); -+} -+ -+ -+void dsi_save_context(void) -+{ -+} -+ -+void dsi_restore_context(void) -+{ -+} -+ -+void dsi_bus_lock(void) -+{ -+ mutex_lock(&dsi.bus_lock); -+} -+EXPORT_SYMBOL(dsi_bus_lock); -+ -+void dsi_bus_unlock(void) -+{ -+ mutex_unlock(&dsi.bus_lock); -+} -+EXPORT_SYMBOL(dsi_bus_unlock); -+ -+static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum, -+ int value) -+{ -+ int t = 100000; -+ -+ while (REG_GET(idx, bitnum, bitnum) != value) { -+ if (--t == 0) -+ return !value; -+ } -+ -+ return value; -+} -+ -+#ifdef DEBUG -+static void dsi_perf_mark_setup(void) -+{ -+ dsi.perf_setup_time = ktime_get(); -+} -+ -+static void dsi_perf_mark_start(void) -+{ -+ dsi.perf_start_time = ktime_get(); -+} -+ -+static void dsi_perf_mark_start_auto(void) -+{ -+ dsi.perf_measure_frames = 0; -+ dsi.perf_start_time_auto = ktime_get(); -+} -+ -+static void dsi_perf_show(const char *name) -+{ -+ ktime_t t, setup_time, trans_time; -+ u32 total_bytes; -+ u32 setup_us, trans_us, total_us; -+ -+ if (!dsi_perf) -+ return; -+ -+ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED) -+ return; -+ -+ t = ktime_get(); -+ -+ setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time); -+ setup_us = (u32)ktime_to_us(setup_time); -+ if (setup_us == 0) -+ setup_us = 1; -+ -+ trans_time = ktime_sub(t, dsi.perf_start_time); -+ trans_us = (u32)ktime_to_us(trans_time); -+ if (trans_us == 0) -+ trans_us = 1; -+ -+ total_us = setup_us + trans_us; -+ -+ total_bytes = dsi.active_update_region.w * -+ dsi.active_update_region.h * -+ dsi.active_update_region.device->ctrl.pixel_size / 8; -+ -+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) { -+ static u32 s_total_trans_us, s_total_setup_us; -+ static u32 s_min_trans_us = 0xffffffff, s_min_setup_us; -+ static u32 s_max_trans_us, s_max_setup_us; -+ const int numframes = 100; -+ ktime_t total_time_auto; -+ u32 total_time_auto_us; -+ -+ dsi.perf_measure_frames++; -+ -+ if (setup_us < s_min_setup_us) -+ s_min_setup_us = setup_us; -+ -+ if (setup_us > s_max_setup_us) -+ s_max_setup_us = setup_us; -+ -+ s_total_setup_us += setup_us; -+ -+ if (trans_us < s_min_trans_us) -+ s_min_trans_us = trans_us; -+ -+ if (trans_us > s_max_trans_us) -+ s_max_trans_us = trans_us; -+ -+ s_total_trans_us += trans_us; -+ -+ if (dsi.perf_measure_frames < numframes) -+ return; -+ -+ total_time_auto = ktime_sub(t, dsi.perf_start_time_auto); -+ total_time_auto_us = (u32)ktime_to_us(total_time_auto); -+ -+ printk(KERN_INFO "DSI(%s): %u fps, setup %u/%u/%u, " -+ "trans %u/%u/%u\n", -+ name, -+ 1000 * 1000 * numframes / total_time_auto_us, -+ s_min_setup_us, -+ s_max_setup_us, -+ s_total_setup_us / numframes, -+ s_min_trans_us, -+ s_max_trans_us, -+ s_total_trans_us / numframes); -+ -+ s_total_setup_us = 0; -+ s_min_setup_us = 0xffffffff; -+ s_max_setup_us = 0; -+ s_total_trans_us = 0; -+ s_min_trans_us = 0xffffffff; -+ s_max_trans_us = 0; -+ dsi_perf_mark_start_auto(); -+ } else { -+ printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " -+ "%u bytes, %u kbytes/sec\n", -+ name, -+ setup_us, -+ trans_us, -+ total_us, -+ 1000*1000 / total_us, -+ total_bytes, -+ total_bytes * 1000 / total_us); -+ } -+} -+#else -+#define dsi_perf_mark_setup() -+#define dsi_perf_mark_start() -+#define dsi_perf_mark_start_auto() -+#define dsi_perf_show(x) -+#endif -+ -+static void print_irq_status(u32 status) -+{ -+#ifndef VERBOSE_IRQ -+ if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) -+ return; -+#endif -+ printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status); -+ -+#define PIS(x) \ -+ if (status & DSI_IRQ_##x) \ -+ printk(#x " "); -+#ifdef VERBOSE_IRQ -+ PIS(VC0); -+ PIS(VC1); -+ PIS(VC2); -+ PIS(VC3); -+#endif -+ PIS(WAKEUP); -+ PIS(RESYNC); -+ PIS(PLL_LOCK); -+ PIS(PLL_UNLOCK); -+ PIS(PLL_RECALL); -+ PIS(COMPLEXIO_ERR); -+ PIS(HS_TX_TIMEOUT); -+ PIS(LP_RX_TIMEOUT); -+ PIS(TE_TRIGGER); -+ PIS(ACK_TRIGGER); -+ PIS(SYNC_LOST); -+ PIS(LDO_POWER_GOOD); -+ PIS(TA_TIMEOUT); -+#undef PIS -+ -+ printk("\n"); -+} -+ -+static void print_irq_status_vc(int channel, u32 status) -+{ -+#ifndef VERBOSE_IRQ -+ if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) -+ return; -+#endif -+ printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status); -+ -+#define PIS(x) \ -+ if (status & DSI_VC_IRQ_##x) \ -+ printk(#x " "); -+ PIS(CS); -+ PIS(ECC_CORR); -+#ifdef VERBOSE_IRQ -+ PIS(PACKET_SENT); -+#endif -+ PIS(FIFO_TX_OVF); -+ PIS(FIFO_RX_OVF); -+ PIS(BTA); -+ PIS(ECC_NO_CORR); -+ PIS(FIFO_TX_UDF); -+ PIS(PP_BUSY_CHANGE); -+#undef PIS -+ printk("\n"); -+} -+ -+static void print_irq_status_cio(u32 status) -+{ -+ printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); -+ -+#define PIS(x) \ -+ if (status & DSI_CIO_IRQ_##x) \ -+ printk(#x " "); -+ PIS(ERRSYNCESC1); -+ PIS(ERRSYNCESC2); -+ PIS(ERRSYNCESC3); -+ PIS(ERRESC1); -+ PIS(ERRESC2); -+ PIS(ERRESC3); -+ PIS(ERRCONTROL1); -+ PIS(ERRCONTROL2); -+ PIS(ERRCONTROL3); -+ PIS(STATEULPS1); -+ PIS(STATEULPS2); -+ PIS(STATEULPS3); -+ PIS(ERRCONTENTIONLP0_1); -+ PIS(ERRCONTENTIONLP1_1); -+ PIS(ERRCONTENTIONLP0_2); -+ PIS(ERRCONTENTIONLP1_2); -+ PIS(ERRCONTENTIONLP0_3); -+ PIS(ERRCONTENTIONLP1_3); -+ PIS(ULPSACTIVENOT_ALL0); -+ PIS(ULPSACTIVENOT_ALL1); -+#undef PIS -+ -+ printk("\n"); -+} -+ -+static int debug_irq; -+ -+/* called from dss */ -+void dsi_irq_handler(void) -+{ -+ u32 irqstatus, vcstatus, ciostatus; -+ int i; -+ -+ irqstatus = dsi_read_reg(DSI_IRQSTATUS); -+ -+ if (irqstatus & DSI_IRQ_ERROR_MASK) { -+ DSSERR("DSI error, irqstatus %x\n", irqstatus); -+ print_irq_status(irqstatus); -+ spin_lock(&dsi.errors_lock); -+ dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK; -+ spin_unlock(&dsi.errors_lock); -+ } else if (debug_irq) { -+ print_irq_status(irqstatus); -+ } -+ -+ for (i = 0; i < 4; ++i) { -+ if ((irqstatus & (1<<i)) == 0) -+ continue; -+ -+ vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i)); -+ -+ if (vcstatus & DSI_VC_IRQ_BTA) -+ complete(&dsi.bta_completion); -+ -+ if (vcstatus & DSI_VC_IRQ_ERROR_MASK) { -+ DSSERR("DSI VC(%d) error, vc irqstatus %x\n", -+ i, vcstatus); -+ print_irq_status_vc(i, vcstatus); -+ } else if (debug_irq) { -+ print_irq_status_vc(i, vcstatus); -+ } -+ -+ dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus); -+ } -+ -+ if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { -+ ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); -+ -+ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus); -+ -+ DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); -+ print_irq_status_cio(ciostatus); -+ } -+ -+ dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); -+} -+ -+ -+static void _dsi_initialize_irq(void) -+{ -+ u32 l; -+ int i; -+ -+ /* disable all interrupts */ -+ dsi_write_reg(DSI_IRQENABLE, 0); -+ for (i = 0; i < 4; ++i) -+ dsi_write_reg(DSI_VC_IRQENABLE(i), 0); -+ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0); -+ -+ /* clear interrupt status */ -+ l = dsi_read_reg(DSI_IRQSTATUS); -+ dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK); -+ -+ for (i = 0; i < 4; ++i) { -+ l = dsi_read_reg(DSI_VC_IRQSTATUS(i)); -+ dsi_write_reg(DSI_VC_IRQSTATUS(i), l); -+ } -+ -+ l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); -+ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l); -+ -+ /* enable error irqs */ -+ l = DSI_IRQ_ERROR_MASK; -+ dsi_write_reg(DSI_IRQENABLE, l); -+ -+ l = DSI_VC_IRQ_ERROR_MASK; -+ for (i = 0; i < 4; ++i) -+ dsi_write_reg(DSI_VC_IRQENABLE(i), l); -+ -+ /* XXX zonda responds incorrectly, causing control error: -+ Exit from LP-ESC mode to LP11 uses wrong transition states on the -+ data lines LP0 and LN0. */ -+ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, -+ -1 & (~DSI_CIO_IRQ_ERRCONTROL2)); -+} -+ -+static u32 dsi_get_errors(void) -+{ -+ unsigned long flags; -+ u32 e; -+ spin_lock_irqsave(&dsi.errors_lock, flags); -+ e = dsi.errors; -+ dsi.errors = 0; -+ spin_unlock_irqrestore(&dsi.errors_lock, flags); -+ return e; -+} -+ -+static void dsi_vc_enable_bta_irq(int channel) -+{ -+ u32 l; -+ -+ dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA); -+ -+ l = dsi_read_reg(DSI_VC_IRQENABLE(channel)); -+ l |= DSI_VC_IRQ_BTA; -+ dsi_write_reg(DSI_VC_IRQENABLE(channel), l); -+} -+ -+static void dsi_vc_disable_bta_irq(int channel) -+{ -+ u32 l; -+ -+ l = dsi_read_reg(DSI_VC_IRQENABLE(channel)); -+ l &= ~DSI_VC_IRQ_BTA; -+ dsi_write_reg(DSI_VC_IRQENABLE(channel), l); -+} -+ -+/* DSI func clock. this could also be DSI2_PLL_FCLK */ -+static inline void enable_clocks(bool enable) -+{ -+ if (enable) -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ else -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+} -+ -+/* source clock for DSI PLL. this could also be PCLKFREE */ -+static inline void dsi_enable_pll_clock(bool enable) -+{ -+ if (enable) -+ dss_clk_enable(DSS_CLK_FCK2); -+ else -+ dss_clk_disable(DSS_CLK_FCK2); -+ -+ if (enable && dsi.pll_locked) { -+ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) -+ DSSERR("cannot lock PLL when enabling clocks\n"); -+ } -+} -+ -+#ifdef DEBUG -+static void _dsi_print_reset_status(void) -+{ -+ u32 l; -+ -+ if (!dss_debug) -+ return; -+ -+ /* A dummy read using the SCP interface to any DSIPHY register is -+ * required after DSIPHY reset to complete the reset of the DSI complex -+ * I/O. */ -+ l = dsi_read_reg(DSI_DSIPHY_CFG5); -+ -+ printk(KERN_DEBUG "DSI resets: "); -+ -+ l = dsi_read_reg(DSI_PLL_STATUS); -+ printk("PLL (%d) ", FLD_GET(l, 0, 0)); -+ -+ l = dsi_read_reg(DSI_COMPLEXIO_CFG1); -+ printk("CIO (%d) ", FLD_GET(l, 29, 29)); -+ -+ l = dsi_read_reg(DSI_DSIPHY_CFG5); -+ printk("PHY (%x, %d, %d, %d)\n", -+ FLD_GET(l, 28, 26), -+ FLD_GET(l, 29, 29), -+ FLD_GET(l, 30, 30), -+ FLD_GET(l, 31, 31)); -+} -+#else -+#define _dsi_print_reset_status() -+#endif -+ -+static inline int dsi_if_enable(bool enable) -+{ -+ DSSDBG("dsi_if_enable(%d)\n", enable); -+ -+ enable = enable ? 1 : 0; -+ REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */ -+ -+ if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) { -+ DSSERR("Failed to set dsi_if_enable to %d\n", enable); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static unsigned long dsi_fclk_rate(void) -+{ -+ unsigned long r; -+ -+ if (dss_get_dsi_clk_source() == 0) { -+ /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */ -+ r = dss_clk_get_rate(DSS_CLK_FCK1); -+ } else { -+ /* DSI FCLK source is DSI2_PLL_FCLK */ -+ r = dsi.dsi2_pll_fclk; -+ } -+ -+ return r; -+} -+ -+static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev) -+{ -+ unsigned n; -+ unsigned long dsi_fclk; -+ unsigned long lp_clk, lp_clk_req; -+ -+ dsi_fclk = dsi_fclk_rate(); -+ -+ lp_clk_req = dssdev->phy.dsi.lp_clk_hz; -+ -+ for (n = 1; n < (1 << 13) - 1; ++n) { -+ lp_clk = dsi_fclk / 2 / n; -+ if (lp_clk <= lp_clk_req) -+ break; -+ } -+ -+ if (n == (1 << 13) - 1) { -+ DSSERR("Failed to find LP_CLK_DIVISOR\n"); -+ return -EINVAL; -+ } -+ -+ DSSDBG("LP_CLK_DIV %u, LP_CLK %lu (req %lu)\n", n, lp_clk, lp_clk_req); -+ -+ REG_FLD_MOD(DSI_CLK_CTRL, n, 12, 0); /* LP_CLK_DIVISOR */ -+ if (dsi_fclk > 30*1000*1000) -+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */ -+ -+ return 0; -+} -+ -+ -+enum dsi_pll_power_state { -+ DSI_PLL_POWER_OFF = 0x0, -+ DSI_PLL_POWER_ON_HSCLK = 0x1, -+ DSI_PLL_POWER_ON_ALL = 0x2, -+ DSI_PLL_POWER_ON_DIV = 0x3, -+}; -+ -+static int dsi_pll_power(enum dsi_pll_power_state state) -+{ -+ int t = 0; -+ -+ REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */ -+ -+ /* PLL_PWR_STATUS */ -+ while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) { -+ udelay(1); -+ if (t++ > 1000) { -+ DSSERR("Failed to set DSI PLL power mode to %d\n", -+ state); -+ return -ENODEV; -+ } -+ } -+ -+ return 0; -+} -+ -+int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck, -+ struct dsi_clock_info *cinfo) -+{ -+ struct dsi_clock_info cur, best; -+ int min_fck_per_pck; -+ int match = 0; -+ unsigned long dss_clk_fck2; -+ -+ dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2); -+ -+ if (req_pck == dsi.cache_req_pck && -+ dsi.cache_cinfo.clkin == dss_clk_fck2) { -+ DSSDBG("DSI clock info found from cache\n"); -+ *cinfo = dsi.cache_cinfo; -+ return 0; -+ } -+ -+ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; -+ -+ if (min_fck_per_pck && -+ req_pck * min_fck_per_pck > DISPC_MAX_FCK) { -+ DSSERR("Requested pixel clock not possible with the current " -+ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " -+ "the constraint off.\n"); -+ min_fck_per_pck = 0; -+ } -+ -+ DSSDBG("dsi_pll_calc\n"); -+ -+retry: -+ memset(&best, 0, sizeof(best)); -+ -+ memset(&cur, 0, sizeof(cur)); -+ cur.clkin = dss_clk_fck2; -+ cur.use_dss2_fck = 1; -+ cur.highfreq = 0; -+ -+ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ -+ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ -+ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ -+ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) { -+ if (cur.highfreq == 0) -+ cur.fint = cur.clkin / cur.regn; -+ else -+ cur.fint = cur.clkin / (2 * cur.regn); -+ -+ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN) -+ continue; -+ -+ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ -+ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) { -+ unsigned long a, b; -+ -+ a = 2 * cur.regm * (cur.clkin/1000); -+ b = cur.regn * (cur.highfreq + 1); -+ cur.dsiphy = a / b * 1000; -+ -+ if (cur.dsiphy > 1800 * 1000 * 1000) -+ break; -+ -+ /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */ -+ for (cur.regm3 = 1; cur.regm3 < REGM3_MAX; -+ ++cur.regm3) { -+ cur.dsi1_pll_fclk = cur.dsiphy / cur.regm3; -+ -+ /* this will narrow down the search a bit, -+ * but still give pixclocks below what was -+ * requested */ -+ if (cur.dsi1_pll_fclk < req_pck) -+ break; -+ -+ if (cur.dsi1_pll_fclk > DISPC_MAX_FCK) -+ continue; -+ -+ if (min_fck_per_pck && -+ cur.dsi1_pll_fclk < -+ req_pck * min_fck_per_pck) -+ continue; -+ -+ match = 1; -+ -+ find_lck_pck_divs(is_tft, req_pck, -+ cur.dsi1_pll_fclk, -+ &cur.lck_div, -+ &cur.pck_div); -+ -+ cur.lck = cur.dsi1_pll_fclk / cur.lck_div; -+ cur.pck = cur.lck / cur.pck_div; -+ -+ if (abs(cur.pck - req_pck) < -+ abs(best.pck - req_pck)) { -+ best = cur; -+ -+ if (cur.pck == req_pck) -+ goto found; -+ } -+ } -+ } -+ } -+found: -+ if (!match) { -+ if (min_fck_per_pck) { -+ DSSERR("Could not find suitable clock settings.\n" -+ "Turning FCK/PCK constraint off and" -+ "trying again.\n"); -+ min_fck_per_pck = 0; -+ goto retry; -+ } -+ -+ DSSERR("Could not find suitable clock settings.\n"); -+ -+ return -EINVAL; -+ } -+ -+ /* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */ -+ best.regm4 = best.dsiphy / 48000000; -+ if (best.regm4 > REGM4_MAX) -+ best.regm4 = REGM4_MAX; -+ else if (best.regm4 == 0) -+ best.regm4 = 1; -+ best.dsi2_pll_fclk = best.dsiphy / best.regm4; -+ -+ if (cinfo) -+ *cinfo = best; -+ -+ dsi.cache_req_pck = req_pck; -+ dsi.cache_clk_freq = 0; -+ dsi.cache_cinfo = best; -+ -+ return 0; -+} -+ -+static int dsi_pll_calc_ddrfreq(unsigned long clk_freq, -+ struct dsi_clock_info *cinfo) -+{ -+ struct dsi_clock_info cur, best; -+ const bool use_dss2_fck = 1; -+ unsigned long datafreq; -+ unsigned long dss_clk_fck2; -+ -+ DSSDBG("dsi_pll_calc_ddrfreq\n"); -+ -+ dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2); -+ -+ if (clk_freq == dsi.cache_clk_freq && -+ dsi.cache_cinfo.clkin == dss_clk_fck2) { -+ DSSDBG("DSI clock info found from cache\n"); -+ *cinfo = dsi.cache_cinfo; -+ return 0; -+ } -+ -+ datafreq = clk_freq * 4; -+ -+ memset(&best, 0, sizeof(best)); -+ -+ memset(&cur, 0, sizeof(cur)); -+ cur.use_dss2_fck = use_dss2_fck; -+ if (use_dss2_fck) { -+ cur.clkin = dss_clk_fck2; -+ cur.highfreq = 0; -+ } else { -+ cur.clkin = dispc_pclk_rate(); -+ if (cur.clkin < 32000000) -+ cur.highfreq = 0; -+ else -+ cur.highfreq = 1; -+ } -+ -+ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ -+ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ -+ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ -+ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) { -+ if (cur.highfreq == 0) -+ cur.fint = cur.clkin / cur.regn; -+ else -+ cur.fint = cur.clkin / (2 * cur.regn); -+ -+ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN) -+ continue; -+ -+ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ -+ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) { -+ unsigned long a, b; -+ -+ a = 2 * cur.regm * (cur.clkin/1000); -+ b = cur.regn * (cur.highfreq + 1); -+ cur.dsiphy = a / b * 1000; -+ -+ if (cur.dsiphy > 1800 * 1000 * 1000) -+ break; -+ -+ if (abs(cur.dsiphy - datafreq) < -+ abs(best.dsiphy - datafreq)) { -+ best = cur; -+ /* DSSDBG("best %ld\n", best.dsiphy); */ -+ } -+ -+ if (cur.dsiphy == datafreq) -+ goto found; -+ } -+ } -+found: -+ /* DSI1_PLL_FCLK (regm3) is not used. Set it to something sane. */ -+ best.regm3 = best.dsiphy / 48000000; -+ if (best.regm3 > REGM3_MAX) -+ best.regm3 = REGM3_MAX; -+ else if (best.regm3 == 0) -+ best.regm3 = 1; -+ best.dsi1_pll_fclk = best.dsiphy / best.regm3; -+ -+ /* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */ -+ best.regm4 = best.dsiphy / 48000000; -+ if (best.regm4 > REGM4_MAX) -+ best.regm4 = REGM4_MAX; -+ else if (best.regm4 == 0) -+ best.regm4 = 1; -+ best.dsi2_pll_fclk = best.dsiphy / best.regm4; -+ -+ if (cinfo) -+ *cinfo = best; -+ -+ dsi.cache_clk_freq = clk_freq; -+ dsi.cache_req_pck = 0; -+ dsi.cache_cinfo = best; -+ -+ return 0; -+} -+ -+int dsi_pll_program(struct dsi_clock_info *cinfo) -+{ -+ int r = 0; -+ u32 l; -+ -+ DSSDBG("dsi_pll_program\n"); -+ -+ dsi.dsiphy = cinfo->dsiphy; -+ dsi.ddr_clk = dsi.dsiphy / 4; -+ dsi.dsi1_pll_fclk = cinfo->dsi1_pll_fclk; -+ dsi.dsi2_pll_fclk = cinfo->dsi2_pll_fclk; -+ -+ DSSDBG("DSI Fint %ld\n", cinfo->fint); -+ -+ DSSDBG("clkin (%s) rate %ld, highfreq %d\n", -+ cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree", -+ cinfo->clkin, -+ cinfo->highfreq); -+ -+ /* DSIPHY == CLKIN4DDR */ -+ DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n", -+ cinfo->regm, -+ cinfo->regn, -+ cinfo->clkin, -+ cinfo->highfreq + 1, -+ cinfo->dsiphy); -+ -+ DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", -+ dsi.dsiphy / 1000 / 1000 / 2); -+ -+ DSSDBG("Clock lane freq %ld Hz\n", dsi.ddr_clk); -+ -+ DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n", -+ cinfo->regm3, cinfo->dsi1_pll_fclk); -+ DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n", -+ cinfo->regm4, cinfo->dsi2_pll_fclk); -+ -+ REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ -+ -+ l = dsi_read_reg(DSI_PLL_CONFIGURATION1); -+ l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ -+ l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */ -+ l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */ -+ l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19); /* DSI_CLOCK_DIV */ -+ l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23); /* DSIPROTO_CLOCK_DIV */ -+ dsi_write_reg(DSI_PLL_CONFIGURATION1, l); -+ -+ l = dsi_read_reg(DSI_PLL_CONFIGURATION2); -+ l = FLD_MOD(l, 7, 4, 1); /* DSI_PLL_FREQSEL */ -+ /* DSI_PLL_CLKSEL */ -+ l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11); -+ l = FLD_MOD(l, cinfo->highfreq, 12, 12); /* DSI_PLL_HIGHFREQ */ -+ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ -+ l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ -+ l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ -+ dsi_write_reg(DSI_PLL_CONFIGURATION2, l); -+ -+ REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ -+ -+ if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) { -+ DSSERR("dsi pll go bit not going down.\n"); -+ r = -EIO; -+ goto err; -+ } -+ -+ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) { -+ DSSERR("cannot lock PLL\n"); -+ r = -EIO; -+ goto err; -+ } -+ -+ dsi.pll_locked = 1; -+ -+ l = dsi_read_reg(DSI_PLL_CONFIGURATION2); -+ l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ -+ l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ -+ l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ -+ l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ -+ l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ -+ l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ -+ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ -+ l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ -+ l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ -+ l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ -+ l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ -+ l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ -+ l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ -+ l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ -+ dsi_write_reg(DSI_PLL_CONFIGURATION2, l); -+ -+ DSSDBG("PLL config done\n"); -+err: -+ return r; -+} -+ -+int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv) -+{ -+ int r = 0; -+ enum dsi_pll_power_state pwstate; -+ struct dispc_clock_info cinfo; -+ -+ DSSDBG("PLL init\n"); -+ -+ enable_clocks(1); -+ dsi_enable_pll_clock(1); -+ -+ /* XXX this should be calculated depending on the screen size, -+ * required framerate and DSI speed. -+ * For now 48MHz is enough for 864x480@60 with 360Mbps/lane -+ * with two lanes */ -+ r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo); -+ if (r) -+ goto err0; -+ -+ r = dispc_set_clock_div(&cinfo); -+ if (r) { -+ DSSERR("Failed to set basic clocks\n"); -+ goto err0; -+ } -+ -+ r = regulator_enable(dsi.vdds_dsi_reg); -+ if (r) -+ goto err0; -+ -+ /* XXX PLL does not come out of reset without this... */ -+ dispc_pck_free_enable(1); -+ -+ if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) { -+ DSSERR("PLL not coming out of reset.\n"); -+ r = -ENODEV; -+ goto err1; -+ } -+ -+ /* XXX ... but if left on, we get problems when planes do not -+ * fill the whole display. No idea about this */ -+ dispc_pck_free_enable(0); -+ -+ if (enable_hsclk && enable_hsdiv) -+ pwstate = DSI_PLL_POWER_ON_ALL; -+ else if (enable_hsclk) -+ pwstate = DSI_PLL_POWER_ON_HSCLK; -+ else if (enable_hsdiv) -+ pwstate = DSI_PLL_POWER_ON_DIV; -+ else -+ pwstate = DSI_PLL_POWER_OFF; -+ -+ r = dsi_pll_power(pwstate); -+ -+ if (r) -+ goto err1; -+ -+ DSSDBG("PLL init done\n"); -+ -+ return 0; -+err1: -+ regulator_disable(dsi.vdds_dsi_reg); -+err0: -+ enable_clocks(0); -+ dsi_enable_pll_clock(0); -+ return r; -+} -+ -+void dsi_pll_uninit(void) -+{ -+ enable_clocks(0); -+ dsi_enable_pll_clock(0); -+ -+ dsi.pll_locked = 0; -+ dsi_pll_power(DSI_PLL_POWER_OFF); -+ regulator_disable(dsi.vdds_dsi_reg); -+ DSSDBG("PLL uninit done\n"); -+} -+ -+unsigned long dsi_get_dsi1_pll_rate(void) -+{ -+ return dsi.dsi1_pll_fclk; -+} -+ -+unsigned long dsi_get_dsi2_pll_rate(void) -+{ -+ return dsi.dsi2_pll_fclk; -+} -+ -+void dsi_dump_clocks(struct seq_file *s) -+{ -+ int clksel; -+ -+ enable_clocks(1); -+ -+ clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11); -+ -+ seq_printf(s, "- dsi -\n"); -+ -+ seq_printf(s, "dsi fclk source = %s\n", -+ dss_get_dsi_clk_source() == 0 ? -+ "dss1_alwon_fclk" : "dsi2_pll_fclk"); -+ -+ seq_printf(s, "dsi pll source = %s\n", -+ clksel == 0 ? -+ "dss2_alwon_fclk" : "pclkfree"); -+ -+ seq_printf(s, "DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n", -+ dsi.dsiphy, dsi.ddr_clk); -+ -+ seq_printf(s, "dsi1_pll_fck\t%lu (%s)\n" -+ "dsi2_pll_fck\t%lu (%s)\n", -+ dsi.dsi1_pll_fclk, -+ dss_get_dispc_clk_source() == 0 ? "off" : "on", -+ dsi.dsi2_pll_fclk, -+ dss_get_dsi_clk_source() == 0 ? "off" : "on"); -+ -+ enable_clocks(0); -+} -+ -+void dsi_dump_regs(struct seq_file *s) -+{ -+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r)) -+ -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ DUMPREG(DSI_REVISION); -+ DUMPREG(DSI_SYSCONFIG); -+ DUMPREG(DSI_SYSSTATUS); -+ DUMPREG(DSI_IRQSTATUS); -+ DUMPREG(DSI_IRQENABLE); -+ DUMPREG(DSI_CTRL); -+ DUMPREG(DSI_COMPLEXIO_CFG1); -+ DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); -+ DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); -+ DUMPREG(DSI_CLK_CTRL); -+ DUMPREG(DSI_TIMING1); -+ DUMPREG(DSI_TIMING2); -+ DUMPREG(DSI_VM_TIMING1); -+ DUMPREG(DSI_VM_TIMING2); -+ DUMPREG(DSI_VM_TIMING3); -+ DUMPREG(DSI_CLK_TIMING); -+ DUMPREG(DSI_TX_FIFO_VC_SIZE); -+ DUMPREG(DSI_RX_FIFO_VC_SIZE); -+ DUMPREG(DSI_COMPLEXIO_CFG2); -+ DUMPREG(DSI_RX_FIFO_VC_FULLNESS); -+ DUMPREG(DSI_VM_TIMING4); -+ DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); -+ DUMPREG(DSI_VM_TIMING5); -+ DUMPREG(DSI_VM_TIMING6); -+ DUMPREG(DSI_VM_TIMING7); -+ DUMPREG(DSI_STOPCLK_TIMING); -+ -+ DUMPREG(DSI_VC_CTRL(0)); -+ DUMPREG(DSI_VC_TE(0)); -+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); -+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); -+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); -+ DUMPREG(DSI_VC_IRQSTATUS(0)); -+ DUMPREG(DSI_VC_IRQENABLE(0)); -+ -+ DUMPREG(DSI_VC_CTRL(1)); -+ DUMPREG(DSI_VC_TE(1)); -+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); -+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); -+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); -+ DUMPREG(DSI_VC_IRQSTATUS(1)); -+ DUMPREG(DSI_VC_IRQENABLE(1)); -+ -+ DUMPREG(DSI_VC_CTRL(2)); -+ DUMPREG(DSI_VC_TE(2)); -+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); -+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); -+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); -+ DUMPREG(DSI_VC_IRQSTATUS(2)); -+ DUMPREG(DSI_VC_IRQENABLE(2)); -+ -+ DUMPREG(DSI_VC_CTRL(3)); -+ DUMPREG(DSI_VC_TE(3)); -+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); -+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); -+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); -+ DUMPREG(DSI_VC_IRQSTATUS(3)); -+ DUMPREG(DSI_VC_IRQENABLE(3)); -+ -+ DUMPREG(DSI_DSIPHY_CFG0); -+ DUMPREG(DSI_DSIPHY_CFG1); -+ DUMPREG(DSI_DSIPHY_CFG2); -+ DUMPREG(DSI_DSIPHY_CFG5); -+ -+ DUMPREG(DSI_PLL_CONTROL); -+ DUMPREG(DSI_PLL_STATUS); -+ DUMPREG(DSI_PLL_GO); -+ DUMPREG(DSI_PLL_CONFIGURATION1); -+ DUMPREG(DSI_PLL_CONFIGURATION2); -+ -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+#undef DUMPREG -+} -+ -+enum dsi_complexio_power_state { -+ DSI_COMPLEXIO_POWER_OFF = 0x0, -+ DSI_COMPLEXIO_POWER_ON = 0x1, -+ DSI_COMPLEXIO_POWER_ULPS = 0x2, -+}; -+ -+static int dsi_complexio_power(enum dsi_complexio_power_state state) -+{ -+ int t = 0; -+ -+ /* PWR_CMD */ -+ REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27); -+ -+ /* PWR_STATUS */ -+ while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) { -+ udelay(1); -+ if (t++ > 1000) { -+ DSSERR("failed to set complexio power state to " -+ "%d\n", state); -+ return -ENODEV; -+ } -+ } -+ -+ return 0; -+} -+ -+static void dsi_complexio_config(struct omap_dss_device *dssdev) -+{ -+ u32 r; -+ -+ int clk_lane = dssdev->phy.dsi.clk_lane; -+ int data1_lane = dssdev->phy.dsi.data1_lane; -+ int data2_lane = dssdev->phy.dsi.data2_lane; -+ int clk_pol = dssdev->phy.dsi.clk_pol; -+ int data1_pol = dssdev->phy.dsi.data1_pol; -+ int data2_pol = dssdev->phy.dsi.data2_pol; -+ -+ r = dsi_read_reg(DSI_COMPLEXIO_CFG1); -+ r = FLD_MOD(r, clk_lane, 2, 0); -+ r = FLD_MOD(r, clk_pol, 3, 3); -+ r = FLD_MOD(r, data1_lane, 6, 4); -+ r = FLD_MOD(r, data1_pol, 7, 7); -+ r = FLD_MOD(r, data2_lane, 10, 8); -+ r = FLD_MOD(r, data2_pol, 11, 11); -+ dsi_write_reg(DSI_COMPLEXIO_CFG1, r); -+ -+ /* The configuration of the DSI complex I/O (number of data lanes, -+ position, differential order) should not be changed while -+ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for -+ the hardware to take into account a new configuration of the complex -+ I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to -+ follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, -+ then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set -+ DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the -+ DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the -+ DSI complex I/O configuration is unknown. */ -+ -+ /* -+ REG_FLD_MOD(DSI_CTRL, 1, 0, 0); -+ REG_FLD_MOD(DSI_CTRL, 0, 0, 0); -+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); -+ REG_FLD_MOD(DSI_CTRL, 1, 0, 0); -+ */ -+} -+ -+static inline unsigned ns2ddr(unsigned ns) -+{ -+ /* convert time in ns to ddr ticks, rounding up */ -+ return (ns * (dsi.ddr_clk/1000/1000) + 999) / 1000; -+} -+ -+static inline unsigned ddr2ns(unsigned ddr) -+{ -+ return ddr * 1000 * 1000 / (dsi.ddr_clk / 1000); -+} -+ -+static void dsi_complexio_timings(void) -+{ -+ u32 r; -+ u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; -+ u32 tlpx_half, tclk_trail, tclk_zero; -+ u32 tclk_prepare; -+ -+ /* calculate timings */ -+ -+ /* 1 * DDR_CLK = 2 * UI */ -+ -+ /* min 40ns + 4*UI max 85ns + 6*UI */ -+ ths_prepare = ns2ddr(70) + 2; -+ -+ /* min 145ns + 10*UI */ -+ ths_prepare_ths_zero = ns2ddr(175) + 2; -+ -+ /* min max(8*UI, 60ns+4*UI) */ -+ ths_trail = ns2ddr(60) + 5; -+ -+ /* min 100ns */ -+ ths_exit = ns2ddr(145); -+ -+ /* tlpx min 50n */ -+ tlpx_half = ns2ddr(25); -+ -+ /* min 60ns */ -+ tclk_trail = ns2ddr(60) + 2; -+ -+ /* min 38ns, max 95ns */ -+ tclk_prepare = ns2ddr(65); -+ -+ /* min tclk-prepare + tclk-zero = 300ns */ -+ tclk_zero = ns2ddr(260); -+ -+ DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", -+ ths_prepare, ddr2ns(ths_prepare), -+ ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero)); -+ DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", -+ ths_trail, ddr2ns(ths_trail), -+ ths_exit, ddr2ns(ths_exit)); -+ -+ DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " -+ "tclk_zero %u (%uns)\n", -+ tlpx_half, ddr2ns(tlpx_half), -+ tclk_trail, ddr2ns(tclk_trail), -+ tclk_zero, ddr2ns(tclk_zero)); -+ DSSDBG("tclk_prepare %u (%uns)\n", -+ tclk_prepare, ddr2ns(tclk_prepare)); -+ -+ /* program timings */ -+ -+ r = dsi_read_reg(DSI_DSIPHY_CFG0); -+ r = FLD_MOD(r, ths_prepare, 31, 24); -+ r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); -+ r = FLD_MOD(r, ths_trail, 15, 8); -+ r = FLD_MOD(r, ths_exit, 7, 0); -+ dsi_write_reg(DSI_DSIPHY_CFG0, r); -+ -+ r = dsi_read_reg(DSI_DSIPHY_CFG1); -+ r = FLD_MOD(r, tlpx_half, 22, 16); -+ r = FLD_MOD(r, tclk_trail, 15, 8); -+ r = FLD_MOD(r, tclk_zero, 7, 0); -+ dsi_write_reg(DSI_DSIPHY_CFG1, r); -+ -+ r = dsi_read_reg(DSI_DSIPHY_CFG2); -+ r = FLD_MOD(r, tclk_prepare, 7, 0); -+ dsi_write_reg(DSI_DSIPHY_CFG2, r); -+} -+ -+ -+static int dsi_complexio_init(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ DSSDBG("dsi_complexio_init\n"); -+ -+ /* CIO_CLK_ICG, enable L3 clk to CIO */ -+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14); -+ -+ /* A dummy read using the SCP interface to any DSIPHY register is -+ * required after DSIPHY reset to complete the reset of the DSI complex -+ * I/O. */ -+ dsi_read_reg(DSI_DSIPHY_CFG5); -+ -+ if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) { -+ DSSERR("ComplexIO PHY not coming out of reset.\n"); -+ r = -ENODEV; -+ goto err; -+ } -+ -+ dsi_complexio_config(dssdev); -+ -+ r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON); -+ -+ if (r) -+ goto err; -+ -+ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) { -+ DSSERR("ComplexIO not coming out of reset.\n"); -+ r = -ENODEV; -+ goto err; -+ } -+ -+ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) { -+ DSSERR("ComplexIO LDO power down.\n"); -+ r = -ENODEV; -+ goto err; -+ } -+ -+ dsi_complexio_timings(); -+ -+ /* -+ The configuration of the DSI complex I/O (number of data lanes, -+ position, differential order) should not be changed while -+ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the -+ hardware to recognize a new configuration of the complex I/O (done -+ in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow -+ this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next -+ reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20] -+ LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN -+ bit to 1. If the sequence is not followed, the DSi complex I/O -+ configuration is undetermined. -+ */ -+ dsi_if_enable(1); -+ dsi_if_enable(0); -+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ -+ dsi_if_enable(1); -+ dsi_if_enable(0); -+ -+ DSSDBG("CIO init done\n"); -+err: -+ return r; -+} -+ -+static void dsi_complexio_uninit(void) -+{ -+ dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF); -+} -+ -+static int _dsi_wait_reset(void) -+{ -+ int i = 0; -+ -+ while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) { -+ if (i++ > 5) { -+ DSSERR("soft reset failed\n"); -+ return -ENODEV; -+ } -+ udelay(1); -+ } -+ -+ return 0; -+} -+ -+static int _dsi_reset(void) -+{ -+ /* Soft reset */ -+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1); -+ return _dsi_wait_reset(); -+} -+ -+ -+static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2, -+ enum fifo_size size3, enum fifo_size size4) -+{ -+ u32 r = 0; -+ int add = 0; -+ int i; -+ -+ dsi.vc[0].fifo_size = size1; -+ dsi.vc[1].fifo_size = size2; -+ dsi.vc[2].fifo_size = size3; -+ dsi.vc[3].fifo_size = size4; -+ -+ for (i = 0; i < 4; i++) { -+ u8 v; -+ int size = dsi.vc[i].fifo_size; -+ -+ if (add + size > 4) { -+ DSSERR("Illegal FIFO configuration\n"); -+ BUG(); -+ } -+ -+ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); -+ r |= v << (8 * i); -+ /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ -+ add += size; -+ } -+ -+ dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r); -+} -+ -+static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2, -+ enum fifo_size size3, enum fifo_size size4) -+{ -+ u32 r = 0; -+ int add = 0; -+ int i; -+ -+ dsi.vc[0].fifo_size = size1; -+ dsi.vc[1].fifo_size = size2; -+ dsi.vc[2].fifo_size = size3; -+ dsi.vc[3].fifo_size = size4; -+ -+ for (i = 0; i < 4; i++) { -+ u8 v; -+ int size = dsi.vc[i].fifo_size; -+ -+ if (add + size > 4) { -+ DSSERR("Illegal FIFO configuration\n"); -+ BUG(); -+ } -+ -+ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); -+ r |= v << (8 * i); -+ /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ -+ add += size; -+ } -+ -+ dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r); -+} -+ -+static int dsi_force_tx_stop_mode_io(void) -+{ -+ u32 r; -+ -+ r = dsi_read_reg(DSI_TIMING1); -+ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ -+ dsi_write_reg(DSI_TIMING1, r); -+ -+ if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) { -+ DSSERR("TX_STOP bit not going down\n"); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static void dsi_vc_print_status(int channel) -+{ -+ u32 r; -+ -+ r = dsi_read_reg(DSI_VC_CTRL(channel)); -+ DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, " -+ "TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ", -+ channel, -+ FLD_GET(r, 5, 5), -+ FLD_GET(r, 6, 6), -+ FLD_GET(r, 15, 15), -+ FLD_GET(r, 16, 16), -+ FLD_GET(r, 20, 20)); -+ -+ r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS); -+ DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff); -+} -+ -+static int dsi_vc_enable(int channel, bool enable) -+{ -+ if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO) -+ DSSDBG("dsi_vc_enable channel %d, enable %d\n", -+ channel, enable); -+ -+ enable = enable ? 1 : 0; -+ -+ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0); -+ -+ if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) { -+ DSSERR("Failed to set dsi_vc_enable to %d\n", enable); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static void dsi_vc_initial_config(int channel) -+{ -+ u32 r; -+ -+ DSSDBGF("%d", channel); -+ -+ r = dsi_read_reg(DSI_VC_CTRL(channel)); -+ -+ if (FLD_GET(r, 15, 15)) /* VC_BUSY */ -+ DSSERR("VC(%d) busy when trying to configure it!\n", -+ channel); -+ -+ r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ -+ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ -+ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ -+ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ -+ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ -+ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ -+ r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ -+ -+ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ -+ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ -+ -+ dsi_write_reg(DSI_VC_CTRL(channel), r); -+ -+ dsi.vc[channel].mode = DSI_VC_MODE_L4; -+} -+ -+static void dsi_vc_config_l4(int channel) -+{ -+ if (dsi.vc[channel].mode == DSI_VC_MODE_L4) -+ return; -+ -+ DSSDBGF("%d", channel); -+ -+ dsi_vc_enable(channel, 0); -+ -+ if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */ -+ DSSERR("vc(%d) busy when trying to config for L4\n", channel); -+ -+ REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */ -+ -+ dsi_vc_enable(channel, 1); -+ -+ dsi.vc[channel].mode = DSI_VC_MODE_L4; -+} -+ -+static void dsi_vc_config_vp(int channel) -+{ -+ if (dsi.vc[channel].mode == DSI_VC_MODE_VP) -+ return; -+ -+ DSSDBGF("%d", channel); -+ -+ dsi_vc_enable(channel, 0); -+ -+ if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */ -+ DSSERR("vc(%d) busy when trying to config for VP\n", channel); -+ -+ REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */ -+ -+ dsi_vc_enable(channel, 1); -+ -+ dsi.vc[channel].mode = DSI_VC_MODE_VP; -+} -+ -+ -+static void dsi_vc_enable_hs(int channel, bool enable) -+{ -+ DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); -+ -+ dsi_vc_enable(channel, 0); -+ dsi_if_enable(0); -+ -+ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9); -+ -+ dsi_vc_enable(channel, 1); -+ dsi_if_enable(1); -+ -+ dsi_force_tx_stop_mode_io(); -+} -+ -+static void dsi_vc_flush_long_data(int channel) -+{ -+ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { -+ u32 val; -+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); -+ DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", -+ (val >> 0) & 0xff, -+ (val >> 8) & 0xff, -+ (val >> 16) & 0xff, -+ (val >> 24) & 0xff); -+ } -+} -+ -+static void dsi_show_rx_ack_with_err(u16 err) -+{ -+ DSSERR("\tACK with ERROR (%#x):\n", err); -+ if (err & (1 << 0)) -+ DSSERR("\t\tSoT Error\n"); -+ if (err & (1 << 1)) -+ DSSERR("\t\tSoT Sync Error\n"); -+ if (err & (1 << 2)) -+ DSSERR("\t\tEoT Sync Error\n"); -+ if (err & (1 << 3)) -+ DSSERR("\t\tEscape Mode Entry Command Error\n"); -+ if (err & (1 << 4)) -+ DSSERR("\t\tLP Transmit Sync Error\n"); -+ if (err & (1 << 5)) -+ DSSERR("\t\tHS Receive Timeout Error\n"); -+ if (err & (1 << 6)) -+ DSSERR("\t\tFalse Control Error\n"); -+ if (err & (1 << 7)) -+ DSSERR("\t\t(reserved7)\n"); -+ if (err & (1 << 8)) -+ DSSERR("\t\tECC Error, single-bit (corrected)\n"); -+ if (err & (1 << 9)) -+ DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); -+ if (err & (1 << 10)) -+ DSSERR("\t\tChecksum Error\n"); -+ if (err & (1 << 11)) -+ DSSERR("\t\tData type not recognized\n"); -+ if (err & (1 << 12)) -+ DSSERR("\t\tInvalid VC ID\n"); -+ if (err & (1 << 13)) -+ DSSERR("\t\tInvalid Transmission Length\n"); -+ if (err & (1 << 14)) -+ DSSERR("\t\t(reserved14)\n"); -+ if (err & (1 << 15)) -+ DSSERR("\t\tDSI Protocol Violation\n"); -+} -+ -+static u16 dsi_vc_flush_receive_data(int channel) -+{ -+ /* RX_FIFO_NOT_EMPTY */ -+ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { -+ u32 val; -+ u8 dt; -+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); -+ DSSDBG("\trawval %#08x\n", val); -+ dt = FLD_GET(val, 5, 0); -+ if (dt == DSI_DT_RX_ACK_WITH_ERR) { -+ u16 err = FLD_GET(val, 23, 8); -+ dsi_show_rx_ack_with_err(err); -+ } else if (dt == DSI_DT_RX_SHORT_READ_1) { -+ DSSDBG("\tDCS short response, 1 byte: %#x\n", -+ FLD_GET(val, 23, 8)); -+ } else if (dt == DSI_DT_RX_SHORT_READ_2) { -+ DSSDBG("\tDCS short response, 2 byte: %#x\n", -+ FLD_GET(val, 23, 8)); -+ } else if (dt == DSI_DT_RX_DCS_LONG_READ) { -+ DSSDBG("\tDCS long response, len %d\n", -+ FLD_GET(val, 23, 8)); -+ dsi_vc_flush_long_data(channel); -+ } else { -+ DSSERR("\tunknown datatype 0x%02x\n", dt); -+ } -+ } -+ return 0; -+} -+ -+static int dsi_vc_send_bta(int channel) -+{ -+ if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO && -+ (dsi.debug_write || dsi.debug_read)) -+ DSSDBG("dsi_vc_send_bta %d\n", channel); -+ -+ WARN_ON(!mutex_is_locked(&dsi.bus_lock)); -+ -+ if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */ -+ DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); -+ dsi_vc_flush_receive_data(channel); -+ } -+ -+ REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ -+ -+ return 0; -+} -+ -+int dsi_vc_send_bta_sync(int channel) -+{ -+ int r = 0; -+ u32 err; -+ -+ INIT_COMPLETION(dsi.bta_completion); -+ -+ dsi_vc_enable_bta_irq(channel); -+ -+ r = dsi_vc_send_bta(channel); -+ if (r) -+ goto err; -+ -+ if (wait_for_completion_timeout(&dsi.bta_completion, -+ msecs_to_jiffies(500)) == 0) { -+ DSSERR("Failed to receive BTA\n"); -+ r = -EIO; -+ goto err; -+ } -+ -+ err = dsi_get_errors(); -+ if (err) { -+ DSSERR("Error while sending BTA: %x\n", err); -+ r = -EIO; -+ goto err; -+ } -+err: -+ dsi_vc_disable_bta_irq(channel); -+ -+ return r; -+} -+EXPORT_SYMBOL(dsi_vc_send_bta_sync); -+ -+static inline void dsi_vc_write_long_header(int channel, u8 data_type, -+ u16 len, u8 ecc) -+{ -+ u32 val; -+ u8 data_id; -+ -+ WARN_ON(!mutex_is_locked(&dsi.bus_lock)); -+ -+ /*data_id = data_type | channel << 6; */ -+ data_id = data_type | dsi.vc[channel].dest_per << 6; -+ -+ val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | -+ FLD_VAL(ecc, 31, 24); -+ -+ dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val); -+} -+ -+static inline void dsi_vc_write_long_payload(int channel, -+ u8 b1, u8 b2, u8 b3, u8 b4) -+{ -+ u32 val; -+ -+ val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; -+ -+/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", -+ b1, b2, b3, b4, val); */ -+ -+ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val); -+} -+ -+static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len, -+ u8 ecc) -+{ -+ /*u32 val; */ -+ int i; -+ u8 *p; -+ int r = 0; -+ u8 b1, b2, b3, b4; -+ -+ if (dsi.debug_write) -+ DSSDBG("dsi_vc_send_long, %d bytes\n", len); -+ -+ /* len + header */ -+ if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) { -+ DSSERR("unable to send long packet: packet too long.\n"); -+ return -EINVAL; -+ } -+ -+ dsi_vc_config_l4(channel); -+ -+ dsi_vc_write_long_header(channel, data_type, len, ecc); -+ -+ /*dsi_vc_print_status(0); */ -+ -+ p = data; -+ for (i = 0; i < len >> 2; i++) { -+ if (dsi.debug_write) -+ DSSDBG("\tsending full packet %d\n", i); -+ /*dsi_vc_print_status(0); */ -+ -+ b1 = *p++; -+ b2 = *p++; -+ b3 = *p++; -+ b4 = *p++; -+ -+ dsi_vc_write_long_payload(channel, b1, b2, b3, b4); -+ } -+ -+ i = len % 4; -+ if (i) { -+ b1 = 0; b2 = 0; b3 = 0; -+ -+ if (dsi.debug_write) -+ DSSDBG("\tsending remainder bytes %d\n", i); -+ -+ switch (i) { -+ case 3: -+ b1 = *p++; -+ b2 = *p++; -+ b3 = *p++; -+ break; -+ case 2: -+ b1 = *p++; -+ b2 = *p++; -+ break; -+ case 1: -+ b1 = *p++; -+ break; -+ } -+ -+ dsi_vc_write_long_payload(channel, b1, b2, b3, 0); -+ } -+ -+ return r; -+} -+ -+static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc) -+{ -+ u32 r; -+ u8 data_id; -+ -+ WARN_ON(!mutex_is_locked(&dsi.bus_lock)); -+ -+ if (dsi.debug_write) -+ DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", -+ channel, -+ data_type, data & 0xff, (data >> 8) & 0xff); -+ -+ dsi_vc_config_l4(channel); -+ -+ if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) { -+ DSSERR("ERROR FIFO FULL, aborting transfer\n"); -+ return -EINVAL; -+ } -+ -+ data_id = data_type | channel << 6; -+ -+ r = (data_id << 0) | (data << 8) | (ecc << 24); -+ -+ dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r); -+ -+ return 0; -+} -+ -+int dsi_vc_send_null(int channel) -+{ -+ u8 nullpkg[] = {0, 0, 0, 0}; -+ return dsi_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0); -+} -+EXPORT_SYMBOL(dsi_vc_send_null); -+ -+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len) -+{ -+ int r; -+ -+ BUG_ON(len == 0); -+ -+ if (len == 1) { -+ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0, -+ data[0], 0); -+ } else if (len == 2) { -+ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1, -+ data[0] | (data[1] << 8), 0); -+ } else { -+ /* 0x39 = DCS Long Write */ -+ r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE, -+ data, len, 0); -+ } -+ -+ return r; -+} -+EXPORT_SYMBOL(dsi_vc_dcs_write_nosync); -+ -+int dsi_vc_dcs_write(int channel, u8 *data, int len) -+{ -+ int r; -+ -+ r = dsi_vc_dcs_write_nosync(channel, data, len); -+ if (r) -+ return r; -+ -+ r = dsi_vc_send_bta_sync(channel); -+ -+ return r; -+} -+EXPORT_SYMBOL(dsi_vc_dcs_write); -+ -+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen) -+{ -+ u32 val; -+ u8 dt; -+ int r; -+ -+ if (dsi.debug_read) -+ DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %u)\n", channel, dcs_cmd); -+ -+ r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0); -+ if (r) -+ return r; -+ -+ r = dsi_vc_send_bta_sync(channel); -+ if (r) -+ return r; -+ -+ /* RX_FIFO_NOT_EMPTY */ -+ if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) { -+ DSSERR("RX fifo empty when trying to read.\n"); -+ return -EIO; -+ } -+ -+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); -+ if (dsi.debug_read) -+ DSSDBG("\theader: %08x\n", val); -+ dt = FLD_GET(val, 5, 0); -+ if (dt == DSI_DT_RX_ACK_WITH_ERR) { -+ u16 err = FLD_GET(val, 23, 8); -+ dsi_show_rx_ack_with_err(err); -+ return -EIO; -+ -+ } else if (dt == DSI_DT_RX_SHORT_READ_1) { -+ u8 data = FLD_GET(val, 15, 8); -+ if (dsi.debug_read) -+ DSSDBG("\tDCS short response, 1 byte: %02x\n", data); -+ -+ if (buflen < 1) -+ return -EIO; -+ -+ buf[0] = data; -+ -+ return 1; -+ } else if (dt == DSI_DT_RX_SHORT_READ_2) { -+ u16 data = FLD_GET(val, 23, 8); -+ if (dsi.debug_read) -+ DSSDBG("\tDCS short response, 2 byte: %04x\n", data); -+ -+ if (buflen < 2) -+ return -EIO; -+ -+ buf[0] = data & 0xff; -+ buf[1] = (data >> 8) & 0xff; -+ -+ return 2; -+ } else if (dt == DSI_DT_RX_DCS_LONG_READ) { -+ int w; -+ int len = FLD_GET(val, 23, 8); -+ if (dsi.debug_read) -+ DSSDBG("\tDCS long response, len %d\n", len); -+ -+ if (len > buflen) -+ return -EIO; -+ -+ /* two byte checksum ends the packet, not included in len */ -+ for (w = 0; w < len + 2;) { -+ int b; -+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); -+ if (dsi.debug_read) -+ DSSDBG("\t\t%02x %02x %02x %02x\n", -+ (val >> 0) & 0xff, -+ (val >> 8) & 0xff, -+ (val >> 16) & 0xff, -+ (val >> 24) & 0xff); -+ -+ for (b = 0; b < 4; ++b) { -+ if (w < len) -+ buf[w] = (val >> (b * 8)) & 0xff; -+ /* we discard the 2 byte checksum */ -+ ++w; -+ } -+ } -+ -+ return len; -+ -+ } else { -+ DSSERR("\tunknown datatype 0x%02x\n", dt); -+ return -EIO; -+ } -+} -+EXPORT_SYMBOL(dsi_vc_dcs_read); -+ -+ -+int dsi_vc_set_max_rx_packet_size(int channel, u16 len) -+{ -+ return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE, -+ len, 0); -+} -+EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size); -+ -+ -+static int dsi_set_lp_rx_timeout(int ns, int x4, int x16) -+{ -+ u32 r; -+ unsigned long fck; -+ int ticks; -+ -+ /* ticks in DSI_FCK */ -+ -+ fck = dsi_fclk_rate(); -+ ticks = (fck / 1000 / 1000) * ns / 1000; -+ -+ if (ticks > 0x1fff) { -+ DSSERR("LP_TX_TO too high\n"); -+ return -EINVAL; -+ } -+ -+ r = dsi_read_reg(DSI_TIMING2); -+ r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ -+ r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */ -+ r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */ -+ r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ -+ dsi_write_reg(DSI_TIMING2, r); -+ -+ DSSDBG("LP_RX_TO %ld ns (%#x ticks)\n", -+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) / -+ (fck / 1000 / 1000), -+ ticks); -+ -+ return 0; -+} -+ -+static int dsi_set_ta_timeout(int ns, int x8, int x16) -+{ -+ u32 r; -+ unsigned long fck; -+ int ticks; -+ -+ /* ticks in DSI_FCK */ -+ -+ fck = dsi_fclk_rate(); -+ ticks = (fck / 1000 / 1000) * ns / 1000; -+ -+ if (ticks > 0x1fff) { -+ DSSERR("TA_TO too high\n"); -+ return -EINVAL; -+ } -+ -+ r = dsi_read_reg(DSI_TIMING1); -+ r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ -+ r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */ -+ r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */ -+ r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ -+ dsi_write_reg(DSI_TIMING1, r); -+ -+ DSSDBG("TA_TO %ld ns (%#x ticks)\n", -+ (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) / -+ (fck / 1000 / 1000), -+ ticks); -+ -+ return 0; -+} -+ -+static int dsi_set_stop_state_counter(int ns, int x4, int x16) -+{ -+ u32 r; -+ unsigned long fck; -+ int ticks; -+ -+ /* ticks in DSI_FCK */ -+ -+ fck = dsi_fclk_rate(); -+ ticks = (fck / 1000 / 1000) * ns / 1000; -+ -+ if (ticks > 0x1fff) { -+ DSSERR("STOP_STATE_COUNTER_IO too high\n"); -+ return -EINVAL; -+ } -+ -+ r = dsi_read_reg(DSI_TIMING1); -+ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ -+ r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */ -+ r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */ -+ r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ -+ dsi_write_reg(DSI_TIMING1, r); -+ -+ DSSDBG("STOP_STATE_COUNTER %ld ns (%#x ticks)\n", -+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) / -+ (fck / 1000 / 1000), -+ ticks); -+ -+ return 0; -+} -+ -+static int dsi_set_hs_tx_timeout(int ns, int x4, int x16) -+{ -+ u32 r; -+ unsigned long fck; -+ int ticks; -+ -+ /* ticks in TxByteClkHS */ -+ -+ fck = dsi.ddr_clk / 4; -+ ticks = (fck / 1000 / 1000) * ns / 1000; -+ -+ if (ticks > 0x1fff) { -+ DSSERR("HS_TX_TO too high\n"); -+ return -EINVAL; -+ } -+ -+ r = dsi_read_reg(DSI_TIMING2); -+ r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ -+ r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */ -+ r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */ -+ r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ -+ dsi_write_reg(DSI_TIMING2, r); -+ -+ DSSDBG("HS_TX_TO %ld ns (%#x ticks)\n", -+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) / -+ (fck / 1000 / 1000), -+ ticks); -+ -+ return 0; -+} -+static int dsi_proto_config(struct omap_dss_device *dssdev) -+{ -+ u32 r; -+ int buswidth = 0; -+ int div; -+ -+ dsi_config_tx_fifo(DSI_FIFO_SIZE_128, -+ DSI_FIFO_SIZE_0, -+ DSI_FIFO_SIZE_0, -+ DSI_FIFO_SIZE_0); -+ -+ dsi_config_rx_fifo(DSI_FIFO_SIZE_128, -+ DSI_FIFO_SIZE_0, -+ DSI_FIFO_SIZE_0, -+ DSI_FIFO_SIZE_0); -+ -+ /* XXX what values for the timeouts? */ -+ dsi_set_stop_state_counter(1000, 0, 0); -+ -+ dsi_set_ta_timeout(50000, 1, 1); -+ -+ /* 3000ns * 16 */ -+ dsi_set_lp_rx_timeout(3000, 0, 1); -+ -+ /* 10000ns * 4 */ -+ dsi_set_hs_tx_timeout(10000, 1, 0); -+ -+ switch (dssdev->ctrl.pixel_size) { -+ case 16: -+ buswidth = 0; -+ break; -+ case 18: -+ buswidth = 1; -+ break; -+ case 24: -+ buswidth = 2; -+ break; -+ default: -+ BUG(); -+ } -+ -+ r = dsi_read_reg(DSI_CTRL); -+ r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ -+ r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ -+ r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ -+ -+ div = dispc_lclk_rate() / dispc_pclk_rate(); -+ r = FLD_MOD(r, div == 2 ? 0 : 1, 4, 4); /* VP_CLK_RATIO */ -+ r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ -+ r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ -+ r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */ -+ r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ -+ r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ -+ r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ -+ r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */ -+ -+ dsi_write_reg(DSI_CTRL, r); -+ -+ dsi_vc_initial_config(0); -+ -+ /* set all vc targets to peripheral 0 */ -+ dsi.vc[0].dest_per = 0; -+ dsi.vc[1].dest_per = 0; -+ dsi.vc[2].dest_per = 0; -+ dsi.vc[3].dest_per = 0; -+ -+ return 0; -+} -+ -+static void dsi_proto_timings(struct omap_dss_device *dssdev) -+{ -+ unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; -+ unsigned tclk_pre, tclk_post; -+ unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; -+ unsigned ths_trail, ths_exit; -+ unsigned ddr_clk_pre, ddr_clk_post; -+ unsigned enter_hs_mode_lat, exit_hs_mode_lat; -+ unsigned ths_eot; -+ u32 r; -+ -+ r = dsi_read_reg(DSI_DSIPHY_CFG0); -+ ths_prepare = FLD_GET(r, 31, 24); -+ ths_prepare_ths_zero = FLD_GET(r, 23, 16); -+ ths_zero = ths_prepare_ths_zero - ths_prepare; -+ ths_trail = FLD_GET(r, 15, 8); -+ ths_exit = FLD_GET(r, 7, 0); -+ -+ r = dsi_read_reg(DSI_DSIPHY_CFG1); -+ tlpx = FLD_GET(r, 22, 16) * 2; -+ tclk_trail = FLD_GET(r, 15, 8); -+ tclk_zero = FLD_GET(r, 7, 0); -+ -+ r = dsi_read_reg(DSI_DSIPHY_CFG2); -+ tclk_prepare = FLD_GET(r, 7, 0); -+ -+ /* min 8*UI */ -+ tclk_pre = 20; -+ /* min 60ns + 52*UI */ -+ tclk_post = ns2ddr(60) + 26; -+ -+ /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */ -+ if (dssdev->phy.dsi.data1_lane != 0 && -+ dssdev->phy.dsi.data2_lane != 0) -+ ths_eot = 2; -+ else -+ ths_eot = 4; -+ -+ ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, -+ 4); -+ ddr_clk_post = DIV_ROUND_UP(tclk_post + tclk_trail, 4) + ths_eot; -+ -+ BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); -+ BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); -+ -+ r = dsi_read_reg(DSI_CLK_TIMING); -+ r = FLD_MOD(r, ddr_clk_pre, 15, 8); -+ r = FLD_MOD(r, ddr_clk_post, 7, 0); -+ dsi_write_reg(DSI_CLK_TIMING, r); -+ -+ DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", -+ ddr_clk_pre, -+ ddr_clk_post); -+ -+ enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + -+ DIV_ROUND_UP(ths_prepare, 4) + -+ DIV_ROUND_UP(ths_zero + 3, 4); -+ -+ exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; -+ -+ r = FLD_VAL(enter_hs_mode_lat, 31, 16) | -+ FLD_VAL(exit_hs_mode_lat, 15, 0); -+ dsi_write_reg(DSI_VM_TIMING7, r); -+ -+ DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", -+ enter_hs_mode_lat, exit_hs_mode_lat); -+} -+ -+ -+#define DSI_DECL_VARS \ -+ int __dsi_cb = 0; u32 __dsi_cv = 0; -+ -+#define DSI_FLUSH(ch) \ -+ if (__dsi_cb > 0) { \ -+ /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \ -+ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \ -+ __dsi_cb = __dsi_cv = 0; \ -+ } -+ -+#define DSI_PUSH(ch, data) \ -+ do { \ -+ __dsi_cv |= (data) << (__dsi_cb * 8); \ -+ /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \ -+ if (++__dsi_cb > 3) \ -+ DSI_FLUSH(ch); \ -+ } while (0) -+ -+static int dsi_update_screen_l4(struct omap_dss_device *dssdev, -+ int x, int y, int w, int h) -+{ -+ /* Note: supports only 24bit colors in 32bit container */ -+ int first = 1; -+ int fifo_stalls = 0; -+ int max_dsi_packet_size; -+ int max_data_per_packet; -+ int max_pixels_per_packet; -+ int pixels_left; -+ int bytespp = dssdev->ctrl.pixel_size / 8; -+ int scr_width; -+ u32 __iomem *data; -+ int start_offset; -+ int horiz_inc; -+ int current_x; -+ struct omap_overlay *ovl; -+ -+ debug_irq = 0; -+ -+ DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n", -+ x, y, w, h); -+ -+ ovl = dssdev->manager->overlays[0]; -+ -+ if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U) -+ return -EINVAL; -+ -+ if (dssdev->ctrl.pixel_size != 24) -+ return -EINVAL; -+ -+ scr_width = ovl->info.screen_width; -+ data = ovl->info.vaddr; -+ -+ start_offset = scr_width * y + x; -+ horiz_inc = scr_width - w; -+ current_x = x; -+ -+ /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes -+ * in fifo */ -+ -+ /* When using CPU, max long packet size is TX buffer size */ -+ max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4; -+ -+ /* we seem to get better perf if we divide the tx fifo to half, -+ and while the other half is being sent, we fill the other half -+ max_dsi_packet_size /= 2; */ -+ -+ max_data_per_packet = max_dsi_packet_size - 4 - 1; -+ -+ max_pixels_per_packet = max_data_per_packet / bytespp; -+ -+ DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet); -+ -+ pixels_left = w * h; -+ -+ DSSDBG("total pixels %d\n", pixels_left); -+ -+ data += start_offset; -+ -+ while (pixels_left > 0) { -+ /* 0x2c = write_memory_start */ -+ /* 0x3c = write_memory_continue */ -+ u8 dcs_cmd = first ? 0x2c : 0x3c; -+ int pixels; -+ DSI_DECL_VARS; -+ first = 0; -+ -+#if 1 -+ /* using fifo not empty */ -+ /* TX_FIFO_NOT_EMPTY */ -+ while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) { -+ udelay(1); -+ fifo_stalls++; -+ if (fifo_stalls > 0xfffff) { -+ DSSERR("fifo stalls overflow, pixels left %d\n", -+ pixels_left); -+ dsi_if_enable(0); -+ return -EIO; -+ } -+ } -+#elif 1 -+ /* using fifo emptiness */ -+ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 < -+ max_dsi_packet_size) { -+ fifo_stalls++; -+ if (fifo_stalls > 0xfffff) { -+ DSSERR("fifo stalls overflow, pixels left %d\n", -+ pixels_left); -+ dsi_if_enable(0); -+ return -EIO; -+ } -+ } -+#else -+ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) { -+ fifo_stalls++; -+ if (fifo_stalls > 0xfffff) { -+ DSSERR("fifo stalls overflow, pixels left %d\n", -+ pixels_left); -+ dsi_if_enable(0); -+ return -EIO; -+ } -+ } -+#endif -+ pixels = min(max_pixels_per_packet, pixels_left); -+ -+ pixels_left -= pixels; -+ -+ dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE, -+ 1 + pixels * bytespp, 0); -+ -+ DSI_PUSH(0, dcs_cmd); -+ -+ while (pixels-- > 0) { -+ u32 pix = __raw_readl(data++); -+ -+ DSI_PUSH(0, (pix >> 16) & 0xff); -+ DSI_PUSH(0, (pix >> 8) & 0xff); -+ DSI_PUSH(0, (pix >> 0) & 0xff); -+ -+ current_x++; -+ if (current_x == x+w) { -+ current_x = x; -+ data += horiz_inc; -+ } -+ } -+ -+ DSI_FLUSH(0); -+ } -+ -+ return 0; -+} -+ -+static void dsi_update_screen_dispc(struct omap_dss_device *dssdev, -+ u16 x, u16 y, u16 w, u16 h) -+{ -+ int bytespp = dssdev->ctrl.pixel_size / 8; -+ int len; -+ int total_len; -+ int packet_payload; -+ int packet_len; -+ u32 l; -+ bool use_te_trigger; -+ const int channel = 0; -+ -+ use_te_trigger = dsi.te_enabled && !dsi.use_ext_te; -+ -+ if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO) -+ DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n", -+ x, y, w, h); -+ -+ len = w * h * bytespp; -+ -+ /* XXX: one packet could be longer, I think? Line buffer is -+ * 1024 x 24bits, but we have to put DCS cmd there also. -+ * 1023 * 3 should work, but causes strange color effects. */ -+ packet_payload = min(w, (u16)1020) * bytespp; -+ -+ packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ -+ total_len = (len / packet_payload) * packet_len; -+ -+ if (len % packet_payload) -+ total_len += (len % packet_payload) + 1; -+ -+ if (0) -+ dsi_vc_print_status(1); -+ -+ l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ -+ dsi_write_reg(DSI_VC_TE(channel), l); -+ -+ dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0); -+ -+ if (use_te_trigger) -+ l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ -+ else -+ l = FLD_MOD(l, 1, 31, 31); /* TE_START */ -+ dsi_write_reg(DSI_VC_TE(channel), l); -+ -+ /* We put SIDLEMODE to no-idle for the duration of the transfer, -+ * because DSS interrupts are not capable of waking up the CPU and the -+ * framedone interrupt could be delayed for quite a long time. I think -+ * the same goes for any DSS interrupts, but for some reason I have not -+ * seen the problem anywhere else than here. -+ */ -+ dispc_disable_sidle(); -+ -+ dss_start_update(dssdev); -+ -+ if (use_te_trigger) { -+ /* disable LP_RX_TO, so that we can receive TE. Time to wait -+ * for TE is longer than the timer allows */ -+ REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ -+ -+ dsi_vc_send_bta(channel); -+ } -+} -+ -+static void dsi_framedone_irq_callback(void *data, u32 mask) -+{ -+ /* Note: We get FRAMEDONE when DISPC has finished sending pixels and -+ * turns itself off. However, DSI still has the pixels in its buffers, -+ * and is sending the data. -+ */ -+ -+ /* SIDLEMODE back to smart-idle */ -+ dispc_enable_sidle(); -+ -+ dsi.framedone_received = true; -+ wake_up(&dsi.waitqueue); -+} -+ -+static void dsi_set_update_region(struct omap_dss_device *dssdev, -+ u16 x, u16 y, u16 w, u16 h) -+{ -+ spin_lock(&dsi.update_lock); -+ if (dsi.update_region.dirty) { -+ dsi.update_region.x = min(x, dsi.update_region.x); -+ dsi.update_region.y = min(y, dsi.update_region.y); -+ dsi.update_region.w = max(w, dsi.update_region.w); -+ dsi.update_region.h = max(h, dsi.update_region.h); -+ } else { -+ dsi.update_region.x = x; -+ dsi.update_region.y = y; -+ dsi.update_region.w = w; -+ dsi.update_region.h = h; -+ } -+ -+ dsi.update_region.device = dssdev; -+ dsi.update_region.dirty = true; -+ -+ spin_unlock(&dsi.update_lock); -+ -+} -+ -+static void dsi_start_auto_update(struct omap_dss_device *dssdev) -+{ -+ u16 w, h; -+ int i; -+ -+ DSSDBG("starting auto update\n"); -+ -+ /* In automatic mode the overlay settings are applied like on DPI/SDI. -+ * Mark the overlays dirty, so that we get the overlays configured, as -+ * manual mode has left them in bad shape after config partia planes */ -+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) { -+ struct omap_overlay *ovl; -+ ovl = omap_dss_get_overlay(i); -+ if (ovl->manager == dssdev->manager) -+ ovl->info_dirty = true; -+ } -+ dssdev->manager->apply(dssdev->manager); -+ -+ dssdev->get_resolution(dssdev, &w, &h); -+ -+ dsi_set_update_region(dssdev, 0, 0, w, h); -+ -+ dsi_perf_mark_start_auto(); -+ -+ wake_up(&dsi.waitqueue); -+} -+ -+static int dsi_set_te(struct omap_dss_device *dssdev, bool enable) -+{ -+ int r; -+ r = dssdev->driver->enable_te(dssdev, enable); -+ /* XXX for some reason, DSI TE breaks if we don't wait here. -+ * Panel bug? Needs more studying */ -+ msleep(100); -+ return r; -+} -+ -+static void dsi_handle_framedone(void) -+{ -+ int r; -+ const int channel = 0; -+ bool use_te_trigger; -+ -+ use_te_trigger = dsi.te_enabled && !dsi.use_ext_te; -+ -+ if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO) -+ DSSDBG("FRAMEDONE\n"); -+ -+ if (use_te_trigger) { -+ /* enable LP_RX_TO again after the TE */ -+ REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ -+ } -+ -+ /* Send BTA after the frame. We need this for the TE to work, as TE -+ * trigger is only sent for BTAs without preceding packet. Thus we need -+ * to BTA after the pixel packets so that next BTA will cause TE -+ * trigger. -+ * -+ * This is not needed when TE is not in use, but we do it anyway to -+ * make sure that the transfer has been completed. It would be more -+ * optimal, but more complex, to wait only just before starting next -+ * transfer. */ -+ r = dsi_vc_send_bta_sync(channel); -+ if (r) -+ DSSERR("BTA after framedone failed\n"); -+ -+#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC -+ dispc_fake_vsync_irq(); -+#endif -+} -+ -+static int dsi_update_thread(void *data) -+{ -+ unsigned long timeout; -+ struct omap_dss_device *device; -+ u16 x, y, w, h; -+ -+ while (1) { -+ bool sched; -+ -+ wait_event_interruptible(dsi.waitqueue, -+ dsi.update_mode == OMAP_DSS_UPDATE_AUTO || -+ (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL && -+ dsi.update_region.dirty == true) || -+ kthread_should_stop()); -+ -+ if (kthread_should_stop()) -+ break; -+ -+ dsi_bus_lock(); -+ -+ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED || -+ kthread_should_stop()) { -+ dsi_bus_unlock(); -+ break; -+ } -+ -+ dsi_perf_mark_setup(); -+ -+ if (dsi.update_region.dirty) { -+ spin_lock(&dsi.update_lock); -+ dsi.active_update_region = dsi.update_region; -+ dsi.update_region.dirty = false; -+ spin_unlock(&dsi.update_lock); -+ } -+ -+ device = dsi.active_update_region.device; -+ x = dsi.active_update_region.x; -+ y = dsi.active_update_region.y; -+ w = dsi.active_update_region.w; -+ h = dsi.active_update_region.h; -+ -+ if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { -+ -+ if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL) { -+ dss_setup_partial_planes(device, -+ &x, &y, &w, &h); -+#if 1 -+ /* XXX there seems to be a bug in this driver -+ * or OMAP hardware. Some updates with certain -+ * widths and x coordinates fail. These widths -+ * are always odd, so "fix" it here for now */ -+ if (w & 1) { -+ u16 dw, dh; -+ device->get_resolution(device, -+ &dw, &dh); -+ if (x + w == dw) -+ x &= ~1; -+ ++w; -+ -+ dss_setup_partial_planes(device, -+ &x, &y, &w, &h); -+ } -+#endif -+ } -+ -+ dispc_set_lcd_size(w, h); -+ } -+ -+ if (dsi.active_update_region.dirty) { -+ dsi.active_update_region.dirty = false; -+ /* XXX TODO we don't need to send the coords, if they -+ * are the same that are already programmed to the -+ * panel. That should speed up manual update a bit */ -+ device->driver->setup_update(device, x, y, w, h); -+ } -+ -+ dsi_perf_mark_start(); -+ -+ if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { -+ dsi_vc_config_vp(0); -+ -+ if (dsi.te_enabled && dsi.use_ext_te) -+ device->driver->wait_for_te(device); -+ -+ dsi.framedone_received = false; -+ -+ dsi_update_screen_dispc(device, x, y, w, h); -+ -+ /* wait for framedone */ -+ timeout = msecs_to_jiffies(1000); -+ timeout = wait_event_timeout(dsi.waitqueue, -+ dsi.framedone_received == true, -+ timeout); -+ -+ if (timeout == 0) { -+ DSSERR("framedone timeout\n"); -+ DSSERR("failed update %d,%d %dx%d\n", -+ x, y, w, h); -+ -+ dispc_enable_sidle(); -+ dispc_enable_lcd_out(0); -+ } else { -+ dsi_handle_framedone(); -+ dsi_perf_show("DISPC"); -+ } -+ } else { -+ dsi_update_screen_l4(device, x, y, w, h); -+ dsi_perf_show("L4"); -+ } -+ -+ sched = atomic_read(&dsi.bus_lock.count) < 0; -+ -+ complete_all(&dsi.update_completion); -+ -+ dsi_bus_unlock(); -+ -+ /* XXX We need to give others chance to get the bus lock. Is -+ * there a better way for this? */ -+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO && sched) -+ schedule_timeout_interruptible(1); -+ } -+ -+ DSSDBG("update thread exiting\n"); -+ -+ return 0; -+} -+ -+ -+ -+/* Display funcs */ -+ -+static int dsi_display_init_dispc(struct omap_dss_device *dssdev) -+{ -+ int r; -+ -+ r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL, -+ DISPC_IRQ_FRAMEDONE); -+ if (r) { -+ DSSERR("can't get FRAMEDONE irq\n"); -+ return r; -+ } -+ -+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT); -+ -+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI); -+ dispc_enable_fifohandcheck(1); -+ -+ dispc_set_tft_data_lines(dssdev->ctrl.pixel_size); -+ -+ { -+ struct omap_video_timings timings = { -+ .hsw = 1, -+ .hfp = 1, -+ .hbp = 1, -+ .vsw = 1, -+ .vfp = 0, -+ .vbp = 0, -+ }; -+ -+ dispc_set_lcd_timings(&timings); -+ } -+ -+ return 0; -+} -+ -+static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev) -+{ -+ omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL, -+ DISPC_IRQ_FRAMEDONE); -+} -+ -+static int dsi_display_init_dsi(struct omap_dss_device *dssdev) -+{ -+ struct dsi_clock_info cinfo; -+ int r; -+ -+ _dsi_print_reset_status(); -+ -+ r = dsi_pll_init(1, 0); -+ if (r) -+ goto err0; -+ -+ r = dsi_pll_calc_ddrfreq(dssdev->phy.dsi.ddr_clk_hz, &cinfo); -+ if (r) -+ goto err1; -+ -+ r = dsi_pll_program(&cinfo); -+ if (r) -+ goto err1; -+ -+ DSSDBG("PLL OK\n"); -+ -+ r = dsi_complexio_init(dssdev); -+ if (r) -+ goto err1; -+ -+ _dsi_print_reset_status(); -+ -+ dsi_proto_timings(dssdev); -+ dsi_set_lp_clk_divisor(dssdev); -+ -+ if (1) -+ _dsi_print_reset_status(); -+ -+ r = dsi_proto_config(dssdev); -+ if (r) -+ goto err2; -+ -+ /* enable interface */ -+ dsi_vc_enable(0, 1); -+ dsi_if_enable(1); -+ dsi_force_tx_stop_mode_io(); -+ -+ if (dssdev->driver->enable) { -+ r = dssdev->driver->enable(dssdev); -+ if (r) -+ goto err3; -+ } -+ -+ /* enable high-speed after initial config */ -+ dsi_vc_enable_hs(0, 1); -+ -+ return 0; -+err3: -+ dsi_if_enable(0); -+err2: -+ dsi_complexio_uninit(); -+err1: -+ dsi_pll_uninit(); -+err0: -+ return r; -+} -+ -+static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->driver->disable) -+ dssdev->driver->disable(dssdev); -+ -+ dsi_complexio_uninit(); -+ dsi_pll_uninit(); -+} -+ -+static int dsi_core_init(void) -+{ -+ /* Autoidle */ -+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0); -+ -+ /* ENWAKEUP */ -+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2); -+ -+ /* SIDLEMODE smart-idle */ -+ REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3); -+ -+ _dsi_initialize_irq(); -+ -+ return 0; -+} -+ -+static int dsi_display_enable(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ DSSDBG("dsi_display_enable\n"); -+ -+ mutex_lock(&dsi.lock); -+ dsi_bus_lock(); -+ -+ r = omap_dss_start_device(dssdev); -+ if (r) { -+ DSSERR("failed to start device\n"); -+ goto err0; -+ } -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { -+ DSSERR("dssdev already enabled\n"); -+ r = -EINVAL; -+ goto err1; -+ } -+ -+ enable_clocks(1); -+ dsi_enable_pll_clock(1); -+ -+ r = _dsi_reset(); -+ if (r) -+ goto err2; -+ -+ dsi_core_init(); -+ -+ r = dsi_display_init_dispc(dssdev); -+ if (r) -+ goto err2; -+ -+ r = dsi_display_init_dsi(dssdev); -+ if (r) -+ goto err3; -+ -+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -+ -+ dsi.use_ext_te = dssdev->phy.dsi.ext_te; -+ r = dsi_set_te(dssdev, dsi.te_enabled); -+ if (r) -+ goto err3; -+ -+ dsi.update_mode = dsi.user_update_mode; -+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) -+ dsi_start_auto_update(dssdev); -+ -+ dsi_bus_unlock(); -+ mutex_unlock(&dsi.lock); -+ -+ return 0; -+ -+err3: -+ dsi_display_uninit_dispc(dssdev); -+err2: -+ enable_clocks(0); -+ dsi_enable_pll_clock(0); -+err1: -+ omap_dss_stop_device(dssdev); -+err0: -+ dsi_bus_unlock(); -+ mutex_unlock(&dsi.lock); -+ DSSDBG("dsi_display_enable FAILED\n"); -+ return r; -+} -+ -+static void dsi_display_disable(struct omap_dss_device *dssdev) -+{ -+ DSSDBG("dsi_display_disable\n"); -+ -+ mutex_lock(&dsi.lock); -+ dsi_bus_lock(); -+ -+ if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED || -+ dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) -+ goto end; -+ -+ dsi.update_mode = OMAP_DSS_UPDATE_DISABLED; -+ dssdev->state = OMAP_DSS_DISPLAY_DISABLED; -+ -+ dsi_display_uninit_dispc(dssdev); -+ -+ dsi_display_uninit_dsi(dssdev); -+ -+ enable_clocks(0); -+ dsi_enable_pll_clock(0); -+ -+ omap_dss_stop_device(dssdev); -+end: -+ dsi_bus_unlock(); -+ mutex_unlock(&dsi.lock); -+} -+ -+static int dsi_display_suspend(struct omap_dss_device *dssdev) -+{ -+ DSSDBG("dsi_display_suspend\n"); -+ -+ mutex_lock(&dsi.lock); -+ dsi_bus_lock(); -+ -+ if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED || -+ dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) -+ goto end; -+ -+ dsi.update_mode = OMAP_DSS_UPDATE_DISABLED; -+ dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; -+ -+ dsi_display_uninit_dispc(dssdev); -+ -+ dsi_display_uninit_dsi(dssdev); -+ -+ enable_clocks(0); -+ dsi_enable_pll_clock(0); -+end: -+ dsi_bus_unlock(); -+ mutex_unlock(&dsi.lock); -+ -+ return 0; -+} -+ -+static int dsi_display_resume(struct omap_dss_device *dssdev) -+{ -+ int r; -+ -+ DSSDBG("dsi_display_resume\n"); -+ -+ mutex_lock(&dsi.lock); -+ dsi_bus_lock(); -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) { -+ DSSERR("dssdev not suspended\n"); -+ r = -EINVAL; -+ goto err0; -+ } -+ -+ enable_clocks(1); -+ dsi_enable_pll_clock(1); -+ -+ r = _dsi_reset(); -+ if (r) -+ goto err1; -+ -+ dsi_core_init(); -+ -+ r = dsi_display_init_dispc(dssdev); -+ if (r) -+ goto err1; -+ -+ r = dsi_display_init_dsi(dssdev); -+ if (r) -+ goto err2; -+ -+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -+ -+ r = dsi_set_te(dssdev, dsi.te_enabled); -+ if (r) -+ goto err2; -+ -+ dsi.update_mode = dsi.user_update_mode; -+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) -+ dsi_start_auto_update(dssdev); -+ -+ dsi_bus_unlock(); -+ mutex_unlock(&dsi.lock); -+ -+ return 0; -+ -+err2: -+ dsi_display_uninit_dispc(dssdev); -+err1: -+ enable_clocks(0); -+ dsi_enable_pll_clock(0); -+err0: -+ dsi_bus_unlock(); -+ mutex_unlock(&dsi.lock); -+ DSSDBG("dsi_display_resume FAILED\n"); -+ return r; -+} -+ -+static int dsi_display_update(struct omap_dss_device *dssdev, -+ u16 x, u16 y, u16 w, u16 h) -+{ -+ int r = 0; -+ u16 dw, dh; -+ -+ DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x, y, w, h); -+ -+ mutex_lock(&dsi.lock); -+ -+ if (dsi.update_mode != OMAP_DSS_UPDATE_MANUAL) -+ goto end; -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) -+ goto end; -+ -+ dssdev->get_resolution(dssdev, &dw, &dh); -+ -+ if (x > dw || y > dh) -+ goto end; -+ -+ if (x + w > dw) -+ w = dw - x; -+ -+ if (y + h > dh) -+ h = dh - y; -+ -+ if (w == 0 || h == 0) -+ goto end; -+ -+ dsi_set_update_region(dssdev, x, y, w, h); -+ -+ wake_up(&dsi.waitqueue); -+ -+end: -+ mutex_unlock(&dsi.lock); -+ -+ return r; -+} -+ -+static int dsi_display_sync(struct omap_dss_device *dssdev) -+{ -+ bool wait; -+ -+ DSSDBG("dsi_display_sync()\n"); -+ -+ mutex_lock(&dsi.lock); -+ dsi_bus_lock(); -+ -+ if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL && -+ dsi.update_region.dirty) { -+ INIT_COMPLETION(dsi.update_completion); -+ wait = true; -+ } else { -+ wait = false; -+ } -+ -+ dsi_bus_unlock(); -+ mutex_unlock(&dsi.lock); -+ -+ if (wait) -+ wait_for_completion_interruptible(&dsi.update_completion); -+ -+ DSSDBG("dsi_display_sync() done\n"); -+ return 0; -+} -+ -+static int dsi_display_set_update_mode(struct omap_dss_device *dssdev, -+ enum omap_dss_update_mode mode) -+{ -+ DSSDBGF("%d", mode); -+ -+ mutex_lock(&dsi.lock); -+ dsi_bus_lock(); -+ -+ if (dsi.update_mode != mode) { -+ dsi.user_update_mode = mode; -+ dsi.update_mode = mode; -+ -+ if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE && -+ mode == OMAP_DSS_UPDATE_AUTO) -+ dsi_start_auto_update(dssdev); -+ } -+ -+ dsi_bus_unlock(); -+ mutex_unlock(&dsi.lock); -+ -+ return 0; -+} -+ -+static enum omap_dss_update_mode dsi_display_get_update_mode( -+ struct omap_dss_device *dssdev) -+{ -+ return dsi.update_mode; -+} -+ -+ -+static int dsi_display_enable_te(struct omap_dss_device *dssdev, bool enable) -+{ -+ int r = 0; -+ -+ DSSDBGF("%d", enable); -+ -+ if (!dssdev->driver->enable_te) -+ return -ENOENT; -+ -+ dsi_bus_lock(); -+ -+ dsi.te_enabled = enable; -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) -+ goto end; -+ -+ r = dsi_set_te(dssdev, enable); -+end: -+ dsi_bus_unlock(); -+ -+ return r; -+} -+ -+static int dsi_display_get_te(struct omap_dss_device *dssdev) -+{ -+ return dsi.te_enabled; -+} -+ -+static int dsi_display_set_rotate(struct omap_dss_device *dssdev, u8 rotate) -+{ -+ -+ DSSDBGF("%d", rotate); -+ -+ if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate) -+ return -EINVAL; -+ -+ dsi_bus_lock(); -+ dssdev->driver->set_rotate(dssdev, rotate); -+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) { -+ u16 w, h; -+ /* the display dimensions may have changed, so set a new -+ * update region */ -+ dssdev->get_resolution(dssdev, &w, &h); -+ dsi_set_update_region(dssdev, 0, 0, w, h); -+ } -+ dsi_bus_unlock(); -+ -+ return 0; -+} -+ -+static u8 dsi_display_get_rotate(struct omap_dss_device *dssdev) -+{ -+ if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate) -+ return 0; -+ -+ return dssdev->driver->get_rotate(dssdev); -+} -+ -+static int dsi_display_set_mirror(struct omap_dss_device *dssdev, bool mirror) -+{ -+ DSSDBGF("%d", mirror); -+ -+ if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror) -+ return -EINVAL; -+ -+ dsi_bus_lock(); -+ dssdev->driver->set_mirror(dssdev, mirror); -+ dsi_bus_unlock(); -+ -+ return 0; -+} -+ -+static bool dsi_display_get_mirror(struct omap_dss_device *dssdev) -+{ -+ if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror) -+ return 0; -+ -+ return dssdev->driver->get_mirror(dssdev); -+} -+ -+static int dsi_display_run_test(struct omap_dss_device *dssdev, int test_num) -+{ -+ int r; -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) -+ return -EIO; -+ -+ DSSDBGF("%d", test_num); -+ -+ dsi_bus_lock(); -+ -+ /* run test first in low speed mode */ -+ dsi_vc_enable_hs(0, 0); -+ -+ if (dssdev->driver->run_test) { -+ r = dssdev->driver->run_test(dssdev, test_num); -+ if (r) -+ goto end; -+ } -+ -+ /* then in high speed */ -+ dsi_vc_enable_hs(0, 1); -+ -+ if (dssdev->driver->run_test) { -+ r = dssdev->driver->run_test(dssdev, test_num); -+ if (r) -+ goto end; -+ } -+ -+end: -+ dsi_vc_enable_hs(0, 1); -+ -+ dsi_bus_unlock(); -+ -+ return r; -+} -+ -+static int dsi_display_memory_read(struct omap_dss_device *dssdev, -+ void *buf, size_t size, -+ u16 x, u16 y, u16 w, u16 h) -+{ -+ int r; -+ -+ DSSDBGF(""); -+ -+ if (!dssdev->driver->memory_read) -+ return -EINVAL; -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) -+ return -EIO; -+ -+ dsi_bus_lock(); -+ -+ r = dssdev->driver->memory_read(dssdev, buf, size, -+ x, y, w, h); -+ -+ dsi_bus_unlock(); -+ -+ return r; -+} -+ -+void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, -+ u32 fifo_size, enum omap_burst_size *burst_size, -+ u32 *fifo_low, u32 *fifo_high) -+{ -+ unsigned burst_size_bytes; -+ -+ *burst_size = OMAP_DSS_BURST_16x32; -+ burst_size_bytes = 16 * 32 / 8; -+ -+ *fifo_high = fifo_size - burst_size_bytes; -+ *fifo_low = 0; -+} -+ -+int dsi_init_display(struct omap_dss_device *dssdev) -+{ -+ DSSDBG("DSI init\n"); -+ -+ dssdev->enable = dsi_display_enable; -+ dssdev->disable = dsi_display_disable; -+ dssdev->suspend = dsi_display_suspend; -+ dssdev->resume = dsi_display_resume; -+ dssdev->update = dsi_display_update; -+ dssdev->sync = dsi_display_sync; -+ dssdev->set_update_mode = dsi_display_set_update_mode; -+ dssdev->get_update_mode = dsi_display_get_update_mode; -+ dssdev->enable_te = dsi_display_enable_te; -+ dssdev->get_te = dsi_display_get_te; -+ -+ dssdev->get_rotate = dsi_display_get_rotate; -+ dssdev->set_rotate = dsi_display_set_rotate; -+ -+ dssdev->get_mirror = dsi_display_get_mirror; -+ dssdev->set_mirror = dsi_display_set_mirror; -+ -+ dssdev->run_test = dsi_display_run_test; -+ dssdev->memory_read = dsi_display_memory_read; -+ -+ dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE; -+ -+ dsi.vc[0].dssdev = dssdev; -+ dsi.vc[1].dssdev = dssdev; -+ -+ return 0; -+} -+ -+int dsi_init(struct platform_device *pdev) -+{ -+ u32 rev; -+ struct sched_param param = { -+ .sched_priority = MAX_USER_RT_PRIO-1 -+ }; -+ -+ spin_lock_init(&dsi.errors_lock); -+ dsi.errors = 0; -+ -+ /* XXX fail properly */ -+ -+ init_completion(&dsi.bta_completion); -+ init_completion(&dsi.update_completion); -+ -+ dsi.thread = kthread_create(dsi_update_thread, NULL, "dsi"); -+ if (IS_ERR(dsi.thread)) { -+ DSSERR("cannot create kthread\n"); -+ return PTR_ERR(dsi.thread); -+ } -+ sched_setscheduler(dsi.thread, SCHED_FIFO, ¶m); -+ -+ init_waitqueue_head(&dsi.waitqueue); -+ spin_lock_init(&dsi.update_lock); -+ -+ mutex_init(&dsi.lock); -+ mutex_init(&dsi.bus_lock); -+ -+ dsi.update_mode = OMAP_DSS_UPDATE_DISABLED; -+ dsi.user_update_mode = OMAP_DSS_UPDATE_DISABLED; -+ -+ dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS); -+ if (!dsi.base) { -+ DSSERR("can't ioremap DSI\n"); -+ return -ENOMEM; -+ } -+ -+ dsi.vdds_dsi_reg = regulator_get(&pdev->dev, "vdds_dsi"); -+ if (IS_ERR(dsi.vdds_dsi_reg)) { -+ iounmap(dsi.base); -+ DSSERR("can't get VDDS_DSI regulator\n"); -+ return PTR_ERR(dsi.vdds_dsi_reg); -+ } -+ -+ enable_clocks(1); -+ -+ rev = dsi_read_reg(DSI_REVISION); -+ printk(KERN_INFO "OMAP DSI rev %d.%d\n", -+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); -+ -+ enable_clocks(0); -+ -+ wake_up_process(dsi.thread); -+ -+ return 0; -+} -+ -+void dsi_exit(void) -+{ -+ kthread_stop(dsi.thread); -+ -+ regulator_put(dsi.vdds_dsi_reg); -+ -+ iounmap(dsi.base); -+ -+ DSSDBG("omap_dsi_exit\n"); -+} -+ ---- /dev/null -+++ b/drivers/video/omap2/dss/dss.c -@@ -0,0 +1,347 @@ -+/* -+ * linux/drivers/video/omap2/dss/dss.c -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#define DSS_SUBSYS_NAME "DSS" -+ -+#include <linux/kernel.h> -+#include <linux/io.h> -+#include <linux/err.h> -+#include <linux/delay.h> -+#include <linux/interrupt.h> -+#include <linux/seq_file.h> -+ -+#include <mach/display.h> -+#include "dss.h" -+ -+#define DSS_BASE 0x48050000 -+ -+#define DSS_SZ_REGS SZ_512 -+ -+struct dss_reg { -+ u16 idx; -+}; -+ -+#define DSS_REG(idx) ((const struct dss_reg) { idx }) -+ -+#define DSS_REVISION DSS_REG(0x0000) -+#define DSS_SYSCONFIG DSS_REG(0x0010) -+#define DSS_SYSSTATUS DSS_REG(0x0014) -+#define DSS_IRQSTATUS DSS_REG(0x0018) -+#define DSS_CONTROL DSS_REG(0x0040) -+#define DSS_SDI_CONTROL DSS_REG(0x0044) -+#define DSS_PLL_CONTROL DSS_REG(0x0048) -+#define DSS_SDI_STATUS DSS_REG(0x005C) -+ -+#define REG_GET(idx, start, end) \ -+ FLD_GET(dss_read_reg(idx), start, end) -+ -+#define REG_FLD_MOD(idx, val, start, end) \ -+ dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) -+ -+static struct { -+ void __iomem *base; -+ -+ u32 ctx[DSS_SZ_REGS / sizeof(u32)]; -+} dss; -+ -+static int _omap_dss_wait_reset(void); -+ -+static inline void dss_write_reg(const struct dss_reg idx, u32 val) -+{ -+ __raw_writel(val, dss.base + idx.idx); -+} -+ -+static inline u32 dss_read_reg(const struct dss_reg idx) -+{ -+ return __raw_readl(dss.base + idx.idx); -+} -+ -+#define SR(reg) \ -+ dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) -+#define RR(reg) \ -+ dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) -+ -+void dss_save_context(void) -+{ -+ if (cpu_is_omap24xx()) -+ return; -+ -+ SR(SYSCONFIG); -+ SR(CONTROL); -+ -+#ifdef CONFIG_OMAP2_DSS_SDI -+ SR(SDI_CONTROL); -+ SR(PLL_CONTROL); -+#endif -+} -+ -+void dss_restore_context(void) -+{ -+ if (_omap_dss_wait_reset()) -+ DSSERR("DSS not coming out of reset after sleep\n"); -+ -+ RR(SYSCONFIG); -+ RR(CONTROL); -+ -+#ifdef CONFIG_OMAP2_DSS_SDI -+ RR(SDI_CONTROL); -+ RR(PLL_CONTROL); -+#endif -+} -+ -+#undef SR -+#undef RR -+ -+void dss_sdi_init(u8 datapairs) -+{ -+ u32 l; -+ -+ BUG_ON(datapairs > 3 || datapairs < 1); -+ -+ l = dss_read_reg(DSS_SDI_CONTROL); -+ l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ -+ l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ -+ l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ -+ dss_write_reg(DSS_SDI_CONTROL, l); -+ -+ l = dss_read_reg(DSS_PLL_CONTROL); -+ l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ -+ l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ -+ l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ -+ dss_write_reg(DSS_PLL_CONTROL, l); -+} -+ -+void dss_sdi_enable(void) -+{ -+ dispc_pck_free_enable(1); -+ -+ /* Reset SDI PLL */ -+ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ -+ udelay(1); /* wait 2x PCLK */ -+ -+ /* Lock SDI PLL */ -+ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ -+ -+ /* Waiting for PLL lock request to complete */ -+ while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) -+ ; -+ -+ /* Clearing PLL_GO bit */ -+ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); -+ -+ /* Waiting for PLL to lock */ -+ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) -+ ; -+ -+ dispc_lcd_enable_signal(1); -+ -+ /* Waiting for SDI reset to complete */ -+ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) -+ ; -+} -+ -+void dss_sdi_disable(void) -+{ -+ dispc_lcd_enable_signal(0); -+ -+ dispc_pck_free_enable(0); -+ -+ /* Reset SDI PLL */ -+ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ -+} -+ -+void dss_dump_regs(struct seq_file *s) -+{ -+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) -+ -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ DUMPREG(DSS_REVISION); -+ DUMPREG(DSS_SYSCONFIG); -+ DUMPREG(DSS_SYSSTATUS); -+ DUMPREG(DSS_IRQSTATUS); -+ DUMPREG(DSS_CONTROL); -+ DUMPREG(DSS_SDI_CONTROL); -+ DUMPREG(DSS_PLL_CONTROL); -+ DUMPREG(DSS_SDI_STATUS); -+ -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+#undef DUMPREG -+} -+ -+void dss_select_clk_source(bool dsi, bool dispc) -+{ -+ u32 r; -+ r = dss_read_reg(DSS_CONTROL); -+ r = FLD_MOD(r, dsi, 1, 1); /* DSI_CLK_SWITCH */ -+ r = FLD_MOD(r, dispc, 0, 0); /* DISPC_CLK_SWITCH */ -+ dss_write_reg(DSS_CONTROL, r); -+} -+ -+int dss_get_dsi_clk_source(void) -+{ -+ return FLD_GET(dss_read_reg(DSS_CONTROL), 1, 1); -+} -+ -+int dss_get_dispc_clk_source(void) -+{ -+ return FLD_GET(dss_read_reg(DSS_CONTROL), 0, 0); -+} -+ -+static irqreturn_t dss_irq_handler_omap2(int irq, void *arg) -+{ -+ dispc_irq_handler(); -+ -+ return IRQ_HANDLED; -+} -+ -+static irqreturn_t dss_irq_handler_omap3(int irq, void *arg) -+{ -+ u32 irqstatus; -+ -+ irqstatus = dss_read_reg(DSS_IRQSTATUS); -+ -+ if (irqstatus & (1<<0)) /* DISPC_IRQ */ -+ dispc_irq_handler(); -+#ifdef CONFIG_OMAP2_DSS_DSI -+ if (irqstatus & (1<<1)) /* DSI_IRQ */ -+ dsi_irq_handler(); -+#endif -+ -+ return IRQ_HANDLED; -+} -+ -+static int _omap_dss_wait_reset(void) -+{ -+ unsigned timeout = 1000; -+ -+ while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) { -+ udelay(1); -+ if (!--timeout) { -+ DSSERR("soft reset failed\n"); -+ return -ENODEV; -+ } -+ } -+ -+ return 0; -+} -+ -+static int _omap_dss_reset(void) -+{ -+ /* Soft reset */ -+ REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1); -+ return _omap_dss_wait_reset(); -+} -+ -+void dss_set_venc_output(enum omap_dss_venc_type type) -+{ -+ int l = 0; -+ -+ if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) -+ l = 0; -+ else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) -+ l = 1; -+ else -+ BUG(); -+ -+ /* venc out selection. 0 = comp, 1 = svideo */ -+ REG_FLD_MOD(DSS_CONTROL, l, 6, 6); -+} -+ -+void dss_set_dac_pwrdn_bgz(bool enable) -+{ -+ REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ -+} -+ -+int dss_init(bool skip_init) -+{ -+ int r; -+ u32 rev; -+ -+ dss.base = ioremap(DSS_BASE, DSS_SZ_REGS); -+ if (!dss.base) { -+ DSSERR("can't ioremap DSS\n"); -+ r = -ENOMEM; -+ goto fail0; -+ } -+ -+ if (!skip_init) { -+ /* disable LCD and DIGIT output. This seems to fix the synclost -+ * problem that we get, if the bootloader starts the DSS and -+ * the kernel resets it */ -+ omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); -+ -+ /* We need to wait here a bit, otherwise we sometimes start to -+ * get synclost errors, and after that only power cycle will -+ * restore DSS functionality. I have no idea why this happens. -+ * And we have to wait _before_ resetting the DSS, but after -+ * enabling clocks. -+ */ -+ msleep(50); -+ -+ _omap_dss_reset(); -+ } -+ -+ /* autoidle */ -+ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); -+ -+ /* Select DPLL */ -+ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); -+ -+#ifdef CONFIG_OMAP2_DSS_VENC -+ REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ -+ REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ -+ REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ -+#endif -+ -+ r = request_irq(INT_24XX_DSS_IRQ, -+ cpu_is_omap24xx() -+ ? dss_irq_handler_omap2 -+ : dss_irq_handler_omap3, -+ 0, "OMAP DSS", NULL); -+ -+ if (r < 0) { -+ DSSERR("omap2 dss: request_irq failed\n"); -+ goto fail1; -+ } -+ -+ dss_save_context(); -+ -+ rev = dss_read_reg(DSS_REVISION); -+ printk(KERN_INFO "OMAP DSS rev %d.%d\n", -+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); -+ -+ return 0; -+ -+fail1: -+ iounmap(dss.base); -+fail0: -+ return r; -+} -+ -+void dss_exit(void) -+{ -+ free_irq(INT_24XX_DSS_IRQ, NULL); -+ -+ iounmap(dss.base); -+} -+ ---- /dev/null -+++ b/drivers/video/omap2/dss/dss.h -@@ -0,0 +1,356 @@ -+/* -+ * linux/drivers/video/omap2/dss/dss.h -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#ifndef __OMAP2_DSS_H -+#define __OMAP2_DSS_H -+ -+#ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT -+#define DEBUG -+#endif -+ -+#ifdef DEBUG -+extern unsigned int dss_debug; -+#ifdef DSS_SUBSYS_NAME -+#define DSSDBG(format, ...) \ -+ if (dss_debug) \ -+ printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \ -+ ## __VA_ARGS__) -+#else -+#define DSSDBG(format, ...) \ -+ if (dss_debug) \ -+ printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__) -+#endif -+ -+#ifdef DSS_SUBSYS_NAME -+#define DSSDBGF(format, ...) \ -+ if (dss_debug) \ -+ printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \ -+ ": %s(" format ")\n", \ -+ __func__, \ -+ ## __VA_ARGS__) -+#else -+#define DSSDBGF(format, ...) \ -+ if (dss_debug) \ -+ printk(KERN_DEBUG "omapdss: " \ -+ ": %s(" format ")\n", \ -+ __func__, \ -+ ## __VA_ARGS__) -+#endif -+ -+#else /* DEBUG */ -+#define DSSDBG(format, ...) -+#define DSSDBGF(format, ...) -+#endif -+ -+ -+#ifdef DSS_SUBSYS_NAME -+#define DSSERR(format, ...) \ -+ printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \ -+ ## __VA_ARGS__) -+#else -+#define DSSERR(format, ...) \ -+ printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__) -+#endif -+ -+#ifdef DSS_SUBSYS_NAME -+#define DSSINFO(format, ...) \ -+ printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \ -+ ## __VA_ARGS__) -+#else -+#define DSSINFO(format, ...) \ -+ printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__) -+#endif -+ -+#ifdef DSS_SUBSYS_NAME -+#define DSSWARN(format, ...) \ -+ printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \ -+ ## __VA_ARGS__) -+#else -+#define DSSWARN(format, ...) \ -+ printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__) -+#endif -+ -+/* OMAP TRM gives bitfields as start:end, where start is the higher bit -+ number. For example 7:0 */ -+#define FLD_MASK(start, end) (((1 << (start - end + 1)) - 1) << (end)) -+#define FLD_VAL(val, start, end) (((val) << end) & FLD_MASK(start, end)) -+#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) -+#define FLD_MOD(orig, val, start, end) \ -+ (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) -+ -+#define DISPC_MAX_FCK 173000000 -+ -+enum omap_burst_size { -+ OMAP_DSS_BURST_4x32 = 0, -+ OMAP_DSS_BURST_8x32 = 1, -+ OMAP_DSS_BURST_16x32 = 2, -+}; -+ -+enum omap_parallel_interface_mode { -+ OMAP_DSS_PARALLELMODE_BYPASS, /* MIPI DPI */ -+ OMAP_DSS_PARALLELMODE_RFBI, /* MIPI DBI */ -+ OMAP_DSS_PARALLELMODE_DSI, -+}; -+ -+enum dss_clock { -+ DSS_CLK_ICK = 1 << 0, -+ DSS_CLK_FCK1 = 1 << 1, -+ DSS_CLK_FCK2 = 1 << 2, -+ DSS_CLK_54M = 1 << 3, -+ DSS_CLK_96M = 1 << 4, -+}; -+ -+struct dispc_clock_info { -+ /* rates that we get with dividers below */ -+ unsigned long fck; -+ unsigned long lck; -+ unsigned long pck; -+ -+ /* dividers */ -+ u16 fck_div; -+ u16 lck_div; -+ u16 pck_div; -+}; -+ -+struct dsi_clock_info { -+ /* rates that we get with dividers below */ -+ unsigned long fint; -+ unsigned long dsiphy; -+ unsigned long clkin; -+ unsigned long dsi1_pll_fclk; -+ unsigned long dsi2_pll_fclk; -+ unsigned long lck; -+ unsigned long pck; -+ -+ /* dividers */ -+ u16 regn; -+ u16 regm; -+ u16 regm3; -+ u16 regm4; -+ -+ u16 lck_div; -+ u16 pck_div; -+ -+ u8 highfreq; -+ bool use_dss2_fck; -+}; -+ -+struct seq_file; -+struct platform_device; -+ -+/* core */ -+void dss_clk_enable(enum dss_clock clks); -+void dss_clk_disable(enum dss_clock clks); -+unsigned long dss_clk_get_rate(enum dss_clock clk); -+int dss_need_ctx_restore(void); -+void dss_dump_clocks(struct seq_file *s); -+struct bus_type *dss_get_bus(void); -+ -+/* display */ -+int dss_suspend_all_devices(void); -+int dss_resume_all_devices(void); -+ -+void dss_init_device(struct platform_device *pdev, -+ struct omap_dss_device *dssdev); -+void dss_uninit_device(struct platform_device *pdev, -+ struct omap_dss_device *dssdev); -+bool dss_use_replication(struct omap_dss_device *dssdev, -+ enum omap_color_mode mode); -+void default_get_overlay_fifo_thresholds(enum omap_plane plane, -+ u32 fifo_size, enum omap_burst_size *burst_size, -+ u32 *fifo_low, u32 *fifo_high); -+ -+/* manager */ -+int dss_init_overlay_managers(struct platform_device *pdev); -+void dss_uninit_overlay_managers(struct platform_device *pdev); -+int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl); -+void dss_setup_partial_planes(struct omap_dss_device *dssdev, -+ u16 *x, u16 *y, u16 *w, u16 *h); -+void dss_start_update(struct omap_dss_device *dssdev); -+ -+/* overlay */ -+void dss_init_overlays(struct platform_device *pdev); -+void dss_uninit_overlays(struct platform_device *pdev); -+int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev); -+void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr); -+#ifdef L4_EXAMPLE -+void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr); -+#endif -+void dss_recheck_connections(struct omap_dss_device *dssdev, bool force); -+ -+/* DSS */ -+int dss_init(bool skip_init); -+void dss_exit(void); -+ -+void dss_save_context(void); -+void dss_restore_context(void); -+ -+void dss_dump_regs(struct seq_file *s); -+ -+void dss_sdi_init(u8 datapairs); -+void dss_sdi_enable(void); -+void dss_sdi_disable(void); -+ -+void dss_select_clk_source(bool dsi, bool dispc); -+int dss_get_dsi_clk_source(void); -+int dss_get_dispc_clk_source(void); -+void dss_set_venc_output(enum omap_dss_venc_type type); -+void dss_set_dac_pwrdn_bgz(bool enable); -+ -+/* SDI */ -+int sdi_init(bool skip_init); -+void sdi_exit(void); -+int sdi_init_display(struct omap_dss_device *display); -+ -+/* DSI */ -+int dsi_init(struct platform_device *pdev); -+void dsi_exit(void); -+ -+void dsi_dump_clocks(struct seq_file *s); -+void dsi_dump_regs(struct seq_file *s); -+ -+void dsi_save_context(void); -+void dsi_restore_context(void); -+ -+int dsi_init_display(struct omap_dss_device *display); -+void dsi_irq_handler(void); -+unsigned long dsi_get_dsi1_pll_rate(void); -+unsigned long dsi_get_dsi2_pll_rate(void); -+int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck, -+ struct dsi_clock_info *cinfo); -+int dsi_pll_program(struct dsi_clock_info *cinfo); -+int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv); -+void dsi_pll_uninit(void); -+void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, -+ u32 fifo_size, enum omap_burst_size *burst_size, -+ u32 *fifo_low, u32 *fifo_high); -+ -+/* DPI */ -+int dpi_init(void); -+void dpi_exit(void); -+int dpi_init_display(struct omap_dss_device *dssdev); -+ -+/* DISPC */ -+int dispc_init(void); -+void dispc_exit(void); -+void dispc_dump_clocks(struct seq_file *s); -+void dispc_dump_regs(struct seq_file *s); -+void dispc_irq_handler(void); -+void dispc_fake_vsync_irq(void); -+ -+void dispc_save_context(void); -+void dispc_restore_context(void); -+ -+void dispc_enable_sidle(void); -+void dispc_disable_sidle(void); -+ -+void dispc_lcd_enable_signal_polarity(bool act_high); -+void dispc_lcd_enable_signal(bool enable); -+void dispc_pck_free_enable(bool enable); -+void dispc_enable_fifohandcheck(bool enable); -+ -+void dispc_set_lcd_size(u16 width, u16 height); -+void dispc_set_digit_size(u16 width, u16 height); -+u32 dispc_get_plane_fifo_size(enum omap_plane plane); -+void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high); -+void dispc_enable_fifomerge(bool enable); -+void dispc_set_burst_size(enum omap_plane plane, -+ enum omap_burst_size burst_size); -+ -+void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr); -+void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr); -+void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y); -+void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height); -+void dispc_set_channel_out(enum omap_plane plane, -+ enum omap_channel channel_out); -+ -+int dispc_setup_plane(enum omap_plane plane, -+ u32 paddr, u16 screen_width, -+ u16 pos_x, u16 pos_y, -+ u16 width, u16 height, -+ u16 out_width, u16 out_height, -+ enum omap_color_mode color_mode, -+ bool ilace, -+ enum omap_dss_rotation_type rotation_type, -+ u8 rotation, bool mirror, -+ u8 global_alpha); -+ -+bool dispc_go_busy(enum omap_channel channel); -+void dispc_go(enum omap_channel channel); -+void dispc_enable_lcd_out(bool enable); -+void dispc_enable_digit_out(bool enable); -+int dispc_enable_plane(enum omap_plane plane, bool enable); -+void dispc_enable_replication(enum omap_plane plane, bool enable); -+ -+void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode); -+void dispc_set_tft_data_lines(u8 data_lines); -+void dispc_set_lcd_display_type(enum omap_lcd_display_type type); -+void dispc_set_loadmode(enum omap_dss_load_mode mode); -+ -+void dispc_set_default_color(enum omap_channel channel, u32 color); -+u32 dispc_get_default_color(enum omap_channel channel); -+void dispc_set_trans_key(enum omap_channel ch, -+ enum omap_dss_trans_key_type type, -+ u32 trans_key); -+void dispc_get_trans_key(enum omap_channel ch, -+ enum omap_dss_trans_key_type *type, -+ u32 *trans_key); -+void dispc_enable_trans_key(enum omap_channel ch, bool enable); -+void dispc_enable_alpha_blending(enum omap_channel ch, bool enable); -+bool dispc_trans_key_enabled(enum omap_channel ch); -+bool dispc_alpha_blending_enabled(enum omap_channel ch); -+ -+bool dispc_lcd_timings_ok(struct omap_video_timings *timings); -+void dispc_set_lcd_timings(struct omap_video_timings *timings); -+unsigned long dispc_fclk_rate(void); -+unsigned long dispc_lclk_rate(void); -+unsigned long dispc_pclk_rate(void); -+void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb); -+void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck, -+ u16 *lck_div, u16 *pck_div); -+int dispc_calc_clock_div(bool is_tft, unsigned long req_pck, -+ struct dispc_clock_info *cinfo); -+int dispc_set_clock_div(struct dispc_clock_info *cinfo); -+int dispc_get_clock_div(struct dispc_clock_info *cinfo); -+void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div); -+ -+ -+/* VENC */ -+int venc_init(struct platform_device *pdev); -+void venc_exit(void); -+void venc_dump_regs(struct seq_file *s); -+int venc_init_display(struct omap_dss_device *display); -+ -+/* RFBI */ -+int rfbi_init(void); -+void rfbi_exit(void); -+void rfbi_dump_regs(struct seq_file *s); -+ -+int rfbi_configure(int rfbi_module, int bpp, int lines); -+void rfbi_enable_rfbi(bool enable); -+void rfbi_transfer_area(u16 width, u16 height, -+ void (callback)(void *data), void *data); -+void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t); -+unsigned long rfbi_get_max_tx_rate(void); -+int rfbi_init_display(struct omap_dss_device *display); -+ -+#endif ---- /dev/null -+++ b/drivers/video/omap2/dss/manager.c -@@ -0,0 +1,1487 @@ -+/* -+ * linux/drivers/video/omap2/dss/manager.c -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#define DSS_SUBSYS_NAME "MANAGER" -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/platform_device.h> -+#include <linux/spinlock.h> -+#include <linux/jiffies.h> -+ -+#include <mach/display.h> -+#include <mach/cpu.h> -+ -+#include "dss.h" -+ -+static int num_managers; -+static struct list_head manager_list; -+ -+static ssize_t manager_name_show(struct omap_overlay_manager *mgr, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%s\n", mgr->name); -+} -+ -+static ssize_t manager_display_show(struct omap_overlay_manager *mgr, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%s\n", -+ mgr->device ? mgr->device->name : "<none>"); -+} -+ -+static ssize_t manager_display_store(struct omap_overlay_manager *mgr, -+ const char *buf, size_t size) -+{ -+ int r = 0; -+ size_t len = size; -+ struct omap_dss_device *dssdev = NULL; -+ -+ int match(struct omap_dss_device *dssdev, void *data) -+ { -+ const char *str = data; -+ return sysfs_streq(dssdev->name, str); -+ } -+ -+ if (buf[size-1] == '\n') -+ --len; -+ -+ if (len > 0) -+ dssdev = omap_dss_find_device((void *)buf, match); -+ -+ if (len > 0 && dssdev == NULL) -+ return -EINVAL; -+ -+ if (dssdev) -+ DSSDBG("display %s found\n", dssdev->name); -+ -+ if (mgr->device) { -+ r = mgr->unset_device(mgr); -+ if (r) { -+ DSSERR("failed to unset display\n"); -+ goto put_device; -+ } -+ } -+ -+ if (dssdev) { -+ r = mgr->set_device(mgr, dssdev); -+ if (r) { -+ DSSERR("failed to set manager\n"); -+ goto put_device; -+ } -+ -+ r = mgr->apply(mgr); -+ if (r) { -+ DSSERR("failed to apply dispc config\n"); -+ goto put_device; -+ } -+ } -+ -+put_device: -+ if (dssdev) -+ omap_dss_put_device(dssdev); -+ -+ return r ? r : size; -+} -+ -+static ssize_t manager_default_color_show(struct omap_overlay_manager *mgr, -+ char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.default_color); -+} -+ -+static ssize_t manager_default_color_store(struct omap_overlay_manager *mgr, -+ const char *buf, size_t size) -+{ -+ struct omap_overlay_manager_info info; -+ u32 color; -+ int r; -+ -+ if (sscanf(buf, "%d", &color) != 1) -+ return -EINVAL; -+ -+ mgr->get_manager_info(mgr, &info); -+ -+ info.default_color = color; -+ -+ r = mgr->set_manager_info(mgr, &info); -+ if (r) -+ return r; -+ -+ r = mgr->apply(mgr); -+ if (r) -+ return r; -+ -+ return size; -+} -+ -+static const char *trans_key_type_str[] = { -+ "gfx-destination", -+ "video-source", -+}; -+ -+static ssize_t manager_trans_key_type_show(struct omap_overlay_manager *mgr, -+ char *buf) -+{ -+ enum omap_dss_trans_key_type key_type; -+ -+ key_type = mgr->info.trans_key_type; -+ BUG_ON(key_type >= ARRAY_SIZE(trans_key_type_str)); -+ -+ return snprintf(buf, PAGE_SIZE, "%s\n", trans_key_type_str[key_type]); -+} -+ -+static ssize_t manager_trans_key_type_store(struct omap_overlay_manager *mgr, -+ const char *buf, size_t size) -+{ -+ enum omap_dss_trans_key_type key_type; -+ struct omap_overlay_manager_info info; -+ int r; -+ -+ for (key_type = OMAP_DSS_COLOR_KEY_GFX_DST; -+ key_type < ARRAY_SIZE(trans_key_type_str); key_type++) { -+ if (sysfs_streq(buf, trans_key_type_str[key_type])) -+ break; -+ } -+ -+ if (key_type == ARRAY_SIZE(trans_key_type_str)) -+ return -EINVAL; -+ -+ mgr->get_manager_info(mgr, &info); -+ -+ info.trans_key_type = key_type; -+ -+ r = mgr->set_manager_info(mgr, &info); -+ if (r) -+ return r; -+ -+ r = mgr->apply(mgr); -+ if (r) -+ return r; -+ -+ return size; -+} -+ -+static ssize_t manager_trans_key_value_show(struct omap_overlay_manager *mgr, -+ char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.trans_key); -+} -+ -+static ssize_t manager_trans_key_value_store(struct omap_overlay_manager *mgr, -+ const char *buf, size_t size) -+{ -+ struct omap_overlay_manager_info info; -+ u32 key_value; -+ int r; -+ -+ if (sscanf(buf, "%d", &key_value) != 1) -+ return -EINVAL; -+ -+ mgr->get_manager_info(mgr, &info); -+ -+ info.trans_key = key_value; -+ -+ r = mgr->set_manager_info(mgr, &info); -+ if (r) -+ return r; -+ -+ r = mgr->apply(mgr); -+ if (r) -+ return r; -+ -+ return size; -+} -+ -+static ssize_t manager_trans_key_enabled_show(struct omap_overlay_manager *mgr, -+ char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.trans_enabled); -+} -+ -+static ssize_t manager_trans_key_enabled_store(struct omap_overlay_manager *mgr, -+ const char *buf, size_t size) -+{ -+ struct omap_overlay_manager_info info; -+ int enable; -+ int r; -+ -+ if (sscanf(buf, "%d", &enable) != 1) -+ return -EINVAL; -+ -+ mgr->get_manager_info(mgr, &info); -+ -+ info.trans_enabled = enable ? true : false; -+ -+ r = mgr->set_manager_info(mgr, &info); -+ if (r) -+ return r; -+ -+ r = mgr->apply(mgr); -+ if (r) -+ return r; -+ -+ return size; -+} -+ -+static ssize_t manager_alpha_blending_enabled_show( -+ struct omap_overlay_manager *mgr, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%d\n", mgr->info.alpha_enabled); -+} -+ -+static ssize_t manager_alpha_blending_enabled_store( -+ struct omap_overlay_manager *mgr, -+ const char *buf, size_t size) -+{ -+ struct omap_overlay_manager_info info; -+ int enable; -+ int r; -+ -+ if (sscanf(buf, "%d", &enable) != 1) -+ return -EINVAL; -+ -+ mgr->get_manager_info(mgr, &info); -+ -+ info.alpha_enabled = enable ? true : false; -+ -+ r = mgr->set_manager_info(mgr, &info); -+ if (r) -+ return r; -+ -+ r = mgr->apply(mgr); -+ if (r) -+ return r; -+ -+ return size; -+} -+ -+struct manager_attribute { -+ struct attribute attr; -+ ssize_t (*show)(struct omap_overlay_manager *, char *); -+ ssize_t (*store)(struct omap_overlay_manager *, const char *, size_t); -+}; -+ -+#define MANAGER_ATTR(_name, _mode, _show, _store) \ -+ struct manager_attribute manager_attr_##_name = \ -+ __ATTR(_name, _mode, _show, _store) -+ -+static MANAGER_ATTR(name, S_IRUGO, manager_name_show, NULL); -+static MANAGER_ATTR(display, S_IRUGO|S_IWUSR, -+ manager_display_show, manager_display_store); -+static MANAGER_ATTR(default_color, S_IRUGO|S_IWUSR, -+ manager_default_color_show, manager_default_color_store); -+static MANAGER_ATTR(trans_key_type, S_IRUGO|S_IWUSR, -+ manager_trans_key_type_show, manager_trans_key_type_store); -+static MANAGER_ATTR(trans_key_value, S_IRUGO|S_IWUSR, -+ manager_trans_key_value_show, manager_trans_key_value_store); -+static MANAGER_ATTR(trans_key_enabled, S_IRUGO|S_IWUSR, -+ manager_trans_key_enabled_show, -+ manager_trans_key_enabled_store); -+static MANAGER_ATTR(alpha_blending_enabled, S_IRUGO|S_IWUSR, -+ manager_alpha_blending_enabled_show, -+ manager_alpha_blending_enabled_store); -+ -+ -+static struct attribute *manager_sysfs_attrs[] = { -+ &manager_attr_name.attr, -+ &manager_attr_display.attr, -+ &manager_attr_default_color.attr, -+ &manager_attr_trans_key_type.attr, -+ &manager_attr_trans_key_value.attr, -+ &manager_attr_trans_key_enabled.attr, -+ &manager_attr_alpha_blending_enabled.attr, -+ NULL -+}; -+ -+static ssize_t manager_attr_show(struct kobject *kobj, struct attribute *attr, -+ char *buf) -+{ -+ struct omap_overlay_manager *manager; -+ struct manager_attribute *manager_attr; -+ -+ manager = container_of(kobj, struct omap_overlay_manager, kobj); -+ manager_attr = container_of(attr, struct manager_attribute, attr); -+ -+ if (!manager_attr->show) -+ return -ENOENT; -+ -+ return manager_attr->show(manager, buf); -+} -+ -+static ssize_t manager_attr_store(struct kobject *kobj, struct attribute *attr, -+ const char *buf, size_t size) -+{ -+ struct omap_overlay_manager *manager; -+ struct manager_attribute *manager_attr; -+ -+ manager = container_of(kobj, struct omap_overlay_manager, kobj); -+ manager_attr = container_of(attr, struct manager_attribute, attr); -+ -+ if (!manager_attr->store) -+ return -ENOENT; -+ -+ return manager_attr->store(manager, buf, size); -+} -+ -+static struct sysfs_ops manager_sysfs_ops = { -+ .show = manager_attr_show, -+ .store = manager_attr_store, -+}; -+ -+static struct kobj_type manager_ktype = { -+ .sysfs_ops = &manager_sysfs_ops, -+ .default_attrs = manager_sysfs_attrs, -+}; -+ -+/* -+ * We have 4 levels of cache for the dispc settings. First two are in SW and -+ * the latter two in HW. -+ * -+ * +--------------------+ -+ * |overlay/manager_info| -+ * +--------------------+ -+ * v -+ * apply() -+ * v -+ * +--------------------+ -+ * | dss_cache | -+ * +--------------------+ -+ * v -+ * configure() -+ * v -+ * +--------------------+ -+ * | shadow registers | -+ * +--------------------+ -+ * v -+ * VFP or lcd/digit_enable -+ * v -+ * +--------------------+ -+ * | registers | -+ * +--------------------+ -+ */ -+ -+struct overlay_cache_data { -+ /* If true, cache changed, but not written to shadow registers. Set -+ * in apply(), cleared when registers written. */ -+ bool dirty; -+ /* If true, shadow registers contain changed values not yet in real -+ * registers. Set when writing to shadow registers, cleared at -+ * VSYNC/EVSYNC */ -+ bool shadow_dirty; -+ -+ bool enabled; -+ -+ u32 paddr; -+ void __iomem *vaddr; -+ u16 screen_width; -+ u16 width; -+ u16 height; -+ enum omap_color_mode color_mode; -+ u8 rotation; -+ enum omap_dss_rotation_type rotation_type; -+ bool mirror; -+ -+ u16 pos_x; -+ u16 pos_y; -+ u16 out_width; /* if 0, out_width == width */ -+ u16 out_height; /* if 0, out_height == height */ -+ u8 global_alpha; -+ -+ enum omap_channel channel; -+ bool replication; -+ bool ilace; -+ -+ enum omap_burst_size burst_size; -+ u32 fifo_low; -+ u32 fifo_high; -+ -+ bool manual_update; -+}; -+ -+struct manager_cache_data { -+ /* If true, cache changed, but not written to shadow registers. Set -+ * in apply(), cleared when registers written. */ -+ bool dirty; -+ /* If true, shadow registers contain changed values not yet in real -+ * registers. Set when writing to shadow registers, cleared at -+ * VSYNC/EVSYNC */ -+ bool shadow_dirty; -+ -+ u32 default_color; -+ -+ enum omap_dss_trans_key_type trans_key_type; -+ u32 trans_key; -+ bool trans_enabled; -+ -+ bool alpha_enabled; -+ -+ bool manual_upd_display; -+ bool manual_update; -+ bool do_manual_update; -+ -+ /* manual update region */ -+ u16 x, y, w, h; -+}; -+ -+static struct { -+ spinlock_t lock; -+ struct overlay_cache_data overlay_cache[3]; -+ struct manager_cache_data manager_cache[2]; -+ -+ bool irq_enabled; -+} dss_cache; -+ -+ -+ -+static int omap_dss_set_device(struct omap_overlay_manager *mgr, -+ struct omap_dss_device *dssdev) -+{ -+ int i; -+ int r; -+ -+ if (dssdev->manager) { -+ DSSERR("display '%s' already has a manager '%s'\n", -+ dssdev->name, dssdev->manager->name); -+ return -EINVAL; -+ } -+ -+ if ((mgr->supported_displays & dssdev->type) == 0) { -+ DSSERR("display '%s' does not support manager '%s'\n", -+ dssdev->name, mgr->name); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < mgr->num_overlays; i++) { -+ struct omap_overlay *ovl = mgr->overlays[i]; -+ -+ if (ovl->manager != mgr || !ovl->info.enabled) -+ continue; -+ -+ r = dss_check_overlay(ovl, dssdev); -+ if (r) -+ return r; -+ } -+ -+ dssdev->manager = mgr; -+ mgr->device = dssdev; -+ mgr->device_changed = true; -+ -+ return 0; -+} -+ -+static int omap_dss_unset_device(struct omap_overlay_manager *mgr) -+{ -+ if (!mgr->device) { -+ DSSERR("failed to unset display, display not set.\n"); -+ return -EINVAL; -+ } -+ -+ mgr->device->manager = NULL; -+ mgr->device = NULL; -+ mgr->device_changed = true; -+ -+ return 0; -+} -+ -+static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr) -+{ -+ unsigned long timeout = msecs_to_jiffies(500); -+ struct manager_cache_data *mc; -+ enum omap_channel channel; -+ u32 irq; -+ int r; -+ int i; -+ -+ if (!mgr->device) -+ return 0; -+ -+ if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC) { -+ irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN; -+ channel = OMAP_DSS_CHANNEL_DIGIT; -+ } else { -+ if (mgr->device->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) { -+ enum omap_dss_update_mode mode; -+ mode = mgr->device->get_update_mode(mgr->device); -+ if (mode != OMAP_DSS_UPDATE_AUTO) -+ return 0; -+ -+ irq = DISPC_IRQ_FRAMEDONE; -+ } else { -+ irq = DISPC_IRQ_VSYNC; -+ } -+ channel = OMAP_DSS_CHANNEL_LCD; -+ } -+ -+ mc = &dss_cache.manager_cache[mgr->id]; -+ i = 0; -+ while (1) { -+ unsigned long flags; -+ bool shadow_dirty, dirty; -+ -+ spin_lock_irqsave(&dss_cache.lock, flags); -+ dirty = mc->dirty; -+ shadow_dirty = mc->shadow_dirty; -+ spin_unlock_irqrestore(&dss_cache.lock, flags); -+ -+ if (!dirty && !shadow_dirty) { -+ r = 0; -+ break; -+ } -+ -+ /* 4 iterations is the worst case: -+ * 1 - initial iteration, dirty = true (between VFP and VSYNC) -+ * 2 - first VSYNC, dirty = true -+ * 3 - dirty = false, shadow_dirty = true -+ * 4 - shadow_dirty = false */ -+ if (i++ == 3) { -+ DSSERR("mgr(%d)->wait_for_go() not finishing\n", -+ mgr->id); -+ r = 0; -+ break; -+ } -+ -+ r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout); -+ if (r == -ERESTARTSYS) -+ break; -+ -+ if (r) { -+ DSSERR("mgr(%d)->wait_for_go() timeout\n", mgr->id); -+ break; -+ } -+ } -+ -+ return r; -+} -+ -+int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl) -+{ -+ unsigned long timeout = msecs_to_jiffies(500); -+ enum omap_channel channel; -+ struct overlay_cache_data *oc; -+ struct omap_dss_device *dssdev; -+ u32 irq; -+ int r; -+ int i; -+ -+ if (!ovl->manager || !ovl->manager->device) -+ return 0; -+ -+ dssdev = ovl->manager->device; -+ -+ if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { -+ irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN; -+ channel = OMAP_DSS_CHANNEL_DIGIT; -+ } else { -+ if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) { -+ enum omap_dss_update_mode mode; -+ mode = dssdev->get_update_mode(dssdev); -+ if (mode != OMAP_DSS_UPDATE_AUTO) -+ return 0; -+ -+ irq = DISPC_IRQ_FRAMEDONE; -+ } else { -+ irq = DISPC_IRQ_VSYNC; -+ } -+ channel = OMAP_DSS_CHANNEL_LCD; -+ } -+ -+ oc = &dss_cache.overlay_cache[ovl->id]; -+ i = 0; -+ while (1) { -+ unsigned long flags; -+ bool shadow_dirty, dirty; -+ -+ spin_lock_irqsave(&dss_cache.lock, flags); -+ dirty = oc->dirty; -+ shadow_dirty = oc->shadow_dirty; -+ spin_unlock_irqrestore(&dss_cache.lock, flags); -+ -+ if (!dirty && !shadow_dirty) { -+ r = 0; -+ break; -+ } -+ -+ /* 4 iterations is the worst case: -+ * 1 - initial iteration, dirty = true (between VFP and VSYNC) -+ * 2 - first VSYNC, dirty = true -+ * 3 - dirty = false, shadow_dirty = true -+ * 4 - shadow_dirty = false */ -+ if (i++ == 3) { -+ DSSERR("ovl(%d)->wait_for_go() not finishing\n", -+ ovl->id); -+ r = 0; -+ break; -+ } -+ -+ r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout); -+ if (r == -ERESTARTSYS) -+ break; -+ -+ if (r) { -+ DSSERR("ovl(%d)->wait_for_go() timeout\n", ovl->id); -+ break; -+ } -+ } -+ -+ return r; -+} -+ -+static int overlay_enabled(struct omap_overlay *ovl) -+{ -+ return ovl->info.enabled && ovl->manager && ovl->manager->device; -+} -+ -+/* Is rect1 a subset of rect2? */ -+static bool rectangle_subset(int x1, int y1, int w1, int h1, -+ int x2, int y2, int w2, int h2) -+{ -+ if (x1 < x2 || y1 < y2) -+ return false; -+ -+ if (x1 + w1 > x2 + w2) -+ return false; -+ -+ if (y1 + h1 > y2 + h2) -+ return false; -+ -+ return true; -+} -+ -+/* Do rect1 and rect2 overlap? */ -+static bool rectangle_intersects(int x1, int y1, int w1, int h1, -+ int x2, int y2, int w2, int h2) -+{ -+ if (x1 >= x2 + w2) -+ return false; -+ -+ if (x2 >= x1 + w1) -+ return false; -+ -+ if (y1 >= y2 + h2) -+ return false; -+ -+ if (y2 >= y1 + h1) -+ return false; -+ -+ return true; -+} -+ -+static bool dispc_is_overlay_scaled(struct overlay_cache_data *oc) -+{ -+ if (oc->out_width != 0 && oc->width != oc->out_width) -+ return true; -+ -+ if (oc->out_height != 0 && oc->height != oc->out_height) -+ return true; -+ -+ return false; -+} -+ -+static int configure_overlay(enum omap_plane plane) -+{ -+ struct overlay_cache_data *c; -+ struct manager_cache_data *mc; -+ u16 outw, outh; -+ u16 x, y, w, h; -+ u32 paddr; -+ int r; -+ -+ DSSDBGF("%d", plane); -+ -+ c = &dss_cache.overlay_cache[plane]; -+ -+ if (!c->enabled) { -+ dispc_enable_plane(plane, 0); -+ return 0; -+ } -+ -+ mc = &dss_cache.manager_cache[c->channel]; -+ -+ x = c->pos_x; -+ y = c->pos_y; -+ w = c->width; -+ h = c->height; -+ outw = c->out_width == 0 ? c->width : c->out_width; -+ outh = c->out_height == 0 ? c->height : c->out_height; -+ paddr = c->paddr; -+ -+ if (c->manual_update && mc->do_manual_update) { -+ unsigned bpp; -+ /* If the overlay is outside the update region, disable it */ -+ if (!rectangle_intersects(mc->x, mc->y, mc->w, mc->h, -+ x, y, outw, outh)) { -+ dispc_enable_plane(plane, 0); -+ return 0; -+ } -+ -+ switch (c->color_mode) { -+ case OMAP_DSS_COLOR_RGB16: -+ case OMAP_DSS_COLOR_ARGB16: -+ case OMAP_DSS_COLOR_YUV2: -+ case OMAP_DSS_COLOR_UYVY: -+ bpp = 16; -+ break; -+ -+ case OMAP_DSS_COLOR_RGB24P: -+ bpp = 24; -+ break; -+ -+ case OMAP_DSS_COLOR_RGB24U: -+ case OMAP_DSS_COLOR_ARGB32: -+ case OMAP_DSS_COLOR_RGBA32: -+ case OMAP_DSS_COLOR_RGBX32: -+ bpp = 32; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ if (dispc_is_overlay_scaled(c)) { -+ /* If the overlay is scaled, the update area has -+ * already been enlarged to cover the whole overlay. We -+ * only need to adjust x/y here */ -+ x = c->pos_x - mc->x; -+ y = c->pos_y - mc->y; -+ } else { -+ if (mc->x > c->pos_x) { -+ x = 0; -+ w -= (mc->x - c->pos_x); -+ paddr += (mc->x - c->pos_x) * bpp / 8; -+ } else { -+ x = c->pos_x - mc->x; -+ } -+ -+ if (mc->y > c->pos_y) { -+ y = 0; -+ h -= (mc->y - c->pos_y); -+ paddr += (mc->y - c->pos_y) * c->screen_width * -+ bpp / 8; -+ } else { -+ y = c->pos_y - mc->y; -+ } -+ -+ if (mc->w < (x+w)) -+ w -= (x+w) - (mc->w); -+ -+ if (mc->h < (y+h)) -+ h -= (y+h) - (mc->h); -+ -+ outw = w; -+ outh = h; -+ } -+ } -+ -+ r = dispc_setup_plane(plane, -+ paddr, -+ c->screen_width, -+ x, y, -+ w, h, -+ outw, outh, -+ c->color_mode, -+ c->ilace, -+ c->rotation_type, -+ c->rotation, -+ c->mirror, -+ c->global_alpha); -+ -+ if (r) { -+ /* this shouldn't happen */ -+ DSSERR("dispc_setup_plane failed for ovl %d\n", plane); -+ dispc_enable_plane(plane, 0); -+ return r; -+ } -+ -+ dispc_enable_replication(plane, c->replication); -+ -+ dispc_set_burst_size(plane, c->burst_size); -+ dispc_setup_plane_fifo(plane, c->fifo_low, c->fifo_high); -+ -+ dispc_enable_plane(plane, 1); -+ -+ return 0; -+} -+ -+static void configure_manager(enum omap_channel channel) -+{ -+ struct manager_cache_data *c; -+ -+ DSSDBGF("%d", channel); -+ -+ c = &dss_cache.manager_cache[channel]; -+ -+ dispc_set_trans_key(channel, c->trans_key_type, c->trans_key); -+ dispc_enable_trans_key(channel, c->trans_enabled); -+ dispc_enable_alpha_blending(channel, c->alpha_enabled); -+} -+ -+/* configure_dispc() tries to write values from cache to shadow registers. -+ * It writes only to those managers/overlays that are not busy. -+ * returns 0 if everything could be written to shadow registers. -+ * returns 1 if not everything could be written to shadow registers. */ -+static int configure_dispc(void) -+{ -+ struct overlay_cache_data *oc; -+ struct manager_cache_data *mc; -+ const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); -+ const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache); -+ int i; -+ int r; -+ bool mgr_busy[2]; -+ bool mgr_go[2]; -+ bool busy; -+ -+ r = 0; -+ busy = false; -+ -+ mgr_busy[0] = dispc_go_busy(0); -+ mgr_busy[1] = dispc_go_busy(1); -+ mgr_go[0] = false; -+ mgr_go[1] = false; -+ -+ /* Commit overlay settings */ -+ for (i = 0; i < num_ovls; ++i) { -+ oc = &dss_cache.overlay_cache[i]; -+ mc = &dss_cache.manager_cache[oc->channel]; -+ -+ if (!oc->dirty) -+ continue; -+ -+ if (oc->manual_update && !mc->do_manual_update) -+ continue; -+ -+ if (mgr_busy[oc->channel]) { -+ busy = true; -+ continue; -+ } -+ -+ r = configure_overlay(i); -+ if (r) -+ DSSERR("configure_overlay %d failed\n", i); -+ -+ oc->dirty = false; -+ oc->shadow_dirty = true; -+ mgr_go[oc->channel] = true; -+ } -+ -+ /* Commit manager settings */ -+ for (i = 0; i < num_mgrs; ++i) { -+ mc = &dss_cache.manager_cache[i]; -+ -+ if (!mc->dirty) -+ continue; -+ -+ if (mc->manual_update && !mc->do_manual_update) -+ continue; -+ -+ if (mgr_busy[i]) { -+ busy = true; -+ continue; -+ } -+ -+ configure_manager(i); -+ mc->dirty = false; -+ mc->shadow_dirty = true; -+ mgr_go[i] = true; -+ } -+ -+ /* set GO */ -+ for (i = 0; i < num_mgrs; ++i) { -+ mc = &dss_cache.manager_cache[i]; -+ -+ if (!mgr_go[i]) -+ continue; -+ -+ /* We don't need GO with manual update display. LCD iface will -+ * always be turned off after frame, and new settings will be -+ * taken in to use at next update */ -+ if (!mc->manual_upd_display) -+ dispc_go(i); -+ } -+ -+ if (busy) -+ r = 1; -+ else -+ r = 0; -+ -+ return r; -+} -+ -+/* Configure dispc for partial update. Return possibly modified update -+ * area */ -+void dss_setup_partial_planes(struct omap_dss_device *dssdev, -+ u16 *xi, u16 *yi, u16 *wi, u16 *hi) -+{ -+ struct overlay_cache_data *oc; -+ struct manager_cache_data *mc; -+ const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); -+ struct omap_overlay_manager *mgr; -+ int i; -+ u16 x, y, w, h; -+ unsigned long flags; -+ -+ x = *xi; -+ y = *yi; -+ w = *wi; -+ h = *hi; -+ -+ DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n", -+ *xi, *yi, *wi, *hi); -+ -+ mgr = dssdev->manager; -+ -+ if (!mgr) { -+ DSSDBG("no manager\n"); -+ return; -+ } -+ -+ spin_lock_irqsave(&dss_cache.lock, flags); -+ -+ /* We need to show the whole overlay if it is scaled. So look for -+ * those, and make the update area larger if found. -+ * Also mark the overlay cache dirty */ -+ for (i = 0; i < num_ovls; ++i) { -+ unsigned x1, y1, x2, y2; -+ unsigned outw, outh; -+ -+ oc = &dss_cache.overlay_cache[i]; -+ -+ if (oc->channel != mgr->id) -+ continue; -+ -+ oc->dirty = true; -+ -+ if (!oc->enabled) -+ continue; -+ -+ if (!dispc_is_overlay_scaled(oc)) -+ continue; -+ -+ outw = oc->out_width == 0 ? oc->width : oc->out_width; -+ outh = oc->out_height == 0 ? oc->height : oc->out_height; -+ -+ /* is the overlay outside the update region? */ -+ if (!rectangle_intersects(x, y, w, h, -+ oc->pos_x, oc->pos_y, -+ outw, outh)) -+ continue; -+ -+ /* if the overlay totally inside the update region? */ -+ if (rectangle_subset(oc->pos_x, oc->pos_y, outw, outh, -+ x, y, w, h)) -+ continue; -+ -+ if (x > oc->pos_x) -+ x1 = oc->pos_x; -+ else -+ x1 = x; -+ -+ if (y > oc->pos_y) -+ y1 = oc->pos_y; -+ else -+ y1 = y; -+ -+ if ((x + w) < (oc->pos_x + outw)) -+ x2 = oc->pos_x + outw; -+ else -+ x2 = x + w; -+ -+ if ((y + h) < (oc->pos_y + outh)) -+ y2 = oc->pos_y + outh; -+ else -+ y2 = y + h; -+ -+ x = x1; -+ y = y1; -+ w = x2 - x1; -+ h = y2 - y1; -+ -+ DSSDBG("changing upd area due to ovl(%d) scaling %d,%d %dx%d\n", -+ i, x, y, w, h); -+ } -+ -+ mc = &dss_cache.manager_cache[mgr->id]; -+ mc->do_manual_update = true; -+ mc->x = x; -+ mc->y = y; -+ mc->w = w; -+ mc->h = h; -+ -+ configure_dispc(); -+ -+ mc->do_manual_update = false; -+ -+ spin_unlock_irqrestore(&dss_cache.lock, flags); -+ -+ *xi = x; -+ *yi = y; -+ *wi = w; -+ *hi = h; -+} -+ -+void dss_start_update(struct omap_dss_device *dssdev) -+{ -+ struct manager_cache_data *mc; -+ struct overlay_cache_data *oc; -+ const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); -+ const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache); -+ struct omap_overlay_manager *mgr; -+ int i; -+ -+ mgr = dssdev->manager; -+ -+ for (i = 0; i < num_ovls; ++i) { -+ oc = &dss_cache.overlay_cache[i]; -+ if (oc->channel != mgr->id) -+ continue; -+ -+ oc->shadow_dirty = false; -+ } -+ -+ for (i = 0; i < num_mgrs; ++i) { -+ mc = &dss_cache.manager_cache[i]; -+ if (mgr->id != i) -+ continue; -+ -+ mc->shadow_dirty = false; -+ } -+ -+ dispc_enable_lcd_out(1); -+} -+ -+static void dss_apply_irq_handler(void *data, u32 mask) -+{ -+ struct manager_cache_data *mc; -+ struct overlay_cache_data *oc; -+ const int num_ovls = ARRAY_SIZE(dss_cache.overlay_cache); -+ const int num_mgrs = ARRAY_SIZE(dss_cache.manager_cache); -+ int i, r; -+ bool mgr_busy[2]; -+ -+ mgr_busy[0] = dispc_go_busy(0); -+ mgr_busy[1] = dispc_go_busy(1); -+ -+ spin_lock(&dss_cache.lock); -+ -+ for (i = 0; i < num_ovls; ++i) { -+ oc = &dss_cache.overlay_cache[i]; -+ if (!mgr_busy[oc->channel]) -+ oc->shadow_dirty = false; -+ } -+ -+ for (i = 0; i < num_mgrs; ++i) { -+ mc = &dss_cache.manager_cache[i]; -+ if (!mgr_busy[i]) -+ mc->shadow_dirty = false; -+ } -+ -+ r = configure_dispc(); -+ if (r == 1) -+ goto end; -+ -+ /* re-read busy flags */ -+ mgr_busy[0] = dispc_go_busy(0); -+ mgr_busy[1] = dispc_go_busy(1); -+ -+ /* keep running as long as there are busy managers, so that -+ * we can collect overlay-applied information */ -+ for (i = 0; i < num_mgrs; ++i) { -+ if (mgr_busy[i]) -+ goto end; -+ } -+ -+ omap_dispc_unregister_isr(dss_apply_irq_handler, NULL, -+ DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD | -+ DISPC_IRQ_EVSYNC_EVEN); -+ dss_cache.irq_enabled = false; -+ -+end: -+ spin_unlock(&dss_cache.lock); -+} -+ -+static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr) -+{ -+ struct overlay_cache_data *oc; -+ struct manager_cache_data *mc; -+ int i; -+ struct omap_overlay *ovl; -+ int num_planes_enabled = 0; -+ bool use_fifomerge; -+ unsigned long flags; -+ int r; -+ -+ DSSDBG("omap_dss_mgr_apply(%s)\n", mgr->name); -+ -+ spin_lock_irqsave(&dss_cache.lock, flags); -+ -+ /* Configure overlays */ -+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) { -+ struct omap_dss_device *dssdev; -+ -+ ovl = omap_dss_get_overlay(i); -+ -+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) -+ continue; -+ -+ oc = &dss_cache.overlay_cache[ovl->id]; -+ -+ if (!overlay_enabled(ovl)) { -+ if (oc->enabled) { -+ oc->enabled = false; -+ oc->dirty = true; -+ } -+ continue; -+ } -+ -+ if (!ovl->info_dirty) { -+ if (oc->enabled) -+ ++num_planes_enabled; -+ continue; -+ } -+ -+ dssdev = ovl->manager->device; -+ -+ if (dss_check_overlay(ovl, dssdev)) { -+ if (oc->enabled) { -+ oc->enabled = false; -+ oc->dirty = true; -+ } -+ continue; -+ } -+ -+ ovl->info_dirty = false; -+ oc->dirty = true; -+ -+ oc->paddr = ovl->info.paddr; -+ oc->vaddr = ovl->info.vaddr; -+ oc->screen_width = ovl->info.screen_width; -+ oc->width = ovl->info.width; -+ oc->height = ovl->info.height; -+ oc->color_mode = ovl->info.color_mode; -+ oc->rotation = ovl->info.rotation; -+ oc->rotation_type = ovl->info.rotation_type; -+ oc->mirror = ovl->info.mirror; -+ oc->pos_x = ovl->info.pos_x; -+ oc->pos_y = ovl->info.pos_y; -+ oc->out_width = ovl->info.out_width; -+ oc->out_height = ovl->info.out_height; -+ oc->global_alpha = ovl->info.global_alpha; -+ -+ oc->replication = -+ dss_use_replication(dssdev, ovl->info.color_mode); -+ -+ oc->ilace = dssdev->type == OMAP_DISPLAY_TYPE_VENC; -+ -+ oc->channel = ovl->manager->id; -+ -+ oc->enabled = true; -+ -+ oc->manual_update = -+ dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE && -+ dssdev->get_update_mode(dssdev) != OMAP_DSS_UPDATE_AUTO; -+ -+ ++num_planes_enabled; -+ } -+ -+ /* Configure managers */ -+ list_for_each_entry(mgr, &manager_list, list) { -+ struct omap_dss_device *dssdev; -+ -+ if (!(mgr->caps & OMAP_DSS_OVL_MGR_CAP_DISPC)) -+ continue; -+ -+ mc = &dss_cache.manager_cache[mgr->id]; -+ -+ if (mgr->device_changed) { -+ mgr->device_changed = false; -+ mgr->info_dirty = true; -+ } -+ -+ if (!mgr->info_dirty) -+ continue; -+ -+ if (!mgr->device) -+ continue; -+ -+ dssdev = mgr->device; -+ -+ mgr->info_dirty = false; -+ mc->dirty = true; -+ -+ mc->default_color = mgr->info.default_color; -+ mc->trans_key_type = mgr->info.trans_key_type; -+ mc->trans_key = mgr->info.trans_key; -+ mc->trans_enabled = mgr->info.trans_enabled; -+ mc->alpha_enabled = mgr->info.alpha_enabled; -+ -+ mc->manual_upd_display = -+ dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE; -+ -+ mc->manual_update = -+ dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE && -+ dssdev->get_update_mode(dssdev) != OMAP_DSS_UPDATE_AUTO; -+ } -+ -+ /* XXX TODO: Try to get fifomerge working. The problem is that it -+ * affects both managers, not individually but at the same time. This -+ * means the change has to be well synchronized. I guess the proper way -+ * is to have a two step process for fifo merge: -+ * fifomerge enable: -+ * 1. disable other planes, leaving one plane enabled -+ * 2. wait until the planes are disabled on HW -+ * 3. config merged fifo thresholds, enable fifomerge -+ * fifomerge disable: -+ * 1. config unmerged fifo thresholds, disable fifomerge -+ * 2. wait until fifo changes are in HW -+ * 3. enable planes -+ */ -+ use_fifomerge = false; -+ -+ /* Configure overlay fifos */ -+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) { -+ struct omap_dss_device *dssdev; -+ u32 size; -+ -+ ovl = omap_dss_get_overlay(i); -+ -+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC)) -+ continue; -+ -+ oc = &dss_cache.overlay_cache[ovl->id]; -+ -+ if (!oc->enabled) -+ continue; -+ -+ dssdev = ovl->manager->device; -+ -+ size = dispc_get_plane_fifo_size(ovl->id); -+ if (use_fifomerge) -+ size *= 3; -+ -+ switch (dssdev->type) { -+ case OMAP_DISPLAY_TYPE_DPI: -+ case OMAP_DISPLAY_TYPE_DBI: -+ case OMAP_DISPLAY_TYPE_SDI: -+ case OMAP_DISPLAY_TYPE_VENC: -+ default_get_overlay_fifo_thresholds(ovl->id, size, -+ &oc->burst_size, &oc->fifo_low, -+ &oc->fifo_high); -+ break; -+#ifdef CONFIG_OMAP2_DSS_DSI -+ case OMAP_DISPLAY_TYPE_DSI: -+ dsi_get_overlay_fifo_thresholds(ovl->id, size, -+ &oc->burst_size, &oc->fifo_low, -+ &oc->fifo_high); -+ break; -+#endif -+ default: -+ BUG(); -+ } -+ } -+ -+ r = 0; -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ if (!dss_cache.irq_enabled) { -+ r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, -+ DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD | -+ DISPC_IRQ_EVSYNC_EVEN); -+ dss_cache.irq_enabled = true; -+ } -+ configure_dispc(); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ spin_unlock_irqrestore(&dss_cache.lock, flags); -+ -+ return r; -+} -+ -+static int dss_check_manager(struct omap_overlay_manager *mgr) -+{ -+ /* OMAP supports only graphics source transparency color key and alpha -+ * blending simultaneously. See TRM 15.4.2.4.2.2 Alpha Mode */ -+ -+ if (mgr->info.alpha_enabled && mgr->info.trans_enabled && -+ mgr->info.trans_key_type != OMAP_DSS_COLOR_KEY_GFX_DST) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int omap_dss_mgr_set_info(struct omap_overlay_manager *mgr, -+ struct omap_overlay_manager_info *info) -+{ -+ int r; -+ struct omap_overlay_manager_info old_info; -+ -+ old_info = mgr->info; -+ mgr->info = *info; -+ -+ r = dss_check_manager(mgr); -+ if (r) { -+ mgr->info = old_info; -+ return r; -+ } -+ -+ mgr->info_dirty = true; -+ -+ return 0; -+} -+ -+static void omap_dss_mgr_get_info(struct omap_overlay_manager *mgr, -+ struct omap_overlay_manager_info *info) -+{ -+ *info = mgr->info; -+} -+ -+static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager) -+{ -+ ++num_managers; -+ list_add_tail(&manager->list, &manager_list); -+} -+ -+int dss_init_overlay_managers(struct platform_device *pdev) -+{ -+ int i, r; -+ -+ spin_lock_init(&dss_cache.lock); -+ -+ INIT_LIST_HEAD(&manager_list); -+ -+ num_managers = 0; -+ -+ for (i = 0; i < 2; ++i) { -+ struct omap_overlay_manager *mgr; -+ mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); -+ -+ BUG_ON(mgr == NULL); -+ -+ switch (i) { -+ case 0: -+ mgr->name = "lcd"; -+ mgr->id = OMAP_DSS_CHANNEL_LCD; -+ mgr->supported_displays = -+ OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | -+ OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI; -+ break; -+ case 1: -+ mgr->name = "tv"; -+ mgr->id = OMAP_DSS_CHANNEL_DIGIT; -+ mgr->supported_displays = OMAP_DISPLAY_TYPE_VENC; -+ break; -+ } -+ -+ mgr->set_device = &omap_dss_set_device; -+ mgr->unset_device = &omap_dss_unset_device; -+ mgr->apply = &omap_dss_mgr_apply; -+ mgr->set_manager_info = &omap_dss_mgr_set_info; -+ mgr->get_manager_info = &omap_dss_mgr_get_info; -+ mgr->wait_for_go = &dss_mgr_wait_for_go; -+ -+ mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC; -+ -+ dss_overlay_setup_dispc_manager(mgr); -+ -+ omap_dss_add_overlay_manager(mgr); -+ -+ r = kobject_init_and_add(&mgr->kobj, &manager_ktype, -+ &pdev->dev.kobj, "manager%d", i); -+ -+ if (r) { -+ DSSERR("failed to create sysfs file\n"); -+ continue; -+ } -+ } -+ -+#ifdef L4_EXAMPLE -+ { -+ int omap_dss_mgr_apply_l4(struct omap_overlay_manager *mgr) -+ { -+ DSSDBG("omap_dss_mgr_apply_l4(%s)\n", mgr->name); -+ -+ return 0; -+ } -+ -+ struct omap_overlay_manager *mgr; -+ mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); -+ -+ BUG_ON(mgr == NULL); -+ -+ mgr->name = "l4"; -+ mgr->supported_displays = -+ OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI; -+ -+ mgr->set_device = &omap_dss_set_device; -+ mgr->unset_device = &omap_dss_unset_device; -+ mgr->apply = &omap_dss_mgr_apply_l4; -+ mgr->set_manager_info = &omap_dss_mgr_set_info; -+ mgr->get_manager_info = &omap_dss_mgr_get_info; -+ -+ dss_overlay_setup_l4_manager(mgr); -+ -+ omap_dss_add_overlay_manager(mgr); -+ -+ r = kobject_init_and_add(&mgr->kobj, &manager_ktype, -+ &pdev->dev.kobj, "managerl4"); -+ -+ if (r) -+ DSSERR("failed to create sysfs file\n"); -+ } -+#endif -+ -+ return 0; -+} -+ -+void dss_uninit_overlay_managers(struct platform_device *pdev) -+{ -+ struct omap_overlay_manager *mgr; -+ -+ while (!list_empty(&manager_list)) { -+ mgr = list_first_entry(&manager_list, -+ struct omap_overlay_manager, list); -+ list_del(&mgr->list); -+ kobject_del(&mgr->kobj); -+ kobject_put(&mgr->kobj); -+ kfree(mgr); -+ } -+ -+ num_managers = 0; -+} -+ -+int omap_dss_get_num_overlay_managers(void) -+{ -+ return num_managers; -+} -+EXPORT_SYMBOL(omap_dss_get_num_overlay_managers); -+ -+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num) -+{ -+ int i = 0; -+ struct omap_overlay_manager *mgr; -+ -+ list_for_each_entry(mgr, &manager_list, list) { -+ if (i++ == num) -+ return mgr; -+ } -+ -+ return NULL; -+} -+EXPORT_SYMBOL(omap_dss_get_overlay_manager); -+ ---- /dev/null -+++ b/drivers/video/omap2/dss/overlay.c -@@ -0,0 +1,673 @@ -+/* -+ * linux/drivers/video/omap2/dss/overlay.c -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#define DSS_SUBSYS_NAME "OVERLAY" -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/err.h> -+#include <linux/sysfs.h> -+#include <linux/kobject.h> -+#include <linux/platform_device.h> -+#include <linux/delay.h> -+ -+#include <mach/display.h> -+ -+#include "dss.h" -+ -+static int num_overlays; -+static struct list_head overlay_list; -+ -+static ssize_t overlay_name_show(struct omap_overlay *ovl, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%s\n", ovl->name); -+} -+ -+static ssize_t overlay_manager_show(struct omap_overlay *ovl, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%s\n", -+ ovl->manager ? ovl->manager->name : "<none>"); -+} -+ -+static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf, -+ size_t size) -+{ -+ int i, r; -+ struct omap_overlay_manager *mgr = NULL; -+ struct omap_overlay_manager *old_mgr; -+ int len = size; -+ -+ if (buf[size-1] == '\n') -+ --len; -+ -+ if (len > 0) { -+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { -+ mgr = omap_dss_get_overlay_manager(i); -+ -+ if (strncmp(buf, mgr->name, len) == 0) -+ break; -+ -+ mgr = NULL; -+ } -+ } -+ -+ if (len > 0 && mgr == NULL) -+ return -EINVAL; -+ -+ if (mgr) -+ DSSDBG("manager %s found\n", mgr->name); -+ -+ if (mgr == ovl->manager) -+ return size; -+ -+ old_mgr = ovl->manager; -+ -+ /* detach old manager */ -+ if (old_mgr) { -+ r = ovl->unset_manager(ovl); -+ if (r) { -+ DSSERR("detach failed\n"); -+ return r; -+ } -+ -+ r = old_mgr->apply(old_mgr); -+ if (r) -+ return r; -+ } -+ -+ if (mgr) { -+ r = ovl->set_manager(ovl, mgr); -+ if (r) { -+ DSSERR("Failed to attach overlay\n"); -+ return r; -+ } -+ -+ r = mgr->apply(mgr); -+ if (r) -+ return r; -+ } -+ -+ return size; -+} -+ -+static ssize_t overlay_input_size_show(struct omap_overlay *ovl, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%d,%d\n", -+ ovl->info.width, ovl->info.height); -+} -+ -+static ssize_t overlay_screen_width_show(struct omap_overlay *ovl, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.screen_width); -+} -+ -+static ssize_t overlay_position_show(struct omap_overlay *ovl, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%d,%d\n", -+ ovl->info.pos_x, ovl->info.pos_y); -+} -+ -+static ssize_t overlay_position_store(struct omap_overlay *ovl, -+ const char *buf, size_t size) -+{ -+ int r; -+ char *last; -+ struct omap_overlay_info info; -+ -+ ovl->get_overlay_info(ovl, &info); -+ -+ info.pos_x = simple_strtoul(buf, &last, 10); -+ ++last; -+ if (last - buf >= size) -+ return -EINVAL; -+ -+ info.pos_y = simple_strtoul(last, &last, 10); -+ -+ r = ovl->set_overlay_info(ovl, &info); -+ if (r) -+ return r; -+ -+ if (ovl->manager) { -+ r = ovl->manager->apply(ovl->manager); -+ if (r) -+ return r; -+ } -+ -+ return size; -+} -+ -+static ssize_t overlay_output_size_show(struct omap_overlay *ovl, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%d,%d\n", -+ ovl->info.out_width, ovl->info.out_height); -+} -+ -+static ssize_t overlay_output_size_store(struct omap_overlay *ovl, -+ const char *buf, size_t size) -+{ -+ int r; -+ char *last; -+ struct omap_overlay_info info; -+ -+ ovl->get_overlay_info(ovl, &info); -+ -+ info.out_width = simple_strtoul(buf, &last, 10); -+ ++last; -+ if (last - buf >= size) -+ return -EINVAL; -+ -+ info.out_height = simple_strtoul(last, &last, 10); -+ -+ r = ovl->set_overlay_info(ovl, &info); -+ if (r) -+ return r; -+ -+ if (ovl->manager) { -+ r = ovl->manager->apply(ovl->manager); -+ if (r) -+ return r; -+ } -+ -+ return size; -+} -+ -+static ssize_t overlay_enabled_show(struct omap_overlay *ovl, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.enabled); -+} -+ -+static ssize_t overlay_enabled_store(struct omap_overlay *ovl, const char *buf, -+ size_t size) -+{ -+ int r; -+ struct omap_overlay_info info; -+ -+ ovl->get_overlay_info(ovl, &info); -+ -+ info.enabled = simple_strtoul(buf, NULL, 10); -+ -+ r = ovl->set_overlay_info(ovl, &info); -+ if (r) -+ return r; -+ -+ if (ovl->manager) { -+ r = ovl->manager->apply(ovl->manager); -+ if (r) -+ return r; -+ } -+ -+ return size; -+} -+ -+static ssize_t overlay_global_alpha_show(struct omap_overlay *ovl, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%d\n", -+ ovl->info.global_alpha); -+} -+ -+static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl, -+ const char *buf, size_t size) -+{ -+ int r; -+ struct omap_overlay_info info; -+ -+ ovl->get_overlay_info(ovl, &info); -+ -+ /* Video1 plane does not support global alpha -+ * to always make it 255 completely opaque -+ */ -+ if (ovl->id == OMAP_DSS_VIDEO1) -+ info.global_alpha = 255; -+ else -+ info.global_alpha = simple_strtoul(buf, NULL, 10); -+ -+ r = ovl->set_overlay_info(ovl, &info); -+ if (r) -+ return r; -+ -+ if (ovl->manager) { -+ r = ovl->manager->apply(ovl->manager); -+ if (r) -+ return r; -+ } -+ -+ return size; -+} -+ -+struct overlay_attribute { -+ struct attribute attr; -+ ssize_t (*show)(struct omap_overlay *, char *); -+ ssize_t (*store)(struct omap_overlay *, const char *, size_t); -+}; -+ -+#define OVERLAY_ATTR(_name, _mode, _show, _store) \ -+ struct overlay_attribute overlay_attr_##_name = \ -+ __ATTR(_name, _mode, _show, _store) -+ -+static OVERLAY_ATTR(name, S_IRUGO, overlay_name_show, NULL); -+static OVERLAY_ATTR(manager, S_IRUGO|S_IWUSR, -+ overlay_manager_show, overlay_manager_store); -+static OVERLAY_ATTR(input_size, S_IRUGO, overlay_input_size_show, NULL); -+static OVERLAY_ATTR(screen_width, S_IRUGO, overlay_screen_width_show, NULL); -+static OVERLAY_ATTR(position, S_IRUGO|S_IWUSR, -+ overlay_position_show, overlay_position_store); -+static OVERLAY_ATTR(output_size, S_IRUGO|S_IWUSR, -+ overlay_output_size_show, overlay_output_size_store); -+static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR, -+ overlay_enabled_show, overlay_enabled_store); -+static OVERLAY_ATTR(global_alpha, S_IRUGO|S_IWUSR, -+ overlay_global_alpha_show, overlay_global_alpha_store); -+ -+static struct attribute *overlay_sysfs_attrs[] = { -+ &overlay_attr_name.attr, -+ &overlay_attr_manager.attr, -+ &overlay_attr_input_size.attr, -+ &overlay_attr_screen_width.attr, -+ &overlay_attr_position.attr, -+ &overlay_attr_output_size.attr, -+ &overlay_attr_enabled.attr, -+ &overlay_attr_global_alpha.attr, -+ NULL -+}; -+ -+static ssize_t overlay_attr_show(struct kobject *kobj, struct attribute *attr, -+ char *buf) -+{ -+ struct omap_overlay *overlay; -+ struct overlay_attribute *overlay_attr; -+ -+ overlay = container_of(kobj, struct omap_overlay, kobj); -+ overlay_attr = container_of(attr, struct overlay_attribute, attr); -+ -+ if (!overlay_attr->show) -+ return -ENOENT; -+ -+ return overlay_attr->show(overlay, buf); -+} -+ -+static ssize_t overlay_attr_store(struct kobject *kobj, struct attribute *attr, -+ const char *buf, size_t size) -+{ -+ struct omap_overlay *overlay; -+ struct overlay_attribute *overlay_attr; -+ -+ overlay = container_of(kobj, struct omap_overlay, kobj); -+ overlay_attr = container_of(attr, struct overlay_attribute, attr); -+ -+ if (!overlay_attr->store) -+ return -ENOENT; -+ -+ return overlay_attr->store(overlay, buf, size); -+} -+ -+static struct sysfs_ops overlay_sysfs_ops = { -+ .show = overlay_attr_show, -+ .store = overlay_attr_store, -+}; -+ -+static struct kobj_type overlay_ktype = { -+ .sysfs_ops = &overlay_sysfs_ops, -+ .default_attrs = overlay_sysfs_attrs, -+}; -+ -+/* Check if overlay parameters are compatible with display */ -+int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev) -+{ -+ struct omap_overlay_info *info; -+ u16 outw, outh; -+ u16 dw, dh; -+ -+ if (!dssdev) -+ return 0; -+ -+ if (!ovl->info.enabled) -+ return 0; -+ -+ info = &ovl->info; -+ -+ if (info->paddr == 0) { -+ DSSDBG("check_overlay failed: paddr 0\n"); -+ return -EINVAL; -+ } -+ -+ dssdev->get_resolution(dssdev, &dw, &dh); -+ -+ DSSDBG("check_overlay %d: (%d,%d %dx%d -> %dx%d) disp (%dx%d)\n", -+ ovl->id, -+ info->pos_x, info->pos_y, -+ info->width, info->height, -+ info->out_width, info->out_height, -+ dw, dh); -+ -+ if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) { -+ outw = info->width; -+ outh = info->height; -+ } else { -+ if (info->out_width == 0) -+ outw = info->width; -+ else -+ outw = info->out_width; -+ -+ if (info->out_height == 0) -+ outh = info->height; -+ else -+ outh = info->out_height; -+ } -+ -+ if (dw < info->pos_x + outw) { -+ DSSDBG("check_overlay failed 1: %d < %d + %d\n", -+ dw, info->pos_x, outw); -+ return -EINVAL; -+ } -+ -+ if (dh < info->pos_y + outh) { -+ DSSDBG("check_overlay failed 2: %d < %d + %d\n", -+ dh, info->pos_y, outh); -+ return -EINVAL; -+ } -+ -+ if ((ovl->supported_modes & info->color_mode) == 0) { -+ DSSERR("overlay doesn't support mode %d\n", info->color_mode); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int dss_ovl_set_overlay_info(struct omap_overlay *ovl, -+ struct omap_overlay_info *info) -+{ -+ int r; -+ struct omap_overlay_info old_info; -+ -+ old_info = ovl->info; -+ ovl->info = *info; -+ -+ if (ovl->manager) { -+ r = dss_check_overlay(ovl, ovl->manager->device); -+ if (r) { -+ ovl->info = old_info; -+ return r; -+ } -+ } -+ -+ ovl->info_dirty = true; -+ -+ return 0; -+} -+ -+static void dss_ovl_get_overlay_info(struct omap_overlay *ovl, -+ struct omap_overlay_info *info) -+{ -+ *info = ovl->info; -+} -+ -+static int dss_ovl_wait_for_go(struct omap_overlay *ovl) -+{ -+ return dss_mgr_wait_for_go_ovl(ovl); -+} -+ -+static int omap_dss_set_manager(struct omap_overlay *ovl, -+ struct omap_overlay_manager *mgr) -+{ -+ if (!mgr) -+ return -EINVAL; -+ -+ if (ovl->manager) { -+ DSSERR("overlay '%s' already has a manager '%s'\n", -+ ovl->name, ovl->manager->name); -+ return -EINVAL; -+ } -+ -+ if (ovl->info.enabled) { -+ DSSERR("overlay has to be disabled to change the manager\n"); -+ return -EINVAL; -+ } -+ -+ ovl->manager = mgr; -+ -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ /* XXX: on manual update display, in auto update mode, a bug happens -+ * here. When an overlay is first enabled on LCD, then it's disabled, -+ * and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT -+ * errors. Waiting before changing the channel_out fixes it. I'm -+ * guessing that the overlay is still somehow being used for the LCD, -+ * but I don't understand how or why. */ -+ msleep(40); -+ dispc_set_channel_out(ovl->id, mgr->id); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ return 0; -+} -+ -+static int omap_dss_unset_manager(struct omap_overlay *ovl) -+{ -+ int r; -+ -+ if (!ovl->manager) { -+ DSSERR("failed to detach overlay: manager not set\n"); -+ return -EINVAL; -+ } -+ -+ if (ovl->info.enabled) { -+ DSSERR("overlay has to be disabled to unset the manager\n"); -+ return -EINVAL; -+ } -+ -+ r = ovl->wait_for_go(ovl); -+ if (r) -+ return r; -+ -+ ovl->manager = NULL; -+ -+ return 0; -+} -+ -+int omap_dss_get_num_overlays(void) -+{ -+ return num_overlays; -+} -+EXPORT_SYMBOL(omap_dss_get_num_overlays); -+ -+struct omap_overlay *omap_dss_get_overlay(int num) -+{ -+ int i = 0; -+ struct omap_overlay *ovl; -+ -+ list_for_each_entry(ovl, &overlay_list, list) { -+ if (i++ == num) -+ return ovl; -+ } -+ -+ return NULL; -+} -+EXPORT_SYMBOL(omap_dss_get_overlay); -+ -+static void omap_dss_add_overlay(struct omap_overlay *overlay) -+{ -+ ++num_overlays; -+ list_add_tail(&overlay->list, &overlay_list); -+} -+ -+static struct omap_overlay *dispc_overlays[3]; -+ -+void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr) -+{ -+ mgr->num_overlays = 3; -+ mgr->overlays = dispc_overlays; -+} -+ -+#ifdef L4_EXAMPLE -+static struct omap_overlay *l4_overlays[1]; -+void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr) -+{ -+ mgr->num_overlays = 1; -+ mgr->overlays = l4_overlays; -+} -+#endif -+ -+void dss_init_overlays(struct platform_device *pdev) -+{ -+ int i, r; -+ -+ INIT_LIST_HEAD(&overlay_list); -+ -+ num_overlays = 0; -+ -+ for (i = 0; i < 3; ++i) { -+ struct omap_overlay *ovl; -+ ovl = kzalloc(sizeof(*ovl), GFP_KERNEL); -+ -+ BUG_ON(ovl == NULL); -+ -+ switch (i) { -+ case 0: -+ ovl->name = "gfx"; -+ ovl->id = OMAP_DSS_GFX; -+ ovl->supported_modes = OMAP_DSS_COLOR_GFX_OMAP3; -+ ovl->caps = OMAP_DSS_OVL_CAP_DISPC; -+ ovl->info.global_alpha = 255; -+ break; -+ case 1: -+ ovl->name = "vid1"; -+ ovl->id = OMAP_DSS_VIDEO1; -+ ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3; -+ ovl->caps = OMAP_DSS_OVL_CAP_SCALE | -+ OMAP_DSS_OVL_CAP_DISPC; -+ ovl->info.global_alpha = 255; -+ break; -+ case 2: -+ ovl->name = "vid2"; -+ ovl->id = OMAP_DSS_VIDEO2; -+ ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3; -+ ovl->caps = OMAP_DSS_OVL_CAP_SCALE | -+ OMAP_DSS_OVL_CAP_DISPC; -+ ovl->info.global_alpha = 255; -+ break; -+ } -+ -+ ovl->set_manager = &omap_dss_set_manager; -+ ovl->unset_manager = &omap_dss_unset_manager; -+ ovl->set_overlay_info = &dss_ovl_set_overlay_info; -+ ovl->get_overlay_info = &dss_ovl_get_overlay_info; -+ ovl->wait_for_go = &dss_ovl_wait_for_go; -+ -+ omap_dss_add_overlay(ovl); -+ -+ r = kobject_init_and_add(&ovl->kobj, &overlay_ktype, -+ &pdev->dev.kobj, "overlay%d", i); -+ -+ if (r) { -+ DSSERR("failed to create sysfs file\n"); -+ continue; -+ } -+ -+ dispc_overlays[i] = ovl; -+ } -+ -+#ifdef L4_EXAMPLE -+ { -+ struct omap_overlay *ovl; -+ ovl = kzalloc(sizeof(*ovl), GFP_KERNEL); -+ -+ BUG_ON(ovl == NULL); -+ -+ ovl->name = "l4"; -+ ovl->supported_modes = OMAP_DSS_COLOR_RGB24U; -+ -+ ovl->set_manager = &omap_dss_set_manager; -+ ovl->unset_manager = &omap_dss_unset_manager; -+ ovl->set_overlay_info = &dss_ovl_set_overlay_info; -+ ovl->get_overlay_info = &dss_ovl_get_overlay_info; -+ -+ omap_dss_add_overlay(ovl); -+ -+ r = kobject_init_and_add(&ovl->kobj, &overlay_ktype, -+ &pdev->dev.kobj, "overlayl4"); -+ -+ if (r) -+ DSSERR("failed to create sysfs file\n"); -+ -+ l4_overlays[0] = ovl; -+ } -+#endif -+} -+ -+/* connect overlays to the new device, if not already connected. if force -+ * selected, connect always. */ -+void dss_recheck_connections(struct omap_dss_device *dssdev, bool force) -+{ -+ int i; -+ struct omap_overlay_manager *lcd_mgr; -+ struct omap_overlay_manager *tv_mgr; -+ struct omap_overlay_manager *mgr = NULL; -+ -+ lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD); -+ tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV); -+ -+ if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) { -+ if (!lcd_mgr->device || force) { -+ if (lcd_mgr->device) -+ lcd_mgr->unset_device(lcd_mgr); -+ lcd_mgr->set_device(lcd_mgr, dssdev); -+ mgr = lcd_mgr; -+ } -+ } -+ -+ if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { -+ if (!tv_mgr->device || force) { -+ if (tv_mgr->device) -+ tv_mgr->unset_device(tv_mgr); -+ tv_mgr->set_device(tv_mgr, dssdev); -+ mgr = tv_mgr; -+ } -+ } -+ -+ if (mgr) { -+ for (i = 0; i < 3; i++) { -+ struct omap_overlay *ovl; -+ ovl = omap_dss_get_overlay(i); -+ if (!ovl->manager || force) { -+ if (ovl->manager) -+ omap_dss_unset_manager(ovl); -+ omap_dss_set_manager(ovl, mgr); -+ } -+ } -+ } -+} -+ -+void dss_uninit_overlays(struct platform_device *pdev) -+{ -+ struct omap_overlay *ovl; -+ -+ while (!list_empty(&overlay_list)) { -+ ovl = list_first_entry(&overlay_list, -+ struct omap_overlay, list); -+ list_del(&ovl->list); -+ kobject_del(&ovl->kobj); -+ kobject_put(&ovl->kobj); -+ kfree(ovl); -+ } -+ -+ num_overlays = 0; -+} -+ ---- /dev/null -+++ b/drivers/video/omap2/dss/rfbi.c -@@ -0,0 +1,1310 @@ -+/* -+ * linux/drivers/video/omap2/dss/rfbi.c -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#define DSS_SUBSYS_NAME "RFBI" -+ -+#include <linux/kernel.h> -+#include <linux/dma-mapping.h> -+#include <linux/vmalloc.h> -+#include <linux/clk.h> -+#include <linux/io.h> -+#include <linux/delay.h> -+#include <linux/kfifo.h> -+#include <linux/ktime.h> -+#include <linux/hrtimer.h> -+#include <linux/seq_file.h> -+ -+#include <mach/board.h> -+#include <mach/display.h> -+#include "dss.h" -+ -+/*#define MEASURE_PERF*/ -+ -+#define RFBI_BASE 0x48050800 -+ -+struct rfbi_reg { u16 idx; }; -+ -+#define RFBI_REG(idx) ((const struct rfbi_reg) { idx }) -+ -+#define RFBI_REVISION RFBI_REG(0x0000) -+#define RFBI_SYSCONFIG RFBI_REG(0x0010) -+#define RFBI_SYSSTATUS RFBI_REG(0x0014) -+#define RFBI_CONTROL RFBI_REG(0x0040) -+#define RFBI_PIXEL_CNT RFBI_REG(0x0044) -+#define RFBI_LINE_NUMBER RFBI_REG(0x0048) -+#define RFBI_CMD RFBI_REG(0x004c) -+#define RFBI_PARAM RFBI_REG(0x0050) -+#define RFBI_DATA RFBI_REG(0x0054) -+#define RFBI_READ RFBI_REG(0x0058) -+#define RFBI_STATUS RFBI_REG(0x005c) -+ -+#define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18) -+#define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18) -+#define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18) -+#define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18) -+#define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18) -+#define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18) -+ -+#define RFBI_VSYNC_WIDTH RFBI_REG(0x0090) -+#define RFBI_HSYNC_WIDTH RFBI_REG(0x0094) -+ -+#define RFBI_CMD_FIFO_LEN_BYTES (16 * sizeof(struct update_param)) -+ -+#define REG_FLD_MOD(idx, val, start, end) \ -+ rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end)) -+ -+/* To work around an RFBI transfer rate limitation */ -+#define OMAP_RFBI_RATE_LIMIT 1 -+ -+enum omap_rfbi_cycleformat { -+ OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0, -+ OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1, -+ OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2, -+ OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3, -+}; -+ -+enum omap_rfbi_datatype { -+ OMAP_DSS_RFBI_DATATYPE_12 = 0, -+ OMAP_DSS_RFBI_DATATYPE_16 = 1, -+ OMAP_DSS_RFBI_DATATYPE_18 = 2, -+ OMAP_DSS_RFBI_DATATYPE_24 = 3, -+}; -+ -+enum omap_rfbi_parallelmode { -+ OMAP_DSS_RFBI_PARALLELMODE_8 = 0, -+ OMAP_DSS_RFBI_PARALLELMODE_9 = 1, -+ OMAP_DSS_RFBI_PARALLELMODE_12 = 2, -+ OMAP_DSS_RFBI_PARALLELMODE_16 = 3, -+}; -+ -+enum update_cmd { -+ RFBI_CMD_UPDATE = 0, -+ RFBI_CMD_SYNC = 1, -+}; -+ -+static int rfbi_convert_timings(struct rfbi_timings *t); -+static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div); -+static void process_cmd_fifo(void); -+ -+static struct { -+ void __iomem *base; -+ -+ unsigned long l4_khz; -+ -+ enum omap_rfbi_datatype datatype; -+ enum omap_rfbi_parallelmode parallelmode; -+ -+ enum omap_rfbi_te_mode te_mode; -+ int te_enabled; -+ -+ void (*framedone_callback)(void *data); -+ void *framedone_callback_data; -+ -+ struct omap_dss_device *dssdev[2]; -+ -+ struct kfifo *cmd_fifo; -+ spinlock_t cmd_lock; -+ struct completion cmd_done; -+ atomic_t cmd_fifo_full; -+ atomic_t cmd_pending; -+#ifdef MEASURE_PERF -+ unsigned perf_bytes; -+ ktime_t perf_setup_time; -+ ktime_t perf_start_time; -+#endif -+} rfbi; -+ -+struct update_region { -+ u16 x; -+ u16 y; -+ u16 w; -+ u16 h; -+}; -+ -+struct update_param { -+ u8 rfbi_module; -+ u8 cmd; -+ -+ union { -+ struct update_region r; -+ struct completion *sync; -+ } par; -+}; -+ -+static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val) -+{ -+ __raw_writel(val, rfbi.base + idx.idx); -+} -+ -+static inline u32 rfbi_read_reg(const struct rfbi_reg idx) -+{ -+ return __raw_readl(rfbi.base + idx.idx); -+} -+ -+static void rfbi_enable_clocks(bool enable) -+{ -+ if (enable) -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ else -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+} -+ -+void omap_rfbi_write_command(const void *buf, u32 len) -+{ -+ rfbi_enable_clocks(1); -+ switch (rfbi.parallelmode) { -+ case OMAP_DSS_RFBI_PARALLELMODE_8: -+ { -+ const u8 *b = buf; -+ for (; len; len--) -+ rfbi_write_reg(RFBI_CMD, *b++); -+ break; -+ } -+ -+ case OMAP_DSS_RFBI_PARALLELMODE_16: -+ { -+ const u16 *w = buf; -+ BUG_ON(len & 1); -+ for (; len; len -= 2) -+ rfbi_write_reg(RFBI_CMD, *w++); -+ break; -+ } -+ -+ case OMAP_DSS_RFBI_PARALLELMODE_9: -+ case OMAP_DSS_RFBI_PARALLELMODE_12: -+ default: -+ BUG(); -+ } -+ rfbi_enable_clocks(0); -+} -+EXPORT_SYMBOL(omap_rfbi_write_command); -+ -+void omap_rfbi_read_data(void *buf, u32 len) -+{ -+ rfbi_enable_clocks(1); -+ switch (rfbi.parallelmode) { -+ case OMAP_DSS_RFBI_PARALLELMODE_8: -+ { -+ u8 *b = buf; -+ for (; len; len--) { -+ rfbi_write_reg(RFBI_READ, 0); -+ *b++ = rfbi_read_reg(RFBI_READ); -+ } -+ break; -+ } -+ -+ case OMAP_DSS_RFBI_PARALLELMODE_16: -+ { -+ u16 *w = buf; -+ BUG_ON(len & ~1); -+ for (; len; len -= 2) { -+ rfbi_write_reg(RFBI_READ, 0); -+ *w++ = rfbi_read_reg(RFBI_READ); -+ } -+ break; -+ } -+ -+ case OMAP_DSS_RFBI_PARALLELMODE_9: -+ case OMAP_DSS_RFBI_PARALLELMODE_12: -+ default: -+ BUG(); -+ } -+ rfbi_enable_clocks(0); -+} -+EXPORT_SYMBOL(omap_rfbi_read_data); -+ -+void omap_rfbi_write_data(const void *buf, u32 len) -+{ -+ rfbi_enable_clocks(1); -+ switch (rfbi.parallelmode) { -+ case OMAP_DSS_RFBI_PARALLELMODE_8: -+ { -+ const u8 *b = buf; -+ for (; len; len--) -+ rfbi_write_reg(RFBI_PARAM, *b++); -+ break; -+ } -+ -+ case OMAP_DSS_RFBI_PARALLELMODE_16: -+ { -+ const u16 *w = buf; -+ BUG_ON(len & 1); -+ for (; len; len -= 2) -+ rfbi_write_reg(RFBI_PARAM, *w++); -+ break; -+ } -+ -+ case OMAP_DSS_RFBI_PARALLELMODE_9: -+ case OMAP_DSS_RFBI_PARALLELMODE_12: -+ default: -+ BUG(); -+ -+ } -+ rfbi_enable_clocks(0); -+} -+EXPORT_SYMBOL(omap_rfbi_write_data); -+ -+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, -+ u16 x, u16 y, -+ u16 w, u16 h) -+{ -+ int start_offset = scr_width * y + x; -+ int horiz_offset = scr_width - w; -+ int i; -+ -+ rfbi_enable_clocks(1); -+ -+ if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 && -+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) { -+ const u16 __iomem *pd = buf; -+ pd += start_offset; -+ -+ for (; h; --h) { -+ for (i = 0; i < w; ++i) { -+ const u8 __iomem *b = (const u8 __iomem *)pd; -+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1)); -+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0)); -+ ++pd; -+ } -+ pd += horiz_offset; -+ } -+ } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 && -+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) { -+ const u32 __iomem *pd = buf; -+ pd += start_offset; -+ -+ for (; h; --h) { -+ for (i = 0; i < w; ++i) { -+ const u8 __iomem *b = (const u8 __iomem *)pd; -+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2)); -+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1)); -+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0)); -+ ++pd; -+ } -+ pd += horiz_offset; -+ } -+ } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 && -+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) { -+ const u16 __iomem *pd = buf; -+ pd += start_offset; -+ -+ for (; h; --h) { -+ for (i = 0; i < w; ++i) { -+ rfbi_write_reg(RFBI_PARAM, __raw_readw(pd)); -+ ++pd; -+ } -+ pd += horiz_offset; -+ } -+ } else { -+ BUG(); -+ } -+ -+ rfbi_enable_clocks(0); -+} -+EXPORT_SYMBOL(omap_rfbi_write_pixels); -+ -+#ifdef MEASURE_PERF -+static void perf_mark_setup(void) -+{ -+ rfbi.perf_setup_time = ktime_get(); -+} -+ -+static void perf_mark_start(void) -+{ -+ rfbi.perf_start_time = ktime_get(); -+} -+ -+static void perf_show(const char *name) -+{ -+ ktime_t t, setup_time, trans_time; -+ u32 total_bytes; -+ u32 setup_us, trans_us, total_us; -+ -+ t = ktime_get(); -+ -+ setup_time = ktime_sub(rfbi.perf_start_time, rfbi.perf_setup_time); -+ setup_us = (u32)ktime_to_us(setup_time); -+ if (setup_us == 0) -+ setup_us = 1; -+ -+ trans_time = ktime_sub(t, rfbi.perf_start_time); -+ trans_us = (u32)ktime_to_us(trans_time); -+ if (trans_us == 0) -+ trans_us = 1; -+ -+ total_us = setup_us + trans_us; -+ -+ total_bytes = rfbi.perf_bytes; -+ -+ DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, " -+ "%u kbytes/sec\n", -+ name, -+ setup_us, -+ trans_us, -+ total_us, -+ 1000*1000 / total_us, -+ total_bytes, -+ total_bytes * 1000 / total_us); -+} -+#else -+#define perf_mark_setup() -+#define perf_mark_start() -+#define perf_show(x) -+#endif -+ -+void rfbi_transfer_area(u16 width, u16 height, -+ void (callback)(void *data), void *data) -+{ -+ u32 l; -+ -+ /*BUG_ON(callback == 0);*/ -+ BUG_ON(rfbi.framedone_callback != NULL); -+ -+ DSSDBG("rfbi_transfer_area %dx%d\n", width, height); -+ -+ dispc_set_lcd_size(width, height); -+ -+ dispc_enable_lcd_out(1); -+ -+ rfbi.framedone_callback = callback; -+ rfbi.framedone_callback_data = data; -+ -+ rfbi_enable_clocks(1); -+ -+ rfbi_write_reg(RFBI_PIXEL_CNT, width * height); -+ -+ l = rfbi_read_reg(RFBI_CONTROL); -+ l = FLD_MOD(l, 1, 0, 0); /* enable */ -+ if (!rfbi.te_enabled) -+ l = FLD_MOD(l, 1, 4, 4); /* ITE */ -+ -+ perf_mark_start(); -+ -+ rfbi_write_reg(RFBI_CONTROL, l); -+} -+ -+static void framedone_callback(void *data, u32 mask) -+{ -+ void (*callback)(void *data); -+ -+ DSSDBG("FRAMEDONE\n"); -+ -+ perf_show("DISPC"); -+ -+ REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0); -+ -+ rfbi_enable_clocks(0); -+ -+ callback = rfbi.framedone_callback; -+ rfbi.framedone_callback = NULL; -+ -+ /*callback(rfbi.framedone_callback_data);*/ -+ -+ atomic_set(&rfbi.cmd_pending, 0); -+ -+ process_cmd_fifo(); -+} -+ -+#if 1 /* VERBOSE */ -+static void rfbi_print_timings(void) -+{ -+ u32 l; -+ u32 time; -+ -+ l = rfbi_read_reg(RFBI_CONFIG(0)); -+ time = 1000000000 / rfbi.l4_khz; -+ if (l & (1 << 4)) -+ time *= 2; -+ -+ DSSDBG("Tick time %u ps\n", time); -+ l = rfbi_read_reg(RFBI_ONOFF_TIME(0)); -+ DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, " -+ "REONTIME %d, REOFFTIME %d\n", -+ l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f, -+ (l >> 20) & 0x0f, (l >> 24) & 0x3f); -+ -+ l = rfbi_read_reg(RFBI_CYCLE_TIME(0)); -+ DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, " -+ "ACCESSTIME %d\n", -+ (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f, -+ (l >> 22) & 0x3f); -+} -+#else -+static void rfbi_print_timings(void) {} -+#endif -+ -+ -+ -+ -+static u32 extif_clk_period; -+ -+static inline unsigned long round_to_extif_ticks(unsigned long ps, int div) -+{ -+ int bus_tick = extif_clk_period * div; -+ return (ps + bus_tick - 1) / bus_tick * bus_tick; -+} -+ -+static int calc_reg_timing(struct rfbi_timings *t, int div) -+{ -+ t->clk_div = div; -+ -+ t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div); -+ -+ t->we_on_time = round_to_extif_ticks(t->we_on_time, div); -+ t->we_off_time = round_to_extif_ticks(t->we_off_time, div); -+ t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div); -+ -+ t->re_on_time = round_to_extif_ticks(t->re_on_time, div); -+ t->re_off_time = round_to_extif_ticks(t->re_off_time, div); -+ t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div); -+ -+ t->access_time = round_to_extif_ticks(t->access_time, div); -+ t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div); -+ t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div); -+ -+ DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n", -+ t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time); -+ DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n", -+ t->we_on_time, t->we_off_time, t->re_cycle_time, -+ t->we_cycle_time); -+ DSSDBG("[reg]rdaccess %d cspulse %d\n", -+ t->access_time, t->cs_pulse_width); -+ -+ return rfbi_convert_timings(t); -+} -+ -+static int calc_extif_timings(struct rfbi_timings *t) -+{ -+ u32 max_clk_div; -+ int div; -+ -+ rfbi_get_clk_info(&extif_clk_period, &max_clk_div); -+ for (div = 1; div <= max_clk_div; div++) { -+ if (calc_reg_timing(t, div) == 0) -+ break; -+ } -+ -+ if (div <= max_clk_div) -+ return 0; -+ -+ DSSERR("can't setup timings\n"); -+ return -1; -+} -+ -+ -+void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t) -+{ -+ int r; -+ -+ if (!t->converted) { -+ r = calc_extif_timings(t); -+ if (r < 0) -+ DSSERR("Failed to calc timings\n"); -+ } -+ -+ BUG_ON(!t->converted); -+ -+ rfbi_enable_clocks(1); -+ rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]); -+ rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]); -+ -+ /* TIMEGRANULARITY */ -+ REG_FLD_MOD(RFBI_CONFIG(rfbi_module), -+ (t->tim[2] ? 1 : 0), 4, 4); -+ -+ rfbi_print_timings(); -+ rfbi_enable_clocks(0); -+} -+ -+static int ps_to_rfbi_ticks(int time, int div) -+{ -+ unsigned long tick_ps; -+ int ret; -+ -+ /* Calculate in picosecs to yield more exact results */ -+ tick_ps = 1000000000 / (rfbi.l4_khz) * div; -+ -+ ret = (time + tick_ps - 1) / tick_ps; -+ -+ return ret; -+} -+ -+#ifdef OMAP_RFBI_RATE_LIMIT -+unsigned long rfbi_get_max_tx_rate(void) -+{ -+ unsigned long l4_rate, dss1_rate; -+ int min_l4_ticks = 0; -+ int i; -+ -+ /* According to TI this can't be calculated so make the -+ * adjustments for a couple of known frequencies and warn for -+ * others. -+ */ -+ static const struct { -+ unsigned long l4_clk; /* HZ */ -+ unsigned long dss1_clk; /* HZ */ -+ unsigned long min_l4_ticks; -+ } ftab[] = { -+ { 55, 132, 7, }, /* 7.86 MPix/s */ -+ { 110, 110, 12, }, /* 9.16 MPix/s */ -+ { 110, 132, 10, }, /* 11 Mpix/s */ -+ { 120, 120, 10, }, /* 12 Mpix/s */ -+ { 133, 133, 10, }, /* 13.3 Mpix/s */ -+ }; -+ -+ l4_rate = rfbi.l4_khz / 1000; -+ dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000; -+ -+ for (i = 0; i < ARRAY_SIZE(ftab); i++) { -+ /* Use a window instead of an exact match, to account -+ * for different DPLL multiplier / divider pairs. -+ */ -+ if (abs(ftab[i].l4_clk - l4_rate) < 3 && -+ abs(ftab[i].dss1_clk - dss1_rate) < 3) { -+ min_l4_ticks = ftab[i].min_l4_ticks; -+ break; -+ } -+ } -+ if (i == ARRAY_SIZE(ftab)) { -+ /* Can't be sure, return anyway the maximum not -+ * rate-limited. This might cause a problem only for the -+ * tearing synchronisation. -+ */ -+ DSSERR("can't determine maximum RFBI transfer rate\n"); -+ return rfbi.l4_khz * 1000; -+ } -+ return rfbi.l4_khz * 1000 / min_l4_ticks; -+} -+#else -+int rfbi_get_max_tx_rate(void) -+{ -+ return rfbi.l4_khz * 1000; -+} -+#endif -+ -+static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div) -+{ -+ *clk_period = 1000000000 / rfbi.l4_khz; -+ *max_clk_div = 2; -+} -+ -+static int rfbi_convert_timings(struct rfbi_timings *t) -+{ -+ u32 l; -+ int reon, reoff, weon, weoff, cson, csoff, cs_pulse; -+ int actim, recyc, wecyc; -+ int div = t->clk_div; -+ -+ if (div <= 0 || div > 2) -+ return -1; -+ -+ /* Make sure that after conversion it still holds that: -+ * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff, -+ * csoff > cson, csoff >= max(weoff, reoff), actim > reon -+ */ -+ weon = ps_to_rfbi_ticks(t->we_on_time, div); -+ weoff = ps_to_rfbi_ticks(t->we_off_time, div); -+ if (weoff <= weon) -+ weoff = weon + 1; -+ if (weon > 0x0f) -+ return -1; -+ if (weoff > 0x3f) -+ return -1; -+ -+ reon = ps_to_rfbi_ticks(t->re_on_time, div); -+ reoff = ps_to_rfbi_ticks(t->re_off_time, div); -+ if (reoff <= reon) -+ reoff = reon + 1; -+ if (reon > 0x0f) -+ return -1; -+ if (reoff > 0x3f) -+ return -1; -+ -+ cson = ps_to_rfbi_ticks(t->cs_on_time, div); -+ csoff = ps_to_rfbi_ticks(t->cs_off_time, div); -+ if (csoff <= cson) -+ csoff = cson + 1; -+ if (csoff < max(weoff, reoff)) -+ csoff = max(weoff, reoff); -+ if (cson > 0x0f) -+ return -1; -+ if (csoff > 0x3f) -+ return -1; -+ -+ l = cson; -+ l |= csoff << 4; -+ l |= weon << 10; -+ l |= weoff << 14; -+ l |= reon << 20; -+ l |= reoff << 24; -+ -+ t->tim[0] = l; -+ -+ actim = ps_to_rfbi_ticks(t->access_time, div); -+ if (actim <= reon) -+ actim = reon + 1; -+ if (actim > 0x3f) -+ return -1; -+ -+ wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div); -+ if (wecyc < weoff) -+ wecyc = weoff; -+ if (wecyc > 0x3f) -+ return -1; -+ -+ recyc = ps_to_rfbi_ticks(t->re_cycle_time, div); -+ if (recyc < reoff) -+ recyc = reoff; -+ if (recyc > 0x3f) -+ return -1; -+ -+ cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div); -+ if (cs_pulse > 0x3f) -+ return -1; -+ -+ l = wecyc; -+ l |= recyc << 6; -+ l |= cs_pulse << 12; -+ l |= actim << 22; -+ -+ t->tim[1] = l; -+ -+ t->tim[2] = div - 1; -+ -+ t->converted = 1; -+ -+ return 0; -+} -+ -+/* xxx FIX module selection missing */ -+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, -+ unsigned hs_pulse_time, unsigned vs_pulse_time, -+ int hs_pol_inv, int vs_pol_inv, int extif_div) -+{ -+ int hs, vs; -+ int min; -+ u32 l; -+ -+ hs = ps_to_rfbi_ticks(hs_pulse_time, 1); -+ vs = ps_to_rfbi_ticks(vs_pulse_time, 1); -+ if (hs < 2) -+ return -EDOM; -+ if (mode == OMAP_DSS_RFBI_TE_MODE_2) -+ min = 2; -+ else /* OMAP_DSS_RFBI_TE_MODE_1 */ -+ min = 4; -+ if (vs < min) -+ return -EDOM; -+ if (vs == hs) -+ return -EINVAL; -+ rfbi.te_mode = mode; -+ DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n", -+ mode, hs, vs, hs_pol_inv, vs_pol_inv); -+ -+ rfbi_enable_clocks(1); -+ rfbi_write_reg(RFBI_HSYNC_WIDTH, hs); -+ rfbi_write_reg(RFBI_VSYNC_WIDTH, vs); -+ -+ l = rfbi_read_reg(RFBI_CONFIG(0)); -+ if (hs_pol_inv) -+ l &= ~(1 << 21); -+ else -+ l |= 1 << 21; -+ if (vs_pol_inv) -+ l &= ~(1 << 20); -+ else -+ l |= 1 << 20; -+ rfbi_enable_clocks(0); -+ -+ return 0; -+} -+EXPORT_SYMBOL(omap_rfbi_setup_te); -+ -+/* xxx FIX module selection missing */ -+int omap_rfbi_enable_te(bool enable, unsigned line) -+{ -+ u32 l; -+ -+ DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode); -+ if (line > (1 << 11) - 1) -+ return -EINVAL; -+ -+ rfbi_enable_clocks(1); -+ l = rfbi_read_reg(RFBI_CONFIG(0)); -+ l &= ~(0x3 << 2); -+ if (enable) { -+ rfbi.te_enabled = 1; -+ l |= rfbi.te_mode << 2; -+ } else -+ rfbi.te_enabled = 0; -+ rfbi_write_reg(RFBI_CONFIG(0), l); -+ rfbi_write_reg(RFBI_LINE_NUMBER, line); -+ rfbi_enable_clocks(0); -+ -+ return 0; -+} -+EXPORT_SYMBOL(omap_rfbi_enable_te); -+ -+#if 0 -+static void rfbi_enable_config(int enable1, int enable2) -+{ -+ u32 l; -+ int cs = 0; -+ -+ if (enable1) -+ cs |= 1<<0; -+ if (enable2) -+ cs |= 1<<1; -+ -+ rfbi_enable_clocks(1); -+ -+ l = rfbi_read_reg(RFBI_CONTROL); -+ -+ l = FLD_MOD(l, cs, 3, 2); -+ l = FLD_MOD(l, 0, 1, 1); -+ -+ rfbi_write_reg(RFBI_CONTROL, l); -+ -+ -+ l = rfbi_read_reg(RFBI_CONFIG(0)); -+ l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */ -+ /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */ -+ /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */ -+ -+ l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */ -+ l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */ -+ l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */ -+ -+ l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0); -+ rfbi_write_reg(RFBI_CONFIG(0), l); -+ -+ rfbi_enable_clocks(0); -+} -+#endif -+ -+int rfbi_configure(int rfbi_module, int bpp, int lines) -+{ -+ u32 l; -+ int cycle1 = 0, cycle2 = 0, cycle3 = 0; -+ enum omap_rfbi_cycleformat cycleformat; -+ enum omap_rfbi_datatype datatype; -+ enum omap_rfbi_parallelmode parallelmode; -+ -+ switch (bpp) { -+ case 12: -+ datatype = OMAP_DSS_RFBI_DATATYPE_12; -+ break; -+ case 16: -+ datatype = OMAP_DSS_RFBI_DATATYPE_16; -+ break; -+ case 18: -+ datatype = OMAP_DSS_RFBI_DATATYPE_18; -+ break; -+ case 24: -+ datatype = OMAP_DSS_RFBI_DATATYPE_24; -+ break; -+ default: -+ BUG(); -+ return 1; -+ } -+ rfbi.datatype = datatype; -+ -+ switch (lines) { -+ case 8: -+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8; -+ break; -+ case 9: -+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9; -+ break; -+ case 12: -+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12; -+ break; -+ case 16: -+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16; -+ break; -+ default: -+ BUG(); -+ return 1; -+ } -+ rfbi.parallelmode = parallelmode; -+ -+ if ((bpp % lines) == 0) { -+ switch (bpp / lines) { -+ case 1: -+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1; -+ break; -+ case 2: -+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1; -+ break; -+ case 3: -+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1; -+ break; -+ default: -+ BUG(); -+ return 1; -+ } -+ } else if ((2 * bpp % lines) == 0) { -+ if ((2 * bpp / lines) == 3) -+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2; -+ else { -+ BUG(); -+ return 1; -+ } -+ } else { -+ BUG(); -+ return 1; -+ } -+ -+ switch (cycleformat) { -+ case OMAP_DSS_RFBI_CYCLEFORMAT_1_1: -+ cycle1 = lines; -+ break; -+ -+ case OMAP_DSS_RFBI_CYCLEFORMAT_2_1: -+ cycle1 = lines; -+ cycle2 = lines; -+ break; -+ -+ case OMAP_DSS_RFBI_CYCLEFORMAT_3_1: -+ cycle1 = lines; -+ cycle2 = lines; -+ cycle3 = lines; -+ break; -+ -+ case OMAP_DSS_RFBI_CYCLEFORMAT_3_2: -+ cycle1 = lines; -+ cycle2 = (lines / 2) | ((lines / 2) << 16); -+ cycle3 = (lines << 16); -+ break; -+ } -+ -+ rfbi_enable_clocks(1); -+ -+ REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */ -+ -+ l = 0; -+ l |= FLD_VAL(parallelmode, 1, 0); -+ l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */ -+ l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */ -+ l |= FLD_VAL(datatype, 6, 5); -+ /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */ -+ l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */ -+ l |= FLD_VAL(cycleformat, 10, 9); -+ l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */ -+ l |= FLD_VAL(0, 16, 16); /* A0POLARITY */ -+ l |= FLD_VAL(0, 17, 17); /* REPOLARITY */ -+ l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */ -+ l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */ -+ l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */ -+ l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */ -+ rfbi_write_reg(RFBI_CONFIG(rfbi_module), l); -+ -+ rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1); -+ rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2); -+ rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3); -+ -+ -+ l = rfbi_read_reg(RFBI_CONTROL); -+ l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */ -+ l = FLD_MOD(l, 0, 1, 1); /* clear bypass */ -+ rfbi_write_reg(RFBI_CONTROL, l); -+ -+ -+ DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n", -+ bpp, lines, cycle1, cycle2, cycle3); -+ -+ rfbi_enable_clocks(0); -+ -+ return 0; -+} -+EXPORT_SYMBOL(rfbi_configure); -+ -+static int rfbi_find_display(struct omap_dss_device *dssdev) -+{ -+ if (dssdev == rfbi.dssdev[0]) -+ return 0; -+ -+ if (dssdev == rfbi.dssdev[1]) -+ return 1; -+ -+ BUG(); -+ return -1; -+} -+ -+ -+static void signal_fifo_waiters(void) -+{ -+ if (atomic_read(&rfbi.cmd_fifo_full) > 0) { -+ /* DSSDBG("SIGNALING: Fifo not full for waiter!\n"); */ -+ complete(&rfbi.cmd_done); -+ atomic_dec(&rfbi.cmd_fifo_full); -+ } -+} -+ -+/* returns 1 for async op, and 0 for sync op */ -+static int do_update(struct omap_dss_device *dssdev, struct update_region *upd) -+{ -+ u16 x = upd->x; -+ u16 y = upd->y; -+ u16 w = upd->w; -+ u16 h = upd->h; -+ -+ perf_mark_setup(); -+ -+ if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { -+ /*dssdev->driver->enable_te(dssdev, 1); */ -+ dss_setup_partial_planes(dssdev, &x, &y, &w, &h); -+ } -+ -+#ifdef MEASURE_PERF -+ rfbi.perf_bytes = w * h * 2; /* XXX always 16bit */ -+#endif -+ -+ dssdev->driver->setup_update(dssdev, x, y, w, h); -+ -+ if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { -+ rfbi_transfer_area(w, h, NULL, NULL); -+ return 1; -+ } else { -+ struct omap_overlay *ovl; -+ void __iomem *addr; -+ int scr_width; -+ -+ ovl = dssdev->manager->overlays[0]; -+ scr_width = ovl->info.screen_width; -+ addr = ovl->info.vaddr; -+ -+ omap_rfbi_write_pixels(addr, scr_width, x, y, w, h); -+ -+ perf_show("L4"); -+ -+ return 0; -+ } -+} -+ -+static void process_cmd_fifo(void) -+{ -+ int len; -+ struct update_param p; -+ struct omap_dss_device *dssdev; -+ unsigned long flags; -+ -+ if (atomic_inc_return(&rfbi.cmd_pending) != 1) -+ return; -+ -+ while (true) { -+ spin_lock_irqsave(rfbi.cmd_fifo->lock, flags); -+ -+ len = __kfifo_get(rfbi.cmd_fifo, (unsigned char *)&p, -+ sizeof(struct update_param)); -+ if (len == 0) { -+ DSSDBG("nothing more in fifo\n"); -+ atomic_set(&rfbi.cmd_pending, 0); -+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags); -+ break; -+ } -+ -+ /* DSSDBG("fifo full %d\n", rfbi.cmd_fifo_full.counter);*/ -+ -+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags); -+ -+ BUG_ON(len != sizeof(struct update_param)); -+ BUG_ON(p.rfbi_module > 1); -+ -+ dssdev = rfbi.dssdev[p.rfbi_module]; -+ -+ if (p.cmd == RFBI_CMD_UPDATE) { -+ if (do_update(dssdev, &p.par.r)) -+ break; /* async op */ -+ } else if (p.cmd == RFBI_CMD_SYNC) { -+ DSSDBG("Signaling SYNC done!\n"); -+ complete(p.par.sync); -+ } else -+ BUG(); -+ } -+ -+ signal_fifo_waiters(); -+} -+ -+static void rfbi_push_cmd(struct update_param *p) -+{ -+ int ret; -+ -+ while (1) { -+ unsigned long flags; -+ int available; -+ -+ spin_lock_irqsave(rfbi.cmd_fifo->lock, flags); -+ available = RFBI_CMD_FIFO_LEN_BYTES - -+ __kfifo_len(rfbi.cmd_fifo); -+ -+/* DSSDBG("%d bytes left in fifo\n", available); */ -+ if (available < sizeof(struct update_param)) { -+ DSSDBG("Going to wait because FIFO FULL..\n"); -+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags); -+ atomic_inc(&rfbi.cmd_fifo_full); -+ wait_for_completion(&rfbi.cmd_done); -+ /*DSSDBG("Woke up because fifo not full anymore\n");*/ -+ continue; -+ } -+ -+ ret = __kfifo_put(rfbi.cmd_fifo, (unsigned char *)p, -+ sizeof(struct update_param)); -+/* DSSDBG("pushed %d bytes\n", ret);*/ -+ -+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags); -+ -+ BUG_ON(ret != sizeof(struct update_param)); -+ -+ break; -+ } -+} -+ -+static void rfbi_push_update(int rfbi_module, int x, int y, int w, int h) -+{ -+ struct update_param p; -+ -+ p.rfbi_module = rfbi_module; -+ p.cmd = RFBI_CMD_UPDATE; -+ -+ p.par.r.x = x; -+ p.par.r.y = y; -+ p.par.r.w = w; -+ p.par.r.h = h; -+ -+ DSSDBG("RFBI pushed %d,%d %dx%d\n", x, y, w, h); -+ -+ rfbi_push_cmd(&p); -+ -+ process_cmd_fifo(); -+} -+ -+static void rfbi_push_sync(int rfbi_module, struct completion *sync_comp) -+{ -+ struct update_param p; -+ -+ p.rfbi_module = rfbi_module; -+ p.cmd = RFBI_CMD_SYNC; -+ p.par.sync = sync_comp; -+ -+ rfbi_push_cmd(&p); -+ -+ DSSDBG("RFBI sync pushed to cmd fifo\n"); -+ -+ process_cmd_fifo(); -+} -+ -+void rfbi_dump_regs(struct seq_file *s) -+{ -+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r)) -+ -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ DUMPREG(RFBI_REVISION); -+ DUMPREG(RFBI_SYSCONFIG); -+ DUMPREG(RFBI_SYSSTATUS); -+ DUMPREG(RFBI_CONTROL); -+ DUMPREG(RFBI_PIXEL_CNT); -+ DUMPREG(RFBI_LINE_NUMBER); -+ DUMPREG(RFBI_CMD); -+ DUMPREG(RFBI_PARAM); -+ DUMPREG(RFBI_DATA); -+ DUMPREG(RFBI_READ); -+ DUMPREG(RFBI_STATUS); -+ -+ DUMPREG(RFBI_CONFIG(0)); -+ DUMPREG(RFBI_ONOFF_TIME(0)); -+ DUMPREG(RFBI_CYCLE_TIME(0)); -+ DUMPREG(RFBI_DATA_CYCLE1(0)); -+ DUMPREG(RFBI_DATA_CYCLE2(0)); -+ DUMPREG(RFBI_DATA_CYCLE3(0)); -+ -+ DUMPREG(RFBI_CONFIG(1)); -+ DUMPREG(RFBI_ONOFF_TIME(1)); -+ DUMPREG(RFBI_CYCLE_TIME(1)); -+ DUMPREG(RFBI_DATA_CYCLE1(1)); -+ DUMPREG(RFBI_DATA_CYCLE2(1)); -+ DUMPREG(RFBI_DATA_CYCLE3(1)); -+ -+ DUMPREG(RFBI_VSYNC_WIDTH); -+ DUMPREG(RFBI_HSYNC_WIDTH); -+ -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+#undef DUMPREG -+} -+ -+int rfbi_init(void) -+{ -+ u32 rev; -+ u32 l; -+ -+ spin_lock_init(&rfbi.cmd_lock); -+ rfbi.cmd_fifo = kfifo_alloc(RFBI_CMD_FIFO_LEN_BYTES, GFP_KERNEL, -+ &rfbi.cmd_lock); -+ if (IS_ERR(rfbi.cmd_fifo)) -+ return -ENOMEM; -+ -+ init_completion(&rfbi.cmd_done); -+ atomic_set(&rfbi.cmd_fifo_full, 0); -+ atomic_set(&rfbi.cmd_pending, 0); -+ -+ rfbi.base = ioremap(RFBI_BASE, SZ_256); -+ if (!rfbi.base) { -+ DSSERR("can't ioremap RFBI\n"); -+ return -ENOMEM; -+ } -+ -+ rfbi_enable_clocks(1); -+ -+ msleep(10); -+ -+ rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000; -+ -+ /* Enable autoidle and smart-idle */ -+ l = rfbi_read_reg(RFBI_SYSCONFIG); -+ l |= (1 << 0) | (2 << 3); -+ rfbi_write_reg(RFBI_SYSCONFIG, l); -+ -+ rev = rfbi_read_reg(RFBI_REVISION); -+ printk(KERN_INFO "OMAP RFBI rev %d.%d\n", -+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); -+ -+ rfbi_enable_clocks(0); -+ -+ return 0; -+} -+ -+void rfbi_exit(void) -+{ -+ DSSDBG("rfbi_exit\n"); -+ -+ kfifo_free(rfbi.cmd_fifo); -+ -+ iounmap(rfbi.base); -+} -+ -+/* struct omap_display support */ -+static int rfbi_display_update(struct omap_dss_device *dssdev, -+ u16 x, u16 y, u16 w, u16 h) -+{ -+ int rfbi_module; -+ -+ if (w == 0 || h == 0) -+ return 0; -+ -+ rfbi_module = rfbi_find_display(dssdev); -+ -+ rfbi_push_update(rfbi_module, x, y, w, h); -+ -+ return 0; -+} -+ -+static int rfbi_display_sync(struct omap_dss_device *dssdev) -+{ -+ struct completion sync_comp; -+ int rfbi_module; -+ -+ rfbi_module = rfbi_find_display(dssdev); -+ -+ init_completion(&sync_comp); -+ rfbi_push_sync(rfbi_module, &sync_comp); -+ DSSDBG("Waiting for SYNC to happen...\n"); -+ wait_for_completion(&sync_comp); -+ DSSDBG("Released from SYNC\n"); -+ return 0; -+} -+ -+static int rfbi_display_enable_te(struct omap_dss_device *dssdev, bool enable) -+{ -+ dssdev->driver->enable_te(dssdev, enable); -+ return 0; -+} -+ -+static int rfbi_display_enable(struct omap_dss_device *dssdev) -+{ -+ int r; -+ -+ r = omap_dss_start_device(dssdev); -+ if (r) { -+ DSSERR("failed to start device\n"); -+ goto err0; -+ } -+ -+ r = omap_dispc_register_isr(framedone_callback, NULL, -+ DISPC_IRQ_FRAMEDONE); -+ if (r) { -+ DSSERR("can't get FRAMEDONE irq\n"); -+ goto err1; -+ } -+ -+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT); -+ -+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI); -+ -+ dispc_set_tft_data_lines(dssdev->ctrl.pixel_size); -+ -+ rfbi_configure(dssdev->phy.rfbi.channel, -+ dssdev->ctrl.pixel_size, -+ dssdev->phy.rfbi.data_lines); -+ -+ rfbi_set_timings(dssdev->phy.rfbi.channel, -+ &dssdev->ctrl.rfbi_timings); -+ -+ -+ if (dssdev->driver->enable) { -+ r = dssdev->driver->enable(dssdev); -+ if (r) -+ goto err2; -+ } -+ -+ return 0; -+err2: -+ omap_dispc_unregister_isr(framedone_callback, NULL, -+ DISPC_IRQ_FRAMEDONE); -+err1: -+ omap_dss_stop_device(dssdev); -+err0: -+ return r; -+} -+ -+static void rfbi_display_disable(struct omap_dss_device *dssdev) -+{ -+ dssdev->driver->disable(dssdev); -+ omap_dispc_unregister_isr(framedone_callback, NULL, -+ DISPC_IRQ_FRAMEDONE); -+ omap_dss_stop_device(dssdev); -+} -+ -+int rfbi_init_display(struct omap_dss_device *dssdev) -+{ -+ dssdev->enable = rfbi_display_enable; -+ dssdev->disable = rfbi_display_disable; -+ dssdev->update = rfbi_display_update; -+ dssdev->sync = rfbi_display_sync; -+ dssdev->enable_te = rfbi_display_enable_te; -+ -+ rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev; -+ -+ dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE; -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/video/omap2/dss/sdi.c -@@ -0,0 +1,261 @@ -+/* -+ * linux/drivers/video/omap2/dss/sdi.c -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#define DSS_SUBSYS_NAME "SDI" -+ -+#include <linux/kernel.h> -+#include <linux/clk.h> -+#include <linux/delay.h> -+#include <linux/err.h> -+ -+#include <mach/board.h> -+#include <mach/display.h> -+#include "dss.h" -+ -+static struct { -+ bool skip_init; -+ bool update_enabled; -+} sdi; -+ -+static void sdi_basic_init(void) -+{ -+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS); -+ -+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT); -+ dispc_set_tft_data_lines(24); -+ dispc_lcd_enable_signal_polarity(1); -+} -+ -+static int sdi_display_enable(struct omap_dss_device *dssdev) -+{ -+ struct omap_video_timings *t = &dssdev->panel.timings; -+ struct dispc_clock_info cinfo; -+ u16 lck_div, pck_div; -+ unsigned long fck; -+ unsigned long pck; -+ int r; -+ -+ r = omap_dss_start_device(dssdev); -+ if (r) { -+ DSSERR("failed to start device\n"); -+ goto err0; -+ } -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { -+ DSSERR("dssdev already enabled\n"); -+ r = -EINVAL; -+ goto err1; -+ } -+ -+ /* In case of skip_init sdi_init has already enabled the clocks */ -+ if (!sdi.skip_init) -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ sdi_basic_init(); -+ -+ /* 15.5.9.1.2 */ -+ dssdev->panel.config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF; -+ -+ dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi, -+ dssdev->panel.acb); -+ -+ if (!sdi.skip_init) -+ r = dispc_calc_clock_div(1, t->pixel_clock * 1000, -+ &cinfo); -+ else -+ r = dispc_get_clock_div(&cinfo); -+ -+ if (r) -+ goto err2; -+ -+ fck = cinfo.fck; -+ lck_div = cinfo.lck_div; -+ pck_div = cinfo.pck_div; -+ -+ pck = fck / lck_div / pck_div / 1000; -+ -+ if (pck != t->pixel_clock) { -+ DSSWARN("Could not find exact pixel clock. Requested %d kHz, " -+ "got %lu kHz\n", -+ t->pixel_clock, pck); -+ -+ t->pixel_clock = pck; -+ } -+ -+ -+ dispc_set_lcd_timings(t); -+ -+ r = dispc_set_clock_div(&cinfo); -+ if (r) -+ goto err2; -+ -+ if (!sdi.skip_init) { -+ dss_sdi_init(dssdev->phy.sdi.datapairs); -+ dss_sdi_enable(); -+ mdelay(2); -+ } -+ -+ dispc_enable_lcd_out(1); -+ -+ if (dssdev->driver->enable) { -+ r = dssdev->driver->enable(dssdev); -+ if (r) -+ goto err3; -+ } -+ -+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -+ -+ sdi.skip_init = 0; -+ -+ return 0; -+err3: -+ dispc_enable_lcd_out(0); -+err2: -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+err1: -+ omap_dss_stop_device(dssdev); -+err0: -+ return r; -+} -+ -+static int sdi_display_resume(struct omap_dss_device *dssdev); -+ -+static void sdi_display_disable(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED) -+ return; -+ -+ if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) -+ sdi_display_resume(dssdev); -+ -+ if (dssdev->driver->disable) -+ dssdev->driver->disable(dssdev); -+ -+ dispc_enable_lcd_out(0); -+ -+ dss_sdi_disable(); -+ -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ dssdev->state = OMAP_DSS_DISPLAY_DISABLED; -+ -+ omap_dss_stop_device(dssdev); -+} -+ -+static int sdi_display_suspend(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) -+ return -EINVAL; -+ -+ if (dssdev->driver->suspend) -+ dssdev->driver->suspend(dssdev); -+ -+ dispc_enable_lcd_out(0); -+ -+ dss_sdi_disable(); -+ -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; -+ -+ return 0; -+} -+ -+static int sdi_display_resume(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) -+ return -EINVAL; -+ -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ -+ dss_sdi_enable(); -+ mdelay(2); -+ -+ dispc_enable_lcd_out(1); -+ -+ if (dssdev->driver->resume) -+ dssdev->driver->resume(dssdev); -+ -+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -+ -+ return 0; -+} -+ -+static int sdi_display_set_update_mode(struct omap_dss_device *dssdev, -+ enum omap_dss_update_mode mode) -+{ -+ if (mode == OMAP_DSS_UPDATE_MANUAL) -+ return -EINVAL; -+ -+ if (mode == OMAP_DSS_UPDATE_DISABLED) { -+ dispc_enable_lcd_out(0); -+ sdi.update_enabled = 0; -+ } else { -+ dispc_enable_lcd_out(1); -+ sdi.update_enabled = 1; -+ } -+ -+ return 0; -+} -+ -+static enum omap_dss_update_mode sdi_display_get_update_mode( -+ struct omap_dss_device *dssdev) -+{ -+ return sdi.update_enabled ? OMAP_DSS_UPDATE_AUTO : -+ OMAP_DSS_UPDATE_DISABLED; -+} -+ -+static void sdi_get_timings(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings) -+{ -+ *timings = dssdev->panel.timings; -+} -+ -+int sdi_init_display(struct omap_dss_device *dssdev) -+{ -+ DSSDBG("SDI init\n"); -+ -+ dssdev->enable = sdi_display_enable; -+ dssdev->disable = sdi_display_disable; -+ dssdev->suspend = sdi_display_suspend; -+ dssdev->resume = sdi_display_resume; -+ dssdev->set_update_mode = sdi_display_set_update_mode; -+ dssdev->get_update_mode = sdi_display_get_update_mode; -+ dssdev->get_timings = sdi_get_timings; -+ -+ return 0; -+} -+ -+int sdi_init(bool skip_init) -+{ -+ /* we store this for first display enable, then clear it */ -+ sdi.skip_init = skip_init; -+ -+ /* -+ * Enable clocks already here, otherwise there would be a toggle -+ * of them until sdi_display_enable is called. -+ */ -+ if (skip_init) -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ return 0; -+} -+ -+void sdi_exit(void) -+{ -+} ---- /dev/null -+++ b/drivers/video/omap2/dss/venc.c -@@ -0,0 +1,797 @@ -+/* -+ * linux/drivers/video/omap2/dss/venc.c -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * VENC settings from TI's DSS driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#define DSS_SUBSYS_NAME "VENC" -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/clk.h> -+#include <linux/err.h> -+#include <linux/io.h> -+#include <linux/mutex.h> -+#include <linux/completion.h> -+#include <linux/delay.h> -+#include <linux/string.h> -+#include <linux/seq_file.h> -+#include <linux/platform_device.h> -+#include <linux/regulator/consumer.h> -+ -+#include <mach/display.h> -+#include <mach/cpu.h> -+ -+#include "dss.h" -+ -+#define VENC_BASE 0x48050C00 -+ -+/* Venc registers */ -+#define VENC_REV_ID 0x00 -+#define VENC_STATUS 0x04 -+#define VENC_F_CONTROL 0x08 -+#define VENC_VIDOUT_CTRL 0x10 -+#define VENC_SYNC_CTRL 0x14 -+#define VENC_LLEN 0x1C -+#define VENC_FLENS 0x20 -+#define VENC_HFLTR_CTRL 0x24 -+#define VENC_CC_CARR_WSS_CARR 0x28 -+#define VENC_C_PHASE 0x2C -+#define VENC_GAIN_U 0x30 -+#define VENC_GAIN_V 0x34 -+#define VENC_GAIN_Y 0x38 -+#define VENC_BLACK_LEVEL 0x3C -+#define VENC_BLANK_LEVEL 0x40 -+#define VENC_X_COLOR 0x44 -+#define VENC_M_CONTROL 0x48 -+#define VENC_BSTAMP_WSS_DATA 0x4C -+#define VENC_S_CARR 0x50 -+#define VENC_LINE21 0x54 -+#define VENC_LN_SEL 0x58 -+#define VENC_L21__WC_CTL 0x5C -+#define VENC_HTRIGGER_VTRIGGER 0x60 -+#define VENC_SAVID__EAVID 0x64 -+#define VENC_FLEN__FAL 0x68 -+#define VENC_LAL__PHASE_RESET 0x6C -+#define VENC_HS_INT_START_STOP_X 0x70 -+#define VENC_HS_EXT_START_STOP_X 0x74 -+#define VENC_VS_INT_START_X 0x78 -+#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C -+#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 -+#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 -+#define VENC_VS_EXT_STOP_Y 0x88 -+#define VENC_AVID_START_STOP_X 0x90 -+#define VENC_AVID_START_STOP_Y 0x94 -+#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 -+#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 -+#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 -+#define VENC_TVDETGP_INT_START_STOP_X 0xB0 -+#define VENC_TVDETGP_INT_START_STOP_Y 0xB4 -+#define VENC_GEN_CTRL 0xB8 -+#define VENC_OUTPUT_CONTROL 0xC4 -+#define VENC_OUTPUT_TEST 0xC8 -+#define VENC_DAC_B__DAC_C 0xC8 -+ -+struct venc_config { -+ u32 f_control; -+ u32 vidout_ctrl; -+ u32 sync_ctrl; -+ u32 llen; -+ u32 flens; -+ u32 hfltr_ctrl; -+ u32 cc_carr_wss_carr; -+ u32 c_phase; -+ u32 gain_u; -+ u32 gain_v; -+ u32 gain_y; -+ u32 black_level; -+ u32 blank_level; -+ u32 x_color; -+ u32 m_control; -+ u32 bstamp_wss_data; -+ u32 s_carr; -+ u32 line21; -+ u32 ln_sel; -+ u32 l21__wc_ctl; -+ u32 htrigger_vtrigger; -+ u32 savid__eavid; -+ u32 flen__fal; -+ u32 lal__phase_reset; -+ u32 hs_int_start_stop_x; -+ u32 hs_ext_start_stop_x; -+ u32 vs_int_start_x; -+ u32 vs_int_stop_x__vs_int_start_y; -+ u32 vs_int_stop_y__vs_ext_start_x; -+ u32 vs_ext_stop_x__vs_ext_start_y; -+ u32 vs_ext_stop_y; -+ u32 avid_start_stop_x; -+ u32 avid_start_stop_y; -+ u32 fid_int_start_x__fid_int_start_y; -+ u32 fid_int_offset_y__fid_ext_start_x; -+ u32 fid_ext_start_y__fid_ext_offset_y; -+ u32 tvdetgp_int_start_stop_x; -+ u32 tvdetgp_int_start_stop_y; -+ u32 gen_ctrl; -+}; -+ -+/* from TRM */ -+static const struct venc_config venc_config_pal_trm = { -+ .f_control = 0, -+ .vidout_ctrl = 1, -+ .sync_ctrl = 0x40, -+ .llen = 0x35F, /* 863 */ -+ .flens = 0x270, /* 624 */ -+ .hfltr_ctrl = 0, -+ .cc_carr_wss_carr = 0x2F7225ED, -+ .c_phase = 0, -+ .gain_u = 0x111, -+ .gain_v = 0x181, -+ .gain_y = 0x140, -+ .black_level = 0x3B, -+ .blank_level = 0x3B, -+ .x_color = 0x7, -+ .m_control = 0x2, -+ .bstamp_wss_data = 0x3F, -+ .s_carr = 0x2A098ACB, -+ .line21 = 0, -+ .ln_sel = 0x01290015, -+ .l21__wc_ctl = 0x0000F603, -+ .htrigger_vtrigger = 0, -+ -+ .savid__eavid = 0x06A70108, -+ .flen__fal = 0x00180270, -+ .lal__phase_reset = 0x00040135, -+ .hs_int_start_stop_x = 0x00880358, -+ .hs_ext_start_stop_x = 0x000F035F, -+ .vs_int_start_x = 0x01A70000, -+ .vs_int_stop_x__vs_int_start_y = 0x000001A7, -+ .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, -+ .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, -+ .vs_ext_stop_y = 0x00000025, -+ .avid_start_stop_x = 0x03530083, -+ .avid_start_stop_y = 0x026C002E, -+ .fid_int_start_x__fid_int_start_y = 0x0001008A, -+ .fid_int_offset_y__fid_ext_start_x = 0x002E0138, -+ .fid_ext_start_y__fid_ext_offset_y = 0x01380001, -+ -+ .tvdetgp_int_start_stop_x = 0x00140001, -+ .tvdetgp_int_start_stop_y = 0x00010001, -+ .gen_ctrl = 0x00FF0000, -+}; -+ -+/* from TRM */ -+static const struct venc_config venc_config_ntsc_trm = { -+ .f_control = 0, -+ .vidout_ctrl = 1, -+ .sync_ctrl = 0x8040, -+ .llen = 0x359, -+ .flens = 0x20C, -+ .hfltr_ctrl = 0, -+ .cc_carr_wss_carr = 0x043F2631, -+ .c_phase = 0, -+ .gain_u = 0x102, -+ .gain_v = 0x16C, -+ .gain_y = 0x12F, -+ .black_level = 0x43, -+ .blank_level = 0x38, -+ .x_color = 0x7, -+ .m_control = 0x1, -+ .bstamp_wss_data = 0x38, -+ .s_carr = 0x21F07C1F, -+ .line21 = 0, -+ .ln_sel = 0x01310011, -+ .l21__wc_ctl = 0x0000F003, -+ .htrigger_vtrigger = 0, -+ -+ .savid__eavid = 0x069300F4, -+ .flen__fal = 0x0016020C, -+ .lal__phase_reset = 0x00060107, -+ .hs_int_start_stop_x = 0x008E0350, -+ .hs_ext_start_stop_x = 0x000F0359, -+ .vs_int_start_x = 0x01A00000, -+ .vs_int_stop_x__vs_int_start_y = 0x020701A0, -+ .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, -+ .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, -+ .vs_ext_stop_y = 0x00000006, -+ .avid_start_stop_x = 0x03480078, -+ .avid_start_stop_y = 0x02060024, -+ .fid_int_start_x__fid_int_start_y = 0x0001008A, -+ .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, -+ .fid_ext_start_y__fid_ext_offset_y = 0x01060006, -+ -+ .tvdetgp_int_start_stop_x = 0x00140001, -+ .tvdetgp_int_start_stop_y = 0x00010001, -+ .gen_ctrl = 0x00F90000, -+}; -+ -+static const struct venc_config venc_config_pal_bdghi = { -+ .f_control = 0, -+ .vidout_ctrl = 0, -+ .sync_ctrl = 0, -+ .hfltr_ctrl = 0, -+ .x_color = 0, -+ .line21 = 0, -+ .ln_sel = 21, -+ .htrigger_vtrigger = 0, -+ .tvdetgp_int_start_stop_x = 0x00140001, -+ .tvdetgp_int_start_stop_y = 0x00010001, -+ .gen_ctrl = 0x00FB0000, -+ -+ .llen = 864-1, -+ .flens = 625-1, -+ .cc_carr_wss_carr = 0x2F7625ED, -+ .c_phase = 0xDF, -+ .gain_u = 0x111, -+ .gain_v = 0x181, -+ .gain_y = 0x140, -+ .black_level = 0x3e, -+ .blank_level = 0x3e, -+ .m_control = 0<<2 | 1<<1, -+ .bstamp_wss_data = 0x42, -+ .s_carr = 0x2a098acb, -+ .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0, -+ .savid__eavid = 0x06A70108, -+ .flen__fal = 23<<16 | 624<<0, -+ .lal__phase_reset = 2<<17 | 310<<0, -+ .hs_int_start_stop_x = 0x00920358, -+ .hs_ext_start_stop_x = 0x000F035F, -+ .vs_int_start_x = 0x1a7<<16, -+ .vs_int_stop_x__vs_int_start_y = 0x000601A7, -+ .vs_int_stop_y__vs_ext_start_x = 0x01AF0036, -+ .vs_ext_stop_x__vs_ext_start_y = 0x27101af, -+ .vs_ext_stop_y = 0x05, -+ .avid_start_stop_x = 0x03530082, -+ .avid_start_stop_y = 0x0270002E, -+ .fid_int_start_x__fid_int_start_y = 0x0005008A, -+ .fid_int_offset_y__fid_ext_start_x = 0x002E0138, -+ .fid_ext_start_y__fid_ext_offset_y = 0x01380005, -+}; -+ -+const struct omap_video_timings omap_dss_pal_timings = { -+ .x_res = 720, -+ .y_res = 574, -+ .pixel_clock = 13500, -+ .hsw = 64, -+ .hfp = 12, -+ .hbp = 68, -+ .vsw = 5, -+ .vfp = 5, -+ .vbp = 41, -+}; -+EXPORT_SYMBOL(omap_dss_pal_timings); -+ -+const struct omap_video_timings omap_dss_ntsc_timings = { -+ .x_res = 720, -+ .y_res = 482, -+ .pixel_clock = 13500, -+ .hsw = 64, -+ .hfp = 16, -+ .hbp = 58, -+ .vsw = 6, -+ .vfp = 6, -+ .vbp = 31, -+}; -+EXPORT_SYMBOL(omap_dss_ntsc_timings); -+ -+static struct { -+ void __iomem *base; -+ struct mutex venc_lock; -+ u32 wss_data; -+ struct regulator *vdda_dac_reg; -+} venc; -+ -+static inline void venc_write_reg(int idx, u32 val) -+{ -+ __raw_writel(val, venc.base + idx); -+} -+ -+static inline u32 venc_read_reg(int idx) -+{ -+ u32 l = __raw_readl(venc.base + idx); -+ return l; -+} -+ -+static void venc_write_config(const struct venc_config *config) -+{ -+ DSSDBG("write venc conf\n"); -+ -+ venc_write_reg(VENC_LLEN, config->llen); -+ venc_write_reg(VENC_FLENS, config->flens); -+ venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); -+ venc_write_reg(VENC_C_PHASE, config->c_phase); -+ venc_write_reg(VENC_GAIN_U, config->gain_u); -+ venc_write_reg(VENC_GAIN_V, config->gain_v); -+ venc_write_reg(VENC_GAIN_Y, config->gain_y); -+ venc_write_reg(VENC_BLACK_LEVEL, config->black_level); -+ venc_write_reg(VENC_BLANK_LEVEL, config->blank_level); -+ venc_write_reg(VENC_M_CONTROL, config->m_control); -+ venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | -+ venc.wss_data); -+ venc_write_reg(VENC_S_CARR, config->s_carr); -+ venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl); -+ venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid); -+ venc_write_reg(VENC_FLEN__FAL, config->flen__fal); -+ venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset); -+ venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x); -+ venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x); -+ venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x); -+ venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y, -+ config->vs_int_stop_x__vs_int_start_y); -+ venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X, -+ config->vs_int_stop_y__vs_ext_start_x); -+ venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y, -+ config->vs_ext_stop_x__vs_ext_start_y); -+ venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); -+ venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x); -+ venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y); -+ venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y, -+ config->fid_int_start_x__fid_int_start_y); -+ venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, -+ config->fid_int_offset_y__fid_ext_start_x); -+ venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, -+ config->fid_ext_start_y__fid_ext_offset_y); -+ -+ venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C)); -+ venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl); -+ venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl); -+ venc_write_reg(VENC_X_COLOR, config->x_color); -+ venc_write_reg(VENC_LINE21, config->line21); -+ venc_write_reg(VENC_LN_SEL, config->ln_sel); -+ venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); -+ venc_write_reg(VENC_TVDETGP_INT_START_STOP_X, -+ config->tvdetgp_int_start_stop_x); -+ venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y, -+ config->tvdetgp_int_start_stop_y); -+ venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl); -+ venc_write_reg(VENC_F_CONTROL, config->f_control); -+ venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl); -+} -+ -+static void venc_reset(void) -+{ -+ int t = 1000; -+ -+ venc_write_reg(VENC_F_CONTROL, 1<<8); -+ while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) { -+ if (--t == 0) { -+ DSSERR("Failed to reset venc\n"); -+ return; -+ } -+ } -+ -+ /* the magical sleep that makes things work */ -+ msleep(20); -+} -+ -+static void venc_enable_clocks(int enable) -+{ -+ if (enable) -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | -+ DSS_CLK_96M); -+ else -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | -+ DSS_CLK_96M); -+} -+ -+static const struct venc_config *venc_timings_to_config( -+ struct omap_video_timings *timings) -+{ -+ if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) -+ return &venc_config_pal_trm; -+ -+ if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) -+ return &venc_config_ntsc_trm; -+ -+ BUG(); -+} -+ -+ -+ -+ -+ -+/* driver */ -+static int venc_panel_probe(struct omap_dss_device *dssdev) -+{ -+ dssdev->panel.timings = omap_dss_pal_timings; -+ -+ return 0; -+} -+ -+static void venc_panel_remove(struct omap_dss_device *dssdev) -+{ -+} -+ -+static int venc_panel_enable(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ /* wait couple of vsyncs until enabling the LCD */ -+ msleep(50); -+ -+ if (dssdev->platform_enable) -+ r = dssdev->platform_enable(dssdev); -+ -+ return r; -+} -+ -+static void venc_panel_disable(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->platform_disable) -+ dssdev->platform_disable(dssdev); -+ -+ /* wait at least 5 vsyncs after disabling the LCD */ -+ -+ msleep(100); -+} -+ -+static int venc_panel_suspend(struct omap_dss_device *dssdev) -+{ -+ venc_panel_disable(dssdev); -+ return 0; -+} -+ -+static int venc_panel_resume(struct omap_dss_device *dssdev) -+{ -+ return venc_panel_enable(dssdev); -+} -+ -+static struct omap_dss_driver venc_driver = { -+ .probe = venc_panel_probe, -+ .remove = venc_panel_remove, -+ -+ .enable = venc_panel_enable, -+ .disable = venc_panel_disable, -+ .suspend = venc_panel_suspend, -+ .resume = venc_panel_resume, -+ -+ .driver = { -+ .name = "venc", -+ .owner = THIS_MODULE, -+ }, -+}; -+/* driver end */ -+ -+ -+ -+int venc_init(struct platform_device *pdev) -+{ -+ u8 rev_id; -+ -+ mutex_init(&venc.venc_lock); -+ -+ venc.wss_data = 0; -+ -+ venc.base = ioremap(VENC_BASE, SZ_1K); -+ if (!venc.base) { -+ DSSERR("can't ioremap VENC\n"); -+ return -ENOMEM; -+ } -+ -+ venc.vdda_dac_reg = regulator_get(&pdev->dev, "vdda_dac"); -+ if (IS_ERR(venc.vdda_dac_reg)) { -+ iounmap(venc.base); -+ DSSERR("can't get VDDA_DAC regulator\n"); -+ return PTR_ERR(venc.vdda_dac_reg); -+ } -+ -+ venc_enable_clocks(1); -+ -+ rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); -+ printk(KERN_INFO "OMAP VENC rev %d\n", rev_id); -+ -+ venc_enable_clocks(0); -+ -+ return omap_dss_register_driver(&venc_driver); -+} -+ -+void venc_exit(void) -+{ -+ omap_dss_unregister_driver(&venc_driver); -+ -+ regulator_put(venc.vdda_dac_reg); -+ -+ iounmap(venc.base); -+} -+ -+static void venc_power_on(struct omap_dss_device *dssdev) -+{ -+ u32 l; -+ -+ venc_enable_clocks(1); -+ -+ venc_reset(); -+ venc_write_config(venc_timings_to_config(&dssdev->panel.timings)); -+ -+ dss_set_venc_output(dssdev->phy.venc.type); -+ dss_set_dac_pwrdn_bgz(1); -+ -+ l = 0; -+ -+ if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) -+ l |= 1 << 1; -+ else /* S-Video */ -+ l |= (1 << 0) | (1 << 2); -+ -+ if (dssdev->phy.venc.invert_polarity == false) -+ l |= 1 << 3; -+ -+ venc_write_reg(VENC_OUTPUT_CONTROL, l); -+ -+ dispc_set_digit_size(dssdev->panel.timings.x_res, -+ dssdev->panel.timings.y_res/2); -+ -+ regulator_enable(venc.vdda_dac_reg); -+ -+ if (dssdev->platform_enable) -+ dssdev->platform_enable(dssdev); -+ -+ dispc_enable_digit_out(1); -+} -+ -+static void venc_power_off(struct omap_dss_device *dssdev) -+{ -+ venc_write_reg(VENC_OUTPUT_CONTROL, 0); -+ dss_set_dac_pwrdn_bgz(0); -+ -+ dispc_enable_digit_out(0); -+ -+ if (dssdev->platform_disable) -+ dssdev->platform_disable(dssdev); -+ -+ regulator_disable(venc.vdda_dac_reg); -+ -+ venc_enable_clocks(0); -+} -+ -+static int venc_enable_display(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ DSSDBG("venc_enable_display\n"); -+ -+ mutex_lock(&venc.venc_lock); -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { -+ r = -EINVAL; -+ goto err; -+ } -+ -+ venc_power_on(dssdev); -+ -+ venc.wss_data = 0; -+ -+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -+err: -+ mutex_unlock(&venc.venc_lock); -+ -+ return r; -+} -+ -+static void venc_disable_display(struct omap_dss_device *dssdev) -+{ -+ DSSDBG("venc_disable_display\n"); -+ -+ mutex_lock(&venc.venc_lock); -+ -+ if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED) -+ goto end; -+ -+ if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) { -+ /* suspended is the same as disabled with venc */ -+ dssdev->state = OMAP_DSS_DISPLAY_DISABLED; -+ goto end; -+ } -+ -+ venc_power_off(dssdev); -+ -+ dssdev->state = OMAP_DSS_DISPLAY_DISABLED; -+end: -+ mutex_unlock(&venc.venc_lock); -+} -+ -+static int venc_display_suspend(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ DSSDBG("venc_display_suspend\n"); -+ -+ mutex_lock(&venc.venc_lock); -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) { -+ r = -EINVAL; -+ goto err; -+ } -+ -+ venc_power_off(dssdev); -+ -+ dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; -+err: -+ mutex_unlock(&venc.venc_lock); -+ -+ return r; -+} -+ -+static int venc_display_resume(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ DSSDBG("venc_display_resume\n"); -+ -+ mutex_lock(&venc.venc_lock); -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) { -+ r = -EINVAL; -+ goto err; -+ } -+ -+ venc_power_on(dssdev); -+ -+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -+err: -+ mutex_unlock(&venc.venc_lock); -+ -+ return r; -+} -+ -+static void venc_get_timings(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings) -+{ -+ *timings = dssdev->panel.timings; -+} -+ -+static void venc_set_timings(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings) -+{ -+ DSSDBG("venc_set_timings\n"); -+ -+ /* Reset WSS data when the TV standard changes. */ -+ if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings))) -+ venc.wss_data = 0; -+ -+ dssdev->panel.timings = *timings; -+ if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { -+ /* turn the venc off and on to get new timings to use */ -+ venc_disable_display(dssdev); -+ venc_enable_display(dssdev); -+ } -+} -+ -+static int venc_check_timings(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings) -+{ -+ DSSDBG("venc_check_timings\n"); -+ -+ if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) -+ return 0; -+ -+ if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) -+ return 0; -+ -+ return -EINVAL; -+} -+ -+static u32 venc_get_wss(struct omap_dss_device *dssdev) -+{ -+ /* Invert due to VENC_L21_WC_CTL:INV=1 */ -+ return (venc.wss_data >> 8) ^ 0xfffff; -+} -+ -+static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss) -+{ -+ const struct venc_config *config; -+ -+ DSSDBG("venc_set_wss\n"); -+ -+ mutex_lock(&venc.venc_lock); -+ -+ config = venc_timings_to_config(&dssdev->panel.timings); -+ -+ /* Invert due to VENC_L21_WC_CTL:INV=1 */ -+ venc.wss_data = (wss ^ 0xfffff) << 8; -+ -+ venc_enable_clocks(1); -+ -+ venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | -+ venc.wss_data); -+ -+ venc_enable_clocks(0); -+ -+ mutex_unlock(&venc.venc_lock); -+ -+ return 0; -+} -+ -+static enum omap_dss_update_mode venc_display_get_update_mode( -+ struct omap_dss_device *dssdev) -+{ -+ if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) -+ return OMAP_DSS_UPDATE_AUTO; -+ else -+ return OMAP_DSS_UPDATE_DISABLED; -+} -+ -+int venc_init_display(struct omap_dss_device *dssdev) -+{ -+ DSSDBG("init_display\n"); -+ -+ dssdev->enable = venc_enable_display; -+ dssdev->disable = venc_disable_display; -+ dssdev->suspend = venc_display_suspend; -+ dssdev->resume = venc_display_resume; -+ dssdev->get_timings = venc_get_timings; -+ dssdev->set_timings = venc_set_timings; -+ dssdev->check_timings = venc_check_timings; -+ dssdev->get_wss = venc_get_wss; -+ dssdev->set_wss = venc_set_wss; -+ dssdev->get_update_mode = venc_display_get_update_mode; -+ -+ return 0; -+} -+ -+void venc_dump_regs(struct seq_file *s) -+{ -+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) -+ -+ venc_enable_clocks(1); -+ -+ DUMPREG(VENC_F_CONTROL); -+ DUMPREG(VENC_VIDOUT_CTRL); -+ DUMPREG(VENC_SYNC_CTRL); -+ DUMPREG(VENC_LLEN); -+ DUMPREG(VENC_FLENS); -+ DUMPREG(VENC_HFLTR_CTRL); -+ DUMPREG(VENC_CC_CARR_WSS_CARR); -+ DUMPREG(VENC_C_PHASE); -+ DUMPREG(VENC_GAIN_U); -+ DUMPREG(VENC_GAIN_V); -+ DUMPREG(VENC_GAIN_Y); -+ DUMPREG(VENC_BLACK_LEVEL); -+ DUMPREG(VENC_BLANK_LEVEL); -+ DUMPREG(VENC_X_COLOR); -+ DUMPREG(VENC_M_CONTROL); -+ DUMPREG(VENC_BSTAMP_WSS_DATA); -+ DUMPREG(VENC_S_CARR); -+ DUMPREG(VENC_LINE21); -+ DUMPREG(VENC_LN_SEL); -+ DUMPREG(VENC_L21__WC_CTL); -+ DUMPREG(VENC_HTRIGGER_VTRIGGER); -+ DUMPREG(VENC_SAVID__EAVID); -+ DUMPREG(VENC_FLEN__FAL); -+ DUMPREG(VENC_LAL__PHASE_RESET); -+ DUMPREG(VENC_HS_INT_START_STOP_X); -+ DUMPREG(VENC_HS_EXT_START_STOP_X); -+ DUMPREG(VENC_VS_INT_START_X); -+ DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y); -+ DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X); -+ DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y); -+ DUMPREG(VENC_VS_EXT_STOP_Y); -+ DUMPREG(VENC_AVID_START_STOP_X); -+ DUMPREG(VENC_AVID_START_STOP_Y); -+ DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y); -+ DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); -+ DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); -+ DUMPREG(VENC_TVDETGP_INT_START_STOP_X); -+ DUMPREG(VENC_TVDETGP_INT_START_STOP_Y); -+ DUMPREG(VENC_GEN_CTRL); -+ DUMPREG(VENC_OUTPUT_CONTROL); -+ DUMPREG(VENC_OUTPUT_TEST); -+ -+ venc_enable_clocks(0); -+ -+#undef DUMPREG -+} ---- /dev/null -+++ b/drivers/video/omap2/omapfb/Kconfig -@@ -0,0 +1,37 @@ -+menuconfig FB_OMAP2 -+ tristate "OMAP2/3 frame buffer support (EXPERIMENTAL)" -+ depends on FB && OMAP2_DSS -+ -+ select OMAP2_VRAM -+ select OMAP2_VRFB -+ select FB_CFB_FILLRECT -+ select FB_CFB_COPYAREA -+ select FB_CFB_IMAGEBLIT -+ help -+ Frame buffer driver for OMAP2/3 based boards. -+ -+config FB_OMAP2_DEBUG_SUPPORT -+ bool "Debug support for OMAP2/3 FB" -+ default y -+ depends on FB_OMAP2 -+ help -+ Support for debug output. You have to enable the actual printing -+ with debug module parameter. -+ -+config FB_OMAP2_FORCE_AUTO_UPDATE -+ bool "Force main display to automatic update mode" -+ depends on FB_OMAP2 -+ help -+ Forces main display to automatic update mode (if possible), -+ and also enables tearsync (if possible). By default -+ displays that support manual update are started in manual -+ update mode. -+ -+config FB_OMAP2_NUM_FBS -+ int "Number of framebuffers" -+ range 1 10 -+ default 3 -+ depends on FB_OMAP2 -+ help -+ Select the number of framebuffers created. OMAP2/3 has 3 overlays -+ so normally this would be 3. ---- /dev/null -+++ b/drivers/video/omap2/omapfb/Makefile -@@ -0,0 +1,2 @@ -+obj-$(CONFIG_FB_OMAP2) += omapfb.o -+omapfb-y := omapfb-main.o omapfb-sysfs.o omapfb-ioctl.o ---- /dev/null -+++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c -@@ -0,0 +1,727 @@ -+/* -+ * linux/drivers/video/omap2/omapfb-ioctl.c -+ * -+ * Copyright (C) 2008 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#include <linux/fb.h> -+#include <linux/device.h> -+#include <linux/uaccess.h> -+#include <linux/platform_device.h> -+#include <linux/mm.h> -+#include <linux/omapfb.h> -+#include <linux/vmalloc.h> -+ -+#include <mach/display.h> -+#include <mach/vrfb.h> -+#include <mach/vram.h> -+ -+#include "omapfb.h" -+ -+static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_device *fbdev = ofbi->fbdev; -+ struct omap_dss_device *display = fb2display(fbi); -+ struct omap_overlay *ovl; -+ struct omap_overlay_info info; -+ int r = 0; -+ -+ DBG("omapfb_setup_plane\n"); -+ -+ if (ofbi->num_overlays != 1) { -+ r = -EINVAL; -+ goto out; -+ } -+ -+ /* XXX uses only the first overlay */ -+ ovl = ofbi->overlays[0]; -+ -+ if (pi->enabled && !ofbi->region.size) { -+ /* -+ * This plane's memory was freed, can't enable it -+ * until it's reallocated. -+ */ -+ r = -EINVAL; -+ goto out; -+ } -+ -+ ovl->get_overlay_info(ovl, &info); -+ -+ info.pos_x = pi->pos_x; -+ info.pos_y = pi->pos_y; -+ info.out_width = pi->out_width; -+ info.out_height = pi->out_height; -+ info.enabled = pi->enabled; -+ -+ r = ovl->set_overlay_info(ovl, &info); -+ if (r) -+ goto out; -+ -+ if (ovl->manager) { -+ r = ovl->manager->apply(ovl->manager); -+ if (r) -+ goto out; -+ } -+ -+ if (display) { -+ u16 w, h; -+ -+ if (display->sync) -+ display->sync(display); -+ -+ display->get_resolution(display, &w, &h); -+ -+ if (display->update) -+ display->update(display, 0, 0, w, h); -+ } -+ -+out: -+ if (r) -+ dev_err(fbdev->dev, "setup_plane failed\n"); -+ return r; -+} -+ -+static int omapfb_query_plane(struct fb_info *fbi, struct omapfb_plane_info *pi) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ -+ if (ofbi->num_overlays != 1) { -+ memset(pi, 0, sizeof(*pi)); -+ } else { -+ struct omap_overlay_info *ovli; -+ struct omap_overlay *ovl; -+ -+ ovl = ofbi->overlays[0]; -+ ovli = &ovl->info; -+ -+ pi->pos_x = ovli->pos_x; -+ pi->pos_y = ovli->pos_y; -+ pi->enabled = ovli->enabled; -+ pi->channel_out = 0; /* xxx */ -+ pi->mirror = 0; -+ pi->out_width = ovli->out_width; -+ pi->out_height = ovli->out_height; -+ } -+ -+ return 0; -+} -+ -+static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_device *fbdev = ofbi->fbdev; -+ struct omapfb2_mem_region *rg; -+ int r, i; -+ size_t size; -+ -+ if (mi->type > OMAPFB_MEMTYPE_MAX) -+ return -EINVAL; -+ -+ size = PAGE_ALIGN(mi->size); -+ -+ rg = &ofbi->region; -+ -+ for (i = 0; i < ofbi->num_overlays; i++) { -+ if (ofbi->overlays[i]->info.enabled) -+ return -EBUSY; -+ } -+ -+ if (rg->size != size || rg->type != mi->type) { -+ r = omapfb_realloc_fbmem(fbi, size, mi->type); -+ if (r) { -+ dev_err(fbdev->dev, "realloc fbmem failed\n"); -+ return r; -+ } -+ } -+ -+ return 0; -+} -+ -+static int omapfb_query_mem(struct fb_info *fbi, struct omapfb_mem_info *mi) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_mem_region *rg; -+ -+ rg = &ofbi->region; -+ memset(mi, 0, sizeof(*mi)); -+ -+ mi->size = rg->size; -+ mi->type = rg->type; -+ -+ return 0; -+} -+ -+static int omapfb_update_window(struct fb_info *fbi, -+ u32 x, u32 y, u32 w, u32 h) -+{ -+ struct omap_dss_device *display = fb2display(fbi); -+ u16 dw, dh; -+ -+ if (!display) -+ return 0; -+ -+ if (w == 0 || h == 0) -+ return 0; -+ -+ display->get_resolution(display, &dw, &dh); -+ -+ if (x + w > dw || y + h > dh) -+ return -EINVAL; -+ -+ display->update(display, x, y, w, h); -+ -+ return 0; -+} -+ -+static int omapfb_set_update_mode(struct fb_info *fbi, -+ enum omapfb_update_mode mode) -+{ -+ struct omap_dss_device *display = fb2display(fbi); -+ enum omap_dss_update_mode um; -+ int r; -+ -+ if (!display || !display->set_update_mode) -+ return -EINVAL; -+ -+ switch (mode) { -+ case OMAPFB_UPDATE_DISABLED: -+ um = OMAP_DSS_UPDATE_DISABLED; -+ break; -+ -+ case OMAPFB_AUTO_UPDATE: -+ um = OMAP_DSS_UPDATE_AUTO; -+ break; -+ -+ case OMAPFB_MANUAL_UPDATE: -+ um = OMAP_DSS_UPDATE_MANUAL; -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ r = display->set_update_mode(display, um); -+ -+ return r; -+} -+ -+static int omapfb_get_update_mode(struct fb_info *fbi, -+ enum omapfb_update_mode *mode) -+{ -+ struct omap_dss_device *display = fb2display(fbi); -+ enum omap_dss_update_mode m; -+ -+ if (!display || !display->get_update_mode) -+ return -EINVAL; -+ -+ m = display->get_update_mode(display); -+ -+ switch (m) { -+ case OMAP_DSS_UPDATE_DISABLED: -+ *mode = OMAPFB_UPDATE_DISABLED; -+ break; -+ case OMAP_DSS_UPDATE_AUTO: -+ *mode = OMAPFB_AUTO_UPDATE; -+ break; -+ case OMAP_DSS_UPDATE_MANUAL: -+ *mode = OMAPFB_MANUAL_UPDATE; -+ break; -+ default: -+ BUG(); -+ } -+ -+ return 0; -+} -+ -+/* XXX this color key handling is a hack... */ -+static struct omapfb_color_key omapfb_color_keys[2]; -+ -+static int _omapfb_set_color_key(struct omap_overlay_manager *mgr, -+ struct omapfb_color_key *ck) -+{ -+ struct omap_overlay_manager_info info; -+ enum omap_dss_trans_key_type kt; -+ int r; -+ -+ mgr->get_manager_info(mgr, &info); -+ -+ if (ck->key_type == OMAPFB_COLOR_KEY_DISABLED) { -+ info.trans_enabled = false; -+ omapfb_color_keys[mgr->id] = *ck; -+ -+ r = mgr->set_manager_info(mgr, &info); -+ if (r) -+ return r; -+ -+ r = mgr->apply(mgr); -+ -+ return r; -+ } -+ -+ switch (ck->key_type) { -+ case OMAPFB_COLOR_KEY_GFX_DST: -+ kt = OMAP_DSS_COLOR_KEY_GFX_DST; -+ break; -+ case OMAPFB_COLOR_KEY_VID_SRC: -+ kt = OMAP_DSS_COLOR_KEY_VID_SRC; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ info.default_color = ck->background; -+ info.trans_key = ck->trans_key; -+ info.trans_key_type = kt; -+ info.trans_enabled = true; -+ -+ omapfb_color_keys[mgr->id] = *ck; -+ -+ r = mgr->set_manager_info(mgr, &info); -+ if (r) -+ return r; -+ -+ r = mgr->apply(mgr); -+ -+ return r; -+} -+ -+static int omapfb_set_color_key(struct fb_info *fbi, -+ struct omapfb_color_key *ck) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_device *fbdev = ofbi->fbdev; -+ int r; -+ int i; -+ struct omap_overlay_manager *mgr = NULL; -+ -+ omapfb_lock(fbdev); -+ -+ for (i = 0; i < ofbi->num_overlays; i++) { -+ if (ofbi->overlays[i]->manager) { -+ mgr = ofbi->overlays[i]->manager; -+ break; -+ } -+ } -+ -+ if (!mgr) { -+ r = -EINVAL; -+ goto err; -+ } -+ -+ r = _omapfb_set_color_key(mgr, ck); -+err: -+ omapfb_unlock(fbdev); -+ -+ return r; -+} -+ -+static int omapfb_get_color_key(struct fb_info *fbi, -+ struct omapfb_color_key *ck) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_device *fbdev = ofbi->fbdev; -+ struct omap_overlay_manager *mgr = NULL; -+ int r = 0; -+ int i; -+ -+ omapfb_lock(fbdev); -+ -+ for (i = 0; i < ofbi->num_overlays; i++) { -+ if (ofbi->overlays[i]->manager) { -+ mgr = ofbi->overlays[i]->manager; -+ break; -+ } -+ } -+ -+ if (!mgr) { -+ r = -EINVAL; -+ goto err; -+ } -+ -+ *ck = omapfb_color_keys[mgr->id]; -+err: -+ omapfb_unlock(fbdev); -+ -+ return r; -+} -+ -+static int omapfb_memory_read(struct fb_info *fbi, -+ struct omapfb_memory_read *mr) -+{ -+ struct omap_dss_device *display = fb2display(fbi); -+ void *buf; -+ int r; -+ -+ if (!display || !display->memory_read) -+ return -ENOENT; -+ -+ if (!access_ok(VERIFY_WRITE, mr->buffer, mr->buffer_size)) -+ return -EFAULT; -+ -+ if (mr->w * mr->h * 3 > mr->buffer_size) -+ return -EINVAL; -+ -+ buf = vmalloc(mr->buffer_size); -+ if (!buf) { -+ DBG("vmalloc failed\n"); -+ return -ENOMEM; -+ } -+ -+ r = display->memory_read(display, buf, mr->buffer_size, -+ mr->x, mr->y, mr->w, mr->h); -+ -+ if (r > 0) { -+ if (copy_to_user(mr->buffer, buf, mr->buffer_size)) -+ r = -EFAULT; -+ } -+ -+ vfree(buf); -+ -+ return r; -+} -+ -+static int omapfb_get_ovl_colormode(struct omapfb2_device *fbdev, -+ struct omapfb_ovl_colormode *mode) -+{ -+ int ovl_idx = mode->overlay_idx; -+ int mode_idx = mode->mode_idx; -+ struct omap_overlay *ovl; -+ enum omap_color_mode supported_modes; -+ struct fb_var_screeninfo var; -+ int i; -+ -+ if (ovl_idx >= fbdev->num_overlays) -+ return -ENODEV; -+ ovl = fbdev->overlays[ovl_idx]; -+ supported_modes = ovl->supported_modes; -+ -+ mode_idx = mode->mode_idx; -+ -+ for (i = 0; i < sizeof(supported_modes) * 8; i++) { -+ if (!(supported_modes & (1 << i))) -+ continue; -+ /* -+ * It's possible that the FB doesn't support a mode -+ * that is supported by the overlay, so call the -+ * following here. -+ */ -+ if (dss_mode_to_fb_mode(1 << i, &var) < 0) -+ continue; -+ -+ mode_idx--; -+ if (mode_idx < 0) -+ break; -+ } -+ -+ if (i == sizeof(supported_modes) * 8) -+ return -ENOENT; -+ -+ mode->bits_per_pixel = var.bits_per_pixel; -+ mode->nonstd = var.nonstd; -+ mode->red = var.red; -+ mode->green = var.green; -+ mode->blue = var.blue; -+ mode->transp = var.transp; -+ -+ return 0; -+} -+ -+static int omapfb_wait_for_go(struct fb_info *fbi) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ int r = 0; -+ int i; -+ -+ for (i = 0; i < ofbi->num_overlays; ++i) { -+ struct omap_overlay *ovl = ofbi->overlays[i]; -+ r = ovl->wait_for_go(ovl); -+ if (r) -+ break; -+ } -+ -+ return r; -+} -+ -+int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_device *fbdev = ofbi->fbdev; -+ struct omap_dss_device *display = fb2display(fbi); -+ -+ union { -+ struct omapfb_update_window_old uwnd_o; -+ struct omapfb_update_window uwnd; -+ struct omapfb_plane_info plane_info; -+ struct omapfb_caps caps; -+ struct omapfb_mem_info mem_info; -+ struct omapfb_color_key color_key; -+ struct omapfb_ovl_colormode ovl_colormode; -+ enum omapfb_update_mode update_mode; -+ int test_num; -+ struct omapfb_memory_read memory_read; -+ struct omapfb_vram_info vram_info; -+ } p; -+ -+ int r = 0; -+ -+ switch (cmd) { -+ case OMAPFB_SYNC_GFX: -+ DBG("ioctl SYNC_GFX\n"); -+ if (!display || !display->sync) { -+ /* DSS1 never returns an error here, so we neither */ -+ /*r = -EINVAL;*/ -+ break; -+ } -+ -+ r = display->sync(display); -+ break; -+ -+ case OMAPFB_UPDATE_WINDOW_OLD: -+ DBG("ioctl UPDATE_WINDOW_OLD\n"); -+ if (!display || !display->update) { -+ r = -EINVAL; -+ break; -+ } -+ -+ if (copy_from_user(&p.uwnd_o, -+ (void __user *)arg, -+ sizeof(p.uwnd_o))) { -+ r = -EFAULT; -+ break; -+ } -+ -+ r = omapfb_update_window(fbi, p.uwnd_o.x, p.uwnd_o.y, -+ p.uwnd_o.width, p.uwnd_o.height); -+ break; -+ -+ case OMAPFB_UPDATE_WINDOW: -+ DBG("ioctl UPDATE_WINDOW\n"); -+ if (!display || !display->update) { -+ r = -EINVAL; -+ break; -+ } -+ -+ if (copy_from_user(&p.uwnd, (void __user *)arg, -+ sizeof(p.uwnd))) { -+ r = -EFAULT; -+ break; -+ } -+ -+ r = omapfb_update_window(fbi, p.uwnd.x, p.uwnd.y, -+ p.uwnd.width, p.uwnd.height); -+ break; -+ -+ case OMAPFB_SETUP_PLANE: -+ DBG("ioctl SETUP_PLANE\n"); -+ if (copy_from_user(&p.plane_info, (void __user *)arg, -+ sizeof(p.plane_info))) -+ r = -EFAULT; -+ else -+ r = omapfb_setup_plane(fbi, &p.plane_info); -+ break; -+ -+ case OMAPFB_QUERY_PLANE: -+ DBG("ioctl QUERY_PLANE\n"); -+ r = omapfb_query_plane(fbi, &p.plane_info); -+ if (r < 0) -+ break; -+ if (copy_to_user((void __user *)arg, &p.plane_info, -+ sizeof(p.plane_info))) -+ r = -EFAULT; -+ break; -+ -+ case OMAPFB_SETUP_MEM: -+ DBG("ioctl SETUP_MEM\n"); -+ if (copy_from_user(&p.mem_info, (void __user *)arg, -+ sizeof(p.mem_info))) -+ r = -EFAULT; -+ else -+ r = omapfb_setup_mem(fbi, &p.mem_info); -+ break; -+ -+ case OMAPFB_QUERY_MEM: -+ DBG("ioctl QUERY_MEM\n"); -+ r = omapfb_query_mem(fbi, &p.mem_info); -+ if (r < 0) -+ break; -+ if (copy_to_user((void __user *)arg, &p.mem_info, -+ sizeof(p.mem_info))) -+ r = -EFAULT; -+ break; -+ -+ case OMAPFB_GET_CAPS: -+ DBG("ioctl GET_CAPS\n"); -+ if (!display) { -+ r = -EINVAL; -+ break; -+ } -+ -+ memset(&p.caps, 0, sizeof(p.caps)); -+ p.caps.ctrl = display->caps; -+ -+ if (copy_to_user((void __user *)arg, &p.caps, sizeof(p.caps))) -+ r = -EFAULT; -+ break; -+ -+ case OMAPFB_GET_OVERLAY_COLORMODE: -+ DBG("ioctl GET_OVERLAY_COLORMODE\n"); -+ if (copy_from_user(&p.ovl_colormode, (void __user *)arg, -+ sizeof(p.ovl_colormode))) { -+ r = -EFAULT; -+ break; -+ } -+ r = omapfb_get_ovl_colormode(fbdev, &p.ovl_colormode); -+ if (r < 0) -+ break; -+ if (copy_to_user((void __user *)arg, &p.ovl_colormode, -+ sizeof(p.ovl_colormode))) -+ r = -EFAULT; -+ break; -+ -+ case OMAPFB_SET_UPDATE_MODE: -+ DBG("ioctl SET_UPDATE_MODE\n"); -+ if (get_user(p.update_mode, (int __user *)arg)) -+ r = -EFAULT; -+ else -+ r = omapfb_set_update_mode(fbi, p.update_mode); -+ break; -+ -+ case OMAPFB_GET_UPDATE_MODE: -+ DBG("ioctl GET_UPDATE_MODE\n"); -+ r = omapfb_get_update_mode(fbi, &p.update_mode); -+ if (r) -+ break; -+ if (put_user(p.update_mode, -+ (enum omapfb_update_mode __user *)arg)) -+ r = -EFAULT; -+ break; -+ -+ case OMAPFB_SET_COLOR_KEY: -+ DBG("ioctl SET_COLOR_KEY\n"); -+ if (copy_from_user(&p.color_key, (void __user *)arg, -+ sizeof(p.color_key))) -+ r = -EFAULT; -+ else -+ r = omapfb_set_color_key(fbi, &p.color_key); -+ break; -+ -+ case OMAPFB_GET_COLOR_KEY: -+ DBG("ioctl GET_COLOR_KEY\n"); -+ r = omapfb_get_color_key(fbi, &p.color_key); -+ if (r) -+ break; -+ if (copy_to_user((void __user *)arg, &p.color_key, -+ sizeof(p.color_key))) -+ r = -EFAULT; -+ break; -+ -+ case OMAPFB_WAITFORVSYNC: -+ DBG("ioctl WAITFORVSYNC\n"); -+ if (!display) { -+ r = -EINVAL; -+ break; -+ } -+ -+ r = display->wait_vsync(display); -+ break; -+ -+ case OMAPFB_WAITFORGO: -+ DBG("ioctl WAITFORGO\n"); -+ if (!display) { -+ r = -EINVAL; -+ break; -+ } -+ -+ r = omapfb_wait_for_go(fbi); -+ break; -+ -+ /* LCD and CTRL tests do the same thing for backward -+ * compatibility */ -+ case OMAPFB_LCD_TEST: -+ DBG("ioctl LCD_TEST\n"); -+ if (get_user(p.test_num, (int __user *)arg)) { -+ r = -EFAULT; -+ break; -+ } -+ if (!display || !display->run_test) { -+ r = -EINVAL; -+ break; -+ } -+ -+ r = display->run_test(display, p.test_num); -+ -+ break; -+ -+ case OMAPFB_CTRL_TEST: -+ DBG("ioctl CTRL_TEST\n"); -+ if (get_user(p.test_num, (int __user *)arg)) { -+ r = -EFAULT; -+ break; -+ } -+ if (!display || !display->run_test) { -+ r = -EINVAL; -+ break; -+ } -+ -+ r = display->run_test(display, p.test_num); -+ -+ break; -+ -+ case OMAPFB_MEMORY_READ: -+ DBG("ioctl MEMORY_READ\n"); -+ -+ if (copy_from_user(&p.memory_read, (void __user *)arg, -+ sizeof(p.memory_read))) { -+ r = -EFAULT; -+ break; -+ } -+ -+ r = omapfb_memory_read(fbi, &p.memory_read); -+ -+ break; -+ -+ case OMAPFB_GET_VRAM_INFO: { -+ unsigned long vram, free, largest; -+ -+ DBG("ioctl GET_VRAM_INFO\n"); -+ -+ omap_vram_get_info(&vram, &free, &largest); -+ p.vram_info.total = vram; -+ p.vram_info.free = free; -+ p.vram_info.largest_free_block = largest; -+ -+ if (copy_to_user((void __user *)arg, &p.vram_info, -+ sizeof(p.vram_info))) -+ r = -EFAULT; -+ break; -+ } -+ -+ default: -+ dev_err(fbdev->dev, "Unknown ioctl 0x%x\n", cmd); -+ r = -EINVAL; -+ } -+ -+ if (r < 0) -+ DBG("ioctl failed: %d\n", r); -+ -+ return r; -+} -+ -+ ---- /dev/null -+++ b/drivers/video/omap2/omapfb/omapfb-main.c -@@ -0,0 +1,2137 @@ -+/* -+ * linux/drivers/video/omap2/omapfb-main.c -+ * -+ * Copyright (C) 2008 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#include <linux/module.h> -+#include <linux/delay.h> -+#include <linux/fb.h> -+#include <linux/dma-mapping.h> -+#include <linux/vmalloc.h> -+#include <linux/device.h> -+#include <linux/platform_device.h> -+#include <linux/omapfb.h> -+ -+#include <mach/display.h> -+#include <mach/vram.h> -+#include <mach/vrfb.h> -+ -+#include "omapfb.h" -+ -+#define MODULE_NAME "omapfb" -+ -+#define OMAPFB_PLANE_XRES_MIN 8 -+#define OMAPFB_PLANE_YRES_MIN 8 -+ -+static char *def_mode; -+static char *def_vram; -+static int def_vrfb; -+static int def_rotate; -+static int def_mirror; -+ -+#ifdef DEBUG -+unsigned int omapfb_debug; -+module_param_named(debug, omapfb_debug, bool, 0644); -+static unsigned int omapfb_test_pattern; -+module_param_named(test, omapfb_test_pattern, bool, 0644); -+#endif -+ -+static int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi); -+ -+#ifdef DEBUG -+static void draw_pixel(struct fb_info *fbi, int x, int y, unsigned color) -+{ -+ struct fb_var_screeninfo *var = &fbi->var; -+ struct fb_fix_screeninfo *fix = &fbi->fix; -+ void __iomem *addr = fbi->screen_base; -+ const unsigned bytespp = var->bits_per_pixel >> 3; -+ const unsigned line_len = fix->line_length / bytespp; -+ -+ int r = (color >> 16) & 0xff; -+ int g = (color >> 8) & 0xff; -+ int b = (color >> 0) & 0xff; -+ -+ if (var->bits_per_pixel == 16) { -+ u16 __iomem *p = (u16 __iomem *)addr; -+ p += y * line_len + x; -+ -+ r = r * 32 / 256; -+ g = g * 64 / 256; -+ b = b * 32 / 256; -+ -+ __raw_writew((r << 11) | (g << 5) | (b << 0), p); -+ } else if (var->bits_per_pixel == 24) { -+ u8 __iomem *p = (u8 __iomem *)addr; -+ p += (y * line_len + x) * 3; -+ -+ __raw_writeb(b, p + 0); -+ __raw_writeb(g, p + 1); -+ __raw_writeb(r, p + 2); -+ } else if (var->bits_per_pixel == 32) { -+ u32 __iomem *p = (u32 __iomem *)addr; -+ p += y * line_len + x; -+ __raw_writel(color, p); -+ } -+} -+ -+static void fill_fb(struct fb_info *fbi) -+{ -+ struct fb_var_screeninfo *var = &fbi->var; -+ const short w = var->xres_virtual; -+ const short h = var->yres_virtual; -+ void __iomem *addr = fbi->screen_base; -+ int y, x; -+ -+ if (!addr) -+ return; -+ -+ DBG("fill_fb %dx%d, line_len %d bytes\n", w, h, fbi->fix.line_length); -+ -+ for (y = 0; y < h; y++) { -+ for (x = 0; x < w; x++) { -+ if (x < 20 && y < 20) -+ draw_pixel(fbi, x, y, 0xffffff); -+ else if (x < 20 && (y > 20 && y < h - 20)) -+ draw_pixel(fbi, x, y, 0xff); -+ else if (y < 20 && (x > 20 && x < w - 20)) -+ draw_pixel(fbi, x, y, 0xff00); -+ else if (x > w - 20 && (y > 20 && y < h - 20)) -+ draw_pixel(fbi, x, y, 0xff0000); -+ else if (y > h - 20 && (x > 20 && x < w - 20)) -+ draw_pixel(fbi, x, y, 0xffff00); -+ else if (x == 20 || x == w - 20 || -+ y == 20 || y == h - 20) -+ draw_pixel(fbi, x, y, 0xffffff); -+ else if (x == y || w - x == h - y) -+ draw_pixel(fbi, x, y, 0xff00ff); -+ else if (w - x == y || x == h - y) -+ draw_pixel(fbi, x, y, 0x00ffff); -+ else if (x > 20 && y > 20 && x < w - 20 && y < h - 20) { -+ int t = x * 3 / w; -+ unsigned r = 0, g = 0, b = 0; -+ unsigned c; -+ if (var->bits_per_pixel == 16) { -+ if (t == 0) -+ b = (y % 32) * 256 / 32; -+ else if (t == 1) -+ g = (y % 64) * 256 / 64; -+ else if (t == 2) -+ r = (y % 32) * 256 / 32; -+ } else { -+ if (t == 0) -+ b = (y % 256); -+ else if (t == 1) -+ g = (y % 256); -+ else if (t == 2) -+ r = (y % 256); -+ } -+ c = (r << 16) | (g << 8) | (b << 0); -+ draw_pixel(fbi, x, y, c); -+ } else { -+ draw_pixel(fbi, x, y, 0); -+ } -+ } -+ } -+} -+#endif -+ -+static unsigned omapfb_get_vrfb_offset(struct omapfb_info *ofbi, int rot) -+{ -+ struct vrfb *vrfb = &ofbi->region.vrfb; -+ unsigned offset; -+ -+ switch (rot) { -+ case FB_ROTATE_UR: -+ offset = 0; -+ break; -+ case FB_ROTATE_CW: -+ offset = vrfb->yoffset; -+ break; -+ case FB_ROTATE_UD: -+ offset = vrfb->yoffset * OMAP_VRFB_LINE_LEN + vrfb->xoffset; -+ break; -+ case FB_ROTATE_CCW: -+ offset = vrfb->xoffset * OMAP_VRFB_LINE_LEN; -+ break; -+ default: -+ BUG(); -+ } -+ -+ offset *= vrfb->bytespp; -+ -+ return offset; -+} -+ -+static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi, int rot) -+{ -+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) { -+ return ofbi->region.vrfb.paddr[rot] -+ + omapfb_get_vrfb_offset(ofbi, rot); -+ } else { -+ return ofbi->region.paddr; -+ } -+} -+ -+static u32 omapfb_get_region_paddr(struct omapfb_info *ofbi) -+{ -+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) -+ return ofbi->region.vrfb.paddr[0]; -+ else -+ return ofbi->region.paddr; -+} -+ -+static void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi) -+{ -+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) -+ return ofbi->region.vrfb.vaddr[0]; -+ else -+ return ofbi->region.vaddr; -+} -+ -+static struct omapfb_colormode omapfb_colormodes[] = { -+ { -+ .dssmode = OMAP_DSS_COLOR_UYVY, -+ .bits_per_pixel = 16, -+ .nonstd = OMAPFB_COLOR_YUV422, -+ }, { -+ .dssmode = OMAP_DSS_COLOR_YUV2, -+ .bits_per_pixel = 16, -+ .nonstd = OMAPFB_COLOR_YUY422, -+ }, { -+ .dssmode = OMAP_DSS_COLOR_ARGB16, -+ .bits_per_pixel = 16, -+ .red = { .length = 4, .offset = 8, .msb_right = 0 }, -+ .green = { .length = 4, .offset = 4, .msb_right = 0 }, -+ .blue = { .length = 4, .offset = 0, .msb_right = 0 }, -+ .transp = { .length = 4, .offset = 12, .msb_right = 0 }, -+ }, { -+ .dssmode = OMAP_DSS_COLOR_RGB16, -+ .bits_per_pixel = 16, -+ .red = { .length = 5, .offset = 11, .msb_right = 0 }, -+ .green = { .length = 6, .offset = 5, .msb_right = 0 }, -+ .blue = { .length = 5, .offset = 0, .msb_right = 0 }, -+ .transp = { .length = 0, .offset = 0, .msb_right = 0 }, -+ }, { -+ .dssmode = OMAP_DSS_COLOR_RGB24P, -+ .bits_per_pixel = 24, -+ .red = { .length = 8, .offset = 16, .msb_right = 0 }, -+ .green = { .length = 8, .offset = 8, .msb_right = 0 }, -+ .blue = { .length = 8, .offset = 0, .msb_right = 0 }, -+ .transp = { .length = 0, .offset = 0, .msb_right = 0 }, -+ }, { -+ .dssmode = OMAP_DSS_COLOR_RGB24U, -+ .bits_per_pixel = 32, -+ .red = { .length = 8, .offset = 16, .msb_right = 0 }, -+ .green = { .length = 8, .offset = 8, .msb_right = 0 }, -+ .blue = { .length = 8, .offset = 0, .msb_right = 0 }, -+ .transp = { .length = 0, .offset = 0, .msb_right = 0 }, -+ }, { -+ .dssmode = OMAP_DSS_COLOR_ARGB32, -+ .bits_per_pixel = 32, -+ .red = { .length = 8, .offset = 16, .msb_right = 0 }, -+ .green = { .length = 8, .offset = 8, .msb_right = 0 }, -+ .blue = { .length = 8, .offset = 0, .msb_right = 0 }, -+ .transp = { .length = 8, .offset = 24, .msb_right = 0 }, -+ }, { -+ .dssmode = OMAP_DSS_COLOR_RGBA32, -+ .bits_per_pixel = 32, -+ .red = { .length = 8, .offset = 24, .msb_right = 0 }, -+ .green = { .length = 8, .offset = 16, .msb_right = 0 }, -+ .blue = { .length = 8, .offset = 8, .msb_right = 0 }, -+ .transp = { .length = 8, .offset = 0, .msb_right = 0 }, -+ }, { -+ .dssmode = OMAP_DSS_COLOR_RGBX32, -+ .bits_per_pixel = 32, -+ .red = { .length = 8, .offset = 24, .msb_right = 0 }, -+ .green = { .length = 8, .offset = 16, .msb_right = 0 }, -+ .blue = { .length = 8, .offset = 8, .msb_right = 0 }, -+ .transp = { .length = 0, .offset = 0, .msb_right = 0 }, -+ }, -+}; -+ -+static bool cmp_var_to_colormode(struct fb_var_screeninfo *var, -+ struct omapfb_colormode *color) -+{ -+ bool cmp_component(struct fb_bitfield *f1, struct fb_bitfield *f2) -+ { -+ return f1->length == f2->length && -+ f1->offset == f2->offset && -+ f1->msb_right == f2->msb_right; -+ } -+ -+ if (var->bits_per_pixel == 0 || -+ var->red.length == 0 || -+ var->blue.length == 0 || -+ var->green.length == 0) -+ return 0; -+ -+ return var->bits_per_pixel == color->bits_per_pixel && -+ cmp_component(&var->red, &color->red) && -+ cmp_component(&var->green, &color->green) && -+ cmp_component(&var->blue, &color->blue) && -+ cmp_component(&var->transp, &color->transp); -+} -+ -+static void assign_colormode_to_var(struct fb_var_screeninfo *var, -+ struct omapfb_colormode *color) -+{ -+ var->bits_per_pixel = color->bits_per_pixel; -+ var->nonstd = color->nonstd; -+ var->red = color->red; -+ var->green = color->green; -+ var->blue = color->blue; -+ var->transp = color->transp; -+} -+ -+static enum omap_color_mode fb_mode_to_dss_mode(struct fb_var_screeninfo *var) -+{ -+ enum omap_color_mode dssmode; -+ int i; -+ -+ /* first match with nonstd field */ -+ if (var->nonstd) { -+ for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) { -+ struct omapfb_colormode *mode = &omapfb_colormodes[i]; -+ if (var->nonstd == mode->nonstd) { -+ assign_colormode_to_var(var, mode); -+ return mode->dssmode; -+ } -+ } -+ -+ return -EINVAL; -+ } -+ -+ /* then try exact match of bpp and colors */ -+ for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) { -+ struct omapfb_colormode *mode = &omapfb_colormodes[i]; -+ if (cmp_var_to_colormode(var, mode)) { -+ assign_colormode_to_var(var, mode); -+ return mode->dssmode; -+ } -+ } -+ -+ /* match with bpp if user has not filled color fields -+ * properly */ -+ switch (var->bits_per_pixel) { -+ case 1: -+ dssmode = OMAP_DSS_COLOR_CLUT1; -+ break; -+ case 2: -+ dssmode = OMAP_DSS_COLOR_CLUT2; -+ break; -+ case 4: -+ dssmode = OMAP_DSS_COLOR_CLUT4; -+ break; -+ case 8: -+ dssmode = OMAP_DSS_COLOR_CLUT8; -+ break; -+ case 12: -+ dssmode = OMAP_DSS_COLOR_RGB12U; -+ break; -+ case 16: -+ dssmode = OMAP_DSS_COLOR_RGB16; -+ break; -+ case 24: -+ dssmode = OMAP_DSS_COLOR_RGB24P; -+ break; -+ case 32: -+ dssmode = OMAP_DSS_COLOR_RGB24U; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) { -+ struct omapfb_colormode *mode = &omapfb_colormodes[i]; -+ if (dssmode == mode->dssmode) { -+ assign_colormode_to_var(var, mode); -+ return mode->dssmode; -+ } -+ } -+ -+ return -EINVAL; -+} -+ -+int dss_mode_to_fb_mode(enum omap_color_mode dssmode, -+ struct fb_var_screeninfo *var) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) { -+ struct omapfb_colormode *mode = &omapfb_colormodes[i]; -+ if (dssmode == mode->dssmode) { -+ assign_colormode_to_var(var, mode); -+ return 0; -+ } -+ } -+ return -ENOENT; -+} -+ -+void set_fb_fix(struct fb_info *fbi) -+{ -+ struct fb_fix_screeninfo *fix = &fbi->fix; -+ struct fb_var_screeninfo *var = &fbi->var; -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_mem_region *rg = &ofbi->region; -+ -+ DBG("set_fb_fix\n"); -+ -+ /* used by open/write in fbmem.c */ -+ fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi); -+ -+ DBG("changing rotation to %d\n", var->rotate); -+ -+ /* used by mmap in fbmem.c */ -+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) { -+ switch (var->nonstd) { -+ case OMAPFB_COLOR_YUV422: -+ case OMAPFB_COLOR_YUY422: -+ fix->line_length = -+ (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 2; -+ break; -+ default: -+ fix->line_length = -+ (OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3; -+ break; -+ } -+ } else -+ fix->line_length = -+ (var->xres_virtual * var->bits_per_pixel) >> 3; -+ fix->smem_start = omapfb_get_region_paddr(ofbi); -+ fix->smem_len = rg->size; -+ -+ fix->type = FB_TYPE_PACKED_PIXELS; -+ -+ if (var->nonstd) -+ fix->visual = FB_VISUAL_PSEUDOCOLOR; -+ else { -+ switch (var->bits_per_pixel) { -+ case 32: -+ case 24: -+ case 16: -+ case 12: -+ fix->visual = FB_VISUAL_TRUECOLOR; -+ /* 12bpp is stored in 16 bits */ -+ break; -+ case 1: -+ case 2: -+ case 4: -+ case 8: -+ fix->visual = FB_VISUAL_PSEUDOCOLOR; -+ break; -+ } -+ } -+ -+ fix->accel = FB_ACCEL_NONE; -+ -+ fix->xpanstep = 1; -+ fix->ypanstep = 1; -+ -+ if (rg->size && ofbi->rotation_type == OMAP_DSS_ROT_VRFB) { -+ unsigned bytespp; -+ bool yuv_mode; -+ enum omap_color_mode mode; -+ -+ mode = fb_mode_to_dss_mode(var); -+ -+ bytespp = var->bits_per_pixel >> 3; -+ -+ if (mode == OMAP_DSS_COLOR_YUV2 || mode == OMAP_DSS_COLOR_UYVY) -+ yuv_mode = true; -+ else -+ yuv_mode = false; -+ -+ omap_vrfb_setup(&rg->vrfb, rg->paddr, -+ var->xres_virtual, -+ var->yres_virtual, -+ bytespp, yuv_mode); -+ } -+} -+ -+/* check new var and possibly modify it to be ok */ -+int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omap_dss_device *display = fb2display(fbi); -+ unsigned long max_frame_size; -+ unsigned long line_size; -+ int xres_min, yres_min; -+ int xres_max, yres_max; -+ enum omap_color_mode mode = 0; -+ int i; -+ int bytespp; -+ -+ DBG("check_fb_var %d\n", ofbi->id); -+ -+ if (ofbi->region.size == 0) -+ return 0; -+ -+ mode = fb_mode_to_dss_mode(var); -+ if (mode < 0) { -+ DBG("cannot convert var to omap dss mode\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < ofbi->num_overlays; ++i) { -+ if ((ofbi->overlays[i]->supported_modes & mode) == 0) { -+ DBG("invalid mode\n"); -+ return -EINVAL; -+ } -+ } -+ -+ if (var->rotate < 0 || var->rotate > 3) -+ return -EINVAL; -+ -+ xres_min = OMAPFB_PLANE_XRES_MIN; -+ xres_max = 2048; -+ yres_min = OMAPFB_PLANE_YRES_MIN; -+ yres_max = 2048; -+ -+ bytespp = var->bits_per_pixel >> 3; -+ -+ /* XXX: some applications seem to set virtual res to 0. */ -+ if (var->xres_virtual == 0) -+ var->xres_virtual = var->xres; -+ -+ if (var->yres_virtual == 0) -+ var->yres_virtual = var->yres; -+ -+ if (var->xres_virtual < xres_min || var->yres_virtual < yres_min) -+ return -EINVAL; -+ -+ if (var->xres < xres_min) -+ var->xres = xres_min; -+ if (var->yres < yres_min) -+ var->yres = yres_min; -+ if (var->xres > xres_max) -+ var->xres = xres_max; -+ if (var->yres > yres_max) -+ var->yres = yres_max; -+ -+ if (var->xres > var->xres_virtual) -+ var->xres = var->xres_virtual; -+ if (var->yres > var->yres_virtual) -+ var->yres = var->yres_virtual; -+ -+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) -+ line_size = OMAP_VRFB_LINE_LEN * bytespp; -+ else -+ line_size = var->xres_virtual * bytespp; -+ -+ max_frame_size = ofbi->region.size; -+ -+ DBG("max frame size %lu, line size %lu\n", max_frame_size, line_size); -+ -+ if (line_size * var->yres_virtual > max_frame_size) { -+ DBG("can't fit FB into memory, reducing y\n"); -+ var->yres_virtual = max_frame_size / line_size; -+ -+ if (var->yres_virtual < yres_min) -+ var->yres_virtual = yres_min; -+ -+ if (var->yres > var->yres_virtual) -+ var->yres = var->yres_virtual; -+ } -+ -+ if (line_size * var->yres_virtual > max_frame_size) { -+ DBG("can't fit FB into memory, reducing x\n"); -+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) -+ return -EINVAL; -+ -+ var->xres_virtual = max_frame_size / var->yres_virtual / -+ bytespp; -+ -+ if (var->xres_virtual < xres_min) -+ var->xres_virtual = xres_min; -+ -+ if (var->xres > var->xres_virtual) -+ var->xres = var->xres_virtual; -+ -+ line_size = var->xres_virtual * bytespp; -+ } -+ -+ if (line_size * var->yres_virtual > max_frame_size) { -+ DBG("cannot fit FB to memory\n"); -+ return -EINVAL; -+ } -+ -+ if (var->xres + var->xoffset > var->xres_virtual) -+ var->xoffset = var->xres_virtual - var->xres; -+ if (var->yres + var->yoffset > var->yres_virtual) -+ var->yoffset = var->yres_virtual - var->yres; -+ -+ DBG("xres = %d, yres = %d, vxres = %d, vyres = %d\n", -+ var->xres, var->yres, -+ var->xres_virtual, var->yres_virtual); -+ -+ var->height = -1; -+ var->width = -1; -+ var->grayscale = 0; -+ -+ if (display && display->get_timings) { -+ struct omap_video_timings timings; -+ display->get_timings(display, &timings); -+ -+ /* pixclock in ps, the rest in pixclock */ -+ var->pixclock = timings.pixel_clock != 0 ? -+ KHZ2PICOS(timings.pixel_clock) : -+ 0; -+ var->left_margin = timings.hfp; -+ var->right_margin = timings.hbp; -+ var->upper_margin = timings.vfp; -+ var->lower_margin = timings.vbp; -+ var->hsync_len = timings.hsw; -+ var->vsync_len = timings.vsw; -+ } else { -+ var->pixclock = 0; -+ var->left_margin = 0; -+ var->right_margin = 0; -+ var->upper_margin = 0; -+ var->lower_margin = 0; -+ var->hsync_len = 0; -+ var->vsync_len = 0; -+ } -+ -+ /* TODO: get these from panel->config */ -+ var->vmode = FB_VMODE_NONINTERLACED; -+ var->sync = 0; -+ -+ return 0; -+} -+ -+/* -+ * --------------------------------------------------------------------------- -+ * fbdev framework callbacks -+ * --------------------------------------------------------------------------- -+ */ -+static int omapfb_open(struct fb_info *fbi, int user) -+{ -+ return 0; -+} -+ -+static int omapfb_release(struct fb_info *fbi, int user) -+{ -+#if 0 -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_device *fbdev = ofbi->fbdev; -+ struct omap_dss_device *display = fb2display(fbi); -+ -+ DBG("Closing fb with plane index %d\n", ofbi->id); -+ -+ omapfb_lock(fbdev); -+ -+ if (display && display->get_update_mode && display->update) { -+ /* XXX this update should be removed, I think. But it's -+ * good for debugging */ -+ if (display->get_update_mode(display) == -+ OMAP_DSS_UPDATE_MANUAL) { -+ u16 w, h; -+ -+ if (display->sync) -+ display->sync(display); -+ -+ display->get_resolution(display, &w, &h); -+ display->update(display, 0, 0, w, h); -+ } -+ } -+ -+ if (display && display->sync) -+ display->sync(display); -+ -+ omapfb_unlock(fbdev); -+#endif -+ return 0; -+} -+ -+/* setup overlay according to the fb */ -+static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl, -+ u16 posx, u16 posy, u16 outw, u16 outh) -+{ -+ int r = 0; -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct fb_var_screeninfo *var = &fbi->var; -+ struct fb_fix_screeninfo *fix = &fbi->fix; -+ enum omap_color_mode mode = 0; -+ int offset; -+ u32 data_start_p; -+ void __iomem *data_start_v; -+ struct omap_overlay_info info; -+ int xres, yres; -+ int screen_width; -+ int mirror; -+ int rotation = var->rotate; -+ int i; -+ -+ for (i = 0; i < ofbi->num_overlays; i++) { -+ if (ovl != ofbi->overlays[i]) -+ continue; -+ -+ rotation = (rotation + ofbi->rotation[i]) % 4; -+ break; -+ } -+ -+ DBG("setup_overlay %d, posx %d, posy %d, outw %d, outh %d\n", ofbi->id, -+ posx, posy, outw, outh); -+ -+ if (rotation == FB_ROTATE_CW || rotation == FB_ROTATE_CCW) { -+ xres = var->yres; -+ yres = var->xres; -+ } else { -+ xres = var->xres; -+ yres = var->yres; -+ } -+ -+ offset = ((var->yoffset * var->xres_virtual + -+ var->xoffset) * var->bits_per_pixel) >> 3; -+ -+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) { -+ data_start_p = omapfb_get_region_rot_paddr(ofbi, rotation); -+ data_start_v = NULL; -+ } else { -+ data_start_p = omapfb_get_region_paddr(ofbi); -+ data_start_v = omapfb_get_region_vaddr(ofbi); -+ } -+ -+ data_start_p += offset; -+ data_start_v += offset; -+ -+ mode = fb_mode_to_dss_mode(var); -+ -+ if (mode == -EINVAL) { -+ DBG("fb_mode_to_dss_mode failed"); -+ r = -EINVAL; -+ goto err; -+ } -+ -+ switch (var->nonstd) { -+ case OMAPFB_COLOR_YUV422: -+ case OMAPFB_COLOR_YUY422: -+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) { -+ screen_width = fix->line_length -+ / (var->bits_per_pixel >> 2); -+ break; -+ } -+ default: -+ screen_width = fix->line_length / (var->bits_per_pixel >> 3); -+ break; -+ } -+ -+ ovl->get_overlay_info(ovl, &info); -+ -+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) -+ mirror = 0; -+ else -+ mirror = ofbi->mirror; -+ -+ info.paddr = data_start_p; -+ info.vaddr = data_start_v; -+ info.screen_width = screen_width; -+ info.width = xres; -+ info.height = yres; -+ info.color_mode = mode; -+ info.rotation_type = ofbi->rotation_type; -+ info.rotation = rotation; -+ info.mirror = mirror; -+ -+ info.pos_x = posx; -+ info.pos_y = posy; -+ info.out_width = outw; -+ info.out_height = outh; -+ -+ r = ovl->set_overlay_info(ovl, &info); -+ if (r) { -+ DBG("ovl->setup_overlay_info failed\n"); -+ goto err; -+ } -+ -+ return 0; -+ -+err: -+ DBG("setup_overlay failed\n"); -+ return r; -+} -+ -+/* apply var to the overlay */ -+int omapfb_apply_changes(struct fb_info *fbi, int init) -+{ -+ int r = 0; -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct fb_var_screeninfo *var = &fbi->var; -+ struct omap_overlay *ovl; -+ u16 posx, posy; -+ u16 outw, outh; -+ int i; -+ -+#ifdef DEBUG -+ if (omapfb_test_pattern) -+ fill_fb(fbi); -+#endif -+ -+ for (i = 0; i < ofbi->num_overlays; i++) { -+ ovl = ofbi->overlays[i]; -+ -+ DBG("apply_changes, fb %d, ovl %d\n", ofbi->id, ovl->id); -+ -+ if (ofbi->region.size == 0) { -+ /* the fb is not available. disable the overlay */ -+ omapfb_overlay_enable(ovl, 0); -+ if (!init && ovl->manager) -+ ovl->manager->apply(ovl->manager); -+ continue; -+ } -+ -+ if (init || (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) { -+ int rotation = (var->rotate + ofbi->rotation[i]) % 4; -+ if (rotation == FB_ROTATE_CW || -+ rotation == FB_ROTATE_CCW) { -+ outw = var->yres; -+ outh = var->xres; -+ } else { -+ outw = var->xres; -+ outh = var->yres; -+ } -+ } else { -+ outw = ovl->info.out_width; -+ outh = ovl->info.out_height; -+ } -+ -+ if (init) { -+ posx = 0; -+ posy = 0; -+ } else { -+ posx = ovl->info.pos_x; -+ posy = ovl->info.pos_y; -+ } -+ -+ r = omapfb_setup_overlay(fbi, ovl, posx, posy, outw, outh); -+ if (r) -+ goto err; -+ -+ if (!init && ovl->manager) -+ ovl->manager->apply(ovl->manager); -+ } -+ return 0; -+err: -+ DBG("apply_changes failed\n"); -+ return r; -+} -+ -+/* checks var and eventually tweaks it to something supported, -+ * DO NOT MODIFY PAR */ -+static int omapfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi) -+{ -+ int r; -+ -+ DBG("check_var(%d)\n", FB2OFB(fbi)->id); -+ -+ r = check_fb_var(fbi, var); -+ -+ return r; -+} -+ -+/* set the video mode according to info->var */ -+static int omapfb_set_par(struct fb_info *fbi) -+{ -+ int r; -+ -+ DBG("set_par(%d)\n", FB2OFB(fbi)->id); -+ -+ set_fb_fix(fbi); -+ r = omapfb_apply_changes(fbi, 0); -+ -+ return r; -+} -+ -+static int omapfb_pan_display(struct fb_var_screeninfo *var, -+ struct fb_info *fbi) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ int r = 0; -+ -+ DBG("pan_display(%d)\n", ofbi->id); -+ -+ if (var->xoffset != fbi->var.xoffset || -+ var->yoffset != fbi->var.yoffset) { -+ struct fb_var_screeninfo new_var; -+ -+ new_var = fbi->var; -+ new_var.xoffset = var->xoffset; -+ new_var.yoffset = var->yoffset; -+ -+ r = check_fb_var(fbi, &new_var); -+ -+ if (r == 0) { -+ fbi->var = new_var; -+ set_fb_fix(fbi); -+ r = omapfb_apply_changes(fbi, 0); -+ } -+ } -+ -+ return r; -+} -+ -+static void mmap_user_open(struct vm_area_struct *vma) -+{ -+ struct omapfb_info *ofbi = (struct omapfb_info *)vma->vm_private_data; -+ -+ atomic_inc(&ofbi->map_count); -+} -+ -+static void mmap_user_close(struct vm_area_struct *vma) -+{ -+ struct omapfb_info *ofbi = (struct omapfb_info *)vma->vm_private_data; -+ -+ atomic_dec(&ofbi->map_count); -+} -+ -+static struct vm_operations_struct mmap_user_ops = { -+ .open = mmap_user_open, -+ .close = mmap_user_close, -+}; -+ -+static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct fb_fix_screeninfo *fix = &fbi->fix; -+ unsigned long off; -+ unsigned long start; -+ u32 len; -+ -+ if (vma->vm_end - vma->vm_start == 0) -+ return 0; -+ if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) -+ return -EINVAL; -+ off = vma->vm_pgoff << PAGE_SHIFT; -+ -+ start = omapfb_get_region_paddr(ofbi); -+ len = fix->smem_len; -+ if (off >= len) -+ return -EINVAL; -+ if ((vma->vm_end - vma->vm_start + off) > len) -+ return -EINVAL; -+ -+ off += start; -+ -+ DBG("user mmap region start %lx, len %d, off %lx\n", start, len, off); -+ -+ vma->vm_pgoff = off >> PAGE_SHIFT; -+ vma->vm_flags |= VM_IO | VM_RESERVED; -+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); -+ vma->vm_ops = &mmap_user_ops; -+ vma->vm_private_data = ofbi; -+ if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT, -+ vma->vm_end - vma->vm_start, vma->vm_page_prot)) -+ return -EAGAIN; -+ /* vm_ops.open won't be called for mmap itself. */ -+ atomic_inc(&ofbi->map_count); -+ return 0; -+} -+ -+/* Store a single color palette entry into a pseudo palette or the hardware -+ * palette if one is available. For now we support only 16bpp and thus store -+ * the entry only to the pseudo palette. -+ */ -+static int _setcolreg(struct fb_info *fbi, u_int regno, u_int red, u_int green, -+ u_int blue, u_int transp, int update_hw_pal) -+{ -+ /*struct omapfb_info *ofbi = FB2OFB(fbi);*/ -+ /*struct omapfb2_device *fbdev = ofbi->fbdev;*/ -+ struct fb_var_screeninfo *var = &fbi->var; -+ int r = 0; -+ -+ enum omapfb_color_format mode = OMAPFB_COLOR_RGB24U; /* XXX */ -+ -+ /*switch (plane->color_mode) {*/ -+ switch (mode) { -+ case OMAPFB_COLOR_YUV422: -+ case OMAPFB_COLOR_YUV420: -+ case OMAPFB_COLOR_YUY422: -+ r = -EINVAL; -+ break; -+ case OMAPFB_COLOR_CLUT_8BPP: -+ case OMAPFB_COLOR_CLUT_4BPP: -+ case OMAPFB_COLOR_CLUT_2BPP: -+ case OMAPFB_COLOR_CLUT_1BPP: -+ /* -+ if (fbdev->ctrl->setcolreg) -+ r = fbdev->ctrl->setcolreg(regno, red, green, blue, -+ transp, update_hw_pal); -+ */ -+ /* Fallthrough */ -+ r = -EINVAL; -+ break; -+ case OMAPFB_COLOR_RGB565: -+ case OMAPFB_COLOR_RGB444: -+ case OMAPFB_COLOR_RGB24P: -+ case OMAPFB_COLOR_RGB24U: -+ if (r != 0) -+ break; -+ -+ if (regno < 0) { -+ r = -EINVAL; -+ break; -+ } -+ -+ if (regno < 16) { -+ u16 pal; -+ pal = ((red >> (16 - var->red.length)) << -+ var->red.offset) | -+ ((green >> (16 - var->green.length)) << -+ var->green.offset) | -+ (blue >> (16 - var->blue.length)); -+ ((u32 *)(fbi->pseudo_palette))[regno] = pal; -+ } -+ break; -+ default: -+ BUG(); -+ } -+ return r; -+} -+ -+static int omapfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, -+ u_int transp, struct fb_info *info) -+{ -+ DBG("setcolreg\n"); -+ -+ return _setcolreg(info, regno, red, green, blue, transp, 1); -+} -+ -+static int omapfb_setcmap(struct fb_cmap *cmap, struct fb_info *info) -+{ -+ int count, index, r; -+ u16 *red, *green, *blue, *transp; -+ u16 trans = 0xffff; -+ -+ DBG("setcmap\n"); -+ -+ red = cmap->red; -+ green = cmap->green; -+ blue = cmap->blue; -+ transp = cmap->transp; -+ index = cmap->start; -+ -+ for (count = 0; count < cmap->len; count++) { -+ if (transp) -+ trans = *transp++; -+ r = _setcolreg(info, index++, *red++, *green++, *blue++, trans, -+ count == cmap->len - 1); -+ if (r != 0) -+ return r; -+ } -+ -+ return 0; -+} -+ -+static void omapfb_vrfb_suspend_all(struct omapfb2_device *fbdev) -+{ -+ int i; -+ -+ for (i = 0; i < fbdev->num_fbs; i++) { -+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]); -+ -+ if (ofbi->region.vrfb.vaddr[0]) -+ omap_vrfb_suspend_ctx(&ofbi->region.vrfb); -+ } -+} -+ -+static void omapfb_vrfb_resume_all(struct omapfb2_device *fbdev) -+{ -+ int i; -+ -+ for (i = 0; i < fbdev->num_fbs; i++) { -+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]); -+ -+ if (ofbi->region.vrfb.vaddr[0]) -+ omap_vrfb_resume_ctx(&ofbi->region.vrfb); -+ } -+} -+ -+static int omapfb_blank(int blank, struct fb_info *fbi) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_device *fbdev = ofbi->fbdev; -+ struct omap_dss_device *display = fb2display(fbi); -+ int do_update = 0; -+ int r = 0; -+ -+ omapfb_lock(fbdev); -+ -+ switch (blank) { -+ case FB_BLANK_UNBLANK: -+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED) -+ goto exit; -+ -+ omapfb_vrfb_resume_all(fbdev); -+ -+ if (display->resume) -+ r = display->resume(display); -+ -+ if (r == 0 && display->get_update_mode && -+ display->get_update_mode(display) == -+ OMAP_DSS_UPDATE_MANUAL) -+ do_update = 1; -+ -+ break; -+ -+ case FB_BLANK_NORMAL: -+ /* FB_BLANK_NORMAL could be implemented. -+ * Needs DSS additions. */ -+ case FB_BLANK_VSYNC_SUSPEND: -+ case FB_BLANK_HSYNC_SUSPEND: -+ case FB_BLANK_POWERDOWN: -+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE) -+ goto exit; -+ -+ if (display->suspend) -+ r = display->suspend(display); -+ -+ omapfb_vrfb_suspend_all(fbdev); -+ -+ break; -+ -+ default: -+ r = -EINVAL; -+ } -+ -+exit: -+ omapfb_unlock(fbdev); -+ -+ if (r == 0 && do_update && display->update) { -+ u16 w, h; -+ display->get_resolution(display, &w, &h); -+ -+ r = display->update(display, 0, 0, w, h); -+ } -+ -+ return r; -+} -+ -+#if 0 -+/* XXX fb_read and fb_write are needed for VRFB */ -+ssize_t omapfb_write(struct fb_info *info, const char __user *buf, -+ size_t count, loff_t *ppos) -+{ -+ DBG("omapfb_write %d, %lu\n", count, (unsigned long)*ppos); -+ /* XXX needed for VRFB */ -+ return count; -+} -+#endif -+ -+static struct fb_ops omapfb_ops = { -+ .owner = THIS_MODULE, -+ .fb_open = omapfb_open, -+ .fb_release = omapfb_release, -+ .fb_fillrect = cfb_fillrect, -+ .fb_copyarea = cfb_copyarea, -+ .fb_imageblit = cfb_imageblit, -+ .fb_blank = omapfb_blank, -+ .fb_ioctl = omapfb_ioctl, -+ .fb_check_var = omapfb_check_var, -+ .fb_set_par = omapfb_set_par, -+ .fb_pan_display = omapfb_pan_display, -+ .fb_mmap = omapfb_mmap, -+ .fb_setcolreg = omapfb_setcolreg, -+ .fb_setcmap = omapfb_setcmap, -+ /*.fb_write = omapfb_write,*/ -+}; -+ -+static void omapfb_free_fbmem(struct fb_info *fbi) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_device *fbdev = ofbi->fbdev; -+ struct omapfb2_mem_region *rg; -+ -+ rg = &ofbi->region; -+ -+ if (rg->paddr) -+ if (omap_vram_free(rg->paddr, rg->size)) -+ dev_err(fbdev->dev, "VRAM FREE failed\n"); -+ -+ if (rg->vaddr) -+ iounmap(rg->vaddr); -+ -+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) { -+ /* unmap the 0 angle rotation */ -+ if (rg->vrfb.vaddr[0]) { -+ iounmap(rg->vrfb.vaddr[0]); -+ omap_vrfb_release_ctx(&rg->vrfb); -+ } -+ } -+ -+ rg->vaddr = NULL; -+ rg->paddr = 0; -+ rg->alloc = 0; -+ rg->size = 0; -+} -+ -+static void clear_fb_info(struct fb_info *fbi) -+{ -+ memset(&fbi->var, 0, sizeof(fbi->var)); -+ memset(&fbi->fix, 0, sizeof(fbi->fix)); -+ strlcpy(fbi->fix.id, MODULE_NAME, sizeof(fbi->fix.id)); -+} -+ -+static int omapfb_free_all_fbmem(struct omapfb2_device *fbdev) -+{ -+ int i; -+ -+ DBG("free all fbmem\n"); -+ -+ for (i = 0; i < fbdev->num_fbs; i++) { -+ struct fb_info *fbi = fbdev->fbs[i]; -+ omapfb_free_fbmem(fbi); -+ clear_fb_info(fbi); -+ } -+ -+ return 0; -+} -+ -+static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size, -+ unsigned long paddr) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_device *fbdev = ofbi->fbdev; -+ struct omapfb2_mem_region *rg; -+ void __iomem *vaddr; -+ int r; -+ -+ rg = &ofbi->region; -+ memset(rg, 0, sizeof(*rg)); -+ -+ size = PAGE_ALIGN(size); -+ -+ if (!paddr) { -+ DBG("allocating %lu bytes for fb %d\n", size, ofbi->id); -+ r = omap_vram_alloc(OMAP_VRAM_MEMTYPE_SDRAM, size, &paddr); -+ } else { -+ DBG("reserving %lu bytes at %lx for fb %d\n", size, paddr, -+ ofbi->id); -+ r = omap_vram_reserve(paddr, size); -+ } -+ -+ if (r) { -+ dev_err(fbdev->dev, "failed to allocate framebuffer\n"); -+ return -ENOMEM; -+ } -+ -+ if (ofbi->rotation_type != OMAP_DSS_ROT_VRFB) { -+ vaddr = ioremap_wc(paddr, size); -+ -+ if (!vaddr) { -+ dev_err(fbdev->dev, "failed to ioremap framebuffer\n"); -+ omap_vram_free(paddr, size); -+ return -ENOMEM; -+ } -+ -+ DBG("allocated VRAM paddr %lx, vaddr %p\n", paddr, vaddr); -+ } else { -+ void __iomem *va; -+ -+ r = omap_vrfb_request_ctx(&rg->vrfb); -+ if (r) { -+ dev_err(fbdev->dev, "vrfb create ctx failed\n"); -+ return r; -+ } -+ -+ /* only ioremap the 0 angle view */ -+ va = ioremap_wc(rg->vrfb.paddr[0], size); -+ -+ if (!va) { -+ printk(KERN_ERR "vrfb: ioremap failed\n"); -+ omap_vrfb_release_ctx(&rg->vrfb); -+ return -ENOMEM; -+ } -+ -+ DBG("ioremapped vrfb area 0 to %p\n", va); -+ -+ rg->vrfb.vaddr[0] = va; -+ -+ vaddr = NULL; -+ } -+ -+ rg->paddr = paddr; -+ rg->vaddr = vaddr; -+ rg->size = size; -+ rg->alloc = 1; -+ -+ return 0; -+} -+ -+/* allocate fbmem using display resolution as reference */ -+static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size, -+ unsigned long paddr) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omap_dss_device *display; -+ int bytespp; -+ -+ display = fb2display(fbi); -+ -+ if (!display) -+ return 0; -+ -+ switch (display->get_recommended_bpp(display)) { -+ case 16: -+ bytespp = 2; -+ break; -+ case 24: -+ bytespp = 4; -+ break; -+ default: -+ bytespp = 4; -+ break; -+ } -+ -+ if (!size) { -+ u16 w, h; -+ -+ display->get_resolution(display, &w, &h); -+ -+ if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) { -+#ifdef DEBUG -+ int oldw = w, oldh = h; -+#endif -+ -+ omap_vrfb_adjust_size(&w, &h, bytespp); -+ -+ /* Because we change the resolution of the 0 degree -+ * view, we need to alloc max(w, h) for height */ -+ h = max(w, h); -+ w = OMAP_VRFB_LINE_LEN; -+ -+ DBG("adjusting fb mem size for VRFB, %dx%d -> %dx%d\n", -+ oldw, oldh, w, h); -+ } -+ -+ size = w * h * bytespp; -+ } -+ -+ if (!size) -+ return 0; -+ -+ return omapfb_alloc_fbmem(fbi, size, paddr); -+} -+ -+static enum omap_color_mode fb_format_to_dss_mode(enum omapfb_color_format fmt) -+{ -+ enum omap_color_mode mode; -+ -+ switch (fmt) { -+ case OMAPFB_COLOR_RGB565: -+ mode = OMAP_DSS_COLOR_RGB16; -+ break; -+ case OMAPFB_COLOR_YUV422: -+ mode = OMAP_DSS_COLOR_YUV2; -+ break; -+ case OMAPFB_COLOR_CLUT_8BPP: -+ mode = OMAP_DSS_COLOR_CLUT8; -+ break; -+ case OMAPFB_COLOR_CLUT_4BPP: -+ mode = OMAP_DSS_COLOR_CLUT4; -+ break; -+ case OMAPFB_COLOR_CLUT_2BPP: -+ mode = OMAP_DSS_COLOR_CLUT2; -+ break; -+ case OMAPFB_COLOR_CLUT_1BPP: -+ mode = OMAP_DSS_COLOR_CLUT1; -+ break; -+ case OMAPFB_COLOR_RGB444: -+ mode = OMAP_DSS_COLOR_RGB12U; -+ break; -+ case OMAPFB_COLOR_YUY422: -+ mode = OMAP_DSS_COLOR_UYVY; -+ break; -+ case OMAPFB_COLOR_ARGB16: -+ mode = OMAP_DSS_COLOR_ARGB16; -+ break; -+ case OMAPFB_COLOR_RGB24U: -+ mode = OMAP_DSS_COLOR_RGB24U; -+ break; -+ case OMAPFB_COLOR_RGB24P: -+ mode = OMAP_DSS_COLOR_RGB24P; -+ break; -+ case OMAPFB_COLOR_ARGB32: -+ mode = OMAP_DSS_COLOR_ARGB32; -+ break; -+ case OMAPFB_COLOR_RGBA32: -+ mode = OMAP_DSS_COLOR_RGBA32; -+ break; -+ case OMAPFB_COLOR_RGBX32: -+ mode = OMAP_DSS_COLOR_RGBX32; -+ break; -+ default: -+ mode = -EINVAL; -+ } -+ -+ return mode; -+} -+ -+static int omapfb_parse_vram_param(const char *param, int max_entries, -+ unsigned long *sizes, unsigned long *paddrs) -+{ -+ int fbnum; -+ unsigned long size; -+ unsigned long paddr = 0; -+ char *p, *start; -+ -+ start = (char *)param; -+ -+ while (1) { -+ p = start; -+ -+ fbnum = simple_strtoul(p, &p, 10); -+ -+ if (p == param) -+ return -EINVAL; -+ -+ if (*p != ':') -+ return -EINVAL; -+ -+ if (fbnum >= max_entries) -+ return -EINVAL; -+ -+ size = memparse(p + 1, &p); -+ -+ if (!size) -+ return -EINVAL; -+ -+ paddr = 0; -+ -+ if (*p == '@') { -+ paddr = simple_strtoul(p + 1, &p, 16); -+ -+ if (!paddr) -+ return -EINVAL; -+ -+ } -+ -+ paddrs[fbnum] = paddr; -+ sizes[fbnum] = size; -+ -+ if (*p == 0) -+ break; -+ -+ if (*p != ',') -+ return -EINVAL; -+ -+ ++p; -+ -+ start = p; -+ } -+ -+ return 0; -+} -+ -+static int omapfb_allocate_all_fbs(struct omapfb2_device *fbdev) -+{ -+ int i, r; -+ unsigned long vram_sizes[10]; -+ unsigned long vram_paddrs[10]; -+ -+ memset(&vram_sizes, 0, sizeof(vram_sizes)); -+ memset(&vram_paddrs, 0, sizeof(vram_paddrs)); -+ -+ if (def_vram && omapfb_parse_vram_param(def_vram, 10, -+ vram_sizes, vram_paddrs)) { -+ dev_err(fbdev->dev, "failed to parse vram parameter\n"); -+ -+ memset(&vram_sizes, 0, sizeof(vram_sizes)); -+ memset(&vram_paddrs, 0, sizeof(vram_paddrs)); -+ } -+ -+ if (fbdev->dev->platform_data) { -+ struct omapfb_platform_data *opd; -+ opd = fbdev->dev->platform_data; -+ for (i = 0; i < opd->mem_desc.region_cnt; ++i) { -+ if (!vram_sizes[i]) { -+ unsigned long size; -+ unsigned long paddr; -+ -+ size = opd->mem_desc.region[i].size; -+ paddr = opd->mem_desc.region[i].paddr; -+ -+ vram_sizes[i] = size; -+ vram_paddrs[i] = paddr; -+ } -+ } -+ } -+ -+ for (i = 0; i < fbdev->num_fbs; i++) { -+ /* allocate memory automatically only for fb0, or if -+ * excplicitly defined with vram or plat data option */ -+ if (i == 0 || vram_sizes[i] != 0) { -+ r = omapfb_alloc_fbmem_display(fbdev->fbs[i], -+ vram_sizes[i], vram_paddrs[i]); -+ -+ if (r) -+ return r; -+ } -+ } -+ -+ for (i = 0; i < fbdev->num_fbs; i++) { -+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]); -+ struct omapfb2_mem_region *rg; -+ rg = &ofbi->region; -+ -+ DBG("region%d phys %08x virt %p size=%lu\n", -+ i, -+ rg->paddr, -+ rg->vaddr, -+ rg->size); -+ } -+ -+ return 0; -+} -+ -+int omapfb_realloc_fbmem(struct fb_info *fbi, unsigned long size, int type) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_device *fbdev = ofbi->fbdev; -+ struct omap_dss_device *display = fb2display(fbi); -+ struct omapfb2_mem_region *rg = &ofbi->region; -+ unsigned long old_size = rg->size; -+ unsigned long old_paddr = rg->paddr; -+ int old_type = rg->type; -+ int r; -+ -+ if (type > OMAPFB_MEMTYPE_MAX) -+ return -EINVAL; -+ -+ size = PAGE_ALIGN(size); -+ -+ if (old_size == size && old_type == type) -+ return 0; -+ -+ if (display && display->sync) -+ display->sync(display); -+ -+ omapfb_free_fbmem(fbi); -+ -+ if (size == 0) { -+ clear_fb_info(fbi); -+ return 0; -+ } -+ -+ r = omapfb_alloc_fbmem(fbi, size, 0); -+ -+ if (r) { -+ if (old_size) -+ omapfb_alloc_fbmem(fbi, old_size, old_paddr); -+ -+ if (rg->size == 0) -+ clear_fb_info(fbi); -+ -+ return r; -+ } -+ -+ if (old_size == size) -+ return 0; -+ -+ if (old_size == 0) { -+ DBG("initializing fb %d\n", ofbi->id); -+ r = omapfb_fb_init(fbdev, fbi); -+ if (r) { -+ DBG("omapfb_fb_init failed\n"); -+ goto err; -+ } -+ r = omapfb_apply_changes(fbi, 1); -+ if (r) { -+ DBG("omapfb_apply_changes failed\n"); -+ goto err; -+ } -+ } else { -+ struct fb_var_screeninfo new_var; -+ memcpy(&new_var, &fbi->var, sizeof(new_var)); -+ r = check_fb_var(fbi, &new_var); -+ if (r) -+ goto err; -+ memcpy(&fbi->var, &new_var, sizeof(fbi->var)); -+ set_fb_fix(fbi); -+ } -+ -+ return 0; -+err: -+ omapfb_free_fbmem(fbi); -+ clear_fb_info(fbi); -+ return r; -+} -+ -+/* initialize fb_info, var, fix to something sane based on the display */ -+static int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi) -+{ -+ struct fb_var_screeninfo *var = &fbi->var; -+ struct omap_dss_device *display = fb2display(fbi); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ int r = 0; -+ -+ fbi->fbops = &omapfb_ops; -+ fbi->flags = FBINFO_FLAG_DEFAULT; -+ fbi->pseudo_palette = fbdev->pseudo_palette; -+ -+ if (ofbi->region.size == 0) { -+ clear_fb_info(fbi); -+ return 0; -+ } -+ -+ var->nonstd = 0; -+ var->bits_per_pixel = 0; -+ -+ var->rotate = def_rotate; -+ -+ /* -+ * Check if there is a default color format set in the board file, -+ * and use this format instead the default deducted from the -+ * display bpp. -+ */ -+ if (fbdev->dev->platform_data) { -+ struct omapfb_platform_data *opd; -+ int id = ofbi->id; -+ -+ opd = fbdev->dev->platform_data; -+ if (opd->mem_desc.region[id].format_used) { -+ enum omap_color_mode mode; -+ enum omapfb_color_format format; -+ -+ format = opd->mem_desc.region[id].format; -+ mode = fb_format_to_dss_mode(format); -+ if (mode < 0) { -+ r = mode; -+ goto err; -+ } -+ r = dss_mode_to_fb_mode(mode, var); -+ if (r < 0) -+ goto err; -+ } -+ } -+ -+ if (display) { -+ u16 w, h; -+ int rotation = (var->rotate + ofbi->rotation[0]) % 4; -+ -+ display->get_resolution(display, &w, &h); -+ -+ if (rotation == FB_ROTATE_CW || -+ rotation == FB_ROTATE_CCW) { -+ var->xres = h; -+ var->yres = w; -+ } else { -+ var->xres = w; -+ var->yres = h; -+ } -+ -+ var->xres_virtual = var->xres; -+ var->yres_virtual = var->yres; -+ -+ if (!var->bits_per_pixel) { -+ switch (display->get_recommended_bpp(display)) { -+ case 16: -+ var->bits_per_pixel = 16; -+ break; -+ case 24: -+ var->bits_per_pixel = 32; -+ break; -+ default: -+ dev_err(fbdev->dev, "illegal display " -+ "bpp\n"); -+ return -EINVAL; -+ } -+ } -+ } else { -+ /* if there's no display, let's just guess some basic values */ -+ var->xres = 320; -+ var->yres = 240; -+ var->xres_virtual = var->xres; -+ var->yres_virtual = var->yres; -+ if (!var->bits_per_pixel) -+ var->bits_per_pixel = 16; -+ } -+ -+ r = check_fb_var(fbi, var); -+ if (r) -+ goto err; -+ -+ set_fb_fix(fbi); -+ -+ r = fb_alloc_cmap(&fbi->cmap, 256, 0); -+ if (r) -+ dev_err(fbdev->dev, "unable to allocate color map memory\n"); -+ -+err: -+ return r; -+} -+ -+static void fbinfo_cleanup(struct omapfb2_device *fbdev, struct fb_info *fbi) -+{ -+ fb_dealloc_cmap(&fbi->cmap); -+} -+ -+ -+static void omapfb_free_resources(struct omapfb2_device *fbdev) -+{ -+ int i; -+ -+ DBG("free_resources\n"); -+ -+ if (fbdev == NULL) -+ return; -+ -+ for (i = 0; i < fbdev->num_fbs; i++) -+ unregister_framebuffer(fbdev->fbs[i]); -+ -+ /* free the reserved fbmem */ -+ omapfb_free_all_fbmem(fbdev); -+ -+ for (i = 0; i < fbdev->num_fbs; i++) { -+ fbinfo_cleanup(fbdev, fbdev->fbs[i]); -+ framebuffer_release(fbdev->fbs[i]); -+ } -+ -+ for (i = 0; i < fbdev->num_displays; i++) { -+ if (fbdev->displays[i]->state != OMAP_DSS_DISPLAY_DISABLED) -+ fbdev->displays[i]->disable(fbdev->displays[i]); -+ -+ omap_dss_put_device(fbdev->displays[i]); -+ } -+ -+ dev_set_drvdata(fbdev->dev, NULL); -+ kfree(fbdev); -+} -+ -+static int omapfb_create_framebuffers(struct omapfb2_device *fbdev) -+{ -+ int r, i; -+ -+ fbdev->num_fbs = 0; -+ -+ DBG("create %d framebuffers\n", CONFIG_FB_OMAP2_NUM_FBS); -+ -+ /* allocate fb_infos */ -+ for (i = 0; i < CONFIG_FB_OMAP2_NUM_FBS; i++) { -+ struct fb_info *fbi; -+ struct omapfb_info *ofbi; -+ -+ fbi = framebuffer_alloc(sizeof(struct omapfb_info), -+ fbdev->dev); -+ -+ if (fbi == NULL) { -+ dev_err(fbdev->dev, -+ "unable to allocate memory for plane info\n"); -+ return -ENOMEM; -+ } -+ -+ clear_fb_info(fbi); -+ -+ fbdev->fbs[i] = fbi; -+ -+ ofbi = FB2OFB(fbi); -+ ofbi->fbdev = fbdev; -+ ofbi->id = i; -+ -+ /* assign these early, so that fb alloc can use them */ -+ ofbi->rotation_type = def_vrfb ? OMAP_DSS_ROT_VRFB : -+ OMAP_DSS_ROT_DMA; -+ ofbi->mirror = def_mirror; -+ -+ fbdev->num_fbs++; -+ } -+ -+ DBG("fb_infos allocated\n"); -+ -+ /* assign overlays for the fbs */ -+ for (i = 0; i < min(fbdev->num_fbs, fbdev->num_overlays); i++) { -+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]); -+ -+ ofbi->overlays[0] = fbdev->overlays[i]; -+ ofbi->num_overlays = 1; -+ } -+ -+ /* allocate fb memories */ -+ r = omapfb_allocate_all_fbs(fbdev); -+ if (r) { -+ dev_err(fbdev->dev, "failed to allocate fbmem\n"); -+ return r; -+ } -+ -+ DBG("fbmems allocated\n"); -+ -+ /* setup fb_infos */ -+ for (i = 0; i < fbdev->num_fbs; i++) { -+ r = omapfb_fb_init(fbdev, fbdev->fbs[i]); -+ if (r) { -+ dev_err(fbdev->dev, "failed to setup fb_info\n"); -+ return r; -+ } -+ } -+ -+ DBG("fb_infos initialized\n"); -+ -+ for (i = 0; i < fbdev->num_fbs; i++) { -+ r = register_framebuffer(fbdev->fbs[i]); -+ if (r != 0) { -+ dev_err(fbdev->dev, -+ "registering framebuffer %d failed\n", i); -+ return r; -+ } -+ } -+ -+ DBG("framebuffers registered\n"); -+ -+ for (i = 0; i < fbdev->num_fbs; i++) { -+ r = omapfb_apply_changes(fbdev->fbs[i], 1); -+ if (r) { -+ dev_err(fbdev->dev, "failed to change mode\n"); -+ return r; -+ } -+ } -+ -+ DBG("create sysfs for fbs\n"); -+ r = omapfb_create_sysfs(fbdev); -+ if (r) { -+ dev_err(fbdev->dev, "failed to create sysfs entries\n"); -+ return r; -+ } -+ -+ /* Enable fb0 */ -+ if (fbdev->num_fbs > 0) { -+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[0]); -+ -+ if (ofbi->num_overlays > 0) { -+ struct omap_overlay *ovl = ofbi->overlays[0]; -+ -+ r = omapfb_overlay_enable(ovl, 1); -+ -+ if (r) { -+ dev_err(fbdev->dev, -+ "failed to enable overlay\n"); -+ return r; -+ } -+ } -+ } -+ -+ DBG("create_framebuffers done\n"); -+ -+ return 0; -+} -+ -+static int omapfb_mode_to_timings(const char *mode_str, -+ struct omap_video_timings *timings, u8 *bpp) -+{ -+ struct fb_info fbi; -+ struct fb_var_screeninfo var; -+ struct fb_ops fbops; -+ int r; -+ -+#ifdef CONFIG_OMAP2_DSS_VENC -+ if (strcmp(mode_str, "pal") == 0) { -+ *timings = omap_dss_pal_timings; -+ *bpp = 0; -+ return 0; -+ } else if (strcmp(mode_str, "ntsc") == 0) { -+ *timings = omap_dss_ntsc_timings; -+ *bpp = 0; -+ return 0; -+ } -+#endif -+ -+ /* this is quite a hack, but I wanted to use the modedb and for -+ * that we need fb_info and var, so we create dummy ones */ -+ -+ memset(&fbi, 0, sizeof(fbi)); -+ memset(&var, 0, sizeof(var)); -+ memset(&fbops, 0, sizeof(fbops)); -+ fbi.fbops = &fbops; -+ -+ r = fb_find_mode(&var, &fbi, mode_str, NULL, 0, NULL, 24); -+ -+ if (r != 0) { -+ timings->pixel_clock = PICOS2KHZ(var.pixclock); -+ timings->hfp = var.left_margin; -+ timings->hbp = var.right_margin; -+ timings->vfp = var.upper_margin; -+ timings->vbp = var.lower_margin; -+ timings->hsw = var.hsync_len; -+ timings->vsw = var.vsync_len; -+ timings->x_res = var.xres; -+ timings->y_res = var.yres; -+ -+ switch (var.bits_per_pixel) { -+ case 16: -+ *bpp = 16; -+ break; -+ case 24: -+ case 32: -+ default: -+ *bpp = 24; -+ break; -+ } -+ -+ return 0; -+ } else { -+ return -EINVAL; -+ } -+} -+ -+static int omapfb_set_def_mode(struct omap_dss_device *display, char *mode_str) -+{ -+ int r; -+ u8 bpp; -+ struct omap_video_timings timings; -+ -+ r = omapfb_mode_to_timings(mode_str, &timings, &bpp); -+ if (r) -+ return r; -+ -+ display->panel.recommended_bpp = bpp; -+ -+ if (!display->check_timings || !display->set_timings) -+ return -EINVAL; -+ -+ r = display->check_timings(display, &timings); -+ if (r) -+ return r; -+ -+ display->set_timings(display, &timings); -+ -+ return 0; -+} -+ -+static int omapfb_parse_def_modes(struct omapfb2_device *fbdev) -+{ -+ char *str, *options, *this_opt; -+ int r = 0; -+ -+ str = kmalloc(strlen(def_mode) + 1, GFP_KERNEL); -+ strcpy(str, def_mode); -+ options = str; -+ -+ while (!r && (this_opt = strsep(&options, ",")) != NULL) { -+ char *p, *display_str, *mode_str; -+ struct omap_dss_device *display; -+ int i; -+ -+ p = strchr(this_opt, ':'); -+ if (!p) { -+ r = -EINVAL; -+ break; -+ } -+ -+ *p = 0; -+ display_str = this_opt; -+ mode_str = p + 1; -+ -+ display = NULL; -+ for (i = 0; i < fbdev->num_displays; ++i) { -+ if (strcmp(fbdev->displays[i]->name, -+ display_str) == 0) { -+ display = fbdev->displays[i]; -+ break; -+ } -+ } -+ -+ if (!display) { -+ r = -EINVAL; -+ break; -+ } -+ -+ r = omapfb_set_def_mode(display, mode_str); -+ if (r) -+ break; -+ } -+ -+ kfree(str); -+ -+ return r; -+} -+ -+static int omapfb_probe(struct platform_device *pdev) -+{ -+ struct omapfb2_device *fbdev = NULL; -+ int r = 0; -+ int i; -+ struct omap_overlay *ovl; -+ struct omap_dss_device *def_display; -+ struct omap_dss_device *dssdev; -+ -+ DBG("omapfb_probe\n"); -+ -+ if (pdev->num_resources != 0) { -+ dev_err(&pdev->dev, "probed for an unknown device\n"); -+ r = -ENODEV; -+ goto err0; -+ } -+ -+ fbdev = kzalloc(sizeof(struct omapfb2_device), GFP_KERNEL); -+ if (fbdev == NULL) { -+ r = -ENOMEM; -+ goto err0; -+ } -+ -+ mutex_init(&fbdev->mtx); -+ -+ fbdev->dev = &pdev->dev; -+ platform_set_drvdata(pdev, fbdev); -+ -+ fbdev->num_displays = 0; -+ dssdev = NULL; -+ for_each_dss_dev(dssdev) { -+ omap_dss_get_device(dssdev); -+ fbdev->displays[fbdev->num_displays++] = dssdev; -+ } -+ -+ if (fbdev->num_displays == 0) { -+ dev_err(&pdev->dev, "no displays\n"); -+ r = -EINVAL; -+ goto cleanup; -+ } -+ -+ fbdev->num_overlays = omap_dss_get_num_overlays(); -+ for (i = 0; i < fbdev->num_overlays; i++) -+ fbdev->overlays[i] = omap_dss_get_overlay(i); -+ -+ fbdev->num_managers = omap_dss_get_num_overlay_managers(); -+ for (i = 0; i < fbdev->num_managers; i++) -+ fbdev->managers[i] = omap_dss_get_overlay_manager(i); -+ -+ if (def_mode && strlen(def_mode) > 0) { -+ if (omapfb_parse_def_modes(fbdev)) -+ dev_warn(&pdev->dev, "cannot parse default modes\n"); -+ } -+ -+ r = omapfb_create_framebuffers(fbdev); -+ if (r) -+ goto cleanup; -+ -+ for (i = 0; i < fbdev->num_managers; i++) { -+ struct omap_overlay_manager *mgr; -+ mgr = fbdev->managers[i]; -+ r = mgr->apply(mgr); -+ if (r) -+ dev_warn(fbdev->dev, "failed to apply dispc config\n"); -+ } -+ -+ DBG("mgr->apply'ed\n"); -+ -+ /* gfx overlay should be the default one. find a display -+ * connected to that, and use it as default display */ -+ ovl = omap_dss_get_overlay(0); -+ if (ovl->manager && ovl->manager->device) { -+ def_display = ovl->manager->device; -+ } else { -+ dev_warn(&pdev->dev, "cannot find default display\n"); -+ def_display = NULL; -+ } -+ -+ if (def_display) { -+ u16 w, h; -+ r = def_display->enable(def_display); -+ if (r) -+ dev_warn(fbdev->dev, "Failed to enable display '%s'\n", -+ def_display->name); -+ -+ /* set the update mode */ -+ if (def_display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) { -+#ifdef CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE -+ if (def_display->enable_te) -+ def_display->enable_te(def_display, 1); -+ if (def_display->set_update_mode) -+ def_display->set_update_mode(def_display, -+ OMAP_DSS_UPDATE_AUTO); -+#else /* MANUAL_UPDATE */ -+ if (def_display->enable_te) -+ def_display->enable_te(def_display, 0); -+ if (def_display->set_update_mode) -+ def_display->set_update_mode(def_display, -+ OMAP_DSS_UPDATE_MANUAL); -+ -+ def_display->get_resolution(def_display, &w, &h); -+ def_display->update(def_display, 0, 0, w, h); -+#endif -+ } else { -+ if (def_display->set_update_mode) -+ def_display->set_update_mode(def_display, -+ OMAP_DSS_UPDATE_AUTO); -+ } -+ } -+ -+ return 0; -+ -+cleanup: -+ omapfb_free_resources(fbdev); -+err0: -+ dev_err(&pdev->dev, "failed to setup omapfb\n"); -+ return r; -+} -+ -+static int omapfb_remove(struct platform_device *pdev) -+{ -+ struct omapfb2_device *fbdev = platform_get_drvdata(pdev); -+ -+ /* FIXME: wait till completion of pending events */ -+ -+ omapfb_remove_sysfs(fbdev); -+ -+ omapfb_free_resources(fbdev); -+ -+ return 0; -+} -+ -+static struct platform_driver omapfb_driver = { -+ .probe = omapfb_probe, -+ .remove = omapfb_remove, -+ .driver = { -+ .name = "omapfb", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init omapfb_init(void) -+{ -+ DBG("omapfb_init\n"); -+ -+ if (platform_driver_register(&omapfb_driver)) { -+ printk(KERN_ERR "failed to register omapfb driver\n"); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+static void __exit omapfb_exit(void) -+{ -+ DBG("omapfb_exit\n"); -+ platform_driver_unregister(&omapfb_driver); -+} -+ -+module_param_named(mode, def_mode, charp, 0); -+module_param_named(vram, def_vram, charp, 0); -+module_param_named(rotate, def_rotate, int, 0); -+module_param_named(vrfb, def_vrfb, bool, 0); -+module_param_named(mirror, def_mirror, bool, 0); -+ -+/* late_initcall to let panel/ctrl drivers loaded first. -+ * I guess better option would be a more dynamic approach, -+ * so that omapfb reacts to new panels when they are loaded */ -+late_initcall(omapfb_init); -+/*module_init(omapfb_init);*/ -+module_exit(omapfb_exit); -+ -+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>"); -+MODULE_DESCRIPTION("OMAP2/3 Framebuffer"); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c -@@ -0,0 +1,507 @@ -+/* -+ * linux/drivers/video/omap2/omapfb-sysfs.c -+ * -+ * Copyright (C) 2008 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#include <linux/fb.h> -+#include <linux/sysfs.h> -+#include <linux/device.h> -+#include <linux/uaccess.h> -+#include <linux/platform_device.h> -+#include <linux/kernel.h> -+#include <linux/mm.h> -+#include <linux/omapfb.h> -+ -+#include <mach/display.h> -+#include <mach/vrfb.h> -+ -+#include "omapfb.h" -+ -+static ssize_t show_rotate_type(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct fb_info *fbi = dev_get_drvdata(dev); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ -+ return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->rotation_type); -+} -+ -+static ssize_t store_rotate_type(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct fb_info *fbi = dev_get_drvdata(dev); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ enum omap_dss_rotation_type rot_type; -+ int r; -+ -+ rot_type = simple_strtoul(buf, NULL, 0); -+ -+ if (rot_type != OMAP_DSS_ROT_DMA && rot_type != OMAP_DSS_ROT_VRFB) -+ return -EINVAL; -+ -+ lock_fb_info(fbi); -+ -+ r = 0; -+ if (rot_type == ofbi->rotation_type) -+ goto out; -+ -+ if (ofbi->region.size) { -+ r = -EBUSY; -+ goto out; -+ } -+ -+ ofbi->rotation_type = rot_type; -+ -+ /* -+ * Since the VRAM for this FB is not allocated at the moment we don't -+ * need to do any further parameter checking at this point. -+ */ -+out: -+ unlock_fb_info(fbi); -+ -+ return r ? r : count; -+} -+ -+ -+static ssize_t show_mirror(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct fb_info *fbi = dev_get_drvdata(dev); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ -+ return snprintf(buf, PAGE_SIZE, "%d\n", ofbi->mirror); -+} -+ -+static ssize_t store_mirror(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct fb_info *fbi = dev_get_drvdata(dev); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ bool mirror; -+ int r; -+ struct fb_var_screeninfo new_var; -+ -+ mirror = simple_strtoul(buf, NULL, 0); -+ -+ if (mirror != 0 && mirror != 1) -+ return -EINVAL; -+ -+ lock_fb_info(fbi); -+ -+ ofbi->mirror = mirror; -+ -+ memcpy(&new_var, &fbi->var, sizeof(new_var)); -+ r = check_fb_var(fbi, &new_var); -+ if (r) -+ goto out; -+ memcpy(&fbi->var, &new_var, sizeof(fbi->var)); -+ -+ set_fb_fix(fbi); -+ -+ r = omapfb_apply_changes(fbi, 0); -+ if (r) -+ goto out; -+ -+ r = count; -+out: -+ unlock_fb_info(fbi); -+ -+ return r; -+} -+ -+static ssize_t show_overlays(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct fb_info *fbi = dev_get_drvdata(dev); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_device *fbdev = ofbi->fbdev; -+ ssize_t l = 0; -+ int t; -+ -+ omapfb_lock(fbdev); -+ lock_fb_info(fbi); -+ -+ for (t = 0; t < ofbi->num_overlays; t++) { -+ struct omap_overlay *ovl = ofbi->overlays[t]; -+ int ovlnum; -+ -+ for (ovlnum = 0; ovlnum < fbdev->num_overlays; ++ovlnum) -+ if (ovl == fbdev->overlays[ovlnum]) -+ break; -+ -+ l += snprintf(buf + l, PAGE_SIZE - l, "%s%d", -+ t == 0 ? "" : ",", ovlnum); -+ } -+ -+ l += snprintf(buf + l, PAGE_SIZE - l, "\n"); -+ -+ unlock_fb_info(fbi); -+ omapfb_unlock(fbdev); -+ -+ return l; -+} -+ -+static struct omapfb_info *get_overlay_fb(struct omapfb2_device *fbdev, -+ struct omap_overlay *ovl) -+{ -+ int i, t; -+ -+ for (i = 0; i < fbdev->num_fbs; i++) { -+ struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]); -+ -+ for (t = 0; t < ofbi->num_overlays; t++) { -+ if (ofbi->overlays[t] == ovl) -+ return ofbi; -+ } -+ } -+ -+ return NULL; -+} -+ -+static ssize_t store_overlays(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct fb_info *fbi = dev_get_drvdata(dev); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ struct omapfb2_device *fbdev = ofbi->fbdev; -+ struct omap_overlay *ovls[OMAPFB_MAX_OVL_PER_FB]; -+ struct omap_overlay *ovl; -+ int num_ovls, r, i; -+ int len; -+ bool added = false; -+ -+ num_ovls = 0; -+ -+ len = strlen(buf); -+ if (buf[len - 1] == '\n') -+ len = len - 1; -+ -+ omapfb_lock(fbdev); -+ lock_fb_info(fbi); -+ -+ if (len > 0) { -+ char *p = (char *)buf; -+ int ovlnum; -+ -+ while (p < buf + len) { -+ int found; -+ if (num_ovls == OMAPFB_MAX_OVL_PER_FB) { -+ r = -EINVAL; -+ goto out; -+ } -+ -+ ovlnum = simple_strtoul(p, &p, 0); -+ if (ovlnum > fbdev->num_overlays) { -+ r = -EINVAL; -+ goto out; -+ } -+ -+ found = 0; -+ for (i = 0; i < num_ovls; ++i) { -+ if (ovls[i] == fbdev->overlays[ovlnum]) { -+ found = 1; -+ break; -+ } -+ } -+ -+ if (!found) -+ ovls[num_ovls++] = fbdev->overlays[ovlnum]; -+ -+ p++; -+ } -+ } -+ -+ for (i = 0; i < num_ovls; ++i) { -+ struct omapfb_info *ofbi2 = get_overlay_fb(fbdev, ovls[i]); -+ if (ofbi2 && ofbi2 != ofbi) { -+ dev_err(fbdev->dev, "overlay already in use\n"); -+ r = -EINVAL; -+ goto out; -+ } -+ } -+ -+ /* detach unused overlays */ -+ for (i = 0; i < ofbi->num_overlays; ++i) { -+ int t, found; -+ -+ ovl = ofbi->overlays[i]; -+ -+ found = 0; -+ -+ for (t = 0; t < num_ovls; ++t) { -+ if (ovl == ovls[t]) { -+ found = 1; -+ break; -+ } -+ } -+ -+ if (found) -+ continue; -+ -+ DBG("detaching %d\n", ofbi->overlays[i]->id); -+ -+ omapfb_overlay_enable(ovl, 0); -+ -+ if (ovl->manager) -+ ovl->manager->apply(ovl->manager); -+ -+ for (t = i + 1; t < ofbi->num_overlays; t++) { -+ ofbi->rotation[t-1] = ofbi->rotation[t]; -+ ofbi->overlays[t-1] = ofbi->overlays[t]; -+ } -+ -+ ofbi->num_overlays--; -+ i--; -+ } -+ -+ for (i = 0; i < num_ovls; ++i) { -+ int t, found; -+ -+ ovl = ovls[i]; -+ -+ found = 0; -+ -+ for (t = 0; t < ofbi->num_overlays; ++t) { -+ if (ovl == ofbi->overlays[t]) { -+ found = 1; -+ break; -+ } -+ } -+ -+ if (found) -+ continue; -+ ofbi->rotation[ofbi->num_overlays] = 0; -+ ofbi->overlays[ofbi->num_overlays++] = ovl; -+ -+ added = true; -+ } -+ -+ if (added) { -+ r = omapfb_apply_changes(fbi, 0); -+ if (r) -+ goto out; -+ } -+ -+ r = count; -+out: -+ unlock_fb_info(fbi); -+ omapfb_unlock(fbdev); -+ -+ return r; -+} -+ -+static ssize_t show_overlays_rotate(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct fb_info *fbi = dev_get_drvdata(dev); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ ssize_t l = 0; -+ int t; -+ -+ lock_fb_info(fbi); -+ -+ for (t = 0; t < ofbi->num_overlays; t++) { -+ l += snprintf(buf + l, PAGE_SIZE - l, "%s%d", -+ t == 0 ? "" : ",", ofbi->rotation[t]); -+ } -+ -+ l += snprintf(buf + l, PAGE_SIZE - l, "\n"); -+ -+ unlock_fb_info(fbi); -+ -+ return l; -+} -+ -+static ssize_t store_overlays_rotate(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ struct fb_info *fbi = dev_get_drvdata(dev); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ int num_ovls = 0, r, i; -+ int len; -+ bool changed = false; -+ u8 rotation[OMAPFB_MAX_OVL_PER_FB]; -+ -+ len = strlen(buf); -+ if (buf[len - 1] == '\n') -+ len = len - 1; -+ -+ lock_fb_info(fbi); -+ -+ if (len > 0) { -+ char *p = (char *)buf; -+ -+ while (p < buf + len) { -+ int rot; -+ -+ if (num_ovls == ofbi->num_overlays) { -+ r = -EINVAL; -+ goto out; -+ } -+ -+ rot = simple_strtoul(p, &p, 0); -+ if (rot < 0 || rot > 3) { -+ r = -EINVAL; -+ goto out; -+ } -+ -+ if (ofbi->rotation[num_ovls] != rot) -+ changed = true; -+ -+ rotation[num_ovls++] = rot; -+ -+ p++; -+ } -+ } -+ -+ if (num_ovls != ofbi->num_overlays) { -+ r = -EINVAL; -+ goto out; -+ } -+ -+ if (changed) { -+ for (i = 0; i < num_ovls; ++i) -+ ofbi->rotation[i] = rotation[i]; -+ -+ r = omapfb_apply_changes(fbi, 0); -+ if (r) -+ goto out; -+ -+ /* FIXME error handling? */ -+ } -+ -+ r = count; -+out: -+ unlock_fb_info(fbi); -+ -+ return r; -+} -+ -+static ssize_t show_size(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct fb_info *fbi = dev_get_drvdata(dev); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ -+ return snprintf(buf, PAGE_SIZE, "%lu\n", ofbi->region.size); -+} -+ -+static ssize_t store_size(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct fb_info *fbi = dev_get_drvdata(dev); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ unsigned long size; -+ int r; -+ int i; -+ -+ size = PAGE_ALIGN(simple_strtoul(buf, NULL, 0)); -+ -+ lock_fb_info(fbi); -+ -+ for (i = 0; i < ofbi->num_overlays; i++) { -+ if (ofbi->overlays[i]->info.enabled) { -+ r = -EBUSY; -+ goto out; -+ } -+ } -+ -+ if (size != ofbi->region.size) { -+ r = omapfb_realloc_fbmem(fbi, size, ofbi->region.type); -+ if (r) { -+ dev_err(dev, "realloc fbmem failed\n"); -+ goto out; -+ } -+ } -+ -+ r = count; -+out: -+ unlock_fb_info(fbi); -+ -+ return r; -+} -+ -+static ssize_t show_phys(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct fb_info *fbi = dev_get_drvdata(dev); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ -+ return snprintf(buf, PAGE_SIZE, "%0x\n", ofbi->region.paddr); -+} -+ -+static ssize_t show_virt(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct fb_info *fbi = dev_get_drvdata(dev); -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ -+ return snprintf(buf, PAGE_SIZE, "%p\n", ofbi->region.vaddr); -+} -+ -+static struct device_attribute omapfb_attrs[] = { -+ __ATTR(rotate_type, S_IRUGO | S_IWUSR, show_rotate_type, -+ store_rotate_type), -+ __ATTR(mirror, S_IRUGO | S_IWUSR, show_mirror, store_mirror), -+ __ATTR(size, S_IRUGO | S_IWUSR, show_size, store_size), -+ __ATTR(overlays, S_IRUGO | S_IWUSR, show_overlays, store_overlays), -+ __ATTR(overlays_rotate, S_IRUGO | S_IWUSR, show_overlays_rotate, -+ store_overlays_rotate), -+ __ATTR(phys_addr, S_IRUGO, show_phys, NULL), -+ __ATTR(virt_addr, S_IRUGO, show_virt, NULL), -+}; -+ -+int omapfb_create_sysfs(struct omapfb2_device *fbdev) -+{ -+ int i; -+ int r; -+ -+ DBG("create sysfs for fbs\n"); -+ for (i = 0; i < fbdev->num_fbs; i++) { -+ int t; -+ for (t = 0; t < ARRAY_SIZE(omapfb_attrs); t++) { -+ r = device_create_file(fbdev->fbs[i]->dev, -+ &omapfb_attrs[t]); -+ -+ if (r) { -+ dev_err(fbdev->dev, "failed to create sysfs " -+ "file\n"); -+ return r; -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+void omapfb_remove_sysfs(struct omapfb2_device *fbdev) -+{ -+ int i, t; -+ -+ DBG("remove sysfs for fbs\n"); -+ for (i = 0; i < fbdev->num_fbs; i++) { -+ for (t = 0; t < ARRAY_SIZE(omapfb_attrs); t++) -+ device_remove_file(fbdev->fbs[i]->dev, -+ &omapfb_attrs[t]); -+ } -+} -+ ---- /dev/null -+++ b/drivers/video/omap2/omapfb/omapfb.h -@@ -0,0 +1,146 @@ -+/* -+ * linux/drivers/video/omap2/omapfb.h -+ * -+ * Copyright (C) 2008 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see <http://www.gnu.org/licenses/>. -+ */ -+ -+#ifndef __DRIVERS_VIDEO_OMAP2_OMAPFB_H__ -+#define __DRIVERS_VIDEO_OMAP2_OMAPFB_H__ -+ -+#ifdef CONFIG_FB_OMAP2_DEBUG_SUPPORT -+#define DEBUG -+#endif -+ -+#include <mach/display.h> -+ -+#ifdef DEBUG -+extern unsigned int omapfb_debug; -+#define DBG(format, ...) \ -+ if (omapfb_debug) \ -+ printk(KERN_DEBUG "OMAPFB: " format, ## __VA_ARGS__) -+#else -+#define DBG(format, ...) -+#endif -+ -+#define FB2OFB(fb_info) ((struct omapfb_info *)(fb_info->par)) -+ -+/* max number of overlays to which a framebuffer data can be direct */ -+#define OMAPFB_MAX_OVL_PER_FB 3 -+ -+struct omapfb2_mem_region { -+ u32 paddr; -+ void __iomem *vaddr; -+ struct vrfb vrfb; -+ unsigned long size; -+ u8 type; /* OMAPFB_PLANE_MEM_* */ -+ bool alloc; /* allocated by the driver */ -+ bool map; /* kernel mapped by the driver */ -+}; -+ -+/* appended to fb_info */ -+struct omapfb_info { -+ int id; -+ struct omapfb2_mem_region region; -+ atomic_t map_count; -+ int num_overlays; -+ struct omap_overlay *overlays[OMAPFB_MAX_OVL_PER_FB]; -+ struct omapfb2_device *fbdev; -+ enum omap_dss_rotation_type rotation_type; -+ u8 rotation[OMAPFB_MAX_OVL_PER_FB]; -+ bool mirror; -+}; -+ -+struct omapfb2_device { -+ struct device *dev; -+ struct mutex mtx; -+ -+ u32 pseudo_palette[17]; -+ -+ int state; -+ -+ unsigned num_fbs; -+ struct fb_info *fbs[10]; -+ -+ unsigned num_displays; -+ struct omap_dss_device *displays[10]; -+ unsigned num_overlays; -+ struct omap_overlay *overlays[10]; -+ unsigned num_managers; -+ struct omap_overlay_manager *managers[10]; -+}; -+ -+struct omapfb_colormode { -+ enum omap_color_mode dssmode; -+ u32 bits_per_pixel; -+ u32 nonstd; -+ struct fb_bitfield red; -+ struct fb_bitfield green; -+ struct fb_bitfield blue; -+ struct fb_bitfield transp; -+}; -+ -+void set_fb_fix(struct fb_info *fbi); -+int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var); -+int omapfb_realloc_fbmem(struct fb_info *fbi, unsigned long size, int type); -+int omapfb_apply_changes(struct fb_info *fbi, int init); -+ -+int omapfb_create_sysfs(struct omapfb2_device *fbdev); -+void omapfb_remove_sysfs(struct omapfb2_device *fbdev); -+ -+int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg); -+ -+int dss_mode_to_fb_mode(enum omap_color_mode dssmode, -+ struct fb_var_screeninfo *var); -+ -+/* find the display connected to this fb, if any */ -+static inline struct omap_dss_device *fb2display(struct fb_info *fbi) -+{ -+ struct omapfb_info *ofbi = FB2OFB(fbi); -+ int i; -+ -+ /* XXX: returns the display connected to first attached overlay */ -+ for (i = 0; i < ofbi->num_overlays; i++) { -+ if (ofbi->overlays[i]->manager) -+ return ofbi->overlays[i]->manager->device; -+ } -+ -+ return NULL; -+} -+ -+static inline void omapfb_lock(struct omapfb2_device *fbdev) -+{ -+ mutex_lock(&fbdev->mtx); -+} -+ -+static inline void omapfb_unlock(struct omapfb2_device *fbdev) -+{ -+ mutex_unlock(&fbdev->mtx); -+} -+ -+static inline int omapfb_overlay_enable(struct omap_overlay *ovl, -+ int enable) -+{ -+ struct omap_overlay_info info; -+ -+ ovl->get_overlay_info(ovl, &info); -+ info.enabled = enable; -+ return ovl->set_overlay_info(ovl, &info); -+} -+ -+#endif ---- /dev/null -+++ b/drivers/video/omap2/vram.c -@@ -0,0 +1,655 @@ -+/* -+ * VRAM manager for OMAP -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+/*#define DEBUG*/ -+ -+#include <linux/kernel.h> -+#include <linux/mm.h> -+#include <linux/list.h> -+#include <linux/seq_file.h> -+#include <linux/bootmem.h> -+#include <linux/completion.h> -+#include <linux/debugfs.h> -+#include <linux/jiffies.h> -+#include <linux/module.h> -+ -+#include <asm/setup.h> -+ -+#include <mach/sram.h> -+#include <mach/vram.h> -+#include <mach/dma.h> -+ -+#ifdef DEBUG -+#define DBG(format, ...) pr_debug("VRAM: " format, ## __VA_ARGS__) -+#else -+#define DBG(format, ...) -+#endif -+ -+#define OMAP2_SRAM_START 0x40200000 -+/* Maximum size, in reality this is smaller if SRAM is partially locked. */ -+#define OMAP2_SRAM_SIZE 0xa0000 /* 640k */ -+ -+/* postponed regions are used to temporarily store region information at boot -+ * time when we cannot yet allocate the region list */ -+#define MAX_POSTPONED_REGIONS 10 -+ -+static bool vram_initialized; -+static int postponed_cnt; -+static struct { -+ unsigned long paddr; -+ size_t size; -+} postponed_regions[MAX_POSTPONED_REGIONS]; -+ -+struct vram_alloc { -+ struct list_head list; -+ unsigned long paddr; -+ unsigned pages; -+}; -+ -+struct vram_region { -+ struct list_head list; -+ struct list_head alloc_list; -+ unsigned long paddr; -+ unsigned pages; -+}; -+ -+static DEFINE_MUTEX(region_mutex); -+static LIST_HEAD(region_list); -+ -+static inline int region_mem_type(unsigned long paddr) -+{ -+ if (paddr >= OMAP2_SRAM_START && -+ paddr < OMAP2_SRAM_START + OMAP2_SRAM_SIZE) -+ return OMAP_VRAM_MEMTYPE_SRAM; -+ else -+ return OMAP_VRAM_MEMTYPE_SDRAM; -+} -+ -+static struct vram_region *omap_vram_create_region(unsigned long paddr, -+ unsigned pages) -+{ -+ struct vram_region *rm; -+ -+ rm = kzalloc(sizeof(*rm), GFP_KERNEL); -+ -+ if (rm) { -+ INIT_LIST_HEAD(&rm->alloc_list); -+ rm->paddr = paddr; -+ rm->pages = pages; -+ } -+ -+ return rm; -+} -+ -+#if 0 -+static void omap_vram_free_region(struct vram_region *vr) -+{ -+ list_del(&vr->list); -+ kfree(vr); -+} -+#endif -+ -+static struct vram_alloc *omap_vram_create_allocation(struct vram_region *vr, -+ unsigned long paddr, unsigned pages) -+{ -+ struct vram_alloc *va; -+ struct vram_alloc *new; -+ -+ new = kzalloc(sizeof(*va), GFP_KERNEL); -+ -+ if (!new) -+ return NULL; -+ -+ new->paddr = paddr; -+ new->pages = pages; -+ -+ list_for_each_entry(va, &vr->alloc_list, list) { -+ if (va->paddr > new->paddr) -+ break; -+ } -+ -+ list_add_tail(&new->list, &va->list); -+ -+ return new; -+} -+ -+static void omap_vram_free_allocation(struct vram_alloc *va) -+{ -+ list_del(&va->list); -+ kfree(va); -+} -+ -+int omap_vram_add_region(unsigned long paddr, size_t size) -+{ -+ struct vram_region *rm; -+ unsigned pages; -+ -+ if (vram_initialized) { -+ DBG("adding region paddr %08lx size %d\n", -+ paddr, size); -+ -+ size &= PAGE_MASK; -+ pages = size >> PAGE_SHIFT; -+ -+ rm = omap_vram_create_region(paddr, pages); -+ if (rm == NULL) -+ return -ENOMEM; -+ -+ list_add(&rm->list, ®ion_list); -+ } else { -+ if (postponed_cnt == MAX_POSTPONED_REGIONS) -+ return -ENOMEM; -+ -+ postponed_regions[postponed_cnt].paddr = paddr; -+ postponed_regions[postponed_cnt].size = size; -+ -+ ++postponed_cnt; -+ } -+ return 0; -+} -+ -+int omap_vram_free(unsigned long paddr, size_t size) -+{ -+ struct vram_region *rm; -+ struct vram_alloc *alloc; -+ unsigned start, end; -+ -+ DBG("free mem paddr %08lx size %d\n", paddr, size); -+ -+ size = PAGE_ALIGN(size); -+ -+ mutex_lock(®ion_mutex); -+ -+ list_for_each_entry(rm, ®ion_list, list) { -+ list_for_each_entry(alloc, &rm->alloc_list, list) { -+ start = alloc->paddr; -+ end = alloc->paddr + (alloc->pages >> PAGE_SHIFT); -+ -+ if (start >= paddr && end < paddr + size) -+ goto found; -+ } -+ } -+ -+ mutex_unlock(®ion_mutex); -+ return -EINVAL; -+ -+found: -+ omap_vram_free_allocation(alloc); -+ -+ mutex_unlock(®ion_mutex); -+ return 0; -+} -+EXPORT_SYMBOL(omap_vram_free); -+ -+static int _omap_vram_reserve(unsigned long paddr, unsigned pages) -+{ -+ struct vram_region *rm; -+ struct vram_alloc *alloc; -+ size_t size; -+ -+ size = pages << PAGE_SHIFT; -+ -+ list_for_each_entry(rm, ®ion_list, list) { -+ unsigned long start, end; -+ -+ DBG("checking region %lx %d\n", rm->paddr, rm->pages); -+ -+ if (region_mem_type(rm->paddr) != region_mem_type(paddr)) -+ continue; -+ -+ start = rm->paddr; -+ end = start + (rm->pages << PAGE_SHIFT) - 1; -+ if (start > paddr || end < paddr + size - 1) -+ continue; -+ -+ DBG("block ok, checking allocs\n"); -+ -+ list_for_each_entry(alloc, &rm->alloc_list, list) { -+ end = alloc->paddr - 1; -+ -+ if (start <= paddr && end >= paddr + size - 1) -+ goto found; -+ -+ start = alloc->paddr + (alloc->pages << PAGE_SHIFT); -+ } -+ -+ end = rm->paddr + (rm->pages << PAGE_SHIFT) - 1; -+ -+ if (!(start <= paddr && end >= paddr + size - 1)) -+ continue; -+found: -+ DBG("found area start %lx, end %lx\n", start, end); -+ -+ if (omap_vram_create_allocation(rm, paddr, pages) == NULL) -+ return -ENOMEM; -+ -+ return 0; -+ } -+ -+ return -ENOMEM; -+} -+ -+int omap_vram_reserve(unsigned long paddr, size_t size) -+{ -+ unsigned pages; -+ int r; -+ -+ DBG("reserve mem paddr %08lx size %d\n", paddr, size); -+ -+ size = PAGE_ALIGN(size); -+ pages = size >> PAGE_SHIFT; -+ -+ mutex_lock(®ion_mutex); -+ -+ r = _omap_vram_reserve(paddr, pages); -+ -+ mutex_unlock(®ion_mutex); -+ -+ return r; -+} -+EXPORT_SYMBOL(omap_vram_reserve); -+ -+static void _omap_vram_dma_cb(int lch, u16 ch_status, void *data) -+{ -+ struct completion *compl = data; -+ complete(compl); -+} -+ -+static int _omap_vram_clear(u32 paddr, unsigned pages) -+{ -+ struct completion compl; -+ unsigned elem_count; -+ unsigned frame_count; -+ int r; -+ int lch; -+ -+ init_completion(&compl); -+ -+ r = omap_request_dma(OMAP_DMA_NO_DEVICE, "VRAM DMA", -+ _omap_vram_dma_cb, -+ &compl, &lch); -+ if (r) { -+ pr_err("VRAM: request_dma failed for memory clear\n"); -+ return -EBUSY; -+ } -+ -+ elem_count = pages * PAGE_SIZE / 4; -+ frame_count = 1; -+ -+ omap_set_dma_transfer_params(lch, OMAP_DMA_DATA_TYPE_S32, -+ elem_count, frame_count, -+ OMAP_DMA_SYNC_ELEMENT, -+ 0, 0); -+ -+ omap_set_dma_dest_params(lch, 0, OMAP_DMA_AMODE_POST_INC, -+ paddr, 0, 0); -+ -+ omap_set_dma_color_mode(lch, OMAP_DMA_CONSTANT_FILL, 0x000000); -+ -+ omap_start_dma(lch); -+ -+ if (wait_for_completion_timeout(&compl, msecs_to_jiffies(1000)) == 0) { -+ omap_stop_dma(lch); -+ pr_err("VRAM: dma timeout while clearing memory\n"); -+ r = -EIO; -+ goto err; -+ } -+ -+ r = 0; -+err: -+ omap_free_dma(lch); -+ -+ return r; -+} -+ -+static int _omap_vram_alloc(int mtype, unsigned pages, unsigned long *paddr) -+{ -+ struct vram_region *rm; -+ struct vram_alloc *alloc; -+ -+ list_for_each_entry(rm, ®ion_list, list) { -+ unsigned long start, end; -+ -+ DBG("checking region %lx %d\n", rm->paddr, rm->pages); -+ -+ if (region_mem_type(rm->paddr) != mtype) -+ continue; -+ -+ start = rm->paddr; -+ -+ list_for_each_entry(alloc, &rm->alloc_list, list) { -+ end = alloc->paddr; -+ -+ if (end - start >= pages << PAGE_SHIFT) -+ goto found; -+ -+ start = alloc->paddr + (alloc->pages << PAGE_SHIFT); -+ } -+ -+ end = rm->paddr + (rm->pages << PAGE_SHIFT); -+found: -+ if (end - start < pages << PAGE_SHIFT) -+ continue; -+ -+ DBG("found %lx, end %lx\n", start, end); -+ -+ alloc = omap_vram_create_allocation(rm, start, pages); -+ if (alloc == NULL) -+ return -ENOMEM; -+ -+ *paddr = start; -+ -+ _omap_vram_clear(start, pages); -+ -+ return 0; -+ } -+ -+ return -ENOMEM; -+} -+ -+int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr) -+{ -+ unsigned pages; -+ int r; -+ -+ BUG_ON(mtype > OMAP_VRAM_MEMTYPE_MAX || !size); -+ -+ DBG("alloc mem type %d size %d\n", mtype, size); -+ -+ size = PAGE_ALIGN(size); -+ pages = size >> PAGE_SHIFT; -+ -+ mutex_lock(®ion_mutex); -+ -+ r = _omap_vram_alloc(mtype, pages, paddr); -+ -+ mutex_unlock(®ion_mutex); -+ -+ return r; -+} -+EXPORT_SYMBOL(omap_vram_alloc); -+ -+void omap_vram_get_info(unsigned long *vram, -+ unsigned long *free_vram, -+ unsigned long *largest_free_block) -+{ -+ struct vram_region *vr; -+ struct vram_alloc *va; -+ -+ *vram = 0; -+ *free_vram = 0; -+ *largest_free_block = 0; -+ -+ mutex_lock(®ion_mutex); -+ -+ list_for_each_entry(vr, ®ion_list, list) { -+ unsigned free; -+ unsigned long pa; -+ -+ pa = vr->paddr; -+ *vram += vr->pages << PAGE_SHIFT; -+ -+ list_for_each_entry(va, &vr->alloc_list, list) { -+ free = va->paddr - pa; -+ *free_vram += free; -+ if (free > *largest_free_block) -+ *largest_free_block = free; -+ pa = va->paddr + (va->pages << PAGE_SHIFT); -+ } -+ -+ free = vr->paddr + (vr->pages << PAGE_SHIFT) - pa; -+ *free_vram += free; -+ if (free > *largest_free_block) -+ *largest_free_block = free; -+ } -+ -+ mutex_unlock(®ion_mutex); -+} -+EXPORT_SYMBOL(omap_vram_get_info); -+ -+#if defined(CONFIG_DEBUG_FS) -+static int vram_debug_show(struct seq_file *s, void *unused) -+{ -+ struct vram_region *vr; -+ struct vram_alloc *va; -+ unsigned size; -+ -+ mutex_lock(®ion_mutex); -+ -+ list_for_each_entry(vr, ®ion_list, list) { -+ size = vr->pages << PAGE_SHIFT; -+ seq_printf(s, "%08lx-%08lx (%d bytes)\n", -+ vr->paddr, vr->paddr + size - 1, -+ size); -+ -+ list_for_each_entry(va, &vr->alloc_list, list) { -+ size = va->pages << PAGE_SHIFT; -+ seq_printf(s, " %08lx-%08lx (%d bytes)\n", -+ va->paddr, va->paddr + size - 1, -+ size); -+ } -+ } -+ -+ mutex_unlock(®ion_mutex); -+ -+ return 0; -+} -+ -+static int vram_debug_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, vram_debug_show, inode->i_private); -+} -+ -+static const struct file_operations vram_debug_fops = { -+ .open = vram_debug_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static int __init omap_vram_create_debugfs(void) -+{ -+ struct dentry *d; -+ -+ d = debugfs_create_file("vram", S_IRUGO, NULL, -+ NULL, &vram_debug_fops); -+ if (IS_ERR(d)) -+ return PTR_ERR(d); -+ -+ return 0; -+} -+#endif -+ -+static __init int omap_vram_init(void) -+{ -+ int i; -+ -+ vram_initialized = 1; -+ -+ for (i = 0; i < postponed_cnt; i++) -+ omap_vram_add_region(postponed_regions[i].paddr, -+ postponed_regions[i].size); -+ -+#ifdef CONFIG_DEBUG_FS -+ if (omap_vram_create_debugfs()) -+ pr_err("VRAM: Failed to create debugfs file\n"); -+#endif -+ -+ return 0; -+} -+ -+arch_initcall(omap_vram_init); -+ -+/* boottime vram alloc stuff */ -+ -+/* set from board file */ -+static u32 omap_vram_sram_start __initdata; -+static u32 omap_vram_sram_size __initdata; -+ -+/* set from board file */ -+static u32 omap_vram_sdram_start __initdata; -+static u32 omap_vram_sdram_size __initdata; -+ -+/* set from kernel cmdline */ -+static u32 omap_vram_def_sdram_size __initdata; -+static u32 omap_vram_def_sdram_start __initdata; -+ -+static void __init omap_vram_early_vram(char **p) -+{ -+ omap_vram_def_sdram_size = memparse(*p, p); -+ if (**p == ',') -+ omap_vram_def_sdram_start = simple_strtoul((*p) + 1, p, 16); -+} -+__early_param("vram=", omap_vram_early_vram); -+ -+/* -+ * Called from map_io. We need to call to this early enough so that we -+ * can reserve the fixed SDRAM regions before VM could get hold of them. -+ */ -+void __init omap_vram_reserve_sdram(void) -+{ -+ struct bootmem_data *bdata; -+ unsigned long sdram_start, sdram_size; -+ u32 paddr; -+ u32 size = 0; -+ -+ /* cmdline arg overrides the board file definition */ -+ if (omap_vram_def_sdram_size) { -+ size = omap_vram_def_sdram_size; -+ paddr = omap_vram_def_sdram_start; -+ } -+ -+ if (!size) { -+ size = omap_vram_sdram_size; -+ paddr = omap_vram_sdram_start; -+ } -+ -+#ifdef CONFIG_OMAP2_VRAM_SIZE -+ if (!size) { -+ size = CONFIG_OMAP2_VRAM_SIZE * 1024 * 1024; -+ paddr = 0; -+ } -+#endif -+ -+ if (!size) -+ return; -+ -+ size = PAGE_ALIGN(size); -+ -+ bdata = NODE_DATA(0)->bdata; -+ sdram_start = bdata->node_min_pfn << PAGE_SHIFT; -+ sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start; -+ -+ if (paddr) { -+ if ((paddr & ~PAGE_MASK) || paddr < sdram_start || -+ paddr + size > sdram_start + sdram_size) { -+ pr_err("Illegal SDRAM region for VRAM\n"); -+ return; -+ } -+ -+ if (reserve_bootmem(paddr, size, BOOTMEM_EXCLUSIVE) < 0) { -+ pr_err("FB: failed to reserve VRAM\n"); -+ return; -+ } -+ } else { -+ if (size > sdram_size) { -+ pr_err("Illegal SDRAM size for VRAM\n"); -+ return; -+ } -+ -+ paddr = virt_to_phys(alloc_bootmem_pages(size)); -+ BUG_ON(paddr & ~PAGE_MASK); -+ } -+ -+ omap_vram_add_region(paddr, size); -+ -+ pr_info("Reserving %u bytes SDRAM for VRAM\n", size); -+} -+ -+/* -+ * Called at sram init time, before anything is pushed to the SRAM stack. -+ * Because of the stack scheme, we will allocate everything from the -+ * start of the lowest address region to the end of SRAM. This will also -+ * include padding for page alignment and possible holes between regions. -+ * -+ * As opposed to the SDRAM case, we'll also do any dynamic allocations at -+ * this point, since the driver built as a module would have problem with -+ * freeing / reallocating the regions. -+ */ -+unsigned long __init omap_vram_reserve_sram(unsigned long sram_pstart, -+ unsigned long sram_vstart, -+ unsigned long sram_size, -+ unsigned long pstart_avail, -+ unsigned long size_avail) -+{ -+ unsigned long pend_avail; -+ unsigned long reserved; -+ u32 paddr; -+ u32 size; -+ -+ paddr = omap_vram_sram_start; -+ size = omap_vram_sram_size; -+ -+ if (!size) -+ return 0; -+ -+ reserved = 0; -+ pend_avail = pstart_avail + size_avail; -+ -+ if (!paddr) { -+ /* Dynamic allocation */ -+ if ((size_avail & PAGE_MASK) < size) { -+ pr_err("Not enough SRAM for VRAM\n"); -+ return 0; -+ } -+ size_avail = (size_avail - size) & PAGE_MASK; -+ paddr = pstart_avail + size_avail; -+ } -+ -+ if (paddr < sram_pstart || -+ paddr + size > sram_pstart + sram_size) { -+ pr_err("Illegal SRAM region for VRAM\n"); -+ return 0; -+ } -+ -+ /* Reserve everything above the start of the region. */ -+ if (pend_avail - paddr > reserved) -+ reserved = pend_avail - paddr; -+ size_avail = pend_avail - reserved - pstart_avail; -+ -+ omap_vram_add_region(paddr, size); -+ -+ if (reserved) -+ pr_info("Reserving %lu bytes SRAM for VRAM\n", reserved); -+ -+ return reserved; -+} -+ -+void __init omap_vram_set_sdram_vram(u32 size, u32 start) -+{ -+ omap_vram_sdram_start = start; -+ omap_vram_sdram_size = size; -+} -+ -+void __init omap_vram_set_sram_vram(u32 size, u32 start) -+{ -+ omap_vram_sram_start = start; -+ omap_vram_sram_size = size; -+} ---- /dev/null -+++ b/drivers/video/omap2/vrfb.c -@@ -0,0 +1,277 @@ -+/* -+ * VRFB Rotation Engine -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/ioport.h> -+#include <linux/io.h> -+#include <linux/bitops.h> -+#include <linux/mutex.h> -+ -+#include <mach/io.h> -+#include <mach/vrfb.h> -+#include <mach/sdrc.h> -+/*#define DEBUG*/ -+ -+#ifdef DEBUG -+#define DBG(format, ...) pr_debug("VRFB: " format, ## __VA_ARGS__) -+#else -+#define DBG(format, ...) -+#endif -+ -+#define SMS_ROT_VIRT_BASE(context, rot) \ -+ (((context >= 4) ? 0xD0000000 : 0x70000000) \ -+ + (0x4000000 * (context)) \ -+ + (0x1000000 * (rot))) -+ -+#define OMAP_VRFB_SIZE (2048 * 2048 * 4) -+ -+#define VRFB_PAGE_WIDTH_EXP 5 /* Assuming SDRAM pagesize= 1024 */ -+#define VRFB_PAGE_HEIGHT_EXP 5 /* 1024 = 2^5 * 2^5 */ -+#define VRFB_PAGE_WIDTH (1 << VRFB_PAGE_WIDTH_EXP) -+#define VRFB_PAGE_HEIGHT (1 << VRFB_PAGE_HEIGHT_EXP) -+#define SMS_IMAGEHEIGHT_OFFSET 16 -+#define SMS_IMAGEWIDTH_OFFSET 0 -+#define SMS_PH_OFFSET 8 -+#define SMS_PW_OFFSET 4 -+#define SMS_PS_OFFSET 0 -+ -+#define VRFB_NUM_CTXS 12 -+/* bitmap of reserved contexts */ -+static unsigned long ctx_map; -+/* bitmap of contexts for which we have to keep the HW context valid */ -+static unsigned long ctx_map_active; -+ -+static DEFINE_MUTEX(ctx_lock); -+ -+/* -+ * Access to this happens from client drivers or the PM core after wake-up. -+ * For the first case we require locking at the driver level, for the second -+ * we don't need locking, since no drivers will run until after the wake-up -+ * has finished. -+ */ -+static struct { -+ u32 physical_ba; -+ u32 control; -+ u32 size; -+} vrfb_hw_context[VRFB_NUM_CTXS]; -+ -+static inline void restore_hw_context(int ctx) -+{ -+ omap2_sms_write_rot_control(vrfb_hw_context[ctx].control, ctx); -+ omap2_sms_write_rot_size(vrfb_hw_context[ctx].size, ctx); -+ omap2_sms_write_rot_physical_ba(vrfb_hw_context[ctx].physical_ba, ctx); -+} -+ -+void omap_vrfb_restore_context(void) -+{ -+ int i; -+ unsigned long map = ctx_map_active; -+ -+ for (i = ffs(map); i; i = ffs(map)) { -+ /* i=1..32 */ -+ i--; -+ map &= ~(1 << i); -+ restore_hw_context(i); -+ } -+} -+ -+void omap_vrfb_adjust_size(u16 *width, u16 *height, -+ u8 bytespp) -+{ -+ *width = ALIGN(*width * bytespp, VRFB_PAGE_WIDTH) / bytespp; -+ *height = ALIGN(*height, VRFB_PAGE_HEIGHT); -+} -+EXPORT_SYMBOL(omap_vrfb_adjust_size); -+ -+void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, -+ u16 width, u16 height, -+ unsigned bytespp, bool yuv_mode) -+{ -+ unsigned pixel_size_exp; -+ u16 vrfb_width; -+ u16 vrfb_height; -+ u8 ctx = vrfb->context; -+ u32 size; -+ u32 control; -+ -+ DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr, -+ width, height, color_mode); -+ -+ /* For YUV2 and UYVY modes VRFB needs to handle pixels a bit -+ * differently. See TRM. */ -+ if (yuv_mode) { -+ bytespp *= 2; -+ width /= 2; -+ } -+ -+ if (bytespp == 4) -+ pixel_size_exp = 2; -+ else if (bytespp == 2) -+ pixel_size_exp = 1; -+ else -+ BUG(); -+ -+ vrfb_width = ALIGN(width * bytespp, VRFB_PAGE_WIDTH) / bytespp; -+ vrfb_height = ALIGN(height, VRFB_PAGE_HEIGHT); -+ -+ DBG("vrfb w %u, h %u bytespp %d\n", vrfb_width, vrfb_height, bytespp); -+ -+ size = vrfb_width << SMS_IMAGEWIDTH_OFFSET; -+ size |= vrfb_height << SMS_IMAGEHEIGHT_OFFSET; -+ -+ control = pixel_size_exp << SMS_PS_OFFSET; -+ control |= VRFB_PAGE_WIDTH_EXP << SMS_PW_OFFSET; -+ control |= VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET; -+ -+ vrfb_hw_context[ctx].physical_ba = paddr; -+ vrfb_hw_context[ctx].size = size; -+ vrfb_hw_context[ctx].control = control; -+ -+ omap2_sms_write_rot_physical_ba(paddr, ctx); -+ omap2_sms_write_rot_size(size, ctx); -+ omap2_sms_write_rot_control(control, ctx); -+ -+ DBG("vrfb offset pixels %d, %d\n", -+ vrfb_width - width, vrfb_height - height); -+ -+ vrfb->xoffset = vrfb_width - width; -+ vrfb->yoffset = vrfb_height - height; -+ vrfb->bytespp = bytespp; -+} -+EXPORT_SYMBOL(omap_vrfb_setup); -+ -+void omap_vrfb_release_ctx(struct vrfb *vrfb) -+{ -+ int rot; -+ int ctx = vrfb->context; -+ -+ if (ctx == 0xff) -+ return; -+ -+ DBG("release ctx %d\n", ctx); -+ -+ mutex_lock(&ctx_lock); -+ -+ BUG_ON(!(ctx_map & (1 << ctx))); -+ -+ clear_bit(ctx, &ctx_map_active); -+ clear_bit(ctx, &ctx_map); -+ -+ for (rot = 0; rot < 4; ++rot) { -+ if (vrfb->paddr[rot]) { -+ release_mem_region(vrfb->paddr[rot], OMAP_VRFB_SIZE); -+ vrfb->paddr[rot] = 0; -+ } -+ } -+ -+ vrfb->context = 0xff; -+ -+ mutex_unlock(&ctx_lock); -+} -+EXPORT_SYMBOL(omap_vrfb_release_ctx); -+ -+int omap_vrfb_request_ctx(struct vrfb *vrfb) -+{ -+ int rot; -+ u32 paddr; -+ u8 ctx; -+ int r; -+ -+ DBG("request ctx\n"); -+ -+ mutex_lock(&ctx_lock); -+ -+ for (ctx = 0; ctx < VRFB_NUM_CTXS; ++ctx) -+ if ((ctx_map & (1 << ctx)) == 0) -+ break; -+ -+ if (ctx == VRFB_NUM_CTXS) { -+ pr_err("vrfb: no free contexts\n"); -+ r = -EBUSY; -+ goto out; -+ } -+ -+ DBG("found free ctx %d\n", ctx); -+ -+ set_bit(ctx, &ctx_map); -+ WARN_ON(ctx_map_active & (1 << ctx)); -+ set_bit(ctx, &ctx_map_active); -+ -+ memset(vrfb, 0, sizeof(*vrfb)); -+ -+ vrfb->context = ctx; -+ -+ for (rot = 0; rot < 4; ++rot) { -+ paddr = SMS_ROT_VIRT_BASE(ctx, rot); -+ if (!request_mem_region(paddr, OMAP_VRFB_SIZE, "vrfb")) { -+ pr_err("vrfb: failed to reserve VRFB " -+ "area for ctx %d, rotation %d\n", -+ ctx, rot * 90); -+ omap_vrfb_release_ctx(vrfb); -+ r = -ENOMEM; -+ goto out; -+ } -+ -+ vrfb->paddr[rot] = paddr; -+ -+ DBG("VRFB %d/%d: %lx\n", ctx, rot*90, vrfb->paddr[rot]); -+ } -+ -+ r = 0; -+out: -+ mutex_unlock(&ctx_lock); -+ return r; -+} -+EXPORT_SYMBOL(omap_vrfb_request_ctx); -+ -+void omap_vrfb_suspend_ctx(struct vrfb *vrfb) -+{ -+ DBG("suspend ctx %d\n", vrfb->context); -+ mutex_lock(&ctx_lock); -+ -+ BUG_ON(vrfb->context >= VRFB_NUM_CTXS); -+ BUG_ON(!((1 << vrfb->context) & ctx_map_active)); -+ -+ clear_bit(vrfb->context, &ctx_map_active); -+ mutex_unlock(&ctx_lock); -+} -+EXPORT_SYMBOL(omap_vrfb_suspend_ctx); -+ -+void omap_vrfb_resume_ctx(struct vrfb *vrfb) -+{ -+ DBG("resume ctx %d\n", vrfb->context); -+ mutex_lock(&ctx_lock); -+ -+ BUG_ON(vrfb->context >= VRFB_NUM_CTXS); -+ BUG_ON((1 << vrfb->context) & ctx_map_active); -+ -+ /* -+ * omap_vrfb_restore_context is normally called by the core domain -+ * save / restore logic, but since this VRFB context was suspended -+ * those calls didn't actually restore the context and now we might -+ * have an invalid context. Do an explicit restore here. -+ */ -+ restore_hw_context(vrfb->context); -+ set_bit(vrfb->context, &ctx_map_active); -+ mutex_unlock(&ctx_lock); -+} -+EXPORT_SYMBOL(omap_vrfb_resume_ctx); -+ ---- /dev/null -+++ b/include/linux/omapfb.h -@@ -0,0 +1,242 @@ -+/* -+ * File: include/linux/omapfb.h -+ * -+ * Framebuffer driver for TI OMAP boards -+ * -+ * Copyright (C) 2004 Nokia Corporation -+ * Author: Imre Deak <imre.deak@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#ifndef __LINUX_OMAPFB_H__ -+#define __LINUX_OMAPFB_H__ -+ -+#include <linux/fb.h> -+#include <linux/ioctl.h> -+#include <linux/types.h> -+ -+/* IOCTL commands. */ -+ -+#define OMAP_IOW(num, dtype) _IOW('O', num, dtype) -+#define OMAP_IOR(num, dtype) _IOR('O', num, dtype) -+#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype) -+#define OMAP_IO(num) _IO('O', num) -+ -+#define OMAPFB_MIRROR OMAP_IOW(31, int) -+#define OMAPFB_SYNC_GFX OMAP_IO(37) -+#define OMAPFB_VSYNC OMAP_IO(38) -+#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int) -+#define OMAPFB_GET_CAPS OMAP_IOR(42, struct omapfb_caps) -+#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int) -+#define OMAPFB_LCD_TEST OMAP_IOW(45, int) -+#define OMAPFB_CTRL_TEST OMAP_IOW(46, int) -+#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old) -+#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key) -+#define OMAPFB_GET_COLOR_KEY OMAP_IOW(51, struct omapfb_color_key) -+#define OMAPFB_SETUP_PLANE OMAP_IOW(52, struct omapfb_plane_info) -+#define OMAPFB_QUERY_PLANE OMAP_IOW(53, struct omapfb_plane_info) -+#define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window) -+#define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info) -+#define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info) -+#define OMAPFB_WAITFORVSYNC OMAP_IO(57) -+#define OMAPFB_MEMORY_READ OMAP_IOR(58, struct omapfb_memory_read) -+#define OMAPFB_GET_OVERLAY_COLORMODE OMAP_IOR(59, struct omapfb_ovl_colormode) -+#define OMAPFB_WAITFORGO OMAP_IO(60) -+#define OMAPFB_GET_VRAM_INFO OMAP_IOR(61, struct omapfb_vram_info) -+ -+#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff -+#define OMAPFB_CAPS_LCDC_MASK 0x00fff000 -+#define OMAPFB_CAPS_PANEL_MASK 0xff000000 -+ -+#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000 -+#define OMAPFB_CAPS_TEARSYNC 0x00002000 -+#define OMAPFB_CAPS_PLANE_RELOCATE_MEM 0x00004000 -+#define OMAPFB_CAPS_PLANE_SCALE 0x00008000 -+#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000 -+#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000 -+#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000 -+#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000 -+#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000 -+ -+/* Values from DSP must map to lower 16-bits */ -+#define OMAPFB_FORMAT_MASK 0x00ff -+#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100 -+#define OMAPFB_FORMAT_FLAG_TEARSYNC 0x0200 -+#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC 0x0400 -+#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY 0x0800 -+#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY 0x1000 -+ -+#define OMAPFB_MEMTYPE_SDRAM 0 -+#define OMAPFB_MEMTYPE_SRAM 1 -+#define OMAPFB_MEMTYPE_MAX 1 -+ -+enum omapfb_color_format { -+ OMAPFB_COLOR_RGB565 = 0, -+ OMAPFB_COLOR_YUV422, -+ OMAPFB_COLOR_YUV420, -+ OMAPFB_COLOR_CLUT_8BPP, -+ OMAPFB_COLOR_CLUT_4BPP, -+ OMAPFB_COLOR_CLUT_2BPP, -+ OMAPFB_COLOR_CLUT_1BPP, -+ OMAPFB_COLOR_RGB444, -+ OMAPFB_COLOR_YUY422, -+ -+ OMAPFB_COLOR_ARGB16, -+ OMAPFB_COLOR_RGB24U, /* RGB24, 32-bit container */ -+ OMAPFB_COLOR_RGB24P, /* RGB24, 24-bit container */ -+ OMAPFB_COLOR_ARGB32, -+ OMAPFB_COLOR_RGBA32, -+ OMAPFB_COLOR_RGBX32, -+}; -+ -+struct omapfb_update_window { -+ __u32 x, y; -+ __u32 width, height; -+ __u32 format; -+ __u32 out_x, out_y; -+ __u32 out_width, out_height; -+ __u32 reserved[8]; -+}; -+ -+struct omapfb_update_window_old { -+ __u32 x, y; -+ __u32 width, height; -+ __u32 format; -+}; -+ -+enum omapfb_plane { -+ OMAPFB_PLANE_GFX = 0, -+ OMAPFB_PLANE_VID1, -+ OMAPFB_PLANE_VID2, -+}; -+ -+enum omapfb_channel_out { -+ OMAPFB_CHANNEL_OUT_LCD = 0, -+ OMAPFB_CHANNEL_OUT_DIGIT, -+}; -+ -+struct omapfb_plane_info { -+ __u32 pos_x; -+ __u32 pos_y; -+ __u8 enabled; -+ __u8 channel_out; -+ __u8 mirror; -+ __u8 reserved1; -+ __u32 out_width; -+ __u32 out_height; -+ __u32 reserved2[12]; -+}; -+ -+struct omapfb_mem_info { -+ __u32 size; -+ __u8 type; -+ __u8 reserved[3]; -+}; -+ -+struct omapfb_caps { -+ __u32 ctrl; -+ __u32 plane_color; -+ __u32 wnd_color; -+}; -+ -+enum omapfb_color_key_type { -+ OMAPFB_COLOR_KEY_DISABLED = 0, -+ OMAPFB_COLOR_KEY_GFX_DST, -+ OMAPFB_COLOR_KEY_VID_SRC, -+}; -+ -+struct omapfb_color_key { -+ __u8 channel_out; -+ __u32 background; -+ __u32 trans_key; -+ __u8 key_type; -+}; -+ -+enum omapfb_update_mode { -+ OMAPFB_UPDATE_DISABLED = 0, -+ OMAPFB_AUTO_UPDATE, -+ OMAPFB_MANUAL_UPDATE -+}; -+ -+struct omapfb_memory_read { -+ __u16 x; -+ __u16 y; -+ __u16 w; -+ __u16 h; -+ size_t buffer_size; -+ void __user *buffer; -+}; -+ -+struct omapfb_ovl_colormode { -+ __u8 overlay_idx; -+ __u8 mode_idx; -+ __u32 bits_per_pixel; -+ __u32 nonstd; -+ struct fb_bitfield red; -+ struct fb_bitfield green; -+ struct fb_bitfield blue; -+ struct fb_bitfield transp; -+}; -+ -+struct omapfb_vram_info { -+ __u32 total; -+ __u32 free; -+ __u32 largest_free_block; -+ __u32 reserved[5]; -+}; -+ -+#ifdef __KERNEL__ -+ -+#include <mach/board.h> -+ -+#ifdef CONFIG_ARCH_OMAP1 -+#define OMAPFB_PLANE_NUM 1 -+#else -+#define OMAPFB_PLANE_NUM 3 -+#endif -+ -+struct omapfb_mem_region { -+ u32 paddr; -+ void __iomem *vaddr; -+ unsigned long size; -+ u8 type; /* OMAPFB_PLANE_MEM_* */ -+ enum omapfb_color_format format;/* OMAPFB_COLOR_* */ -+ unsigned format_used:1; /* Must be set when format is set. -+ * Needed b/c of the badly chosen 0 -+ * base for OMAPFB_COLOR_* values -+ */ -+ unsigned alloc:1; /* allocated by the driver */ -+ unsigned map:1; /* kernel mapped by the driver */ -+}; -+ -+struct omapfb_mem_desc { -+ int region_cnt; -+ struct omapfb_mem_region region[OMAPFB_PLANE_NUM]; -+}; -+ -+struct omapfb_platform_data { -+ struct omap_lcd_config lcd; -+ struct omapfb_mem_desc mem_desc; -+ void *ctrl_platform_data; -+}; -+ -+/* in arch/arm/plat-omap/fb.c */ -+extern void omapfb_set_ctrl_platform_data(void *pdata); -+extern void omapfb_reserve_sdram(void); -+ -+#endif -+ -+#endif /* __OMAPFB_H */ diff --git a/target/linux/omap35xx/patches-2.6.32/002-OMAP.patch b/target/linux/omap35xx/patches-2.6.32/002-OMAP.patch deleted file mode 100644 index e2c9056..0000000 --- a/target/linux/omap35xx/patches-2.6.32/002-OMAP.patch +++ /dev/null @@ -1,9583 +0,0 @@ ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1511,6 +1511,10 @@ source "net/Kconfig" - - source "drivers/Kconfig" - -+if ARCH_OMAP -+source "drivers/cbus/Kconfig" -+endif -+ - source "fs/Kconfig" - - source "arch/arm/Kconfig.debug" ---- a/arch/arm/mach-omap1/board-fsample.c -+++ b/arch/arm/mach-omap1/board-fsample.c -@@ -107,7 +107,7 @@ static struct resource smc91x_resources[ - .flags = IORESOURCE_MEM, - }, - [1] = { -- .start = INT_730_MPU_EXT_NIRQ, -+ .start = INT_7XX_MPU_EXT_NIRQ, - .end = 0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -@@ -196,8 +196,8 @@ static struct platform_device smc91x_dev - - static struct resource kp_resources[] = { - [0] = { -- .start = INT_730_MPUIO_KEYPAD, -- .end = INT_730_MPUIO_KEYPAD, -+ .start = INT_7XX_MPUIO_KEYPAD, -+ .end = INT_7XX_MPUIO_KEYPAD, - .flags = IORESOURCE_IRQ, - }, - }; -@@ -309,7 +309,7 @@ static void __init omap_fsample_map_io(v - /* - * Hold GSM Reset until needed - */ -- omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL); -+ omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL); - - /* - * UARTs -> done automagically by 8250 driver -@@ -320,21 +320,21 @@ static void __init omap_fsample_map_io(v - */ - - /* Flash: CS0 timings setup */ -- omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0); -- omap_writel(0x00000088, OMAP730_FLASH_ACFG_0); -+ omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0); -+ omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0); - - /* - * Ethernet support through the debug board - * CS1 timings setup - */ -- omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1); -- omap_writel(0x00000000, OMAP730_FLASH_ACFG_1); -+ omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1); -+ omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1); - - /* - * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, - * It is used as the Ethernet controller interrupt - */ -- omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9); -+ omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9); - } - - MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample") ---- a/arch/arm/mach-omap1/board-perseus2.c -+++ b/arch/arm/mach-omap1/board-perseus2.c -@@ -74,7 +74,7 @@ static struct resource smc91x_resources[ - .flags = IORESOURCE_MEM, - }, - [1] = { -- .start = INT_730_MPU_EXT_NIRQ, -+ .start = INT_7XX_MPU_EXT_NIRQ, - .end = 0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -@@ -163,8 +163,8 @@ static struct platform_device smc91x_dev - - static struct resource kp_resources[] = { - [0] = { -- .start = INT_730_MPUIO_KEYPAD, -- .end = INT_730_MPUIO_KEYPAD, -+ .start = INT_7XX_MPUIO_KEYPAD, -+ .end = INT_7XX_MPUIO_KEYPAD, - .flags = IORESOURCE_IRQ, - }, - }; -@@ -270,7 +270,7 @@ static void __init omap_perseus2_map_io( - /* - * Hold GSM Reset until needed - */ -- omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL); -+ omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL); - - /* - * UARTs -> done automagically by 8250 driver -@@ -281,21 +281,21 @@ static void __init omap_perseus2_map_io( - */ - - /* Flash: CS0 timings setup */ -- omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0); -- omap_writel(0x00000088, OMAP730_FLASH_ACFG_0); -+ omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0); -+ omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0); - - /* - * Ethernet support through the debug board - * CS1 timings setup - */ -- omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1); -- omap_writel(0x00000000, OMAP730_FLASH_ACFG_1); -+ omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1); -+ omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1); - - /* - * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, - * It is used as the Ethernet controller interrupt - */ -- omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9); -+ omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9); - } - - MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") ---- a/arch/arm/mach-omap1/clock.c -+++ b/arch/arm/mach-omap1/clock.c -@@ -69,13 +69,13 @@ struct omap_clk { - } - - #define CK_310 (1 << 0) --#define CK_730 (1 << 1) -+#define CK_7XX (1 << 1) - #define CK_1510 (1 << 2) - #define CK_16XX (1 << 3) - - static struct omap_clk omap_clks[] = { - /* non-ULPD clocks */ -- CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310), -+ CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), - /* CK_GEN1 clocks */ - CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), -@@ -83,7 +83,7 @@ static struct omap_clk omap_clks[] = { - CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), -- CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), -+ CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), - CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), -@@ -97,7 +97,7 @@ static struct omap_clk omap_clks[] = { - CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), - CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), - /* CK_GEN3 clocks */ -- CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_730), -+ CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), - CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), - CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX), - CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), -@@ -108,7 +108,7 @@ static struct omap_clk omap_clks[] = { - CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), - CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), - CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), -- CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_730), -+ CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), - CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), - /* ULPD clocks */ - CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), -@@ -398,7 +398,7 @@ static int omap1_select_table_rate(struc - * Reprogramming the DPLL is tricky, it must be done from SRAM. - * (on 730, bit 13 must always be 1) - */ -- if (cpu_is_omap730()) -+ if (cpu_is_omap7xx()) - omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); - else - omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); -@@ -783,8 +783,8 @@ int __init omap1_clk_init(void) - cpu_mask |= CK_16XX; - if (cpu_is_omap1510()) - cpu_mask |= CK_1510; -- if (cpu_is_omap730()) -- cpu_mask |= CK_730; -+ if (cpu_is_omap7xx()) -+ cpu_mask |= CK_7XX; - if (cpu_is_omap310()) - cpu_mask |= CK_310; - -@@ -800,7 +800,7 @@ int __init omap1_clk_init(void) - crystal_type = info->system_clock_type; - } - --#if defined(CONFIG_ARCH_OMAP730) -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) - ck_ref.rate = 13000000; - #elif defined(CONFIG_ARCH_OMAP16XX) - if (crystal_type == 2) -@@ -847,7 +847,7 @@ int __init omap1_clk_init(void) - printk(KERN_ERR "System frequencies not set. Check your config.\n"); - /* Guess sane values (60MHz) */ - omap_writew(0x2290, DPLL_CTL); -- omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); -+ omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); - ck_dpll1.rate = 60000000; - } - #endif -@@ -862,7 +862,7 @@ int __init omap1_clk_init(void) - - #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) - /* Select slicer output as OMAP input clock */ -- omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); -+ omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL); - #endif - - /* Amstrad Delta wants BCLK high when inactive */ -@@ -873,7 +873,7 @@ int __init omap1_clk_init(void) - - /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ - /* (on 730, bit 13 must not be cleared) */ -- if (cpu_is_omap730()) -+ if (cpu_is_omap7xx()) - omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); - else - omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); ---- a/arch/arm/mach-omap1/io.c -+++ b/arch/arm/mach-omap1/io.c -@@ -36,33 +36,17 @@ static struct map_desc omap_io_desc[] __ - } - }; - --#ifdef CONFIG_ARCH_OMAP730 --static struct map_desc omap730_io_desc[] __initdata = { -+#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) -+static struct map_desc omap7xx_io_desc[] __initdata = { - { -- .virtual = OMAP730_DSP_BASE, -- .pfn = __phys_to_pfn(OMAP730_DSP_START), -- .length = OMAP730_DSP_SIZE, -+ .virtual = OMAP7XX_DSP_BASE, -+ .pfn = __phys_to_pfn(OMAP7XX_DSP_START), -+ .length = OMAP7XX_DSP_SIZE, - .type = MT_DEVICE - }, { -- .virtual = OMAP730_DSPREG_BASE, -- .pfn = __phys_to_pfn(OMAP730_DSPREG_START), -- .length = OMAP730_DSPREG_SIZE, -- .type = MT_DEVICE -- } --}; --#endif -- --#ifdef CONFIG_ARCH_OMAP850 --static struct map_desc omap850_io_desc[] __initdata = { -- { -- .virtual = OMAP850_DSP_BASE, -- .pfn = __phys_to_pfn(OMAP850_DSP_START), -- .length = OMAP850_DSP_SIZE, -- .type = MT_DEVICE -- }, { -- .virtual = OMAP850_DSPREG_BASE, -- .pfn = __phys_to_pfn(OMAP850_DSPREG_START), -- .length = OMAP850_DSPREG_SIZE, -+ .virtual = OMAP7XX_DSPREG_BASE, -+ .pfn = __phys_to_pfn(OMAP7XX_DSPREG_START), -+ .length = OMAP7XX_DSPREG_SIZE, - .type = MT_DEVICE - } - }; -@@ -120,18 +104,11 @@ void __init omap1_map_common_io(void) - */ - omap_check_revision(); - --#ifdef CONFIG_ARCH_OMAP730 -- if (cpu_is_omap730()) { -- iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc)); -- } --#endif -- --#ifdef CONFIG_ARCH_OMAP850 -- if (cpu_is_omap850()) { -- iotable_init(omap850_io_desc, ARRAY_SIZE(omap850_io_desc)); -+#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) -+ if (cpu_is_omap7xx()) { -+ iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc)); - } - #endif -- - #ifdef CONFIG_ARCH_OMAP15XX - if (cpu_is_omap15xx()) { - iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); ---- a/arch/arm/mach-omap1/irq.c -+++ b/arch/arm/mach-omap1/irq.c -@@ -137,16 +137,8 @@ static void omap_irq_set_cfg(int irq, in - irq_bank_writel(val, bank, offset); - } - --#ifdef CONFIG_ARCH_OMAP730 --static struct omap_irq_bank omap730_irq_banks[] = { -- { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, -- { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, -- { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, --}; --#endif -- --#ifdef CONFIG_ARCH_OMAP850 --static struct omap_irq_bank omap850_irq_banks[] = { -+#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) -+static struct omap_irq_bank omap7xx_irq_banks[] = { - { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, - { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, - { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, -@@ -186,16 +178,10 @@ void __init omap_init_irq(void) - { - int i, j; - --#ifdef CONFIG_ARCH_OMAP730 -- if (cpu_is_omap730()) { -- irq_banks = omap730_irq_banks; -- irq_bank_count = ARRAY_SIZE(omap730_irq_banks); -- } --#endif --#ifdef CONFIG_ARCH_OMAP850 -- if (cpu_is_omap850()) { -- irq_banks = omap850_irq_banks; -- irq_bank_count = ARRAY_SIZE(omap850_irq_banks); -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ if (cpu_is_omap7xx()) { -+ irq_banks = omap7xx_irq_banks; -+ irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); - } - #endif - #ifdef CONFIG_ARCH_OMAP15XX -@@ -247,10 +233,8 @@ void __init omap_init_irq(void) - - /* Unmask level 2 handler */ - -- if (cpu_is_omap730()) -- omap_unmask_irq(INT_730_IH2_IRQ); -- else if (cpu_is_omap850()) -- omap_unmask_irq(INT_850_IH2_IRQ); -+ if (cpu_is_omap7xx()) -+ omap_unmask_irq(INT_7XX_IH2_IRQ); - else if (cpu_is_omap15xx()) - omap_unmask_irq(INT_1510_IH2_IRQ); - else if (cpu_is_omap16xx()) ---- a/arch/arm/mach-omap1/mcbsp.c -+++ b/arch/arm/mach-omap1/mcbsp.c -@@ -79,29 +79,29 @@ static struct omap_mcbsp_ops omap1_mcbsp - .free = omap1_mcbsp_free, - }; - --#ifdef CONFIG_ARCH_OMAP730 --static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = { -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { - { -- .phys_base = OMAP730_MCBSP1_BASE, -+ .phys_base = OMAP7XX_MCBSP1_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP1_RX, - .dma_tx_sync = OMAP_DMA_MCBSP1_TX, -- .rx_irq = INT_730_McBSP1RX, -- .tx_irq = INT_730_McBSP1TX, -+ .rx_irq = INT_7XX_McBSP1RX, -+ .tx_irq = INT_7XX_McBSP1TX, - .ops = &omap1_mcbsp_ops, - }, - { -- .phys_base = OMAP730_MCBSP2_BASE, -+ .phys_base = OMAP7XX_MCBSP2_BASE, - .dma_rx_sync = OMAP_DMA_MCBSP3_RX, - .dma_tx_sync = OMAP_DMA_MCBSP3_TX, -- .rx_irq = INT_730_McBSP2RX, -- .tx_irq = INT_730_McBSP2TX, -+ .rx_irq = INT_7XX_McBSP2RX, -+ .tx_irq = INT_7XX_McBSP2TX, - .ops = &omap1_mcbsp_ops, - }, - }; --#define OMAP730_MCBSP_PDATA_SZ ARRAY_SIZE(omap730_mcbsp_pdata) -+#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata) - #else --#define omap730_mcbsp_pdata NULL --#define OMAP730_MCBSP_PDATA_SZ 0 -+#define omap7xx_mcbsp_pdata NULL -+#define OMAP7XX_MCBSP_PDATA_SZ 0 - #endif - - #ifdef CONFIG_ARCH_OMAP15XX -@@ -172,8 +172,8 @@ static struct omap_mcbsp_platform_data o - - int __init omap1_mcbsp_init(void) - { -- if (cpu_is_omap730()) -- omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ; -+ if (cpu_is_omap7xx()) -+ omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; - if (cpu_is_omap15xx()) - omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; - if (cpu_is_omap16xx()) -@@ -184,9 +184,9 @@ int __init omap1_mcbsp_init(void) - if (!mcbsp_ptr) - return -ENOMEM; - -- if (cpu_is_omap730()) -- omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata, -- OMAP730_MCBSP_PDATA_SZ); -+ if (cpu_is_omap7xx()) -+ omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata, -+ OMAP7XX_MCBSP_PDATA_SZ); - - if (cpu_is_omap15xx()) - omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, ---- a/arch/arm/mach-omap1/mux.c -+++ b/arch/arm/mach-omap1/mux.c -@@ -35,47 +35,28 @@ - - static struct omap_mux_cfg arch_mux_cfg; - --#ifdef CONFIG_ARCH_OMAP730 --static struct pin_config __initdata_or_module omap730_pins[] = { --MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0) --MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 24, 1, 0) --MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 28, 1, 0) --MUX_CFG_730("F3_730_KBR3", 13, 1, 0, 0, 1, 0) --MUX_CFG_730("D2_730_KBR4", 13, 5, 0, 4, 1, 0) --MUX_CFG_730("C2_730_KBC0", 13, 9, 0, 8, 1, 0) --MUX_CFG_730("D3_730_KBC1", 13, 13, 0, 12, 1, 0) --MUX_CFG_730("E4_730_KBC2", 13, 17, 0, 16, 1, 0) --MUX_CFG_730("F4_730_KBC3", 13, 21, 0, 20, 1, 0) --MUX_CFG_730("E3_730_KBC4", 13, 25, 0, 24, 1, 0) -- --MUX_CFG_730("AA17_730_USB_DM", 2, 21, 0, 20, 0, 0) --MUX_CFG_730("W16_730_USB_PU_EN", 2, 25, 0, 24, 0, 0) --MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0) -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+static struct pin_config __initdata_or_module omap7xx_pins[] = { -+MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0) -+MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0) -+MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0) -+MUX_CFG_7XX("F3_7XX_KBR3", 13, 1, 0, 0, 1, 0) -+MUX_CFG_7XX("D2_7XX_KBR4", 13, 5, 0, 4, 1, 0) -+MUX_CFG_7XX("C2_7XX_KBC0", 13, 9, 0, 8, 1, 0) -+MUX_CFG_7XX("D3_7XX_KBC1", 13, 13, 0, 12, 1, 0) -+MUX_CFG_7XX("E4_7XX_KBC2", 13, 17, 0, 16, 1, 0) -+MUX_CFG_7XX("F4_7XX_KBC3", 13, 21, 0, 20, 1, 0) -+MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0) -+ -+MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0) -+MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0) -+MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 0, 28, 0, 0) - }; --#define OMAP730_PINS_SZ ARRAY_SIZE(omap730_pins) -+#define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins) - #else --#define omap730_pins NULL --#define OMAP730_PINS_SZ 0 --#endif /* CONFIG_ARCH_OMAP730 */ -- --#ifdef CONFIG_ARCH_OMAP850 --struct pin_config __initdata_or_module omap850_pins[] = { --MUX_CFG_850("E2_850_KBR0", 12, 21, 0, 20, 1, 0) --MUX_CFG_850("J7_850_KBR1", 12, 25, 0, 24, 1, 0) --MUX_CFG_850("E1_850_KBR2", 12, 29, 0, 28, 1, 0) --MUX_CFG_850("F3_850_KBR3", 13, 1, 0, 0, 1, 0) --MUX_CFG_850("D2_850_KBR4", 13, 5, 0, 4, 1, 0) --MUX_CFG_850("C2_850_KBC0", 13, 9, 0, 8, 1, 0) --MUX_CFG_850("D3_850_KBC1", 13, 13, 0, 12, 1, 0) --MUX_CFG_850("E4_850_KBC2", 13, 17, 0, 16, 1, 0) --MUX_CFG_850("F4_850_KBC3", 13, 21, 0, 20, 1, 0) --MUX_CFG_850("E3_850_KBC4", 13, 25, 0, 24, 1, 0) -- --MUX_CFG_850("AA17_850_USB_DM", 2, 21, 0, 20, 0, 0) --MUX_CFG_850("W16_850_USB_PU_EN", 2, 25, 0, 24, 0, 0) --MUX_CFG_850("W17_850_USB_VBUSI", 2, 29, 0, 28, 0, 0) --}; --#endif -+#define omap7xx_pins NULL -+#define OMAP7XX_PINS_SZ 0 -+#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */ - - #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) - static struct pin_config __initdata_or_module omap1xxx_pins[] = { -@@ -438,11 +419,6 @@ int __init_or_module omap1_cfg_reg(const - printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", - cfg->pull_name, cfg->pull_reg, pull_orig, pull); - } -- --#ifdef CONFIG_ARCH_OMAP850 -- omap_mux_register(omap850_pins, ARRAY_SIZE(omap850_pins)); --#endif -- - #endif - - #ifdef CONFIG_OMAP_MUX_ERRORS -@@ -454,9 +430,9 @@ int __init_or_module omap1_cfg_reg(const - - int __init omap1_mux_init(void) - { -- if (cpu_is_omap730()) { -- arch_mux_cfg.pins = omap730_pins; -- arch_mux_cfg.size = OMAP730_PINS_SZ; -+ if (cpu_is_omap7xx()) { -+ arch_mux_cfg.pins = omap7xx_pins; -+ arch_mux_cfg.size = OMAP7XX_PINS_SZ; - arch_mux_cfg.cfg_reg = omap1_cfg_reg; - } - ---- a/arch/arm/mach-omap1/pm.c -+++ b/arch/arm/mach-omap1/pm.c -@@ -62,7 +62,7 @@ - static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; - static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; - static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; --static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE]; -+static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE]; - static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; - static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; - -@@ -183,9 +183,9 @@ static void omap_pm_wakeup_setup(void) - * drivers must still separately call omap_set_gpio_wakeup() to - * wake up to a GPIO interrupt. - */ -- if (cpu_is_omap730()) -- level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) | -- OMAP_IRQ_BIT(INT_730_IH2_IRQ); -+ if (cpu_is_omap7xx()) -+ level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) | -+ OMAP_IRQ_BIT(INT_7XX_IH2_IRQ); - else if (cpu_is_omap15xx()) - level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | - OMAP_IRQ_BIT(INT_1510_IH2_IRQ); -@@ -195,10 +195,10 @@ static void omap_pm_wakeup_setup(void) - - omap_writel(~level1_wake, OMAP_IH1_MIR); - -- if (cpu_is_omap730()) { -+ if (cpu_is_omap7xx()) { - omap_writel(~level2_wake, OMAP_IH2_0_MIR); -- omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | -- OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), -+ omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) | -+ OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)), - OMAP_IH2_1_MIR); - } else if (cpu_is_omap15xx()) { - level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); -@@ -253,15 +253,15 @@ void omap1_pm_suspend(void) - * Save interrupt, MPUI, ARM and UPLD control registers. - */ - -- if (cpu_is_omap730()) { -- MPUI730_SAVE(OMAP_IH1_MIR); -- MPUI730_SAVE(OMAP_IH2_0_MIR); -- MPUI730_SAVE(OMAP_IH2_1_MIR); -- MPUI730_SAVE(MPUI_CTRL); -- MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG); -- MPUI730_SAVE(MPUI_DSP_API_CONFIG); -- MPUI730_SAVE(EMIFS_CONFIG); -- MPUI730_SAVE(EMIFF_SDRAM_CONFIG); -+ if (cpu_is_omap7xx()) { -+ MPUI7XX_SAVE(OMAP_IH1_MIR); -+ MPUI7XX_SAVE(OMAP_IH2_0_MIR); -+ MPUI7XX_SAVE(OMAP_IH2_1_MIR); -+ MPUI7XX_SAVE(MPUI_CTRL); -+ MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); -+ MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); -+ MPUI7XX_SAVE(EMIFS_CONFIG); -+ MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); - - } else if (cpu_is_omap15xx()) { - MPUI1510_SAVE(OMAP_IH1_MIR); -@@ -306,7 +306,7 @@ void omap1_pm_suspend(void) - omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); - - /* shut down dsp_ck */ -- if (!cpu_is_omap730()) -+ if (!cpu_is_omap7xx()) - omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); - - /* temporarily enabling api_ck to access DSP registers */ -@@ -383,12 +383,12 @@ void omap1_pm_suspend(void) - ULPD_RESTORE(ULPD_CLOCK_CTRL); - ULPD_RESTORE(ULPD_STATUS_REQ); - -- if (cpu_is_omap730()) { -- MPUI730_RESTORE(EMIFS_CONFIG); -- MPUI730_RESTORE(EMIFF_SDRAM_CONFIG); -- MPUI730_RESTORE(OMAP_IH1_MIR); -- MPUI730_RESTORE(OMAP_IH2_0_MIR); -- MPUI730_RESTORE(OMAP_IH2_1_MIR); -+ if (cpu_is_omap7xx()) { -+ MPUI7XX_RESTORE(EMIFS_CONFIG); -+ MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG); -+ MPUI7XX_RESTORE(OMAP_IH1_MIR); -+ MPUI7XX_RESTORE(OMAP_IH2_0_MIR); -+ MPUI7XX_RESTORE(OMAP_IH2_1_MIR); - } else if (cpu_is_omap15xx()) { - MPUI1510_RESTORE(MPUI_CTRL); - MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); -@@ -461,13 +461,13 @@ static int omap_pm_read_proc( - ULPD_SAVE(ULPD_DPLL_CTRL); - ULPD_SAVE(ULPD_POWER_CTRL); - -- if (cpu_is_omap730()) { -- MPUI730_SAVE(MPUI_CTRL); -- MPUI730_SAVE(MPUI_DSP_STATUS); -- MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG); -- MPUI730_SAVE(MPUI_DSP_API_CONFIG); -- MPUI730_SAVE(EMIFF_SDRAM_CONFIG); -- MPUI730_SAVE(EMIFS_CONFIG); -+ if (cpu_is_omap7xx()) { -+ MPUI7XX_SAVE(MPUI_CTRL); -+ MPUI7XX_SAVE(MPUI_DSP_STATUS); -+ MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); -+ MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); -+ MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); -+ MPUI7XX_SAVE(EMIFS_CONFIG); - } else if (cpu_is_omap15xx()) { - MPUI1510_SAVE(MPUI_CTRL); - MPUI1510_SAVE(MPUI_DSP_STATUS); -@@ -517,20 +517,20 @@ static int omap_pm_read_proc( - ULPD_SHOW(ULPD_STATUS_REQ), - ULPD_SHOW(ULPD_POWER_CTRL)); - -- if (cpu_is_omap730()) { -+ if (cpu_is_omap7xx()) { - my_buffer_offset += sprintf(my_base + my_buffer_offset, -- "MPUI730_CTRL_REG 0x%-8x \n" -- "MPUI730_DSP_STATUS_REG: 0x%-8x \n" -- "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n" -- "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n" -- "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n" -- "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n", -- MPUI730_SHOW(MPUI_CTRL), -- MPUI730_SHOW(MPUI_DSP_STATUS), -- MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG), -- MPUI730_SHOW(MPUI_DSP_API_CONFIG), -- MPUI730_SHOW(EMIFF_SDRAM_CONFIG), -- MPUI730_SHOW(EMIFS_CONFIG)); -+ "MPUI7XX_CTRL_REG 0x%-8x \n" -+ "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n" -+ "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n" -+ "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n" -+ "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n" -+ "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n", -+ MPUI7XX_SHOW(MPUI_CTRL), -+ MPUI7XX_SHOW(MPUI_DSP_STATUS), -+ MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG), -+ MPUI7XX_SHOW(MPUI_DSP_API_CONFIG), -+ MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG), -+ MPUI7XX_SHOW(EMIFS_CONFIG)); - } else if (cpu_is_omap15xx()) { - my_buffer_offset += sprintf(my_base + my_buffer_offset, - "MPUI1510_CTRL_REG 0x%-8x \n" -@@ -668,9 +668,9 @@ static int __init omap_pm_init(void) - * These routines need to be in SRAM as that's the only - * memory the MPU can see when it wakes up. - */ -- if (cpu_is_omap730()) { -- omap_sram_suspend = omap_sram_push(omap730_cpu_suspend, -- omap730_cpu_suspend_sz); -+ if (cpu_is_omap7xx()) { -+ omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend, -+ omap7xx_cpu_suspend_sz); - } else if (cpu_is_omap15xx()) { - omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, - omap1510_cpu_suspend_sz); -@@ -686,8 +686,8 @@ static int __init omap_pm_init(void) - - pm_idle = omap1_pm_idle; - -- if (cpu_is_omap730()) -- setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq); -+ if (cpu_is_omap7xx()) -+ setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq); - else if (cpu_is_omap16xx()) - setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq); - -@@ -700,8 +700,8 @@ static int __init omap_pm_init(void) - omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); - - /* Configure IDLECT3 */ -- if (cpu_is_omap730()) -- omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3); -+ if (cpu_is_omap7xx()) -+ omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3); - else if (cpu_is_omap16xx()) - omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); - ---- a/arch/arm/mach-omap1/pm.h -+++ b/arch/arm/mach-omap1/pm.h -@@ -98,13 +98,14 @@ - #define OMAP1610_IDLECT3 0xfffece24 - #define OMAP1610_IDLE_LOOP_REQUEST 0x0400 - --#define OMAP730_IDLECT1_SLEEP_VAL 0x16c7 --#define OMAP730_IDLECT2_SLEEP_VAL 0x09c7 --#define OMAP730_IDLECT3_VAL 0x3f --#define OMAP730_IDLECT3 0xfffece24 --#define OMAP730_IDLE_LOOP_REQUEST 0x0C00 -+#define OMAP7XX_IDLECT1_SLEEP_VAL 0x16c7 -+#define OMAP7XX_IDLECT2_SLEEP_VAL 0x09c7 -+#define OMAP7XX_IDLECT3_VAL 0x3f -+#define OMAP7XX_IDLECT3 0xfffece24 -+#define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00 - - #if !defined(CONFIG_ARCH_OMAP730) && \ -+ !defined(CONFIG_ARCH_OMAP850) && \ - !defined(CONFIG_ARCH_OMAP15XX) && \ - !defined(CONFIG_ARCH_OMAP16XX) - #warning "Power management for this processor not implemented yet" -@@ -122,17 +123,17 @@ extern void allow_idle_sleep(void); - extern void omap1_pm_idle(void); - extern void omap1_pm_suspend(void); - --extern void omap730_cpu_suspend(unsigned short, unsigned short); -+extern void omap7xx_cpu_suspend(unsigned short, unsigned short); - extern void omap1510_cpu_suspend(unsigned short, unsigned short); - extern void omap1610_cpu_suspend(unsigned short, unsigned short); --extern void omap730_idle_loop_suspend(void); -+extern void omap7xx_idle_loop_suspend(void); - extern void omap1510_idle_loop_suspend(void); - extern void omap1610_idle_loop_suspend(void); - --extern unsigned int omap730_cpu_suspend_sz; -+extern unsigned int omap7xx_cpu_suspend_sz; - extern unsigned int omap1510_cpu_suspend_sz; - extern unsigned int omap1610_cpu_suspend_sz; --extern unsigned int omap730_idle_loop_suspend_sz; -+extern unsigned int omap7xx_idle_loop_suspend_sz; - extern unsigned int omap1510_idle_loop_suspend_sz; - extern unsigned int omap1610_idle_loop_suspend_sz; - -@@ -155,9 +156,9 @@ extern void omap_serial_wake_trigger(int - #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) - #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] - --#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x) --#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x)) --#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] -+#define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x) -+#define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x)) -+#define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] - - #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) - #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) -@@ -232,24 +233,24 @@ enum mpui1510_save_state { - #endif - }; - --enum mpui730_save_state { -- MPUI730_SLEEP_SAVE_START = 0, -+enum mpui7xx_save_state { -+ MPUI7XX_SLEEP_SAVE_START = 0, - /* - * MPUI registers 32 bits - */ -- MPUI730_SLEEP_SAVE_MPUI_CTRL, -- MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, -- MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG, -- MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS, -- MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, -- MPUI730_SLEEP_SAVE_EMIFS_CONFIG, -- MPUI730_SLEEP_SAVE_OMAP_IH1_MIR, -- MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR, -- MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR, --#if defined(CONFIG_ARCH_OMAP730) -- MPUI730_SLEEP_SAVE_SIZE -+ MPUI7XX_SLEEP_SAVE_MPUI_CTRL, -+ MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, -+ MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG, -+ MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS, -+ MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, -+ MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG, -+ MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR, -+ MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR, -+ MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR, -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ MPUI7XX_SLEEP_SAVE_SIZE - #else -- MPUI730_SLEEP_SAVE_SIZE = 0 -+ MPUI7XX_SLEEP_SAVE_SIZE = 0 - #endif - }; - ---- a/arch/arm/mach-omap1/serial.c -+++ b/arch/arm/mach-omap1/serial.c -@@ -64,7 +64,6 @@ static void __init omap_serial_reset(str - - static struct plat_serial8250_port serial_platform_data[] = { - { -- .membase = OMAP1_IO_ADDRESS(OMAP_UART1_BASE), - .mapbase = OMAP_UART1_BASE, - .irq = INT_UART1, - .flags = UPF_BOOT_AUTOCONF, -@@ -73,7 +72,6 @@ static struct plat_serial8250_port seria - .uartclk = OMAP16XX_BASE_BAUD * 16, - }, - { -- .membase = OMAP1_IO_ADDRESS(OMAP_UART2_BASE), - .mapbase = OMAP_UART2_BASE, - .irq = INT_UART2, - .flags = UPF_BOOT_AUTOCONF, -@@ -82,7 +80,6 @@ static struct plat_serial8250_port seria - .uartclk = OMAP16XX_BASE_BAUD * 16, - }, - { -- .membase = OMAP1_IO_ADDRESS(OMAP_UART3_BASE), - .mapbase = OMAP_UART3_BASE, - .irq = INT_UART3, - .flags = UPF_BOOT_AUTOCONF, -@@ -90,7 +87,6 @@ static struct plat_serial8250_port seria - .regshift = 2, - .uartclk = OMAP16XX_BASE_BAUD * 16, - }, -- { }, - }; - - static struct platform_device serial_device = { -@@ -110,18 +106,11 @@ void __init omap_serial_init(void) - { - int i; - -- if (cpu_is_omap730()) { -+ if (cpu_is_omap7xx()) { - serial_platform_data[0].regshift = 0; - serial_platform_data[1].regshift = 0; -- serial_platform_data[0].irq = INT_730_UART_MODEM_1; -- serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2; -- } -- -- if (cpu_is_omap850()) { -- serial_platform_data[0].regshift = 0; -- serial_platform_data[1].regshift = 0; -- serial_platform_data[0].irq = INT_850_UART_MODEM_1; -- serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2; -+ serial_platform_data[0].irq = INT_7XX_UART_MODEM_1; -+ serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2; - } - - if (cpu_is_omap15xx()) { ---- a/arch/arm/mach-omap1/sleep.S -+++ b/arch/arm/mach-omap1/sleep.S -@@ -1,7 +1,7 @@ - /* - * linux/arch/arm/mach-omap1/sleep.S - * -- * Low-level OMAP730/1510/1610 sleep/wakeUp support -+ * Low-level OMAP7XX/1510/1610 sleep/wakeUp support - * - * Initial SA1110 code: - * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> -@@ -57,8 +57,8 @@ - * - */ - --#if defined(CONFIG_ARCH_OMAP730) --ENTRY(omap730_cpu_suspend) -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ENTRY(omap7xx_cpu_suspend) - - @ save registers on stack - stmfd sp!, {r0 - r12, lr} -@@ -91,13 +91,13 @@ ENTRY(omap730_cpu_suspend) - - @ turn off clock domains - @ do not disable PERCK (0x04) -- mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff -- orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00 -+ mov r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff -+ orr r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00 - strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] - - @ request ARM idle -- mov r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff -- orr r3, r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff00 -+ mov r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff -+ orr r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00 - strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] - - @ disable instruction cache -@@ -113,7 +113,7 @@ ENTRY(omap730_cpu_suspend) - mov r2, #0 - mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt - /* -- * omap730_cpu_suspend()'s resume point. -+ * omap7xx_cpu_suspend()'s resume point. - * - * It will just start executing here, so we'll restore stuff from the - * stack. -@@ -132,9 +132,9 @@ ENTRY(omap730_cpu_suspend) - @ restore regs and return - ldmfd sp!, {r0 - r12, pc} - --ENTRY(omap730_cpu_suspend_sz) -- .word . - omap730_cpu_suspend --#endif /* CONFIG_ARCH_OMAP730 */ -+ENTRY(omap7xx_cpu_suspend_sz) -+ .word . - omap7xx_cpu_suspend -+#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */ - - #ifdef CONFIG_ARCH_OMAP15XX - ENTRY(omap1510_cpu_suspend) ---- a/arch/arm/mach-omap2/Makefile -+++ b/arch/arm/mach-omap2/Makefile -@@ -80,6 +80,7 @@ obj-$(CONFIG_MACH_OMAP_4430SDP) += boar - # Platform specific device init code - obj-y += usb-musb.o - obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o -+obj-y += usb-ehci.o - - onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o - obj-y += $(onenand-m) $(onenand-y) ---- a/arch/arm/mach-omap2/board-2430sdp.c -+++ b/arch/arm/mach-omap2/board-2430sdp.c -@@ -221,7 +221,7 @@ static void __init omap_2430sdp_map_io(v - MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") - /* Maintainer: Syed Khasim - Texas Instruments Inc */ - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap_2430sdp_map_io, - .init_irq = omap_2430sdp_init_irq, ---- a/arch/arm/mach-omap2/board-3430sdp.c -+++ b/arch/arm/mach-omap2/board-3430sdp.c -@@ -618,6 +618,18 @@ static void enable_board_wakeup_source(v - omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */ - } - -+static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { -+ -+ .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, -+ .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, -+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, -+ -+ .phy_reset = true, -+ .reset_gpio_port[0] = 57, -+ .reset_gpio_port[1] = 61, -+ .reset_gpio_port[2] = -EINVAL -+}; -+ - static void __init omap_3430sdp_init(void) - { - omap3430_i2c_init(); -@@ -635,6 +647,7 @@ static void __init omap_3430sdp_init(voi - board_smc91x_init(); - sdp3430_display_init(); - enable_board_wakeup_source(); -+ usb_ehci_init(&ehci_pdata); - } - - static void __init omap_3430sdp_map_io(void) -@@ -646,7 +659,7 @@ static void __init omap_3430sdp_map_io(v - MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") - /* Maintainer: Syed Khasim - Texas Instruments Inc */ - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap_3430sdp_map_io, - .init_irq = omap_3430sdp_init_irq, ---- a/arch/arm/mach-omap2/board-4430sdp.c -+++ b/arch/arm/mach-omap2/board-4430sdp.c -@@ -52,8 +52,17 @@ static struct omap_board_config_kernel s - - static void __init gic_init_irq(void) - { -- gic_dist_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29); -- gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); -+ void __iomem *base; -+ -+ /* Static mapping, never released */ -+ base = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); -+ BUG_ON(!base); -+ gic_dist_init(0, base, 29); -+ -+ /* Static mapping, never released */ -+ base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_256); -+ BUG_ON(!base); -+ gic_cpu_init(0, OMAP44XX_GIC_CPU_BASE); - } - - static void __init omap_4430sdp_init_irq(void) -@@ -84,7 +93,7 @@ static void __init omap_4430sdp_map_io(v - MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") - /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap_4430sdp_map_io, - .init_irq = omap_4430sdp_init_irq, ---- a/arch/arm/mach-omap2/board-apollon.c -+++ b/arch/arm/mach-omap2/board-apollon.c -@@ -333,7 +333,7 @@ static void __init omap_apollon_map_io(v - MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") - /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap_apollon_map_io, - .init_irq = omap_apollon_init_irq, ---- a/arch/arm/mach-omap2/board-generic.c -+++ b/arch/arm/mach-omap2/board-generic.c -@@ -56,7 +56,7 @@ static void __init omap_generic_map_io(v - MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") - /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap_generic_map_io, - .init_irq = omap_generic_init_irq, ---- a/arch/arm/mach-omap2/board-h4.c -+++ b/arch/arm/mach-omap2/board-h4.c -@@ -376,7 +376,7 @@ static void __init omap_h4_map_io(void) - MACHINE_START(OMAP_H4, "OMAP2420 H4 board") - /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap_h4_map_io, - .init_irq = omap_h4_init_irq, ---- a/arch/arm/mach-omap2/board-ldp.c -+++ b/arch/arm/mach-omap2/board-ldp.c -@@ -399,7 +399,7 @@ static void __init omap_ldp_map_io(void) - - MACHINE_START(OMAP_LDP, "OMAP LDP board") - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap_ldp_map_io, - .init_irq = omap_ldp_init_irq, ---- a/arch/arm/mach-omap2/board-n8x0.c -+++ b/arch/arm/mach-omap2/board-n8x0.c -@@ -121,7 +121,7 @@ static void __init n8x0_init_machine(voi - - MACHINE_START(NOKIA_N800, "Nokia N800") - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = n8x0_map_io, - .init_irq = n8x0_init_irq, -@@ -131,7 +131,7 @@ MACHINE_END - - MACHINE_START(NOKIA_N810, "Nokia N810") - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = n8x0_map_io, - .init_irq = n8x0_init_irq, -@@ -141,7 +141,7 @@ MACHINE_END - - MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = n8x0_map_io, - .init_irq = n8x0_init_irq, ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -400,6 +400,18 @@ static void __init omap3beagle_flash_ini - } - } - -+static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { -+ -+ .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, -+ .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, -+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, -+ -+ .phy_reset = true, -+ .reset_gpio_port[0] = -EINVAL, -+ .reset_gpio_port[1] = 147, -+ .reset_gpio_port[2] = -EINVAL -+}; -+ - static void __init omap3_beagle_init(void) - { - omap3_beagle_i2c_init(); -@@ -413,6 +425,7 @@ static void __init omap3_beagle_init(voi - gpio_direction_output(170, true); - - usb_musb_init(); -+ usb_ehci_init(&ehci_pdata); - omap3beagle_flash_init(); - - /* Ensure SDRC pins are mux'd for self-refresh */ -@@ -429,7 +442,7 @@ static void __init omap3_beagle_map_io(v - MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") - /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap3_beagle_map_io, - .init_irq = omap3_beagle_init_irq, ---- a/arch/arm/mach-omap2/board-omap3evm.c -+++ b/arch/arm/mach-omap2/board-omap3evm.c -@@ -297,6 +297,18 @@ static struct platform_device *omap3_evm - &omap3evm_smc911x_device, - }; - -+static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { -+ -+ .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, -+ .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, -+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, -+ -+ .phy_reset = true, -+ .reset_gpio_port[0] = -EINVAL, -+ .reset_gpio_port[1] = 135, -+ .reset_gpio_port[2] = -EINVAL -+}; -+ - static void __init omap3_evm_init(void) - { - omap3_evm_i2c_init(); -@@ -312,6 +324,9 @@ static void __init omap3_evm_init(void) - usb_nop_xceiv_register(); - #endif - usb_musb_init(); -+ /* Setup EHCI phy reset padconfig */ -+ omap_cfg_reg(AF4_34XX_GPIO135_OUT); -+ usb_ehci_init(&ehci_pdata); - ads7846_dev_init(); - } - -@@ -324,7 +339,7 @@ static void __init omap3_evm_map_io(void - MACHINE_START(OMAP3EVM, "OMAP3 EVM") - /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap3_evm_map_io, - .init_irq = omap3_evm_init_irq, ---- a/arch/arm/mach-omap2/board-omap3pandora.c -+++ b/arch/arm/mach-omap2/board-omap3pandora.c -@@ -387,6 +387,18 @@ static struct platform_device *omap3pand - &pandora_keys_gpio, - }; - -+static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { -+ -+ .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, -+ .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, -+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, -+ -+ .phy_reset = true, -+ .reset_gpio_port[0] = 16, -+ .reset_gpio_port[1] = -EINVAL, -+ .reset_gpio_port[2] = -EINVAL -+}; -+ - static void __init omap3pandora_init(void) - { - omap3pandora_i2c_init(); -@@ -396,6 +408,7 @@ static void __init omap3pandora_init(voi - spi_register_board_info(omap3pandora_spi_board_info, - ARRAY_SIZE(omap3pandora_spi_board_info)); - omap3pandora_ads7846_init(); -+ usb_ehci_init(&ehci_pdata); - pandora_keys_gpio_init(); - usb_musb_init(); - -@@ -412,7 +425,7 @@ static void __init omap3pandora_map_io(v - - MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap3pandora_map_io, - .init_irq = omap3pandora_init_irq, ---- a/arch/arm/mach-omap2/board-overo.c -+++ b/arch/arm/mach-omap2/board-overo.c -@@ -384,6 +384,18 @@ static struct platform_device *overo_dev - &overo_lcd_device, - }; - -+static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { -+ .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, -+ .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, -+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, -+ -+ .phy_reset = true, -+ .reset_gpio_port[0] = -EINVAL, -+ .reset_gpio_port[1] = OVERO_GPIO_USBH_NRESET, -+ .reset_gpio_port[2] = -EINVAL -+}; -+ -+ - static void __init overo_init(void) - { - overo_i2c_init(); -@@ -391,6 +403,7 @@ static void __init overo_init(void) - omap_serial_init(); - overo_flash_init(); - usb_musb_init(); -+ usb_ehci_init(&ehci_pdata); - overo_ads7846_init(); - overo_init_smsc911x(); - -@@ -433,14 +446,6 @@ static void __init overo_init(void) - else - printk(KERN_ERR "could not obtain gpio for " - "OVERO_GPIO_USBH_CPEN\n"); -- -- if ((gpio_request(OVERO_GPIO_USBH_NRESET, -- "OVERO_GPIO_USBH_NRESET") == 0) && -- (gpio_direction_output(OVERO_GPIO_USBH_NRESET, 1) == 0)) -- gpio_export(OVERO_GPIO_USBH_NRESET, 0); -- else -- printk(KERN_ERR "could not obtain gpio for " -- "OVERO_GPIO_USBH_NRESET\n"); - } - - static void __init overo_map_io(void) -@@ -451,7 +456,7 @@ static void __init overo_map_io(void) - - MACHINE_START(OVERO, "Gumstix Overo") - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = overo_map_io, - .init_irq = overo_init_irq, ---- a/arch/arm/mach-omap2/board-rx51.c -+++ b/arch/arm/mach-omap2/board-rx51.c -@@ -84,7 +84,7 @@ static void __init rx51_map_io(void) - MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") - /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */ - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = rx51_map_io, - .init_irq = rx51_init_irq, ---- a/arch/arm/mach-omap2/board-zoom2.c -+++ b/arch/arm/mach-omap2/board-zoom2.c -@@ -282,7 +282,7 @@ static void __init omap_zoom2_map_io(voi - - MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") - .phys_io = 0x48000000, -- .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, - .boot_params = 0x80000100, - .map_io = omap_zoom2_map_io, - .init_irq = omap_zoom2_init_irq, ---- a/arch/arm/mach-omap2/cm.h -+++ b/arch/arm/mach-omap2/cm.h -@@ -17,11 +17,11 @@ - #include "prcm-common.h" - - #define OMAP2420_CM_REGADDR(module, reg) \ -- OMAP2_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) -+ OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) - #define OMAP2430_CM_REGADDR(module, reg) \ -- OMAP2_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) -+ OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) - #define OMAP34XX_CM_REGADDR(module, reg) \ -- OMAP2_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) -+ OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) - - /* - * Architecture-specific global CM registers ---- a/arch/arm/mach-omap2/id.c -+++ b/arch/arm/mach-omap2/id.c -@@ -28,6 +28,7 @@ - static struct omap_chip_id omap_chip; - static unsigned int omap_revision; - -+u32 omap3_features; - - unsigned int omap_rev(void) - { -@@ -155,12 +156,37 @@ void __init omap24xx_check_revision(void - pr_info("\n"); - } - --void __init omap34xx_check_revision(void) -+#define OMAP3_CHECK_FEATURE(status,feat) \ -+ if (((status & OMAP3_ ##feat## _MASK) \ -+ >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ -+ omap3_features |= OMAP3_HAS_ ##feat; \ -+ } -+ -+void __init omap3_check_features(void) -+{ -+ u32 status; -+ -+ omap3_features = 0; -+ -+ status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); -+ -+ OMAP3_CHECK_FEATURE(status, L2CACHE); -+ OMAP3_CHECK_FEATURE(status, IVA); -+ OMAP3_CHECK_FEATURE(status, SGX); -+ OMAP3_CHECK_FEATURE(status, NEON); -+ OMAP3_CHECK_FEATURE(status, ISP); -+ -+ /* -+ * TODO: Get additional info (where applicable) -+ * e.g. Size of L2 cache. -+ */ -+} -+ -+void __init omap3_check_revision(void) - { - u32 cpuid, idcode; - u16 hawkeye; - u8 rev; -- char *rev_name = "ES1.0"; - - /* - * We cannot access revision registers on ES1.0. -@@ -170,7 +196,7 @@ void __init omap34xx_check_revision(void - cpuid = read_cpuid(CPUID_ID); - if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { - omap_revision = OMAP3430_REV_ES1_0; -- goto out; -+ return; - } - - /* -@@ -183,33 +209,111 @@ void __init omap34xx_check_revision(void - hawkeye = (idcode >> 12) & 0xffff; - rev = (idcode >> 28) & 0xff; - -- if (hawkeye == 0xb7ae) { -+ switch (hawkeye) { -+ case 0xb7ae: -+ /* Handle 34xx/35xx devices */ - switch (rev) { -- case 0: -+ case 0: /* Take care of early samples */ -+ case 1: - omap_revision = OMAP3430_REV_ES2_0; -- rev_name = "ES2.0"; - break; - case 2: - omap_revision = OMAP3430_REV_ES2_1; -- rev_name = "ES2.1"; - break; - case 3: - omap_revision = OMAP3430_REV_ES3_0; -- rev_name = "ES3.0"; - break; - case 4: - omap_revision = OMAP3430_REV_ES3_1; -- rev_name = "ES3.1"; - break; - default: - /* Use the latest known revision as default */ - omap_revision = OMAP3430_REV_ES3_1; -- rev_name = "Unknown revision\n"; - } -+ break; -+ case 0xb891: -+ /* Handle 36xx devices */ -+ switch (rev) { -+ case 0: -+ omap_revision = OMAP3630_REV_ES1_0; -+ break; -+ default: -+ /* Use the latest known revision as default */ -+ omap_revision = OMAP3630_REV_ES1_0; -+ } -+ break; -+ default: -+ /* Unknown default to latest silicon rev as default*/ -+ omap_revision = OMAP3630_REV_ES1_0; - } -+} - --out: -- pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); -+#define OMAP3_SHOW_FEATURE(feat) \ -+ if (omap3_has_ ##feat()) { \ -+ pr_info (" - "#feat" : Y"); \ -+ } else { \ -+ pr_info (" - "#feat" : N"); \ -+ } -+ -+void __init omap3_cpuinfo(void) -+{ -+ u8 rev = GET_OMAP_REVISION(); -+ char cpu_name[16], cpu_rev[16]; -+ -+ /* OMAP3430 and OMAP3530 are assumed to be same. -+ * -+ * OMAP3525, OMAP3515 and OMAP3503 can be detected only based -+ * on available features. Upon detection, update the CPU id -+ * and CPU class bits. -+ */ -+ if (cpu_is_omap3630()) -+ strcpy(cpu_name, "3630"); -+ else if (omap3_has_iva() && omap3_has_sgx()) -+ strcpy(cpu_name, "3430/3530"); -+ else if (omap3_has_sgx()) { -+ omap_revision = OMAP3525_REV(rev); -+ strcpy(cpu_name, "3525"); -+ } -+ else if (omap3_has_iva()) { -+ omap_revision = OMAP3515_REV(rev); -+ strcpy(cpu_name, "3515"); -+ } -+ else { -+ omap_revision = OMAP3503_REV(rev); -+ strcpy(cpu_name, "3503"); -+ } -+ -+ switch (rev) { -+ case OMAP_REVBITS_00: -+ strcpy(cpu_rev, "1.0"); -+ break; -+ case OMAP_REVBITS_10: -+ strcpy(cpu_rev, "2.0"); -+ break; -+ case OMAP_REVBITS_20: -+ strcpy(cpu_rev, "2.1"); -+ break; -+ case OMAP_REVBITS_30: -+ strcpy(cpu_rev, "3.0"); -+ break; -+ case OMAP_REVBITS_40: -+ strcpy(cpu_rev, "3.1"); -+ break; -+ default: -+ /* Use the latest known revision as default */ -+ strcpy(cpu_rev, "3.1"); -+ } -+ -+ /* -+ * Print verbose information -+ */ -+ pr_info("OMAP%s ES%s\n", cpu_name, cpu_rev); -+ -+ OMAP3_SHOW_FEATURE(l2cache); -+ OMAP3_SHOW_FEATURE(iva); -+ OMAP3_SHOW_FEATURE(sgx); -+ OMAP3_SHOW_FEATURE(neon); -+ OMAP3_SHOW_FEATURE(isp); - } - - /* -@@ -223,8 +327,11 @@ void __init omap2_check_revision(void) - */ - if (cpu_is_omap24xx()) - omap24xx_check_revision(); -- else if (cpu_is_omap34xx()) -- omap34xx_check_revision(); -+ else if (cpu_is_omap34xx()) { -+ omap3_check_features(); -+ omap3_check_revision(); -+ omap3_cpuinfo(); -+ } - else if (cpu_is_omap44xx()) { - printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n"); - return; ---- a/arch/arm/mach-omap2/io.c -+++ b/arch/arm/mach-omap2/io.c -@@ -204,6 +204,24 @@ static struct map_desc omap44xx_io_desc[ - .type = MT_DEVICE, - }, - { -+ .virtual = OMAP44XX_EMIF1_VIRT, -+ .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS), -+ .length = OMAP44XX_EMIF1_SIZE, -+ .type = MT_DEVICE, -+ }, -+ { -+ .virtual = OMAP44XX_EMIF2_VIRT, -+ .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS), -+ .length = OMAP44XX_EMIF2_SIZE, -+ .type = MT_DEVICE, -+ }, -+ { -+ .virtual = OMAP44XX_DMM_VIRT, -+ .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS), -+ .length = OMAP44XX_DMM_SIZE, -+ .type = MT_DEVICE, -+ }, -+ { - .virtual = L4_PER_44XX_VIRT, - .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), - .length = L4_PER_44XX_SIZE, ---- a/arch/arm/mach-omap2/irq.c -+++ b/arch/arm/mach-omap2/irq.c -@@ -178,12 +178,20 @@ void __init omap_init_irq(void) - int i; - - for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { -+ unsigned long base; - struct omap_irq_bank *bank = irq_banks + i; - - if (cpu_is_omap24xx()) -- bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE); -+ base = OMAP24XX_IC_BASE; - else if (cpu_is_omap34xx()) -- bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE); -+ base = OMAP34XX_IC_BASE; -+ -+ /* Static mapping, never released */ -+ bank->base_reg = ioremap(base, SZ_4K); -+ if (!bank->base_reg) { -+ printk(KERN_ERR "Could not ioremap irq bank%i\n", i); -+ continue; -+ } - - omap_irq_bank_init_one(bank); - ---- a/arch/arm/mach-omap2/omap-smp.c -+++ b/arch/arm/mach-omap2/omap-smp.c -@@ -26,11 +26,11 @@ - #include <mach/hardware.h> - - /* Registers used for communicating startup information */ --#define OMAP4_AUXCOREBOOT_REG0 (OMAP44XX_VA_WKUPGEN_BASE + 0x800) --#define OMAP4_AUXCOREBOOT_REG1 (OMAP44XX_VA_WKUPGEN_BASE + 0x804) -+static void __iomem *omap4_auxcoreboot_reg0; -+static void __iomem *omap4_auxcoreboot_reg1; - - /* SCU base address */ --static void __iomem *scu_base = OMAP44XX_VA_SCU_BASE; -+static void __iomem *scu_base; - - /* - * Use SCU config register to count number of cores -@@ -46,6 +46,8 @@ static DEFINE_SPINLOCK(boot_lock); - - void __cpuinit platform_secondary_init(unsigned int cpu) - { -+ void __iomem *gic_cpu_base; -+ - trace_hardirqs_off(); - - /* -@@ -54,7 +56,10 @@ void __cpuinit platform_secondary_init(u - * for us: do so - */ - -- gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); -+ /* Static mapping, never released */ -+ gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_256); -+ BUG_ON(!gic_cpu_base); -+ gic_cpu_init(0, gic_cpu_base); - - /* - * Synchronise with the boot thread. -@@ -79,7 +84,7 @@ int __cpuinit boot_secondary(unsigned in - * the AuxCoreBoot1 register is updated with cpu state - * A barrier is added to ensure that write buffer is drained - */ -- __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1); -+ __raw_writel(cpu, omap4_auxcoreboot_reg1); - smp_wmb(); - - timeout = jiffies + (1 * HZ); -@@ -104,7 +109,7 @@ static void __init wakeup_secondary(void - * A barrier is added to ensure that write buffer is drained - */ - __raw_writel(virt_to_phys(omap_secondary_startup), \ -- OMAP4_AUXCOREBOOT_REG0); -+ omap4_auxcoreboot_reg0); - smp_wmb(); - - /* -@@ -130,6 +135,7 @@ void __init smp_prepare_cpus(unsigned in - { - unsigned int ncores = get_core_count(); - unsigned int cpu = smp_processor_id(); -+ void __iomem *omap4_wkupgen_base; - int i; - - /* sanity check */ -@@ -161,6 +167,16 @@ void __init smp_prepare_cpus(unsigned in - for (i = 0; i < max_cpus; i++) - set_cpu_present(i, true); - -+ /* Never released */ -+ omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K); -+ BUG_ON(!omap4_wkupgen_base); -+ omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800; -+ omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x804; -+ -+ /* Never released */ -+ scu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_256); -+ BUG_ON(!scu_base); -+ - if (max_cpus > 1) { - /* - * Enable the local timer or broadcast device for the ---- a/arch/arm/mach-omap2/omap_hwmod.c -+++ b/arch/arm/mach-omap2/omap_hwmod.c -@@ -496,6 +496,7 @@ static void __iomem *_find_mpu_rt_base(s - struct omap_hwmod_addr_space *mem; - int i; - int found = 0; -+ void __iomem *va_start; - - if (!oh || oh->slaves_cnt == 0) - return NULL; -@@ -509,16 +510,20 @@ static void __iomem *_find_mpu_rt_base(s - } - } - -- /* XXX use ioremap() instead? */ -- -- if (found) -+ if (found) { -+ va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); -+ if (!va_start) { -+ pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); -+ return NULL; -+ } - pr_debug("omap_hwmod: %s: MPU register target at va %p\n", -- oh->name, OMAP2_IO_ADDRESS(mem->pa_start)); -- else -+ oh->name, va_start); -+ } else { - pr_debug("omap_hwmod: %s: no MPU register target found\n", - oh->name); -+ } - -- return (found) ? OMAP2_IO_ADDRESS(mem->pa_start) : NULL; -+ return (found) ? va_start : NULL; - } - - /** -@@ -1148,6 +1153,7 @@ int omap_hwmod_unregister(struct omap_hw - pr_debug("omap_hwmod: %s: unregistering\n", oh->name); - - mutex_lock(&omap_hwmod_mutex); -+ iounmap(oh->_rt_va); - list_del(&oh->node); - mutex_unlock(&omap_hwmod_mutex); - ---- a/arch/arm/mach-omap2/pm-debug.c -+++ b/arch/arm/mach-omap2/pm-debug.c -@@ -51,7 +51,8 @@ int omap2_pm_debug; - regs[reg_count++].val = __raw_readl(reg) - #define DUMP_INTC_REG(reg, off) \ - regs[reg_count].name = #reg; \ -- regs[reg_count++].val = __raw_readl(OMAP2_IO_ADDRESS(0x480fe000 + (off))) -+ regs[reg_count++].val = \ -+ __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off))) - - static int __init pm_dbg_init(void); - ---- a/arch/arm/mach-omap2/prm.h -+++ b/arch/arm/mach-omap2/prm.h -@@ -17,11 +17,11 @@ - #include "prcm-common.h" - - #define OMAP2420_PRM_REGADDR(module, reg) \ -- OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) -+ OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) - #define OMAP2430_PRM_REGADDR(module, reg) \ -- OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) -+ OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) - #define OMAP34XX_PRM_REGADDR(module, reg) \ -- OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) -+ OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) - - /* - * Architecture-specific global PRM registers ---- a/arch/arm/mach-omap2/sdrc.h -+++ b/arch/arm/mach-omap2/sdrc.h -@@ -48,9 +48,12 @@ static inline u32 sms_read_reg(u16 reg) - return __raw_readl(OMAP_SMS_REGADDR(reg)); - } - #else --#define OMAP242X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) --#define OMAP243X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) --#define OMAP34XX_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) -+#define OMAP242X_SDRC_REGADDR(reg) \ -+ OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) -+#define OMAP243X_SDRC_REGADDR(reg) \ -+ OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) -+#define OMAP34XX_SDRC_REGADDR(reg) \ -+ OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) - #endif /* __ASSEMBLER__ */ - - #endif ---- a/arch/arm/mach-omap2/serial.c -+++ b/arch/arm/mach-omap2/serial.c -@@ -73,7 +73,6 @@ static LIST_HEAD(uart_list); - - static struct plat_serial8250_port serial_platform_data0[] = { - { -- .membase = OMAP2_IO_ADDRESS(OMAP_UART1_BASE), - .mapbase = OMAP_UART1_BASE, - .irq = 72, - .flags = UPF_BOOT_AUTOCONF, -@@ -87,7 +86,6 @@ static struct plat_serial8250_port seria - - static struct plat_serial8250_port serial_platform_data1[] = { - { -- .membase = OMAP2_IO_ADDRESS(OMAP_UART2_BASE), - .mapbase = OMAP_UART2_BASE, - .irq = 73, - .flags = UPF_BOOT_AUTOCONF, -@@ -101,7 +99,6 @@ static struct plat_serial8250_port seria - - static struct plat_serial8250_port serial_platform_data2[] = { - { -- .membase = OMAP2_IO_ADDRESS(OMAP_UART3_BASE), - .mapbase = OMAP_UART3_BASE, - .irq = 74, - .flags = UPF_BOOT_AUTOCONF, -@@ -116,7 +113,6 @@ static struct plat_serial8250_port seria - #ifdef CONFIG_ARCH_OMAP4 - static struct plat_serial8250_port serial_platform_data3[] = { - { -- .membase = OMAP2_IO_ADDRESS(OMAP_UART4_BASE), - .mapbase = OMAP_UART4_BASE, - .irq = 70, - .flags = UPF_BOOT_AUTOCONF, -@@ -539,7 +535,7 @@ static inline void omap_uart_idle_init(s - #define DEV_CREATE_FILE(dev, attr) - #endif /* CONFIG_PM */ - --static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = { -+static struct omap_uart_state omap_uart[] = { - { - .pdev = { - .name = "serial8250", -@@ -589,12 +585,22 @@ void __init omap_serial_early_init(void) - * if not needed. - */ - -- for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { -+ for (i = 0; i < ARRAY_SIZE(omap_uart); i++) { - struct omap_uart_state *uart = &omap_uart[i]; - struct platform_device *pdev = &uart->pdev; - struct device *dev = &pdev->dev; - struct plat_serial8250_port *p = dev->platform_data; - -+ /* -+ * Module 4KB + L4 interconnect 4KB -+ * Static mapping, never released -+ */ -+ p->membase = ioremap(p->mapbase, SZ_8K); -+ if (!p->membase) { -+ printk(KERN_ERR "ioremap failed for uart%i\n", i + 1); -+ continue; -+ } -+ - sprintf(name, "uart%d_ick", i+1); - uart->ick = clk_get(NULL, name); - if (IS_ERR(uart->ick)) { -@@ -631,7 +637,7 @@ void __init omap_serial_init(void) - { - int i; - -- for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { -+ for (i = 0; i < ARRAY_SIZE(omap_uart); i++) { - struct omap_uart_state *uart = &omap_uart[i]; - struct platform_device *pdev = &uart->pdev; - struct device *dev = &pdev->dev; ---- a/arch/arm/mach-omap2/sram242x.S -+++ b/arch/arm/mach-omap2/sram242x.S -@@ -128,7 +128,7 @@ omap242x_sdi_prcm_voltctrl: - prcm_mask_val: - .word 0xFFFF3FFC - omap242x_sdi_timer_32ksynct_cr: -- .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) -+ .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) - ENTRY(omap242x_sram_ddr_init_sz) - .word . - omap242x_sram_ddr_init - -@@ -224,7 +224,7 @@ omap242x_srs_prcm_voltctrl: - ddr_prcm_mask_val: - .word 0xFFFF3FFC - omap242x_srs_timer_32ksynct: -- .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) -+ .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) - - ENTRY(omap242x_sram_reprogram_sdrc_sz) - .word . - omap242x_sram_reprogram_sdrc ---- a/arch/arm/mach-omap2/sram243x.S -+++ b/arch/arm/mach-omap2/sram243x.S -@@ -128,7 +128,7 @@ omap243x_sdi_prcm_voltctrl: - prcm_mask_val: - .word 0xFFFF3FFC - omap243x_sdi_timer_32ksynct_cr: -- .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) -+ .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) - ENTRY(omap243x_sram_ddr_init_sz) - .word . - omap243x_sram_ddr_init - -@@ -224,7 +224,7 @@ omap243x_srs_prcm_voltctrl: - ddr_prcm_mask_val: - .word 0xFFFF3FFC - omap243x_srs_timer_32ksynct: -- .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) -+ .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) - - ENTRY(omap243x_sram_reprogram_sdrc_sz) - .word . - omap243x_sram_reprogram_sdrc ---- a/arch/arm/mach-omap2/timer-gp.c -+++ b/arch/arm/mach-omap2/timer-gp.c -@@ -231,7 +231,8 @@ static void __init omap2_gp_clocksource_ - static void __init omap2_gp_timer_init(void) - { - #ifdef CONFIG_LOCAL_TIMERS -- twd_base = OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE); -+ twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); -+ BUG_ON(!twd_base); - #endif - omap_dm_timer_init(); - ---- /dev/null -+++ b/arch/arm/mach-omap2/usb-ehci.c -@@ -0,0 +1,192 @@ -+/* -+ * linux/arch/arm/mach-omap2/usb-ehci.c -+ * -+ * This file will contain the board specific details for the -+ * Synopsys EHCI host controller on OMAP3430 -+ * -+ * Copyright (C) 2007 Texas Instruments -+ * Author: Vikram Pandita <vikram.pandita@ti.com> -+ * -+ * Generalization by: -+ * Felipe Balbi <felipe.balbi@nokia.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include <linux/types.h> -+#include <linux/errno.h> -+#include <linux/delay.h> -+#include <linux/platform_device.h> -+#include <linux/clk.h> -+#include <asm/io.h> -+#include <mach/mux.h> -+ -+#include <mach/hardware.h> -+#include <mach/irqs.h> -+#include <mach/usb.h> -+ -+#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) -+ -+static struct resource ehci_resources[] = { -+ { -+ .start = OMAP34XX_EHCI_BASE, -+ .end = OMAP34XX_EHCI_BASE + SZ_1K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .start = OMAP34XX_UHH_CONFIG_BASE, -+ .end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .start = OMAP34XX_USBTLL_BASE, -+ .end = OMAP34XX_USBTLL_BASE + SZ_4K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ { /* general IRQ */ -+ .start = INT_34XX_EHCI_IRQ, -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static u64 ehci_dmamask = ~(u32)0; -+static struct platform_device ehci_device = { -+ .name = "ehci-omap", -+ .id = 0, -+ .dev = { -+ .dma_mask = &ehci_dmamask, -+ .coherent_dma_mask = 0xffffffff, -+ .platform_data = NULL, -+ }, -+ .num_resources = ARRAY_SIZE(ehci_resources), -+ .resource = ehci_resources, -+}; -+ -+/* MUX settings for EHCI pins */ -+/* -+ * setup_ehci_io_mux - initialize IO pad mux for USBHOST -+ */ -+static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode) -+{ -+ switch (port_mode[0]) { -+ case EHCI_HCD_OMAP_MODE_PHY: -+ omap_cfg_reg(Y9_3430_USB1HS_PHY_STP); -+ omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK); -+ omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR); -+ omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT); -+ omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0); -+ omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1); -+ omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2); -+ omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3); -+ omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4); -+ omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5); -+ omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6); -+ omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7); -+ break; -+ case EHCI_HCD_OMAP_MODE_TLL: -+ omap_cfg_reg(Y9_3430_USB1HS_TLL_STP); -+ omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK); -+ omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR); -+ omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT); -+ omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0); -+ omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1); -+ omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2); -+ omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3); -+ omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4); -+ omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5); -+ omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6); -+ omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7); -+ break; -+ case EHCI_HCD_OMAP_MODE_UNKNOWN: -+ /* FALLTHROUGH */ -+ default: -+ break; -+ } -+ -+ switch (port_mode[1]) { -+ case EHCI_HCD_OMAP_MODE_PHY: -+ omap_cfg_reg(AA10_3430_USB2HS_PHY_STP); -+ omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK); -+ omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR); -+ omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT); -+ omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0); -+ omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1); -+ omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2); -+ omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3); -+ omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4); -+ omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5); -+ omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6); -+ omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7); -+ break; -+ case EHCI_HCD_OMAP_MODE_TLL: -+ omap_cfg_reg(AA10_3430_USB2HS_TLL_STP); -+ omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK); -+ omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR); -+ omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT); -+ omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0); -+ omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1); -+ omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2); -+ omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3); -+ omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4); -+ omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5); -+ omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6); -+ omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7); -+ break; -+ case EHCI_HCD_OMAP_MODE_UNKNOWN: -+ /* FALLTHROUGH */ -+ default: -+ break; -+ } -+ -+ switch (port_mode[2]) { -+ case EHCI_HCD_OMAP_MODE_PHY: -+ printk(KERN_WARNING "Port3 can't be used in PHY mode\n"); -+ break; -+ case EHCI_HCD_OMAP_MODE_TLL: -+ omap_cfg_reg(AB3_3430_USB3HS_TLL_STP); -+ omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK); -+ omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR); -+ omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT); -+ omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0); -+ omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1); -+ omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2); -+ omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3); -+ omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4); -+ omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5); -+ omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6); -+ omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7); -+ break; -+ case EHCI_HCD_OMAP_MODE_UNKNOWN: -+ /* FALLTHROUGH */ -+ default: -+ break; -+ } -+ -+ return; -+} -+ -+void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata) -+{ -+ platform_device_add_data(&ehci_device, pdata, sizeof(*pdata)); -+ -+ /* Setup Pin IO MUX for EHCI */ -+ if (cpu_is_omap34xx()) -+ setup_ehci_io_mux(pdata->port_mode); -+ -+ if (platform_device_register(&ehci_device) < 0) { -+ printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n"); -+ return; -+ } -+} -+ -+#else -+ -+void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata) -+ -+{ -+} -+ -+#endif /* CONFIG_USB_EHCI_HCD */ -+ ---- a/arch/arm/plat-omap/common.c -+++ b/arch/arm/plat-omap/common.c -@@ -224,12 +224,12 @@ static void __init __omap2_set_globals(s - - static struct omap_globals omap242x_globals = { - .class = OMAP242X_CLASS, -- .tap = OMAP2_IO_ADDRESS(0x48014000), -- .sdrc = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE), -- .sms = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE), -- .ctrl = OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE), -- .prm = OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE), -- .cm = OMAP2_IO_ADDRESS(OMAP2420_CM_BASE), -+ .tap = OMAP2_L4_IO_ADDRESS(0x48014000), -+ .sdrc = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), -+ .sms = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE), -+ .ctrl = OMAP2_L4_IO_ADDRESS(OMAP2420_CTRL_BASE), -+ .prm = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE), -+ .cm = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), - }; - - void __init omap2_set_globals_242x(void) -@@ -242,12 +242,12 @@ void __init omap2_set_globals_242x(void) - - static struct omap_globals omap243x_globals = { - .class = OMAP243X_CLASS, -- .tap = OMAP2_IO_ADDRESS(0x4900a000), -- .sdrc = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE), -- .sms = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE), -- .ctrl = OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE), -- .prm = OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE), -- .cm = OMAP2_IO_ADDRESS(OMAP2430_CM_BASE), -+ .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), -+ .sdrc = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), -+ .sms = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE), -+ .ctrl = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), -+ .prm = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE), -+ .cm = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), - }; - - void __init omap2_set_globals_243x(void) -@@ -260,12 +260,12 @@ void __init omap2_set_globals_243x(void) - - static struct omap_globals omap343x_globals = { - .class = OMAP343X_CLASS, -- .tap = OMAP2_IO_ADDRESS(0x4830A000), -- .sdrc = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE), -- .sms = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE), -- .ctrl = OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE), -- .prm = OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE), -- .cm = OMAP2_IO_ADDRESS(OMAP3430_CM_BASE), -+ .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), -+ .sdrc = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), -+ .sms = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE), -+ .ctrl = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), -+ .prm = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE), -+ .cm = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), - }; - - void __init omap2_set_globals_343x(void) -@@ -277,10 +277,10 @@ void __init omap2_set_globals_343x(void) - #if defined(CONFIG_ARCH_OMAP4) - static struct omap_globals omap4_globals = { - .class = OMAP443X_CLASS, -- .tap = OMAP2_IO_ADDRESS(0x4830a000), -- .ctrl = OMAP2_IO_ADDRESS(OMAP443X_CTRL_BASE), -- .prm = OMAP2_IO_ADDRESS(OMAP4430_PRM_BASE), -- .cm = OMAP2_IO_ADDRESS(OMAP4430_CM_BASE), -+ .tap = OMAP2_L4_IO_ADDRESS(0x4830a000), -+ .ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE), -+ .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), -+ .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), - }; - - void __init omap2_set_globals_443x(void) ---- a/arch/arm/plat-omap/devices.c -+++ b/arch/arm/plat-omap/devices.c -@@ -113,17 +113,17 @@ static void omap_init_kp(void) - omap_cfg_reg(E19_1610_KBR4); - omap_cfg_reg(N19_1610_KBR5); - } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { -- omap_cfg_reg(E2_730_KBR0); -- omap_cfg_reg(J7_730_KBR1); -- omap_cfg_reg(E1_730_KBR2); -- omap_cfg_reg(F3_730_KBR3); -- omap_cfg_reg(D2_730_KBR4); -- -- omap_cfg_reg(C2_730_KBC0); -- omap_cfg_reg(D3_730_KBC1); -- omap_cfg_reg(E4_730_KBC2); -- omap_cfg_reg(F4_730_KBC3); -- omap_cfg_reg(E3_730_KBC4); -+ omap_cfg_reg(E2_7XX_KBR0); -+ omap_cfg_reg(J7_7XX_KBR1); -+ omap_cfg_reg(E1_7XX_KBR2); -+ omap_cfg_reg(F3_7XX_KBR3); -+ omap_cfg_reg(D2_7XX_KBR4); -+ -+ omap_cfg_reg(C2_7XX_KBC0); -+ omap_cfg_reg(D3_7XX_KBC1); -+ omap_cfg_reg(E4_7XX_KBC2); -+ omap_cfg_reg(F4_7XX_KBC3); -+ omap_cfg_reg(E3_7XX_KBC4); - } else if (machine_is_omap_h4()) { - omap_cfg_reg(T19_24XX_KBR0); - omap_cfg_reg(R19_24XX_KBR1); ---- a/arch/arm/plat-omap/dma.c -+++ b/arch/arm/plat-omap/dma.c -@@ -2359,40 +2359,46 @@ EXPORT_SYMBOL(omap_stop_lcd_dma); - - static int __init omap_init_dma(void) - { -+ unsigned long base; - int ch, r; - - if (cpu_class_is_omap1()) { -- omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE); -+ base = OMAP1_DMA_BASE; - dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; - } else if (cpu_is_omap24xx()) { -- omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE); -+ base = OMAP24XX_DMA4_BASE; - dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; - } else if (cpu_is_omap34xx()) { -- omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE); -+ base = OMAP34XX_DMA4_BASE; - dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; - } else if (cpu_is_omap44xx()) { -- omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE); -+ base = OMAP44XX_DMA4_BASE; - dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; - } else { - pr_err("DMA init failed for unsupported omap\n"); - return -ENODEV; - } - -+ omap_dma_base = ioremap(base, SZ_4K); -+ BUG_ON(!omap_dma_base); -+ - if (cpu_class_is_omap2() && omap_dma_reserve_channels - && (omap_dma_reserve_channels <= dma_lch_count)) - dma_lch_count = omap_dma_reserve_channels; - - dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, - GFP_KERNEL); -- if (!dma_chan) -- return -ENOMEM; -+ if (!dma_chan) { -+ r = -ENOMEM; -+ goto out_unmap; -+ } - - if (cpu_class_is_omap2()) { - dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * - dma_lch_count, GFP_KERNEL); - if (!dma_linked_lch) { -- kfree(dma_chan); -- return -ENOMEM; -+ r = -ENOMEM; -+ goto out_free; - } - } - -@@ -2466,7 +2472,7 @@ static int __init omap_init_dma(void) - for (i = 0; i < ch; i++) - free_irq(omap1_dma_irq[i], - (void *) (i + 1)); -- return r; -+ goto out_free; - } - } - } -@@ -2508,11 +2514,19 @@ static int __init omap_init_dma(void) - "(error %d)\n", r); - for (i = 0; i < dma_chan_count; i++) - free_irq(omap1_dma_irq[i], (void *) (i + 1)); -- return r; -+ goto out_free; - } - } - - return 0; -+ -+out_free: -+ kfree(dma_chan); -+ -+out_unmap: -+ iounmap(omap_dma_base); -+ -+ return r; - } - - arch_initcall(omap_init_dma); ---- a/arch/arm/plat-omap/dmtimer.c -+++ b/arch/arm/plat-omap/dmtimer.c -@@ -742,16 +742,17 @@ EXPORT_SYMBOL_GPL(omap_dm_timers_active) - int __init omap_dm_timer_init(void) - { - struct omap_dm_timer *timer; -- int i; -+ int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ - - if (!(cpu_is_omap16xx() || cpu_class_is_omap2())) - return -ENODEV; - - spin_lock_init(&dm_timer_lock); - -- if (cpu_class_is_omap1()) -+ if (cpu_class_is_omap1()) { - dm_timers = omap1_dm_timers; -- else if (cpu_is_omap24xx()) { -+ map_size = SZ_2K; -+ } else if (cpu_is_omap24xx()) { - dm_timers = omap2_dm_timers; - dm_source_names = omap2_dm_source_names; - dm_source_clocks = omap2_dm_source_clocks; -@@ -774,10 +775,11 @@ int __init omap_dm_timer_init(void) - - for (i = 0; i < dm_timer_count; i++) { - timer = &dm_timers[i]; -- if (cpu_class_is_omap1()) -- timer->io_base = OMAP1_IO_ADDRESS(timer->phys_base); -- else -- timer->io_base = OMAP2_IO_ADDRESS(timer->phys_base); -+ -+ /* Static mapping, never released */ -+ timer->io_base = ioremap(timer->phys_base, map_size); -+ BUG_ON(!timer->io_base); -+ - #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) - if (cpu_class_is_omap2()) { ---- a/arch/arm/plat-omap/gpio.c -+++ b/arch/arm/plat-omap/gpio.c -@@ -31,7 +31,7 @@ - /* - * OMAP1510 GPIO registers - */ --#define OMAP1510_GPIO_BASE OMAP1_IO_ADDRESS(0xfffce000) -+#define OMAP1510_GPIO_BASE 0xfffce000 - #define OMAP1510_GPIO_DATA_INPUT 0x00 - #define OMAP1510_GPIO_DATA_OUTPUT 0x04 - #define OMAP1510_GPIO_DIR_CONTROL 0x08 -@@ -45,10 +45,10 @@ - /* - * OMAP1610 specific GPIO registers - */ --#define OMAP1610_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbe400) --#define OMAP1610_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbec00) --#define OMAP1610_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbb400) --#define OMAP1610_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbbc00) -+#define OMAP1610_GPIO1_BASE 0xfffbe400 -+#define OMAP1610_GPIO2_BASE 0xfffbec00 -+#define OMAP1610_GPIO3_BASE 0xfffbb400 -+#define OMAP1610_GPIO4_BASE 0xfffbbc00 - #define OMAP1610_GPIO_REVISION 0x0000 - #define OMAP1610_GPIO_SYSCONFIG 0x0010 - #define OMAP1610_GPIO_SYSSTATUS 0x0014 -@@ -68,52 +68,36 @@ - #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 - - /* -- * OMAP730 specific GPIO registers -+ * OMAP7XX specific GPIO registers - */ --#define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000) --#define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800) --#define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000) --#define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800) --#define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000) --#define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800) --#define OMAP730_GPIO_DATA_INPUT 0x00 --#define OMAP730_GPIO_DATA_OUTPUT 0x04 --#define OMAP730_GPIO_DIR_CONTROL 0x08 --#define OMAP730_GPIO_INT_CONTROL 0x0c --#define OMAP730_GPIO_INT_MASK 0x10 --#define OMAP730_GPIO_INT_STATUS 0x14 -+#define OMAP7XX_GPIO1_BASE 0xfffbc000 -+#define OMAP7XX_GPIO2_BASE 0xfffbc800 -+#define OMAP7XX_GPIO3_BASE 0xfffbd000 -+#define OMAP7XX_GPIO4_BASE 0xfffbd800 -+#define OMAP7XX_GPIO5_BASE 0xfffbe000 -+#define OMAP7XX_GPIO6_BASE 0xfffbe800 -+#define OMAP7XX_GPIO_DATA_INPUT 0x00 -+#define OMAP7XX_GPIO_DATA_OUTPUT 0x04 -+#define OMAP7XX_GPIO_DIR_CONTROL 0x08 -+#define OMAP7XX_GPIO_INT_CONTROL 0x0c -+#define OMAP7XX_GPIO_INT_MASK 0x10 -+#define OMAP7XX_GPIO_INT_STATUS 0x14 - --/* -- * OMAP850 specific GPIO registers -- */ --#define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000) --#define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800) --#define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000) --#define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800) --#define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000) --#define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800) --#define OMAP850_GPIO_DATA_INPUT 0x00 --#define OMAP850_GPIO_DATA_OUTPUT 0x04 --#define OMAP850_GPIO_DIR_CONTROL 0x08 --#define OMAP850_GPIO_INT_CONTROL 0x0c --#define OMAP850_GPIO_INT_MASK 0x10 --#define OMAP850_GPIO_INT_STATUS 0x14 -- --#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE) -+#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE - - /* - * omap24xx specific GPIO registers - */ --#define OMAP242X_GPIO1_BASE OMAP2_IO_ADDRESS(0x48018000) --#define OMAP242X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4801a000) --#define OMAP242X_GPIO3_BASE OMAP2_IO_ADDRESS(0x4801c000) --#define OMAP242X_GPIO4_BASE OMAP2_IO_ADDRESS(0x4801e000) -- --#define OMAP243X_GPIO1_BASE OMAP2_IO_ADDRESS(0x4900C000) --#define OMAP243X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4900E000) --#define OMAP243X_GPIO3_BASE OMAP2_IO_ADDRESS(0x49010000) --#define OMAP243X_GPIO4_BASE OMAP2_IO_ADDRESS(0x49012000) --#define OMAP243X_GPIO5_BASE OMAP2_IO_ADDRESS(0x480B6000) -+#define OMAP242X_GPIO1_BASE 0x48018000 -+#define OMAP242X_GPIO2_BASE 0x4801a000 -+#define OMAP242X_GPIO3_BASE 0x4801c000 -+#define OMAP242X_GPIO4_BASE 0x4801e000 -+ -+#define OMAP243X_GPIO1_BASE 0x4900C000 -+#define OMAP243X_GPIO2_BASE 0x4900E000 -+#define OMAP243X_GPIO3_BASE 0x49010000 -+#define OMAP243X_GPIO4_BASE 0x49012000 -+#define OMAP243X_GPIO5_BASE 0x480B6000 - - #define OMAP24XX_GPIO_REVISION 0x0000 - #define OMAP24XX_GPIO_SYSCONFIG 0x0010 -@@ -170,24 +154,25 @@ - * omap34xx specific GPIO registers - */ - --#define OMAP34XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x48310000) --#define OMAP34XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x49050000) --#define OMAP34XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x49052000) --#define OMAP34XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x49054000) --#define OMAP34XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x49056000) --#define OMAP34XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x49058000) -+#define OMAP34XX_GPIO1_BASE 0x48310000 -+#define OMAP34XX_GPIO2_BASE 0x49050000 -+#define OMAP34XX_GPIO3_BASE 0x49052000 -+#define OMAP34XX_GPIO4_BASE 0x49054000 -+#define OMAP34XX_GPIO5_BASE 0x49056000 -+#define OMAP34XX_GPIO6_BASE 0x49058000 - - /* - * OMAP44XX specific GPIO registers - */ --#define OMAP44XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x4a310000) --#define OMAP44XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x48055000) --#define OMAP44XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x48057000) --#define OMAP44XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x48059000) --#define OMAP44XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x4805B000) --#define OMAP44XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x4805D000) -+#define OMAP44XX_GPIO1_BASE 0x4a310000 -+#define OMAP44XX_GPIO2_BASE 0x48055000 -+#define OMAP44XX_GPIO3_BASE 0x48057000 -+#define OMAP44XX_GPIO4_BASE 0x48059000 -+#define OMAP44XX_GPIO5_BASE 0x4805B000 -+#define OMAP44XX_GPIO6_BASE 0x4805D000 - - struct gpio_bank { -+ unsigned long pbase; - void __iomem *base; - u16 irq; - u16 virtual_irq_start; -@@ -215,96 +200,111 @@ struct gpio_bank { - #define METHOD_MPUIO 0 - #define METHOD_GPIO_1510 1 - #define METHOD_GPIO_1610 2 --#define METHOD_GPIO_730 3 --#define METHOD_GPIO_850 4 -+#define METHOD_GPIO_7XX 3 - #define METHOD_GPIO_24XX 5 - - #ifdef CONFIG_ARCH_OMAP16XX - static struct gpio_bank gpio_bank_1610[5] = { -- { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, -- { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, -- { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, -- { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, -- { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, -+ { OMAP1_MPUIO_VBASE, 0, INT_MPUIO, IH_MPUIO_BASE, -+ METHOD_MPUIO }, -+ { OMAP1610_GPIO1_BASE, 0, INT_GPIO_BANK1, IH_GPIO_BASE, -+ METHOD_GPIO_1610 }, -+ { OMAP1610_GPIO2_BASE, 0, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, -+ METHOD_GPIO_1610 }, -+ { OMAP1610_GPIO3_BASE, 0, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, -+ METHOD_GPIO_1610 }, -+ { OMAP1610_GPIO4_BASE, 0, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, -+ METHOD_GPIO_1610 }, - }; - #endif - - #ifdef CONFIG_ARCH_OMAP15XX - static struct gpio_bank gpio_bank_1510[2] = { -- { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, -- { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } --}; --#endif -- --#ifdef CONFIG_ARCH_OMAP730 --static struct gpio_bank gpio_bank_730[7] = { -- { OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, -- { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, -- { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, -- { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, -- { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, -- { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, -- { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, -+ { OMAP1_MPUIO_VBASE, 0, INT_MPUIO, IH_MPUIO_BASE, -+ METHOD_MPUIO }, -+ { OMAP1510_GPIO_BASE, 0, INT_GPIO_BANK1, IH_GPIO_BASE, -+ METHOD_GPIO_1510 } - }; - #endif - --#ifdef CONFIG_ARCH_OMAP850 --static struct gpio_bank gpio_bank_850[7] = { -- { OMAP1_MPUIO_VBASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, -- { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 }, -- { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 }, -- { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 }, -- { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 }, -- { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 }, -- { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 }, -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+static struct gpio_bank gpio_bank_7xx[7] = { -+ { OMAP1_MPUIO_VBASE, 0, INT_7XX_MPUIO, IH_MPUIO_BASE, -+ METHOD_MPUIO }, -+ { OMAP7XX_GPIO1_BASE, 0, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, -+ METHOD_GPIO_7XX }, -+ { OMAP7XX_GPIO2_BASE, 0, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, -+ METHOD_GPIO_7XX }, -+ { OMAP7XX_GPIO3_BASE, 0, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, -+ METHOD_GPIO_7XX }, -+ { OMAP7XX_GPIO4_BASE, 0, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, -+ METHOD_GPIO_7XX }, -+ { OMAP7XX_GPIO5_BASE, 0, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, -+ METHOD_GPIO_7XX }, -+ { OMAP7XX_GPIO6_BASE, 0, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, -+ METHOD_GPIO_7XX }, - }; - #endif - -- - #ifdef CONFIG_ARCH_OMAP24XX - - static struct gpio_bank gpio_bank_242x[4] = { -- { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, -- { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, -- { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, -- { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, -+ { OMAP242X_GPIO1_BASE, 0, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, -+ METHOD_GPIO_24XX }, -+ { OMAP242X_GPIO2_BASE, 0, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, -+ METHOD_GPIO_24XX }, -+ { OMAP242X_GPIO3_BASE, 0, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, -+ METHOD_GPIO_24XX }, -+ { OMAP242X_GPIO4_BASE, 0, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, -+ METHOD_GPIO_24XX }, - }; - - static struct gpio_bank gpio_bank_243x[5] = { -- { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, -- { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, -- { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, -- { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, -- { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, -+ { OMAP243X_GPIO1_BASE, 0, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, -+ METHOD_GPIO_24XX }, -+ { OMAP243X_GPIO2_BASE, 0, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, -+ METHOD_GPIO_24XX }, -+ { OMAP243X_GPIO3_BASE, 0, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, -+ METHOD_GPIO_24XX }, -+ { OMAP243X_GPIO4_BASE, 0, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, -+ METHOD_GPIO_24XX }, -+ { OMAP243X_GPIO5_BASE, 0, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, -+ METHOD_GPIO_24XX }, - }; - - #endif - - #ifdef CONFIG_ARCH_OMAP34XX - static struct gpio_bank gpio_bank_34xx[6] = { -- { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, -- { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, -- { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, -- { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, -- { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, -- { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX }, -+ { OMAP34XX_GPIO1_BASE, 0, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, -+ METHOD_GPIO_24XX }, -+ { OMAP34XX_GPIO2_BASE, 0, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, -+ METHOD_GPIO_24XX }, -+ { OMAP34XX_GPIO3_BASE, 0, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, -+ METHOD_GPIO_24XX }, -+ { OMAP34XX_GPIO4_BASE, 0, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, -+ METHOD_GPIO_24XX }, -+ { OMAP34XX_GPIO5_BASE, 0, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, -+ METHOD_GPIO_24XX }, -+ { OMAP34XX_GPIO6_BASE, 0, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, -+ METHOD_GPIO_24XX }, - }; - - #endif - - #ifdef CONFIG_ARCH_OMAP4 - static struct gpio_bank gpio_bank_44xx[6] = { -- { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \ -+ { OMAP44XX_GPIO1_BASE, 0, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, - METHOD_GPIO_24XX }, -- { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \ -+ { OMAP44XX_GPIO2_BASE, 0, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, - METHOD_GPIO_24XX }, -- { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \ -+ { OMAP44XX_GPIO3_BASE, 0, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, - METHOD_GPIO_24XX }, -- { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \ -+ { OMAP44XX_GPIO4_BASE, 0, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, - METHOD_GPIO_24XX }, -- { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \ -+ { OMAP44XX_GPIO5_BASE, 0, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, - METHOD_GPIO_24XX }, -- { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \ -+ { OMAP44XX_GPIO6_BASE, 0, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, - METHOD_GPIO_24XX }, - }; - -@@ -402,14 +402,9 @@ static void _set_gpio_direction(struct g - reg += OMAP1610_GPIO_DIRECTION; - break; - #endif --#ifdef CONFIG_ARCH_OMAP730 -- case METHOD_GPIO_730: -- reg += OMAP730_GPIO_DIR_CONTROL; -- break; --#endif --#ifdef CONFIG_ARCH_OMAP850 -- case METHOD_GPIO_850: -- reg += OMAP850_GPIO_DIR_CONTROL; -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ case METHOD_GPIO_7XX: -+ reg += OMAP7XX_GPIO_DIR_CONTROL; - break; - #endif - #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) -@@ -469,19 +464,9 @@ static void _set_gpio_dataout(struct gpi - l = 1 << gpio; - break; - #endif --#ifdef CONFIG_ARCH_OMAP730 -- case METHOD_GPIO_730: -- reg += OMAP730_GPIO_DATA_OUTPUT; -- l = __raw_readl(reg); -- if (enable) -- l |= 1 << gpio; -- else -- l &= ~(1 << gpio); -- break; --#endif --#ifdef CONFIG_ARCH_OMAP850 -- case METHOD_GPIO_850: -- reg += OMAP850_GPIO_DATA_OUTPUT; -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ case METHOD_GPIO_7XX: -+ reg += OMAP7XX_GPIO_DATA_OUTPUT; - l = __raw_readl(reg); - if (enable) - l |= 1 << gpio; -@@ -537,14 +522,9 @@ static int _get_gpio_datain(struct gpio_ - reg += OMAP1610_GPIO_DATAIN; - break; - #endif --#ifdef CONFIG_ARCH_OMAP730 -- case METHOD_GPIO_730: -- reg += OMAP730_GPIO_DATA_INPUT; -- break; --#endif --#ifdef CONFIG_ARCH_OMAP850 -- case METHOD_GPIO_850: -- reg += OMAP850_GPIO_DATA_INPUT; -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ case METHOD_GPIO_7XX: -+ reg += OMAP7XX_GPIO_DATA_INPUT; - break; - #endif - #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) -@@ -588,14 +568,9 @@ static int _get_gpio_dataout(struct gpio - reg += OMAP1610_GPIO_DATAOUT; - break; - #endif --#ifdef CONFIG_ARCH_OMAP730 -- case METHOD_GPIO_730: -- reg += OMAP730_GPIO_DATA_OUTPUT; -- break; --#endif --#ifdef CONFIG_ARCH_OMAP850 -- case METHOD_GPIO_850: -- reg += OMAP850_GPIO_DATA_OUTPUT; -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ case METHOD_GPIO_7XX: -+ reg += OMAP7XX_GPIO_DATA_OUTPUT; - break; - #endif - #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ -@@ -797,21 +772,9 @@ static int _set_gpio_triggering(struct g - __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); - break; - #endif --#ifdef CONFIG_ARCH_OMAP730 -- case METHOD_GPIO_730: -- reg += OMAP730_GPIO_INT_CONTROL; -- l = __raw_readl(reg); -- if (trigger & IRQ_TYPE_EDGE_RISING) -- l |= 1 << gpio; -- else if (trigger & IRQ_TYPE_EDGE_FALLING) -- l &= ~(1 << gpio); -- else -- goto bad; -- break; --#endif --#ifdef CONFIG_ARCH_OMAP850 -- case METHOD_GPIO_850: -- reg += OMAP850_GPIO_INT_CONTROL; -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ case METHOD_GPIO_7XX: -+ reg += OMAP7XX_GPIO_INT_CONTROL; - l = __raw_readl(reg); - if (trigger & IRQ_TYPE_EDGE_RISING) - l |= 1 << gpio; -@@ -897,14 +860,9 @@ static void _clear_gpio_irqbank(struct g - reg += OMAP1610_GPIO_IRQSTATUS1; - break; - #endif --#ifdef CONFIG_ARCH_OMAP730 -- case METHOD_GPIO_730: -- reg += OMAP730_GPIO_INT_STATUS; -- break; --#endif --#ifdef CONFIG_ARCH_OMAP850 -- case METHOD_GPIO_850: -- reg += OMAP850_GPIO_INT_STATUS; -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ case METHOD_GPIO_7XX: -+ reg += OMAP7XX_GPIO_INT_STATUS; - break; - #endif - #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) -@@ -971,16 +929,9 @@ static u32 _get_gpio_irqbank_mask(struct - mask = 0xffff; - break; - #endif --#ifdef CONFIG_ARCH_OMAP730 -- case METHOD_GPIO_730: -- reg += OMAP730_GPIO_INT_MASK; -- mask = 0xffffffff; -- inv = 1; -- break; --#endif --#ifdef CONFIG_ARCH_OMAP850 -- case METHOD_GPIO_850: -- reg += OMAP850_GPIO_INT_MASK; -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ case METHOD_GPIO_7XX: -+ reg += OMAP7XX_GPIO_INT_MASK; - mask = 0xffffffff; - inv = 1; - break; -@@ -1044,19 +995,9 @@ static void _enable_gpio_irqbank(struct - l = gpio_mask; - break; - #endif --#ifdef CONFIG_ARCH_OMAP730 -- case METHOD_GPIO_730: -- reg += OMAP730_GPIO_INT_MASK; -- l = __raw_readl(reg); -- if (enable) -- l &= ~(gpio_mask); -- else -- l |= gpio_mask; -- break; --#endif --#ifdef CONFIG_ARCH_OMAP850 -- case METHOD_GPIO_850: -- reg += OMAP850_GPIO_INT_MASK; -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ case METHOD_GPIO_7XX: -+ reg += OMAP7XX_GPIO_INT_MASK; - l = __raw_readl(reg); - if (enable) - l &= ~(gpio_mask); -@@ -1249,13 +1190,9 @@ static void gpio_irq_handler(unsigned in - if (bank->method == METHOD_GPIO_1610) - isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; - #endif --#ifdef CONFIG_ARCH_OMAP730 -- if (bank->method == METHOD_GPIO_730) -- isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; --#endif --#ifdef CONFIG_ARCH_OMAP850 -- if (bank->method == METHOD_GPIO_850) -- isr_reg = bank->base + OMAP850_GPIO_INT_STATUS; -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ if (bank->method == METHOD_GPIO_7XX) -+ isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; - #endif - #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) - if (bank->method == METHOD_GPIO_24XX) -@@ -1524,11 +1461,8 @@ static int gpio_is_input(struct gpio_ban - case METHOD_GPIO_1610: - reg += OMAP1610_GPIO_DIRECTION; - break; -- case METHOD_GPIO_730: -- reg += OMAP730_GPIO_DIR_CONTROL; -- break; -- case METHOD_GPIO_850: -- reg += OMAP850_GPIO_DIR_CONTROL; -+ case METHOD_GPIO_7XX: -+ reg += OMAP7XX_GPIO_DIR_CONTROL; - break; - case METHOD_GPIO_24XX: - reg += OMAP24XX_GPIO_OE; -@@ -1607,6 +1541,23 @@ static struct clk * gpio5_fck; - static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; - #endif - -+static void __init omap_gpio_show_rev(void) -+{ -+ u32 rev; -+ -+ if (cpu_is_omap16xx()) -+ rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); -+ else if (cpu_is_omap24xx() || cpu_is_omap34xx()) -+ rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); -+ else if (cpu_is_omap44xx()) -+ rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION); -+ else -+ return; -+ -+ printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", -+ (rev >> 4) & 0x0f, rev & 0x0f); -+} -+ - /* This lock class tells lockdep that GPIO irqs are in a different - * category than their parents, so it won't report false recursion. - */ -@@ -1617,6 +1568,7 @@ static int __init _omap_gpio_init(void) - int i; - int gpio = 0; - struct gpio_bank *bank; -+ int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ - char clk_name[11]; - - initialized = 1; -@@ -1679,77 +1631,45 @@ static int __init _omap_gpio_init(void) - - #ifdef CONFIG_ARCH_OMAP15XX - if (cpu_is_omap15xx()) { -- printk(KERN_INFO "OMAP1510 GPIO hardware\n"); - gpio_bank_count = 2; - gpio_bank = gpio_bank_1510; -+ bank_size = SZ_2K; - } - #endif - #if defined(CONFIG_ARCH_OMAP16XX) - if (cpu_is_omap16xx()) { -- u32 rev; -- - gpio_bank_count = 5; - gpio_bank = gpio_bank_1610; -- rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); -- printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", -- (rev >> 4) & 0x0f, rev & 0x0f); -+ bank_size = SZ_2K; - } - #endif --#ifdef CONFIG_ARCH_OMAP730 -- if (cpu_is_omap730()) { -- printk(KERN_INFO "OMAP730 GPIO hardware\n"); -- gpio_bank_count = 7; -- gpio_bank = gpio_bank_730; -- } --#endif --#ifdef CONFIG_ARCH_OMAP850 -- if (cpu_is_omap850()) { -- printk(KERN_INFO "OMAP850 GPIO hardware\n"); -+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+ if (cpu_is_omap7xx()) { - gpio_bank_count = 7; -- gpio_bank = gpio_bank_850; -+ gpio_bank = gpio_bank_7xx; -+ bank_size = SZ_2K; - } - #endif -- - #ifdef CONFIG_ARCH_OMAP24XX - if (cpu_is_omap242x()) { -- int rev; -- - gpio_bank_count = 4; - gpio_bank = gpio_bank_242x; -- rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); -- printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", -- (rev >> 4) & 0x0f, rev & 0x0f); - } - if (cpu_is_omap243x()) { -- int rev; -- - gpio_bank_count = 5; - gpio_bank = gpio_bank_243x; -- rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); -- printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", -- (rev >> 4) & 0x0f, rev & 0x0f); - } - #endif - #ifdef CONFIG_ARCH_OMAP34XX - if (cpu_is_omap34xx()) { -- int rev; -- - gpio_bank_count = OMAP34XX_NR_GPIOS; - gpio_bank = gpio_bank_34xx; -- rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); -- printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n", -- (rev >> 4) & 0x0f, rev & 0x0f); - } - #endif - #ifdef CONFIG_ARCH_OMAP4 - if (cpu_is_omap44xx()) { -- int rev; -- - gpio_bank_count = OMAP34XX_NR_GPIOS; - gpio_bank = gpio_bank_44xx; -- rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION); -- printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n", -- (rev >> 4) & 0x0f, rev & 0x0f); - } - #endif - for (i = 0; i < gpio_bank_count; i++) { -@@ -1757,6 +1677,14 @@ static int __init _omap_gpio_init(void) - - bank = &gpio_bank[i]; - spin_lock_init(&bank->lock); -+ -+ /* Static mapping, never released */ -+ bank->base = ioremap(bank->pbase, bank_size); -+ if (!bank->base) { -+ printk(KERN_ERR "Could not ioremap gpio bank%i\n", i); -+ continue; -+ } -+ - if (bank_is_mpuio(bank)) - __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); - if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { -@@ -1768,11 +1696,11 @@ static int __init _omap_gpio_init(void) - __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); - __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); - } -- if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) { -- __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); -- __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); -+ if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { -+ __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK); -+ __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS); - -- gpio_count = 32; /* 730 has 32-bit GPIOs */ -+ gpio_count = 32; /* 7xx has 32-bit GPIOs */ - } - - #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ -@@ -1862,6 +1790,8 @@ static int __init _omap_gpio_init(void) - if (cpu_is_omap34xx()) - omap_writel(1 << 0, 0x48306814); - -+ omap_gpio_show_rev(); -+ - return 0; - } - -@@ -2160,8 +2090,7 @@ static int dbg_gpio_show(struct seq_file - - if (bank_is_mpuio(bank)) - gpio = OMAP_MPUIO(0); -- else if (cpu_class_is_omap2() || cpu_is_omap730() || -- cpu_is_omap850()) -+ else if (cpu_class_is_omap2() || cpu_is_omap7xx()) - bankwidth = 32; - - for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { ---- a/arch/arm/plat-omap/include/mach/control.h -+++ b/arch/arm/plat-omap/include/mach/control.h -@@ -20,15 +20,18 @@ - - #ifndef __ASSEMBLY__ - #define OMAP242X_CTRL_REGADDR(reg) \ -- OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) -+ OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) - #define OMAP243X_CTRL_REGADDR(reg) \ -- OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) -+ OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) - #define OMAP343X_CTRL_REGADDR(reg) \ -- OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) -+ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) - #else --#define OMAP242X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) --#define OMAP243X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) --#define OMAP343X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) -+#define OMAP242X_CTRL_REGADDR(reg) \ -+ OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) -+#define OMAP243X_CTRL_REGADDR(reg) \ -+ OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) -+#define OMAP343X_CTRL_REGADDR(reg) \ -+ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) - #endif /* __ASSEMBLY__ */ - - /* -@@ -202,6 +205,40 @@ - #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) - #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) - -+/* -+ * CONTROL OMAP STATUS register to identify OMAP3 features -+ */ -+#define OMAP3_CONTROL_OMAP_STATUS 0x044c -+ -+#define OMAP3_SGX_SHIFT 13 -+#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT) -+#define FEAT_SGX_FULL 0 -+#define FEAT_SGX_HALF 1 -+#define FEAT_SGX_NONE 2 -+ -+#define OMAP3_IVA_SHIFT 12 -+#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT) -+#define FEAT_IVA 0 -+#define FEAT_IVA_NONE 1 -+ -+#define OMAP3_L2CACHE_SHIFT 10 -+#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT) -+#define FEAT_L2CACHE_NONE 0 -+#define FEAT_L2CACHE_64KB 1 -+#define FEAT_L2CACHE_128KB 2 -+#define FEAT_L2CACHE_256KB 3 -+ -+#define OMAP3_ISP_SHIFT 5 -+#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT) -+#define FEAT_ISP 0 -+#define FEAT_ISP_NONE 1 -+ -+#define OMAP3_NEON_SHIFT 4 -+#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT) -+#define FEAT_NEON 0 -+#define FEAT_NEON_NONE 1 -+ -+ - #ifndef __ASSEMBLY__ - #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) ---- a/arch/arm/plat-omap/include/mach/cpu.h -+++ b/arch/arm/plat-omap/include/mach/cpu.h -@@ -30,6 +30,8 @@ - #ifndef __ASM_ARCH_OMAP_CPU_H - #define __ASM_ARCH_OMAP_CPU_H - -+#include <linux/bitops.h> -+ - /* - * Omap device type i.e. EMU/HS/TST/GP/BAD - */ -@@ -57,6 +59,23 @@ struct omap_chip_id { - unsigned int omap_rev(void); - - /* -+ * Define CPU revision bits -+ * -+ * Verbose meaning of the revision bits may be different for a silicon -+ * family. This difference can be handled separately. -+ */ -+#define OMAP_REVBITS_00 0x00 -+#define OMAP_REVBITS_10 0x10 -+#define OMAP_REVBITS_20 0x20 -+#define OMAP_REVBITS_30 0x30 -+#define OMAP_REVBITS_40 0x40 -+ -+/* -+ * Get the CPU revision for OMAP devices -+ */ -+#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) -+ -+/* - * Test if multicore OMAP support is needed - */ - #undef MULTI_OMAP1 -@@ -161,6 +180,7 @@ IS_OMAP_CLASS(34xx, 0x34) - IS_OMAP_SUBCLASS(242x, 0x242) - IS_OMAP_SUBCLASS(243x, 0x243) - IS_OMAP_SUBCLASS(343x, 0x343) -+IS_OMAP_SUBCLASS(363x, 0x363) - - #define cpu_is_omap7xx() 0 - #define cpu_is_omap15xx() 0 -@@ -301,7 +321,12 @@ IS_OMAP_TYPE(3430, 0x3430) - #define cpu_is_omap2422() 0 - #define cpu_is_omap2423() 0 - #define cpu_is_omap2430() 0 -+#define cpu_is_omap3503() 0 -+#define cpu_is_omap3515() 0 -+#define cpu_is_omap3525() 0 -+#define cpu_is_omap3530() 0 - #define cpu_is_omap3430() 0 -+#define cpu_is_omap3630() 0 - - /* - * Whether we have MULTI_OMAP1 or not, we still need to distinguish -@@ -351,7 +376,23 @@ IS_OMAP_TYPE(3430, 0x3430) - - #if defined(CONFIG_ARCH_OMAP34XX) - # undef cpu_is_omap3430 -+# undef cpu_is_omap3503 -+# undef cpu_is_omap3515 -+# undef cpu_is_omap3525 -+# undef cpu_is_omap3530 - # define cpu_is_omap3430() is_omap3430() -+# define cpu_is_omap3503 (cpu_is_omap3430() && \ -+ (!omap3_has_iva()) && \ -+ (!omap3_has_sgx())) -+# define cpu_is_omap3515 (cpu_is_omap3430() && \ -+ (omap3_has_iva()) && \ -+ (!omap3_has_sgx())) -+# define cpu_is_omap3525 (cpu_is_omap3430() && \ -+ (omap3_has_sgx()) && \ -+ (!omap3_has_iva())) -+# define cpu_is_omap3530 (cpu_is_omap3430()) -+# undef cpu_is_omap3630 -+# define cpu_is_omap3630() is_omap363x() - #endif - - # if defined(CONFIG_ARCH_OMAP4) -@@ -382,6 +423,14 @@ IS_OMAP_TYPE(3430, 0x3430) - #define OMAP3430_REV_ES3_0 0x34303034 - #define OMAP3430_REV_ES3_1 0x34304034 - -+#define OMAP3630_REV_ES1_0 0x36300034 -+ -+#define OMAP35XX_CLASS 0x35000034 -+#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 12)) -+#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 12)) -+#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 12)) -+#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 12)) -+ - #define OMAP443X_CLASS 0x44300034 - - /* -@@ -423,4 +472,27 @@ IS_OMAP_TYPE(3430, 0x3430) - int omap_chip_is(struct omap_chip_id oci); - void omap2_check_revision(void); - -+/* -+ * Runtime detection of OMAP3 features -+ */ -+extern u32 omap3_features; -+ -+#define OMAP3_HAS_L2CACHE BIT(0) -+#define OMAP3_HAS_IVA BIT(1) -+#define OMAP3_HAS_SGX BIT(2) -+#define OMAP3_HAS_NEON BIT(3) -+#define OMAP3_HAS_ISP BIT(4) -+ -+#define OMAP3_HAS_FEATURE(feat,flag) \ -+static inline unsigned int omap3_has_ ##feat(void) \ -+{ \ -+ return (omap3_features & OMAP3_HAS_ ##flag); \ -+} \ -+ -+OMAP3_HAS_FEATURE(l2cache, L2CACHE) -+OMAP3_HAS_FEATURE(sgx, SGX) -+OMAP3_HAS_FEATURE(iva, IVA) -+OMAP3_HAS_FEATURE(neon, NEON) -+OMAP3_HAS_FEATURE(isp, ISP) -+ - #endif ---- a/arch/arm/plat-omap/include/mach/debug-macro.S -+++ b/arch/arm/plat-omap/include/mach/debug-macro.S -@@ -27,7 +27,7 @@ - - #elif CONFIG_ARCH_OMAP2 - moveq \rx, #0x48000000 @ physical base address -- movne \rx, #0xd8000000 @ virtual base -+ movne \rx, #0xfa000000 @ virtual base - orr \rx, \rx, #0x0006a000 - #ifdef CONFIG_OMAP_LL_DEBUG_UART2 - add \rx, \rx, #0x00002000 @ UART 2 -@@ -38,7 +38,7 @@ - - #elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - moveq \rx, #0x48000000 @ physical base address -- movne \rx, #0xd8000000 @ virtual base -+ movne \rx, #0xfa000000 @ virtual base - orr \rx, \rx, #0x0006a000 - #ifdef CONFIG_OMAP_LL_DEBUG_UART2 - add \rx, \rx, #0x00002000 @ UART 2 ---- a/arch/arm/plat-omap/include/mach/entry-macro.S -+++ b/arch/arm/plat-omap/include/mach/entry-macro.S -@@ -17,11 +17,11 @@ - - #if defined(CONFIG_ARCH_OMAP1) - --#if defined(CONFIG_ARCH_OMAP730) && \ -+#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \ - (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) --#error "FIXME: OMAP730 doesn't support multiple-OMAP" --#elif defined(CONFIG_ARCH_OMAP730) --#define INT_IH2_IRQ INT_730_IH2_IRQ -+#error "FIXME: OMAP7XX doesn't support multiple-OMAP" -+#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+#define INT_IH2_IRQ INT_7XX_IH2_IRQ - #elif defined(CONFIG_ARCH_OMAP15XX) - #define INT_IH2_IRQ INT_1510_IH2_IRQ - #elif defined(CONFIG_ARCH_OMAP16XX) -@@ -68,9 +68,9 @@ - - /* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ - #if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) --#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE) -+#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) - #elif defined(CONFIG_ARCH_OMAP34XX) --#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE) -+#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) - #endif - #if defined(CONFIG_ARCH_OMAP4) - #include <mach/omap44xx.h> -@@ -104,6 +104,8 @@ - - .endm - #else -+#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) -+ - /* - * The interrupt numbering scheme is defined in the - * interrupt controller spec. To wit: ---- a/arch/arm/plat-omap/include/mach/hardware.h -+++ b/arch/arm/plat-omap/include/mach/hardware.h -@@ -280,7 +280,7 @@ - * --------------------------------------------------------------------------- - */ - --#include "omap730.h" -+#include "omap7xx.h" - #include "omap1510.h" - #include "omap16xx.h" - #include "omap24xx.h" ---- a/arch/arm/plat-omap/include/mach/io.h -+++ b/arch/arm/plat-omap/include/mach/io.h -@@ -63,8 +63,24 @@ - #define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ - #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) - --#define OMAP2_IO_OFFSET 0x90000000 --#define OMAP2_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */ -+#define OMAP2_L3_IO_OFFSET 0x90000000 -+#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ -+ -+ -+#define OMAP2_L4_IO_OFFSET 0xb2000000 -+#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */ -+ -+#define OMAP4_L3_IO_OFFSET 0xb4000000 -+#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ -+ -+#define OMAP4_L3_PER_IO_OFFSET 0xb1100000 -+#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) -+ -+#define OMAP4_GPMC_IO_OFFSET 0xa9000000 -+#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET) -+ -+#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ -+#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) - - /* - * ---------------------------------------------------------------------------- -@@ -83,24 +99,27 @@ - */ - - /* We map both L3 and L4 on OMAP2 */ --#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */ --#define L3_24XX_VIRT 0xf8000000 -+#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/ -+#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET) - #define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ --#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */ --#define L4_24XX_VIRT 0xd8000000 -+#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */ -+#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET) - #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ - --#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */ --#define L4_WK_243X_VIRT 0xd9000000 -+#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */ -+#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET) - #define L4_WK_243X_SIZE SZ_1M --#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */ --#define OMAP243X_GPMC_VIRT 0xFE000000 -+#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE -+#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET) -+ /* 0x6e000000 --> 0xfe000000 */ - #define OMAP243X_GPMC_SIZE SZ_1M - #define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE --#define OMAP243X_SDRC_VIRT 0xFD000000 -+ /* 0x6D000000 --> 0xfd000000 */ -+#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) - #define OMAP243X_SDRC_SIZE SZ_1M - #define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE --#define OMAP243X_SMS_VIRT 0xFC000000 -+ /* 0x6c000000 --> 0xfc000000 */ -+#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET) - #define OMAP243X_SMS_SIZE SZ_1M - - /* DSP */ -@@ -121,12 +140,12 @@ - */ - - /* We map both L3 and L4 on OMAP3 */ --#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */ --#define L3_34XX_VIRT 0xf8000000 -+#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */ -+#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET) - #define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ - --#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */ --#define L4_34XX_VIRT 0xd8000000 -+#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */ -+#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET) - #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ - - /* -@@ -134,28 +153,33 @@ - * VPOM3430 was not working for Int controller - */ - --#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */ --#define L4_WK_34XX_VIRT 0xd8300000 -+#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */ -+#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET) - #define L4_WK_34XX_SIZE SZ_1M - --#define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */ --#define L4_PER_34XX_VIRT 0xd9000000 -+#define L4_PER_34XX_PHYS L4_PER_34XX_BASE -+ /* 0x49000000 --> 0xfb000000 */ -+#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) - #define L4_PER_34XX_SIZE SZ_1M - --#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */ --#define L4_EMU_34XX_VIRT 0xe4000000 --#define L4_EMU_34XX_SIZE SZ_64M -- --#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */ --#define OMAP34XX_GPMC_VIRT 0xFE000000 -+#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE -+ /* 0x54000000 --> 0xfe800000 */ -+#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET) -+#define L4_EMU_34XX_SIZE SZ_8M -+ -+#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE -+ /* 0x6e000000 --> 0xfe000000 */ -+#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET) - #define OMAP34XX_GPMC_SIZE SZ_1M - --#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */ --#define OMAP343X_SMS_VIRT 0xFC000000 -+#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE -+ /* 0x6c000000 --> 0xfc000000 */ -+#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET) - #define OMAP343X_SMS_SIZE SZ_1M - --#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */ --#define OMAP343X_SDRC_VIRT 0xFD000000 -+#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE -+ /* 0x6D000000 --> 0xfd000000 */ -+#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) - #define OMAP343X_SDRC_SIZE SZ_1M - - /* DSP */ -@@ -176,32 +200,54 @@ - */ - - /* We map both L3 and L4 on OMAP4 */ --#define L3_44XX_PHYS L3_44XX_BASE --#define L3_44XX_VIRT 0xd4000000 -+#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */ -+#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET) - #define L3_44XX_SIZE SZ_1M - --#define L4_44XX_PHYS L4_44XX_BASE --#define L4_44XX_VIRT 0xda000000 -+#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */ -+#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) - #define L4_44XX_SIZE SZ_4M - - --#define L4_WK_44XX_PHYS L4_WK_44XX_BASE --#define L4_WK_44XX_VIRT 0xda300000 -+#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */ -+#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET) - #define L4_WK_44XX_SIZE SZ_1M - - #define L4_PER_44XX_PHYS L4_PER_44XX_BASE --#define L4_PER_44XX_VIRT 0xd8000000 -+ /* 0x48000000 --> 0xfa000000 */ -+#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) - #define L4_PER_44XX_SIZE SZ_4M - -+#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE -+ /* 0x49000000 --> 0xfb000000 */ -+#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) -+#define L4_ABE_44XX_SIZE SZ_1M -+ - #define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE --#define L4_EMU_44XX_VIRT 0xe4000000 --#define L4_EMU_44XX_SIZE SZ_64M -+ /* 0x54000000 --> 0xfe800000 */ -+#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET) -+#define L4_EMU_44XX_SIZE SZ_8M - - #define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE --#define OMAP44XX_GPMC_VIRT 0xe0000000 -+ /* 0x50000000 --> 0xf9000000 */ -+#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET) - #define OMAP44XX_GPMC_SIZE SZ_1M - - -+#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE -+ /* 0x4c000000 --> 0xfd100000 */ -+#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET) -+#define OMAP44XX_EMIF1_SIZE SZ_1M -+ -+#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE -+ /* 0x4d000000 --> 0xfd200000 */ -+#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET) -+#define OMAP44XX_EMIF2_SIZE SZ_1M -+ -+#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE -+ /* 0x4e000000 --> 0xfd300000 */ -+#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET) -+#define OMAP44XX_DMM_SIZE SZ_1M - /* - * ---------------------------------------------------------------------------- - * Omap specific register access ---- a/arch/arm/plat-omap/include/mach/irqs.h -+++ b/arch/arm/plat-omap/include/mach/irqs.h -@@ -86,49 +86,26 @@ - #define INT_1610_SSR_FIFO_0 29 - - /* -- * OMAP-730 specific IRQ numbers for interrupt handler 1 -+ * OMAP-7xx specific IRQ numbers for interrupt handler 1 - */ --#define INT_730_IH2_FIQ 0 --#define INT_730_IH2_IRQ 1 --#define INT_730_USB_NON_ISO 2 --#define INT_730_USB_ISO 3 --#define INT_730_ICR 4 --#define INT_730_EAC 5 --#define INT_730_GPIO_BANK1 6 --#define INT_730_GPIO_BANK2 7 --#define INT_730_GPIO_BANK3 8 --#define INT_730_McBSP2TX 10 --#define INT_730_McBSP2RX 11 --#define INT_730_McBSP2RX_OVF 12 --#define INT_730_LCD_LINE 14 --#define INT_730_GSM_PROTECT 15 --#define INT_730_TIMER3 16 --#define INT_730_GPIO_BANK5 17 --#define INT_730_GPIO_BANK6 18 --#define INT_730_SPGIO_WR 29 -- --/* -- * OMAP-850 specific IRQ numbers for interrupt handler 1 -- */ --#define INT_850_IH2_FIQ 0 --#define INT_850_IH2_IRQ 1 --#define INT_850_USB_NON_ISO 2 --#define INT_850_USB_ISO 3 --#define INT_850_ICR 4 --#define INT_850_EAC 5 --#define INT_850_GPIO_BANK1 6 --#define INT_850_GPIO_BANK2 7 --#define INT_850_GPIO_BANK3 8 --#define INT_850_McBSP2TX 10 --#define INT_850_McBSP2RX 11 --#define INT_850_McBSP2RX_OVF 12 --#define INT_850_LCD_LINE 14 --#define INT_850_GSM_PROTECT 15 --#define INT_850_TIMER3 16 --#define INT_850_GPIO_BANK5 17 --#define INT_850_GPIO_BANK6 18 --#define INT_850_SPGIO_WR 29 -- -+#define INT_7XX_IH2_FIQ 0 -+#define INT_7XX_IH2_IRQ 1 -+#define INT_7XX_USB_NON_ISO 2 -+#define INT_7XX_USB_ISO 3 -+#define INT_7XX_ICR 4 -+#define INT_7XX_EAC 5 -+#define INT_7XX_GPIO_BANK1 6 -+#define INT_7XX_GPIO_BANK2 7 -+#define INT_7XX_GPIO_BANK3 8 -+#define INT_7XX_McBSP2TX 10 -+#define INT_7XX_McBSP2RX 11 -+#define INT_7XX_McBSP2RX_OVF 12 -+#define INT_7XX_LCD_LINE 14 -+#define INT_7XX_GSM_PROTECT 15 -+#define INT_7XX_TIMER3 16 -+#define INT_7XX_GPIO_BANK5 17 -+#define INT_7XX_GPIO_BANK6 18 -+#define INT_7XX_SPGIO_WR 29 - - /* - * IRQ numbers for interrupt handler 2 -@@ -206,120 +183,62 @@ - #define INT_1610_SHA1MD5 (91 + IH2_BASE) - - /* -- * OMAP-730 specific IRQ numbers for interrupt handler 2 -- */ --#define INT_730_HW_ERRORS (0 + IH2_BASE) --#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE) --#define INT_730_CFCD (2 + IH2_BASE) --#define INT_730_CFIREQ (3 + IH2_BASE) --#define INT_730_I2C (4 + IH2_BASE) --#define INT_730_PCC (5 + IH2_BASE) --#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE) --#define INT_730_SPI_100K_1 (7 + IH2_BASE) --#define INT_730_SYREN_SPI (8 + IH2_BASE) --#define INT_730_VLYNQ (9 + IH2_BASE) --#define INT_730_GPIO_BANK4 (10 + IH2_BASE) --#define INT_730_McBSP1TX (11 + IH2_BASE) --#define INT_730_McBSP1RX (12 + IH2_BASE) --#define INT_730_McBSP1RX_OF (13 + IH2_BASE) --#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE) --#define INT_730_UART_MODEM_1 (15 + IH2_BASE) --#define INT_730_MCSI (16 + IH2_BASE) --#define INT_730_uWireTX (17 + IH2_BASE) --#define INT_730_uWireRX (18 + IH2_BASE) --#define INT_730_SMC_CD (19 + IH2_BASE) --#define INT_730_SMC_IREQ (20 + IH2_BASE) --#define INT_730_HDQ_1WIRE (21 + IH2_BASE) --#define INT_730_TIMER32K (22 + IH2_BASE) --#define INT_730_MMC_SDIO (23 + IH2_BASE) --#define INT_730_UPLD (24 + IH2_BASE) --#define INT_730_USB_HHC_1 (27 + IH2_BASE) --#define INT_730_USB_HHC_2 (28 + IH2_BASE) --#define INT_730_USB_GENI (29 + IH2_BASE) --#define INT_730_USB_OTG (30 + IH2_BASE) --#define INT_730_CAMERA_IF (31 + IH2_BASE) --#define INT_730_RNG (32 + IH2_BASE) --#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE) --#define INT_730_DBB_RF_EN (34 + IH2_BASE) --#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE) --#define INT_730_SHA1_MD5 (36 + IH2_BASE) --#define INT_730_SPI_100K_2 (37 + IH2_BASE) --#define INT_730_RNG_IDLE (38 + IH2_BASE) --#define INT_730_MPUIO (39 + IH2_BASE) --#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) --#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE) --#define INT_730_LLPC_OE_RISING (42 + IH2_BASE) --#define INT_730_LLPC_VSYNC (43 + IH2_BASE) --#define INT_730_WAKE_UP_REQ (46 + IH2_BASE) --#define INT_730_DMA_CH6 (53 + IH2_BASE) --#define INT_730_DMA_CH7 (54 + IH2_BASE) --#define INT_730_DMA_CH8 (55 + IH2_BASE) --#define INT_730_DMA_CH9 (56 + IH2_BASE) --#define INT_730_DMA_CH10 (57 + IH2_BASE) --#define INT_730_DMA_CH11 (58 + IH2_BASE) --#define INT_730_DMA_CH12 (59 + IH2_BASE) --#define INT_730_DMA_CH13 (60 + IH2_BASE) --#define INT_730_DMA_CH14 (61 + IH2_BASE) --#define INT_730_DMA_CH15 (62 + IH2_BASE) --#define INT_730_NAND (63 + IH2_BASE) -- --/* -- * OMAP-850 specific IRQ numbers for interrupt handler 2 -+ * OMAP-7xx specific IRQ numbers for interrupt handler 2 - */ --#define INT_850_HW_ERRORS (0 + IH2_BASE) --#define INT_850_NFIQ_PWR_FAIL (1 + IH2_BASE) --#define INT_850_CFCD (2 + IH2_BASE) --#define INT_850_CFIREQ (3 + IH2_BASE) --#define INT_850_I2C (4 + IH2_BASE) --#define INT_850_PCC (5 + IH2_BASE) --#define INT_850_MPU_EXT_NIRQ (6 + IH2_BASE) --#define INT_850_SPI_100K_1 (7 + IH2_BASE) --#define INT_850_SYREN_SPI (8 + IH2_BASE) --#define INT_850_VLYNQ (9 + IH2_BASE) --#define INT_850_GPIO_BANK4 (10 + IH2_BASE) --#define INT_850_McBSP1TX (11 + IH2_BASE) --#define INT_850_McBSP1RX (12 + IH2_BASE) --#define INT_850_McBSP1RX_OF (13 + IH2_BASE) --#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE) --#define INT_850_UART_MODEM_1 (15 + IH2_BASE) --#define INT_850_MCSI (16 + IH2_BASE) --#define INT_850_uWireTX (17 + IH2_BASE) --#define INT_850_uWireRX (18 + IH2_BASE) --#define INT_850_SMC_CD (19 + IH2_BASE) --#define INT_850_SMC_IREQ (20 + IH2_BASE) --#define INT_850_HDQ_1WIRE (21 + IH2_BASE) --#define INT_850_TIMER32K (22 + IH2_BASE) --#define INT_850_MMC_SDIO (23 + IH2_BASE) --#define INT_850_UPLD (24 + IH2_BASE) --#define INT_850_USB_HHC_1 (27 + IH2_BASE) --#define INT_850_USB_HHC_2 (28 + IH2_BASE) --#define INT_850_USB_GENI (29 + IH2_BASE) --#define INT_850_USB_OTG (30 + IH2_BASE) --#define INT_850_CAMERA_IF (31 + IH2_BASE) --#define INT_850_RNG (32 + IH2_BASE) --#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE) --#define INT_850_DBB_RF_EN (34 + IH2_BASE) --#define INT_850_MPUIO_KEYPAD (35 + IH2_BASE) --#define INT_850_SHA1_MD5 (36 + IH2_BASE) --#define INT_850_SPI_100K_2 (37 + IH2_BASE) --#define INT_850_RNG_IDLE (38 + IH2_BASE) --#define INT_850_MPUIO (39 + IH2_BASE) --#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) --#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE) --#define INT_850_LLPC_OE_RISING (42 + IH2_BASE) --#define INT_850_LLPC_VSYNC (43 + IH2_BASE) --#define INT_850_WAKE_UP_REQ (46 + IH2_BASE) --#define INT_850_DMA_CH6 (53 + IH2_BASE) --#define INT_850_DMA_CH7 (54 + IH2_BASE) --#define INT_850_DMA_CH8 (55 + IH2_BASE) --#define INT_850_DMA_CH9 (56 + IH2_BASE) --#define INT_850_DMA_CH10 (57 + IH2_BASE) --#define INT_850_DMA_CH11 (58 + IH2_BASE) --#define INT_850_DMA_CH12 (59 + IH2_BASE) --#define INT_850_DMA_CH13 (60 + IH2_BASE) --#define INT_850_DMA_CH14 (61 + IH2_BASE) --#define INT_850_DMA_CH15 (62 + IH2_BASE) --#define INT_850_NAND (63 + IH2_BASE) -+#define INT_7XX_HW_ERRORS (0 + IH2_BASE) -+#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) -+#define INT_7XX_CFCD (2 + IH2_BASE) -+#define INT_7XX_CFIREQ (3 + IH2_BASE) -+#define INT_7XX_I2C (4 + IH2_BASE) -+#define INT_7XX_PCC (5 + IH2_BASE) -+#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) -+#define INT_7XX_SPI_100K_1 (7 + IH2_BASE) -+#define INT_7XX_SYREN_SPI (8 + IH2_BASE) -+#define INT_7XX_VLYNQ (9 + IH2_BASE) -+#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) -+#define INT_7XX_McBSP1TX (11 + IH2_BASE) -+#define INT_7XX_McBSP1RX (12 + IH2_BASE) -+#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) -+#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) -+#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) -+#define INT_7XX_MCSI (16 + IH2_BASE) -+#define INT_7XX_uWireTX (17 + IH2_BASE) -+#define INT_7XX_uWireRX (18 + IH2_BASE) -+#define INT_7XX_SMC_CD (19 + IH2_BASE) -+#define INT_7XX_SMC_IREQ (20 + IH2_BASE) -+#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) -+#define INT_7XX_TIMER32K (22 + IH2_BASE) -+#define INT_7XX_MMC_SDIO (23 + IH2_BASE) -+#define INT_7XX_UPLD (24 + IH2_BASE) -+#define INT_7XX_USB_HHC_1 (27 + IH2_BASE) -+#define INT_7XX_USB_HHC_2 (28 + IH2_BASE) -+#define INT_7XX_USB_GENI (29 + IH2_BASE) -+#define INT_7XX_USB_OTG (30 + IH2_BASE) -+#define INT_7XX_CAMERA_IF (31 + IH2_BASE) -+#define INT_7XX_RNG (32 + IH2_BASE) -+#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) -+#define INT_7XX_DBB_RF_EN (34 + IH2_BASE) -+#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) -+#define INT_7XX_SHA1_MD5 (36 + IH2_BASE) -+#define INT_7XX_SPI_100K_2 (37 + IH2_BASE) -+#define INT_7XX_RNG_IDLE (38 + IH2_BASE) -+#define INT_7XX_MPUIO (39 + IH2_BASE) -+#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) -+#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) -+#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) -+#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) -+#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) -+#define INT_7XX_DMA_CH6 (53 + IH2_BASE) -+#define INT_7XX_DMA_CH7 (54 + IH2_BASE) -+#define INT_7XX_DMA_CH8 (55 + IH2_BASE) -+#define INT_7XX_DMA_CH9 (56 + IH2_BASE) -+#define INT_7XX_DMA_CH10 (57 + IH2_BASE) -+#define INT_7XX_DMA_CH11 (58 + IH2_BASE) -+#define INT_7XX_DMA_CH12 (59 + IH2_BASE) -+#define INT_7XX_DMA_CH13 (60 + IH2_BASE) -+#define INT_7XX_DMA_CH14 (61 + IH2_BASE) -+#define INT_7XX_DMA_CH15 (62 + IH2_BASE) -+#define INT_7XX_NAND (63 + IH2_BASE) - - #define INT_24XX_SYS_NIRQ 7 - #define INT_24XX_SDMA_IRQ0 12 ---- a/arch/arm/plat-omap/include/mach/mcbsp.h -+++ b/arch/arm/plat-omap/include/mach/mcbsp.h -@@ -30,8 +30,8 @@ - #include <mach/hardware.h> - #include <mach/clock.h> - --#define OMAP730_MCBSP1_BASE 0xfffb1000 --#define OMAP730_MCBSP2_BASE 0xfffb1800 -+#define OMAP7XX_MCBSP1_BASE 0xfffb1000 -+#define OMAP7XX_MCBSP2_BASE 0xfffb1800 - - #define OMAP1510_MCBSP1_BASE 0xe1011800 - #define OMAP1510_MCBSP2_BASE 0xfffb1000 -@@ -58,7 +58,7 @@ - #define OMAP44XX_MCBSP3_BASE 0x49026000 - #define OMAP44XX_MCBSP4_BASE 0x48074000 - --#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) -+#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) - - #define OMAP_MCBSP_REG_DRR2 0x00 - #define OMAP_MCBSP_REG_DRR1 0x02 ---- a/arch/arm/plat-omap/include/mach/mux.h -+++ b/arch/arm/plat-omap/include/mach/mux.h -@@ -51,23 +51,13 @@ - .pu_pd_reg = PU_PD_SEL_##reg, \ - .pu_pd_val = status, - --#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \ -- .mux_reg = OMAP730_IO_CONF_##reg, \ -+#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \ -+ .mux_reg = OMAP7XX_IO_CONF_##reg, \ - .mask_offset = mode_offset, \ - .mask = mode, - --#define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \ -- .pull_reg = OMAP730_IO_CONF_##reg, \ -- .pull_bit = bit, \ -- .pull_val = status, -- --#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \ -- .mux_reg = OMAP850_IO_CONF_##reg, \ -- .mask_offset = mode_offset, \ -- .mask = mode, -- --#define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \ -- .pull_reg = OMAP850_IO_CONF_##reg, \ -+#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \ -+ .pull_reg = OMAP7XX_IO_CONF_##reg, \ - .pull_bit = bit, \ - .pull_val = status, - -@@ -84,21 +74,12 @@ - #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ - .pu_pd_val = status, - --#define MUX_REG_730(reg, mode_offset, mode) \ -- .mux_reg = OMAP730_IO_CONF_##reg, \ -+#define MUX_REG_7XX(reg, mode_offset, mode) \ -+ .mux_reg = OMAP7XX_IO_CONF_##reg, \ - .mask_offset = mode_offset, \ - .mask = mode, - --#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \ -- .pull_bit = bit, \ -- .pull_val = status, -- --#define MUX_REG_850(reg, mode_offset, mode) \ -- .mux_reg = OMAP850_IO_CONF_##reg, \ -- .mask_offset = mode_offset, \ -- .mask = mode, -- --#define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \ -+#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \ - .pull_bit = bit, \ - .pull_val = status, - -@@ -118,32 +99,21 @@ - - /* - * OMAP730/850 has a slightly different config for the pin mux. -- * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and -+ * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and - * not the FUNC_MUX_CTRL_x regs from hardware.h - * - for pull-up/down, only has one enable bit which is is in the same register - * as mux config - */ --#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \ -+#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \ - pull_bit, pull_status, debug_status)\ - { \ - .name = desc, \ - .debug = debug_status, \ -- MUX_REG_730(mux_reg, mode_offset, mode) \ -- PULL_REG_730(mux_reg, pull_bit, pull_status) \ -+ MUX_REG_7XX(mux_reg, mode_offset, mode) \ -+ PULL_REG_7XX(mux_reg, pull_bit, pull_status) \ - PU_PD_REG(NA, 0) \ - }, - --#define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \ -- pull_bit, pull_status, debug_status)\ --{ \ -- .name = desc, \ -- .debug = debug_status, \ -- MUX_REG_850(mux_reg, mode_offset, mode) \ -- PULL_REG_850(mux_reg, pull_bit, pull_status) \ -- PU_PD_REG(NA, 0) \ --}, -- -- - #define MUX_CFG_24XX(desc, reg_offset, mode, \ - pull_en, pull_mode, dbg) \ - { \ -@@ -232,45 +202,25 @@ struct pin_config { - - }; - --enum omap730_index { -+enum omap7xx_index { - /* OMAP 730 keyboard */ -- E2_730_KBR0, -- J7_730_KBR1, -- E1_730_KBR2, -- F3_730_KBR3, -- D2_730_KBR4, -- C2_730_KBC0, -- D3_730_KBC1, -- E4_730_KBC2, -- F4_730_KBC3, -- E3_730_KBC4, -- -- /* USB */ -- AA17_730_USB_DM, -- W16_730_USB_PU_EN, -- W17_730_USB_VBUSI, --}; -- --enum omap850_index { -- /* OMAP 850 keyboard */ -- E2_850_KBR0, -- J7_850_KBR1, -- E1_850_KBR2, -- F3_850_KBR3, -- D2_850_KBR4, -- C2_850_KBC0, -- D3_850_KBC1, -- E4_850_KBC2, -- F4_850_KBC3, -- E3_850_KBC4, -+ E2_7XX_KBR0, -+ J7_7XX_KBR1, -+ E1_7XX_KBR2, -+ F3_7XX_KBR3, -+ D2_7XX_KBR4, -+ C2_7XX_KBC0, -+ D3_7XX_KBC1, -+ E4_7XX_KBC2, -+ F4_7XX_KBC3, -+ E3_7XX_KBC4, - - /* USB */ -- AA17_850_USB_DM, -- W16_850_USB_PU_EN, -- W17_850_USB_VBUSI, -+ AA17_7XX_USB_DM, -+ W16_7XX_USB_PU_EN, -+ W17_7XX_USB_VBUSI, - }; - -- - enum omap1xxx_index { - /* UART1 (BT_UART_GATING)*/ - UART1_TX = 0, ---- a/arch/arm/plat-omap/include/mach/omap34xx.h -+++ b/arch/arm/plat-omap/include/mach/omap34xx.h -@@ -74,8 +74,12 @@ - - #define OMAP34XX_IVA_INTC_BASE 0x40000000 - #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) --#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000) - #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) -+#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000) -+#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400) -+#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800) -+#define OMAP34XX_SR1_BASE 0x480C9000 -+#define OMAP34XX_SR2_BASE 0x480CB000 - - #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) - ---- a/arch/arm/plat-omap/include/mach/omap44xx.h -+++ b/arch/arm/plat-omap/include/mach/omap44xx.h -@@ -22,6 +22,9 @@ - #define L4_PER_44XX_BASE 0x48000000 - #define L4_EMU_44XX_BASE 0x54000000 - #define L3_44XX_BASE 0x44000000 -+#define OMAP44XX_EMIF1_BASE 0x4c000000 -+#define OMAP44XX_EMIF2_BASE 0x4d000000 -+#define OMAP44XX_DMM_BASE 0x4e000000 - #define OMAP4430_32KSYNCT_BASE 0x4a304000 - #define OMAP4430_CM_BASE 0x4a004000 - #define OMAP4430_PRM_BASE 0x48306000 -@@ -33,14 +36,9 @@ - #define IRQ_SIR_IRQ 0x0040 - #define OMAP44XX_GIC_DIST_BASE 0x48241000 - #define OMAP44XX_GIC_CPU_BASE 0x48240100 --#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) - #define OMAP44XX_SCU_BASE 0x48240000 --#define OMAP44XX_VA_SCU_BASE OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE) - #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 --#define OMAP44XX_VA_LOCAL_TWD_BASE OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE) --#define OMAP44XX_LOCAL_TWD_SIZE 0x00000100 - #define OMAP44XX_WKUPGEN_BASE 0x48281000 --#define OMAP44XX_VA_WKUPGEN_BASE OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE) - - #endif /* __ASM_ARCH_OMAP44XX_H */ - ---- /dev/null -+++ b/arch/arm/plat-omap/include/mach/omap7xx.h -@@ -0,0 +1,104 @@ -+/* arch/arm/plat-omap/include/mach/omap7xx.h -+ * -+ * Hardware definitions for TI OMAP7XX processor. -+ * -+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> -+ * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net> -+ * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN -+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF -+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#ifndef __ASM_ARCH_OMAP7XX_H -+#define __ASM_ARCH_OMAP7XX_H -+ -+/* -+ * ---------------------------------------------------------------------------- -+ * Base addresses -+ * ---------------------------------------------------------------------------- -+ */ -+ -+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ -+ -+#define OMAP7XX_DSP_BASE 0xE0000000 -+#define OMAP7XX_DSP_SIZE 0x50000 -+#define OMAP7XX_DSP_START 0xE0000000 -+ -+#define OMAP7XX_DSPREG_BASE 0xE1000000 -+#define OMAP7XX_DSPREG_SIZE SZ_128K -+#define OMAP7XX_DSPREG_START 0xE1000000 -+ -+/* -+ * ---------------------------------------------------------------------------- -+ * OMAP7XX specific configuration registers -+ * ---------------------------------------------------------------------------- -+ */ -+#define OMAP7XX_CONFIG_BASE 0xfffe1000 -+#define OMAP7XX_IO_CONF_0 0xfffe1070 -+#define OMAP7XX_IO_CONF_1 0xfffe1074 -+#define OMAP7XX_IO_CONF_2 0xfffe1078 -+#define OMAP7XX_IO_CONF_3 0xfffe107c -+#define OMAP7XX_IO_CONF_4 0xfffe1080 -+#define OMAP7XX_IO_CONF_5 0xfffe1084 -+#define OMAP7XX_IO_CONF_6 0xfffe1088 -+#define OMAP7XX_IO_CONF_7 0xfffe108c -+#define OMAP7XX_IO_CONF_8 0xfffe1090 -+#define OMAP7XX_IO_CONF_9 0xfffe1094 -+#define OMAP7XX_IO_CONF_10 0xfffe1098 -+#define OMAP7XX_IO_CONF_11 0xfffe109c -+#define OMAP7XX_IO_CONF_12 0xfffe10a0 -+#define OMAP7XX_IO_CONF_13 0xfffe10a4 -+ -+#define OMAP7XX_MODE_1 0xfffe1010 -+#define OMAP7XX_MODE_2 0xfffe1014 -+ -+/* CSMI specials: in terms of base + offset */ -+#define OMAP7XX_MODE2_OFFSET 0x14 -+ -+/* -+ * ---------------------------------------------------------------------------- -+ * OMAP7XX traffic controller configuration registers -+ * ---------------------------------------------------------------------------- -+ */ -+#define OMAP7XX_FLASH_CFG_0 0xfffecc10 -+#define OMAP7XX_FLASH_ACFG_0 0xfffecc50 -+#define OMAP7XX_FLASH_CFG_1 0xfffecc14 -+#define OMAP7XX_FLASH_ACFG_1 0xfffecc54 -+ -+/* -+ * ---------------------------------------------------------------------------- -+ * OMAP7XX DSP control registers -+ * ---------------------------------------------------------------------------- -+ */ -+#define OMAP7XX_ICR_BASE 0xfffbb800 -+#define OMAP7XX_DSP_M_CTL 0xfffbb804 -+#define OMAP7XX_DSP_MMU_BASE 0xfffed200 -+ -+/* -+ * ---------------------------------------------------------------------------- -+ * OMAP7XX PCC_UPLD configuration registers -+ * ---------------------------------------------------------------------------- -+ */ -+#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900) -+#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00) -+ -+#endif /* __ASM_ARCH_OMAP7XX_H */ -+ ---- a/arch/arm/plat-omap/include/mach/sdrc.h -+++ b/arch/arm/plat-omap/include/mach/sdrc.h -@@ -80,11 +80,11 @@ - */ - - #define OMAP242X_SMS_REGADDR(reg) \ -- (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg) -+ (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg) - #define OMAP243X_SMS_REGADDR(reg) \ -- (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg) -+ (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg) - #define OMAP343X_SMS_REGADDR(reg) \ -- (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg) -+ (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg) - - /* SMS register offsets - read/write with sms_{read,write}_reg() */ - ---- a/arch/arm/plat-omap/include/mach/serial.h -+++ b/arch/arm/plat-omap/include/mach/serial.h -@@ -20,26 +20,22 @@ - #define OMAP_UART1_BASE 0xfffb0000 - #define OMAP_UART2_BASE 0xfffb0800 - #define OMAP_UART3_BASE 0xfffb9800 --#define OMAP_MAX_NR_PORTS 3 - #elif defined(CONFIG_ARCH_OMAP2) - /* OMAP2 serial ports */ - #define OMAP_UART1_BASE 0x4806a000 - #define OMAP_UART2_BASE 0x4806c000 - #define OMAP_UART3_BASE 0x4806e000 --#define OMAP_MAX_NR_PORTS 3 - #elif defined(CONFIG_ARCH_OMAP3) - /* OMAP3 serial ports */ - #define OMAP_UART1_BASE 0x4806a000 - #define OMAP_UART2_BASE 0x4806c000 - #define OMAP_UART3_BASE 0x49020000 --#define OMAP_MAX_NR_PORTS 3 - #elif defined(CONFIG_ARCH_OMAP4) - /* OMAP4 serial ports */ - #define OMAP_UART1_BASE 0x4806a000 - #define OMAP_UART2_BASE 0x4806c000 - #define OMAP_UART3_BASE 0x48020000 - #define OMAP_UART4_BASE 0x4806e000 --#define OMAP_MAX_NR_PORTS 4 - #endif - - #define OMAP1510_BASE_BAUD (12000000/16) ---- a/arch/arm/plat-omap/include/mach/uncompress.h -+++ b/arch/arm/plat-omap/include/mach/uncompress.h -@@ -25,6 +25,7 @@ unsigned int system_rev; - - #define UART_OMAP_MDR1 0x08 /* mode definition register */ - #define OMAP_ID_730 0x355F -+#define OMAP_ID_850 0x362C - #define ID_MASK 0x7fff - #define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) - #define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK -@@ -53,7 +54,7 @@ static void putc(int c) - /* MMU is not on, so cpu_is_omapXXXX() won't work here */ - unsigned int omap_id = omap_get_id(); - -- if (omap_id == OMAP_ID_730) -+ if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850) - shift = 0; - - if (check_port(uart, shift)) ---- a/arch/arm/plat-omap/include/mach/usb.h -+++ b/arch/arm/plat-omap/include/mach/usb.h -@@ -5,6 +5,21 @@ - - #include <mach/board.h> - -+#define OMAP3_HS_USB_PORTS 3 -+enum ehci_hcd_omap_mode { -+ EHCI_HCD_OMAP_MODE_UNKNOWN, -+ EHCI_HCD_OMAP_MODE_PHY, -+ EHCI_HCD_OMAP_MODE_TLL, -+}; -+ -+struct ehci_hcd_omap_platform_data { -+ enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS]; -+ unsigned phy_reset:1; -+ -+ /* have to be valid if phy_reset is true and portx is in phy mode */ -+ int reset_gpio_port[OMAP3_HS_USB_PORTS]; -+}; -+ - /*-------------------------------------------------------------------------*/ - - #define OMAP1_OTG_BASE 0xfffb0400 -@@ -29,6 +44,8 @@ - - extern void usb_musb_init(void); - -+extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata); -+ - #endif - - void omap_usb_init(struct omap_usb_config *pdata); ---- a/arch/arm/plat-omap/include/mach/vmalloc.h -+++ b/arch/arm/plat-omap/include/mach/vmalloc.h -@@ -17,5 +17,5 @@ - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ --#define VMALLOC_END (PAGE_OFFSET + 0x18000000) -+#define VMALLOC_END (PAGE_OFFSET + 0x38000000) - ---- a/arch/arm/plat-omap/io.c -+++ b/arch/arm/plat-omap/io.c -@@ -13,7 +13,7 @@ - #include <linux/io.h> - #include <linux/mm.h> - --#include <mach/omap730.h> -+#include <mach/omap7xx.h> - #include <mach/omap1510.h> - #include <mach/omap16xx.h> - #include <mach/omap24xx.h> -@@ -33,13 +33,13 @@ void __iomem *omap_ioremap(unsigned long - if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE)) - return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT); - } -- if (cpu_is_omap730()) { -- if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE)) -- return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START); -- -- if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE)) -- return XLATE(p, OMAP730_DSPREG_BASE, -- OMAP730_DSPREG_START); -+ if (cpu_is_omap7xx()) { -+ if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE)) -+ return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START); -+ -+ if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE)) -+ return XLATE(p, OMAP7XX_DSPREG_BASE, -+ OMAP7XX_DSPREG_START); - } - if (cpu_is_omap15xx()) { - if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE)) -@@ -114,6 +114,14 @@ void __iomem *omap_ioremap(unsigned long - return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT); - if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE)) - return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT); -+ if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE)) -+ return XLATE(p, OMAP44XX_EMIF1_PHYS, \ -+ OMAP44XX_EMIF1_VIRT); -+ if (BETWEEN(p, OMAP44XX_EMIF2_PHYS, OMAP44XX_EMIF2_SIZE)) -+ return XLATE(p, OMAP44XX_EMIF2_PHYS, \ -+ OMAP44XX_EMIF2_VIRT); -+ if (BETWEEN(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_SIZE)) -+ return XLATE(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_VIRT); - if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE)) - return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT); - if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE)) -@@ -142,7 +150,7 @@ u8 omap_readb(u32 pa) - if (cpu_class_is_omap1()) - return __raw_readb(OMAP1_IO_ADDRESS(pa)); - else -- return __raw_readb(OMAP2_IO_ADDRESS(pa)); -+ return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); - } - EXPORT_SYMBOL(omap_readb); - -@@ -151,7 +159,7 @@ u16 omap_readw(u32 pa) - if (cpu_class_is_omap1()) - return __raw_readw(OMAP1_IO_ADDRESS(pa)); - else -- return __raw_readw(OMAP2_IO_ADDRESS(pa)); -+ return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); - } - EXPORT_SYMBOL(omap_readw); - -@@ -160,7 +168,7 @@ u32 omap_readl(u32 pa) - if (cpu_class_is_omap1()) - return __raw_readl(OMAP1_IO_ADDRESS(pa)); - else -- return __raw_readl(OMAP2_IO_ADDRESS(pa)); -+ return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); - } - EXPORT_SYMBOL(omap_readl); - -@@ -169,7 +177,7 @@ void omap_writeb(u8 v, u32 pa) - if (cpu_class_is_omap1()) - __raw_writeb(v, OMAP1_IO_ADDRESS(pa)); - else -- __raw_writeb(v, OMAP2_IO_ADDRESS(pa)); -+ __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); - } - EXPORT_SYMBOL(omap_writeb); - -@@ -178,7 +186,7 @@ void omap_writew(u16 v, u32 pa) - if (cpu_class_is_omap1()) - __raw_writew(v, OMAP1_IO_ADDRESS(pa)); - else -- __raw_writew(v, OMAP2_IO_ADDRESS(pa)); -+ __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); - } - EXPORT_SYMBOL(omap_writew); - -@@ -187,6 +195,6 @@ void omap_writel(u32 v, u32 pa) - if (cpu_class_is_omap1()) - __raw_writel(v, OMAP1_IO_ADDRESS(pa)); - else -- __raw_writel(v, OMAP2_IO_ADDRESS(pa)); -+ __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); - } - EXPORT_SYMBOL(omap_writel); ---- a/arch/arm/plat-omap/omap_device.c -+++ b/arch/arm/plat-omap/omap_device.c -@@ -103,21 +103,6 @@ - /* Private functions */ - - /** -- * _read_32ksynct - read the OMAP 32K sync timer -- * -- * Returns the current value of the 32KiHz synchronization counter. -- * XXX this should be generalized to simply read the system clocksource. -- * XXX this should be moved to a separate synctimer32k.c file -- */ --static u32 _read_32ksynct(void) --{ -- if (!cpu_class_is_omap2()) -- BUG(); -- -- return __raw_readl(OMAP2_IO_ADDRESS(OMAP_32KSYNCT_BASE + 0x010)); --} -- --/** - * _omap_device_activate - increase device readiness - * @od: struct omap_device * - * @ignore_lat: increase to latency target (0) or full readiness (1)? -@@ -133,13 +118,13 @@ static u32 _read_32ksynct(void) - */ - static int _omap_device_activate(struct omap_device *od, u8 ignore_lat) - { -- u32 a, b; -+ struct timespec a, b, c; - - pr_debug("omap_device: %s: activating\n", od->pdev.name); - - while (od->pm_lat_level > 0) { - struct omap_device_pm_latency *odpl; -- int act_lat = 0; -+ unsigned long long act_lat = 0; - - od->pm_lat_level--; - -@@ -149,20 +134,22 @@ static int _omap_device_activate(struct - (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit)) - break; - -- a = _read_32ksynct(); -+ getnstimeofday(&a); - - /* XXX check return code */ - odpl->activate_func(od); - -- b = _read_32ksynct(); -+ getnstimeofday(&b); - -- act_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */ -+ c = timespec_sub(b, a); -+ act_lat = timespec_to_ns(&c) * NSEC_PER_USEC; - - pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time " -- "%d usec\n", od->pdev.name, od->pm_lat_level, act_lat); -+ "%llu usec\n", od->pdev.name, od->pm_lat_level, -+ act_lat); - - WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: " -- "activate step %d took longer than expected (%d > %d)\n", -+ "activate step %d took longer than expected (%llu > %d)\n", - od->pdev.name, od->pdev.id, od->pm_lat_level, - act_lat, odpl->activate_lat); - -@@ -188,13 +175,13 @@ static int _omap_device_activate(struct - */ - static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat) - { -- u32 a, b; -+ struct timespec a, b, c; - - pr_debug("omap_device: %s: deactivating\n", od->pdev.name); - - while (od->pm_lat_level < od->pm_lats_cnt) { - struct omap_device_pm_latency *odpl; -- int deact_lat = 0; -+ unsigned long long deact_lat = 0; - - odpl = od->pm_lats + od->pm_lat_level; - -@@ -203,23 +190,24 @@ static int _omap_device_deactivate(struc - od->_dev_wakeup_lat_limit)) - break; - -- a = _read_32ksynct(); -+ getnstimeofday(&a); - - /* XXX check return code */ - odpl->deactivate_func(od); - -- b = _read_32ksynct(); -+ getnstimeofday(&b); - -- deact_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */ -+ c = timespec_sub(b, a); -+ deact_lat = timespec_to_ns(&c) * NSEC_PER_USEC; - - pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time " -- "%d usec\n", od->pdev.name, od->pm_lat_level, -+ "%llu usec\n", od->pdev.name, od->pm_lat_level, - deact_lat); - - WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: " -- "deactivate step %d took longer than expected (%d > %d)\n", -- od->pdev.name, od->pdev.id, od->pm_lat_level, -- deact_lat, odpl->deactivate_lat); -+ "deactivate step %d took longer than expected " -+ "(%llu > %d)\n", od->pdev.name, od->pdev.id, -+ od->pm_lat_level, deact_lat, odpl->deactivate_lat); - - od->dev_wakeup_lat += odpl->activate_lat; - ---- a/arch/arm/plat-omap/sram.c -+++ b/arch/arm/plat-omap/sram.c -@@ -42,14 +42,14 @@ - #define OMAP1_SRAM_VA VMALLOC_END - #define OMAP2_SRAM_PA 0x40200000 - #define OMAP2_SRAM_PUB_PA 0x4020f800 --#define OMAP2_SRAM_VA 0xe3000000 -+#define OMAP2_SRAM_VA 0xfe400000 - #define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800) - #define OMAP3_SRAM_PA 0x40200000 --#define OMAP3_SRAM_VA 0xe3000000 -+#define OMAP3_SRAM_VA 0xfe400000 - #define OMAP3_SRAM_PUB_PA 0x40208000 - #define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000) - #define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/ --#define OMAP4_SRAM_VA 0xd7000000 /*0xd70f0000*/ -+#define OMAP4_SRAM_VA 0xfe400000 /*0xfe4f0000*/ - - #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) - #define SRAM_BOOTLOADER_SZ 0x00 -@@ -57,16 +57,16 @@ - #define SRAM_BOOTLOADER_SZ 0x80 - #endif - --#define OMAP24XX_VA_REQINFOPERM0 OMAP2_IO_ADDRESS(0x68005048) --#define OMAP24XX_VA_READPERM0 OMAP2_IO_ADDRESS(0x68005050) --#define OMAP24XX_VA_WRITEPERM0 OMAP2_IO_ADDRESS(0x68005058) -- --#define OMAP34XX_VA_REQINFOPERM0 OMAP2_IO_ADDRESS(0x68012848) --#define OMAP34XX_VA_READPERM0 OMAP2_IO_ADDRESS(0x68012850) --#define OMAP34XX_VA_WRITEPERM0 OMAP2_IO_ADDRESS(0x68012858) --#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_IO_ADDRESS(0x68012880) --#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_IO_ADDRESS(0x6C000048) --#define OMAP34XX_VA_CONTROL_STAT OMAP2_IO_ADDRESS(0x480022F0) -+#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048) -+#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050) -+#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058) -+ -+#define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848) -+#define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850) -+#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858) -+#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880) -+#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048) -+#define OMAP34XX_VA_CONTROL_STAT OMAP2_L4_IO_ADDRESS(0x480022F0) - - #define GP_DEVICE 0x300 - ---- a/arch/arm/plat-omap/usb.c -+++ b/arch/arm/plat-omap/usb.c -@@ -614,8 +614,8 @@ omap_otg_init(struct omap_usb_config *co - if (config->otg || config->register_host) { - syscon &= ~HST_IDLE_EN; - ohci_device.dev.platform_data = config; -- if (cpu_is_omap730()) -- ohci_resources[1].start = INT_730_USB_HHC_1; -+ if (cpu_is_omap7xx()) -+ ohci_resources[1].start = INT_7XX_USB_HHC_1; - status = platform_device_register(&ohci_device); - if (status) - pr_debug("can't register OHCI device, %d\n", status); -@@ -626,8 +626,8 @@ omap_otg_init(struct omap_usb_config *co - if (config->otg) { - syscon &= ~OTG_IDLE_EN; - otg_device.dev.platform_data = config; -- if (cpu_is_omap730()) -- otg_resources[1].start = INT_730_USB_OTG; -+ if (cpu_is_omap7xx()) -+ otg_resources[1].start = INT_7XX_USB_OTG; - status = platform_device_register(&otg_device); - if (status) - pr_debug("can't register OTG device, %d\n", status); -@@ -731,7 +731,7 @@ static inline void omap_1510_usb_init(st - - void __init omap_usb_init(struct omap_usb_config *pdata) - { -- if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx()) -+ if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) - omap_otg_init(pdata); - else if (cpu_is_omap15xx()) - omap_1510_usb_init(pdata); ---- a/drivers/Makefile -+++ b/drivers/Makefile -@@ -72,7 +72,7 @@ obj-$(CONFIG_GAMEPORT) += input/gamepor - obj-$(CONFIG_INPUT) += input/ - obj-$(CONFIG_I2O) += message/ - obj-$(CONFIG_RTC_LIB) += rtc/ --obj-y += i2c/ media/ -+obj-y += i2c/ media/ cbus/ - obj-$(CONFIG_PPS) += pps/ - obj-$(CONFIG_W1) += w1/ - obj-$(CONFIG_POWER_SUPPLY) += power/ ---- /dev/null -+++ b/drivers/cbus/Kconfig -@@ -0,0 +1,89 @@ -+# -+# CBUS device configuration -+# -+ -+menu "CBUS support" -+ -+config CBUS -+ depends on ARCH_OMAP -+ bool "CBUS support on OMAP" -+ ---help--- -+ CBUS is a proprietary serial protocol by Nokia. It is mainly -+ used for accessing Energy Management auxiliary chips. -+ -+ If you want CBUS support, you should say Y here. -+ -+config CBUS_TAHVO -+ depends on CBUS -+ bool "Support for Tahvo" -+ ---help--- -+ Tahvo is a mixed signal ASIC with some system features -+ -+ If you want Tahvo support, you should say Y here. -+ -+config CBUS_TAHVO_USER -+ depends on CBUS_TAHVO -+ bool "Support for Tahvo user space functions" -+ ---help--- -+ If you want support for Tahvo's user space read/write etc. functions, -+ you should say Y here. -+ -+config CBUS_TAHVO_USB -+ depends on CBUS_TAHVO && USB -+ tristate "Support for Tahvo USB transceiver" -+ ---help--- -+ If you want Tahvo support for USB transceiver, say Y or M here. -+ -+config CBUS_TAHVO_USB_HOST_BY_DEFAULT -+ depends on CBUS_TAHVO_USB && USB_OTG -+ boolean "Device in USB host mode by default" -+ ---help--- -+ Say Y here, if you want the device to enter USB host mode -+ by default on bootup. -+ -+config CBUS_RETU -+ depends on CBUS -+ bool "Support for Retu" -+ ---help--- -+ Retu is a mixed signal ASIC with some system features -+ -+ If you want Retu support, you should say Y here. -+ -+config CBUS_RETU_USER -+ depends on CBUS_RETU -+ bool "Support for Retu user space functions" -+ ---help--- -+ If you want support for Retu's user space read/write etc. functions, -+ you should say Y here. -+ -+config CBUS_RETU_POWERBUTTON -+ depends on CBUS_RETU -+ bool "Support for Retu power button" -+ ---help--- -+ The power button on Nokia 770 is connected to the Retu ASIC. -+ -+ If you want support for the Retu power button, you should say Y here. -+ -+config CBUS_RETU_RTC -+ depends on CBUS_RETU && SYSFS -+ tristate "Support for Retu pseudo-RTC" -+ ---help--- -+ Say Y here if you want support for the device that alleges to be an -+ RTC in Retu. This will expose a sysfs interface for it. -+ -+config CBUS_RETU_WDT -+ depends on CBUS_RETU && SYSFS -+ tristate "Support for Retu watchdog timer" -+ ---help--- -+ Say Y here if you want support for the watchdog in Retu. This will -+ expose a sysfs interface to grok it. -+ -+config CBUS_RETU_HEADSET -+ depends on CBUS_RETU && SYSFS -+ tristate "Support for headset detection with Retu/Vilma" -+ ---help--- -+ Say Y here if you want support detecting a headset that's connected -+ to Retu/Vilma. Detection state and events are exposed through -+ sysfs. -+ -+endmenu ---- /dev/null -+++ b/drivers/cbus/Makefile -@@ -0,0 +1,14 @@ -+# -+# Makefile for CBUS. -+# -+ -+obj-$(CONFIG_CBUS) += cbus.o -+obj-$(CONFIG_CBUS_TAHVO) += tahvo.o -+obj-$(CONFIG_CBUS_RETU) += retu.o -+obj-$(CONFIG_CBUS_TAHVO_USB) += tahvo-usb.o -+obj-$(CONFIG_CBUS_RETU_POWERBUTTON) += retu-pwrbutton.o -+obj-$(CONFIG_CBUS_RETU_RTC) += retu-rtc.o -+obj-$(CONFIG_CBUS_RETU_WDT) += retu-wdt.o -+obj-$(CONFIG_CBUS_TAHVO_USER) += tahvo-user.o -+obj-$(CONFIG_CBUS_RETU_USER) += retu-user.o -+obj-$(CONFIG_CBUS_RETU_HEADSET) += retu-headset.o ---- /dev/null -+++ b/drivers/cbus/cbus.c -@@ -0,0 +1,293 @@ -+/* -+ * drivers/cbus/cbus.c -+ * -+ * Support functions for CBUS serial protocol -+ * -+ * Copyright (C) 2004, 2005 Nokia Corporation -+ * -+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>, -+ * David Weinehall <david.weinehall@nokia.com>, and -+ * Mikko Ylinen <mikko.k.ylinen@nokia.com> -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/device.h> -+#include <linux/init.h> -+#include <linux/kernel.h> -+#include <linux/delay.h> -+#include <linux/spinlock.h> -+#include <linux/gpio.h> -+ -+#include <mach/board.h> -+#include <mach/board-nokia.h> -+ -+#include <asm/io.h> -+ -+#include "cbus.h" -+ -+struct cbus_host *cbus_host = NULL; -+ -+#ifdef CONFIG_ARCH_OMAP1 -+/* We use our own MPUIO functions to get closer to 1MHz bus speed */ -+ -+static inline void cbus_set_gpio_direction(u32 base, int mpuio, int is_input) -+{ -+ u16 w; -+ -+ mpuio &= 0x0f; -+ w = __raw_readw(base + OMAP_MPUIO_IO_CNTL); -+ if (is_input) -+ w |= 1 << mpuio; -+ else -+ w &= ~(1 << mpuio); -+ __raw_writew(w, base + OMAP_MPUIO_IO_CNTL); -+ -+} -+ -+static inline void cbus_set_gpio_dataout(u32 base, int mpuio, int enable) -+{ -+ u16 w; -+ -+ mpuio &= 0x0f; -+ w = __raw_readw(base + OMAP_MPUIO_OUTPUT); -+ if (enable) -+ w |= 1 << mpuio; -+ else -+ w &= ~(1 << mpuio); -+ __raw_writew(w, base + OMAP_MPUIO_OUTPUT); -+} -+ -+static inline int cbus_get_gpio_datain(u32 base, int mpuio) -+{ -+ mpuio &= 0x0f; -+ -+ return (__raw_readw(base + OMAP_MPUIO_INPUT_LATCH) & (1 << mpuio)) != 0; -+} -+ -+static void cbus_send_bit(struct cbus_host *host, u32 base, int bit, -+ int set_to_input) -+{ -+ cbus_set_gpio_dataout(base, host->dat_gpio, bit ? 1 : 0); -+ cbus_set_gpio_dataout(base, host->clk_gpio, 1); -+ -+ /* The data bit is read on the rising edge of CLK */ -+ if (set_to_input) -+ cbus_set_gpio_direction(base, host->dat_gpio, 1); -+ -+ cbus_set_gpio_dataout(base, host->clk_gpio, 0); -+} -+ -+static u8 cbus_receive_bit(struct cbus_host *host, u32 base) -+{ -+ u8 ret; -+ -+ cbus_set_gpio_dataout(base, host->clk_gpio, 1); -+ ret = cbus_get_gpio_datain(base, host->dat_gpio); -+ cbus_set_gpio_dataout(base, host->clk_gpio, 0); -+ -+ return ret; -+} -+ -+#define cbus_output(base, gpio, val) cbus_set_gpio_direction(base, gpio, 0) -+ -+#else -+ -+#define cbus_output(base, gpio, val) gpio_direction_output(gpio, val) -+#define cbus_set_gpio_dataout(base, gpio, enable) gpio_set_value(gpio, enable) -+#define cbus_get_gpio_datain(base, int, gpio) gpio_get_value(gpio) -+ -+static void _cbus_send_bit(struct cbus_host *host, int bit, int set_to_input) -+{ -+ gpio_set_value(host->dat_gpio, bit ? 1 : 0); -+ gpio_set_value(host->clk_gpio, 1); -+ -+ /* The data bit is read on the rising edge of CLK */ -+ if (set_to_input) -+ gpio_direction_input(host->dat_gpio); -+ -+ gpio_set_value(host->clk_gpio, 0); -+} -+ -+static u8 _cbus_receive_bit(struct cbus_host *host) -+{ -+ u8 ret; -+ -+ gpio_set_value(host->clk_gpio, 1); -+ ret = gpio_get_value(host->dat_gpio); -+ gpio_set_value(host->clk_gpio, 0); -+ -+ return ret; -+} -+ -+#define cbus_send_bit(host, base, bit, set_to_input) _cbus_send_bit(host, bit, set_to_input) -+#define cbus_receive_bit(host, base) _cbus_receive_bit(host) -+ -+#endif -+ -+static int cbus_transfer(struct cbus_host *host, int dev, int reg, int data) -+{ -+ int i; -+ int is_read = 0; -+ unsigned long flags; -+ u32 base; -+ -+#ifdef CONFIG_ARCH_OMAP1 -+ base = OMAP1_IO_ADDRESS(OMAP_MPUIO_BASE); -+#else -+ base = 0; -+#endif -+ -+ if (data < 0) -+ is_read = 1; -+ -+ /* We don't want interrupts disturbing our transfer */ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ /* Reset state and start of transfer, SEL stays down during transfer */ -+ cbus_set_gpio_dataout(base, host->sel_gpio, 0); -+ -+ /* Set the DAT pin to output */ -+ cbus_output(base, host->dat_gpio, 1); -+ -+ /* Send the device address */ -+ for (i = 3; i > 0; i--) -+ cbus_send_bit(host, base, dev & (1 << (i - 1)), 0); -+ -+ /* Send the rw flag */ -+ cbus_send_bit(host, base, is_read, 0); -+ -+ /* Send the register address */ -+ for (i = 5; i > 0; i--) { -+ int set_to_input = 0; -+ -+ if (is_read && i == 1) -+ set_to_input = 1; -+ -+ cbus_send_bit(host, base, reg & (1 << (i - 1)), set_to_input); -+ } -+ -+ if (!is_read) { -+ for (i = 16; i > 0; i--) -+ cbus_send_bit(host, base, data & (1 << (i - 1)), 0); -+ } else { -+ cbus_set_gpio_dataout(base, host->clk_gpio, 1); -+ data = 0; -+ -+ for (i = 16; i > 0; i--) { -+ u8 bit = cbus_receive_bit(host, base); -+ -+ if (bit) -+ data |= 1 << (i - 1); -+ } -+ } -+ -+ /* Indicate end of transfer, SEL goes up until next transfer */ -+ cbus_set_gpio_dataout(base, host->sel_gpio, 1); -+ cbus_set_gpio_dataout(base, host->clk_gpio, 1); -+ cbus_set_gpio_dataout(base, host->clk_gpio, 0); -+ -+ spin_unlock_irqrestore(&host->lock, flags); -+ -+ return is_read ? data : 0; -+} -+ -+/* -+ * Read a given register from the device -+ */ -+int cbus_read_reg(struct cbus_host *host, int dev, int reg) -+{ -+ return cbus_host ? cbus_transfer(host, dev, reg, -1) : -ENODEV; -+} -+ -+/* -+ * Write to a given register of the device -+ */ -+int cbus_write_reg(struct cbus_host *host, int dev, int reg, u16 val) -+{ -+ return cbus_host ? cbus_transfer(host, dev, reg, (int)val) : -ENODEV; -+} -+ -+int __init cbus_bus_init(void) -+{ -+ const struct omap_cbus_config * cbus_config; -+ struct cbus_host *chost; -+ int ret; -+ -+ chost = kmalloc(sizeof (*chost), GFP_KERNEL); -+ if (chost == NULL) -+ return -ENOMEM; -+ -+ memset(chost, 0, sizeof (*chost)); -+ -+ spin_lock_init(&chost->lock); -+ -+ cbus_config = omap_get_config(OMAP_TAG_CBUS, struct omap_cbus_config); -+ -+ if (cbus_config == NULL) { -+ printk(KERN_ERR "cbus: Unable to retrieve config data\n"); -+ return -ENODATA; -+ } -+ -+ chost->clk_gpio = cbus_config->clk_gpio; -+ chost->dat_gpio = cbus_config->dat_gpio; -+ chost->sel_gpio = cbus_config->sel_gpio; -+ -+#ifdef CONFIG_ARCH_OMAP1 -+ if (!OMAP_GPIO_IS_MPUIO(chost->clk_gpio) || -+ !OMAP_GPIO_IS_MPUIO(chost->dat_gpio) || -+ !OMAP_GPIO_IS_MPUIO(chost->sel_gpio)) { -+ printk(KERN_ERR "cbus: Only MPUIO pins supported\n"); -+ ret = -ENODEV; -+ goto exit1; -+ } -+#endif -+ -+ if ((ret = gpio_request(chost->clk_gpio, "CBUS clk")) < 0) -+ goto exit1; -+ -+ if ((ret = gpio_request(chost->dat_gpio, "CBUS data")) < 0) -+ goto exit2; -+ -+ if ((ret = gpio_request(chost->sel_gpio, "CBUS sel")) < 0) -+ goto exit3; -+ -+ gpio_direction_output(chost->clk_gpio, 0); -+ gpio_direction_input(chost->dat_gpio); -+ gpio_direction_output(chost->sel_gpio, 1); -+ -+ gpio_set_value(chost->clk_gpio, 1); -+ gpio_set_value(chost->clk_gpio, 0); -+ -+ cbus_host = chost; -+ -+ return 0; -+exit3: -+ gpio_free(chost->dat_gpio); -+exit2: -+ gpio_free(chost->clk_gpio); -+exit1: -+ kfree(chost); -+ return ret; -+} -+ -+subsys_initcall(cbus_bus_init); -+ -+EXPORT_SYMBOL(cbus_host); -+EXPORT_SYMBOL(cbus_read_reg); -+EXPORT_SYMBOL(cbus_write_reg); -+ -+MODULE_DESCRIPTION("CBUS serial protocol"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Juha Yrjölä, David Weinehall, and Mikko Ylinen"); ---- /dev/null -+++ b/drivers/cbus/cbus.h -@@ -0,0 +1,36 @@ -+/* -+ * drivers/cbus/cbus.h -+ * -+ * Copyright (C) 2004, 2005 Nokia Corporation -+ * -+ * Written by Juha Yrjölä <juha.yrjola@nokia.com> and -+ * David Weinehall <david.weinehall@nokia.com> -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __DRIVERS_CBUS_CBUS_H -+#define __DRIVERS_CBUS_CBUS_H -+ -+struct cbus_host { -+ int clk_gpio, dat_gpio, sel_gpio; -+ spinlock_t lock; -+}; -+ -+extern struct cbus_host *cbus_host; -+ -+extern int cbus_read_reg(struct cbus_host *host, int dev, int reg); -+extern int cbus_write_reg(struct cbus_host *host, int dev, int reg, u16 val); -+ -+#endif /* __DRIVERS_CBUS_CBUS_H */ ---- /dev/null -+++ b/drivers/cbus/retu-headset.c -@@ -0,0 +1,355 @@ -+/** -+ * Retu/Vilma headset detection -+ * -+ * Copyright (C) 2006 Nokia Corporation -+ * -+ * Written by Juha Yrjölä -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/module.h> -+#include <linux/init.h> -+#include <linux/kernel.h> -+#include <linux/delay.h> -+#include <linux/input.h> -+#include <linux/platform_device.h> -+ -+#include "retu.h" -+ -+#define RETU_ADC_CHANNEL_HOOKDET 0x05 -+ -+#define RETU_HEADSET_KEY KEY_PHONE -+ -+struct retu_headset { -+ spinlock_t lock; -+ struct mutex mutex; -+ struct platform_device *pdev; -+ struct input_dev *idev; -+ unsigned bias_enabled; -+ unsigned detection_enabled; -+ unsigned pressed; -+ struct timer_list enable_timer; -+ struct timer_list detect_timer; -+}; -+ -+static void retu_headset_set_bias(int enable) -+{ -+ if (enable) { -+ retu_set_clear_reg_bits(RETU_REG_AUDTXR, -+ (1 << 0) | (1 << 1), 0); -+ msleep(2); -+ retu_set_clear_reg_bits(RETU_REG_AUDTXR, 1 << 3, 0); -+ } else { -+ retu_set_clear_reg_bits(RETU_REG_AUDTXR, 0, -+ (1 << 0) | (1 << 1) | (1 << 3)); -+ } -+} -+ -+static void retu_headset_enable(struct retu_headset *hs) -+{ -+ mutex_lock(&hs->mutex); -+ if (!hs->bias_enabled) { -+ hs->bias_enabled = 1; -+ retu_headset_set_bias(1); -+ } -+ mutex_unlock(&hs->mutex); -+} -+ -+static void retu_headset_disable(struct retu_headset *hs) -+{ -+ mutex_lock(&hs->mutex); -+ if (hs->bias_enabled) { -+ hs->bias_enabled = 0; -+ retu_headset_set_bias(0); -+ } -+ mutex_unlock(&hs->mutex); -+} -+ -+static void retu_headset_det_enable(struct retu_headset *hs) -+{ -+ mutex_lock(&hs->mutex); -+ if (!hs->detection_enabled) { -+ hs->detection_enabled = 1; -+ retu_set_clear_reg_bits(RETU_REG_CC1, (1 << 10) | (1 << 8), 0); -+ retu_enable_irq(RETU_INT_HOOK); -+ } -+ mutex_unlock(&hs->mutex); -+} -+ -+static void retu_headset_det_disable(struct retu_headset *hs) -+{ -+ unsigned long flags; -+ -+ mutex_lock(&hs->mutex); -+ if (hs->detection_enabled) { -+ hs->detection_enabled = 0; -+ retu_disable_irq(RETU_INT_HOOK); -+ del_timer_sync(&hs->enable_timer); -+ del_timer_sync(&hs->detect_timer); -+ spin_lock_irqsave(&hs->lock, flags); -+ if (hs->pressed) -+ input_report_key(hs->idev, RETU_HEADSET_KEY, 0); -+ spin_unlock_irqrestore(&hs->lock, flags); -+ retu_set_clear_reg_bits(RETU_REG_CC1, 0, (1 << 10) | (1 << 8)); -+ } -+ mutex_unlock(&hs->mutex); -+} -+ -+static ssize_t retu_headset_hookdet_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ int val; -+ -+ val = retu_read_adc(RETU_ADC_CHANNEL_HOOKDET); -+ return sprintf(buf, "%d\n", val); -+} -+ -+static DEVICE_ATTR(hookdet, S_IRUGO, retu_headset_hookdet_show, NULL); -+ -+static ssize_t retu_headset_enable_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct retu_headset *hs = dev_get_drvdata(dev); -+ -+ return sprintf(buf, "%u\n", hs->bias_enabled); -+} -+ -+static ssize_t retu_headset_enable_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct retu_headset *hs = dev_get_drvdata(dev); -+ int enable; -+ -+ if (sscanf(buf, "%u", &enable) != 1) -+ return -EINVAL; -+ if (enable) -+ retu_headset_enable(hs); -+ else -+ retu_headset_disable(hs); -+ return count; -+} -+ -+static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR | S_IWGRP, -+ retu_headset_enable_show, retu_headset_enable_store); -+ -+static ssize_t retu_headset_enable_det_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct retu_headset *hs = dev_get_drvdata(dev); -+ -+ return sprintf(buf, "%u\n", hs->detection_enabled); -+} -+ -+static ssize_t retu_headset_enable_det_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct retu_headset *hs = dev_get_drvdata(dev); -+ int enable; -+ -+ if (sscanf(buf, "%u", &enable) != 1) -+ return -EINVAL; -+ if (enable) -+ retu_headset_det_enable(hs); -+ else -+ retu_headset_det_disable(hs); -+ return count; -+} -+ -+static DEVICE_ATTR(enable_det, S_IRUGO | S_IWUSR | S_IWGRP, -+ retu_headset_enable_det_show, -+ retu_headset_enable_det_store); -+ -+static void retu_headset_hook_interrupt(unsigned long arg) -+{ -+ struct retu_headset *hs = (struct retu_headset *) arg; -+ unsigned long flags; -+ -+ retu_ack_irq(RETU_INT_HOOK); -+ spin_lock_irqsave(&hs->lock, flags); -+ if (!hs->pressed) { -+ /* Headset button was just pressed down. */ -+ hs->pressed = 1; -+ input_report_key(hs->idev, RETU_HEADSET_KEY, 1); -+ } -+ spin_unlock_irqrestore(&hs->lock, flags); -+ retu_set_clear_reg_bits(RETU_REG_CC1, 0, (1 << 10) | (1 << 8)); -+ mod_timer(&hs->enable_timer, jiffies + msecs_to_jiffies(50)); -+} -+ -+static void retu_headset_enable_timer(unsigned long arg) -+{ -+ struct retu_headset *hs = (struct retu_headset *) arg; -+ -+ retu_set_clear_reg_bits(RETU_REG_CC1, (1 << 10) | (1 << 8), 0); -+ mod_timer(&hs->detect_timer, jiffies + msecs_to_jiffies(350)); -+} -+ -+static void retu_headset_detect_timer(unsigned long arg) -+{ -+ struct retu_headset *hs = (struct retu_headset *) arg; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&hs->lock, flags); -+ if (hs->pressed) { -+ hs->pressed = 0; -+ input_report_key(hs->idev, RETU_HEADSET_KEY, 0); -+ } -+ spin_unlock_irqrestore(&hs->lock, flags); -+} -+ -+static int __init retu_headset_probe(struct platform_device *pdev) -+{ -+ struct retu_headset *hs; -+ int r; -+ -+ hs = kzalloc(sizeof(*hs), GFP_KERNEL); -+ if (hs == NULL) -+ return -ENOMEM; -+ -+ hs->pdev = pdev; -+ -+ hs->idev = input_allocate_device(); -+ if (hs->idev == NULL) { -+ r = -ENOMEM; -+ goto err1; -+ } -+ hs->idev->name = "retu-headset"; -+ hs->idev->dev.parent = &pdev->dev; -+ set_bit(EV_KEY, hs->idev->evbit); -+ set_bit(RETU_HEADSET_KEY, hs->idev->keybit); -+ r = input_register_device(hs->idev); -+ if (r < 0) -+ goto err2; -+ -+ r = device_create_file(&pdev->dev, &dev_attr_hookdet); -+ if (r < 0) -+ goto err3; -+ r = device_create_file(&pdev->dev, &dev_attr_enable); -+ if (r < 0) -+ goto err4; -+ r = device_create_file(&pdev->dev, &dev_attr_enable_det); -+ if (r < 0) -+ goto err5; -+ platform_set_drvdata(pdev, hs); -+ -+ spin_lock_init(&hs->lock); -+ mutex_init(&hs->mutex); -+ setup_timer(&hs->enable_timer, retu_headset_enable_timer, -+ (unsigned long) hs); -+ setup_timer(&hs->detect_timer, retu_headset_detect_timer, -+ (unsigned long) hs); -+ -+ r = retu_request_irq(RETU_INT_HOOK, retu_headset_hook_interrupt, -+ (unsigned long) hs, "hookdet"); -+ if (r != 0) { -+ dev_err(&pdev->dev, "hookdet IRQ not available\n"); -+ goto err6; -+ } -+ retu_disable_irq(RETU_INT_HOOK); -+ return 0; -+err6: -+ device_remove_file(&pdev->dev, &dev_attr_enable_det); -+err5: -+ device_remove_file(&pdev->dev, &dev_attr_enable); -+err4: -+ device_remove_file(&pdev->dev, &dev_attr_hookdet); -+err3: -+ input_unregister_device(hs->idev); -+err2: -+ input_free_device(hs->idev); -+err1: -+ kfree(hs); -+ return r; -+} -+ -+static int retu_headset_remove(struct platform_device *pdev) -+{ -+ struct retu_headset *hs = platform_get_drvdata(pdev); -+ -+ device_remove_file(&pdev->dev, &dev_attr_hookdet); -+ device_remove_file(&pdev->dev, &dev_attr_enable); -+ device_remove_file(&pdev->dev, &dev_attr_enable_det); -+ retu_headset_disable(hs); -+ retu_headset_det_disable(hs); -+ retu_free_irq(RETU_INT_HOOK); -+ input_unregister_device(hs->idev); -+ input_free_device(hs->idev); -+ return 0; -+} -+ -+static int retu_headset_suspend(struct platform_device *pdev, -+ pm_message_t mesg) -+{ -+ struct retu_headset *hs = platform_get_drvdata(pdev); -+ -+ mutex_lock(&hs->mutex); -+ if (hs->bias_enabled) -+ retu_headset_set_bias(0); -+ mutex_unlock(&hs->mutex); -+ -+ return 0; -+} -+ -+static int retu_headset_resume(struct platform_device *pdev) -+{ -+ struct retu_headset *hs = platform_get_drvdata(pdev); -+ -+ mutex_lock(&hs->mutex); -+ if (hs->bias_enabled) -+ retu_headset_set_bias(1); -+ mutex_unlock(&hs->mutex); -+ -+ return 0; -+} -+ -+static struct platform_driver retu_headset_driver = { -+ .probe = retu_headset_probe, -+ .remove = retu_headset_remove, -+ .suspend = retu_headset_suspend, -+ .resume = retu_headset_resume, -+ .driver = { -+ .name = "retu-headset", -+ }, -+}; -+ -+static int __init retu_headset_init(void) -+{ -+ int r; -+ -+ printk(KERN_INFO "Retu/Vilma headset driver initializing\n"); -+ -+ r = platform_driver_register(&retu_headset_driver); -+ if (r < 0) -+ return r; -+ -+ return 0; -+} -+ -+static void __exit retu_headset_exit(void) -+{ -+ platform_driver_unregister(&retu_headset_driver); -+} -+ -+module_init(retu_headset_init); -+module_exit(retu_headset_exit); -+ -+MODULE_DESCRIPTION("Retu/Vilma headset detection"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Juha Yrjölä"); ---- /dev/null -+++ b/drivers/cbus/retu-pwrbutton.c -@@ -0,0 +1,118 @@ -+/** -+ * drivers/cbus/retu-pwrbutton.c -+ * -+ * Driver for sending retu power button event to input-layer -+ * -+ * Copyright (C) 2004 Nokia Corporation -+ * -+ * Written by Ari Saastamoinen <ari.saastamoinen@elektrobit.com> -+ * -+ * Contact Juha Yrjölä <juha.yrjola@nokia.com> -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/module.h> -+#include <linux/init.h> -+#include <linux/kernel.h> -+#include <linux/errno.h> -+#include <linux/input.h> -+#include <linux/timer.h> -+#include <linux/jiffies.h> -+#include <linux/bitops.h> -+ -+#include "retu.h" -+ -+#define RETU_STATUS_PWRONX (1 << 5) -+ -+#define PWRBTN_DELAY 20 -+#define PWRBTN_UP 0 -+#define PWRBTN_PRESSED 1 -+ -+static int pwrbtn_state; -+static struct input_dev *pwrbtn_dev; -+static struct timer_list pwrbtn_timer; -+ -+static void retubutton_timer_func(unsigned long arg) -+{ -+ int state; -+ -+ if (retu_read_reg(RETU_REG_STATUS) & RETU_STATUS_PWRONX) -+ state = PWRBTN_UP; -+ else -+ state = PWRBTN_PRESSED; -+ -+ if (pwrbtn_state != state) { -+ input_report_key(pwrbtn_dev, KEY_POWER, state); -+ pwrbtn_state = state; -+ } -+} -+ -+/** -+ * Interrupt function is called whenever power button key is pressed -+ * or released. -+ */ -+static void retubutton_irq(unsigned long arg) -+{ -+ retu_ack_irq(RETU_INT_PWR); -+ mod_timer(&pwrbtn_timer, jiffies + msecs_to_jiffies(PWRBTN_DELAY)); -+} -+ -+/** -+ * Init function. -+ * Allocates interrupt for power button and registers itself to input layer. -+ */ -+static int __init retubutton_init(void) -+{ -+ int irq; -+ -+ printk(KERN_INFO "Retu power button driver initialized\n"); -+ irq = RETU_INT_PWR; -+ -+ init_timer(&pwrbtn_timer); -+ pwrbtn_timer.function = retubutton_timer_func; -+ -+ if (retu_request_irq(irq, &retubutton_irq, 0, "PwrOnX") < 0) { -+ printk(KERN_ERR "%s@%s: Cannot allocate irq\n", -+ __FUNCTION__, __FILE__); -+ return -EBUSY; -+ } -+ -+ pwrbtn_dev = input_allocate_device(); -+ if (!pwrbtn_dev) -+ return -ENOMEM; -+ -+ pwrbtn_dev->evbit[0] = BIT_MASK(EV_KEY); -+ pwrbtn_dev->keybit[BIT_WORD(KEY_POWER)] = BIT_MASK(KEY_POWER); -+ pwrbtn_dev->name = "retu-pwrbutton"; -+ -+ return input_register_device(pwrbtn_dev); -+} -+ -+/** -+ * Cleanup function which is called when driver is unloaded -+ */ -+static void __exit retubutton_exit(void) -+{ -+ retu_free_irq(RETU_INT_PWR); -+ del_timer_sync(&pwrbtn_timer); -+ input_unregister_device(pwrbtn_dev); -+} -+ -+module_init(retubutton_init); -+module_exit(retubutton_exit); -+ -+MODULE_DESCRIPTION("Retu Power Button"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Ari Saastamoinen"); ---- /dev/null -+++ b/drivers/cbus/retu-rtc.c -@@ -0,0 +1,477 @@ -+/** -+ * drivers/cbus/retu-rtc.c -+ * -+ * Support for Retu RTC -+ * -+ * Copyright (C) 2004, 2005 Nokia Corporation -+ * -+ * Written by Paul Mundt <paul.mundt@nokia.com> and -+ * Igor Stoppa <igor.stoppa@nokia.com> -+ * -+ * The Retu RTC is essentially a partial read-only RTC that gives us Retu's -+ * idea of what time actually is. It's left as a userspace excercise to map -+ * this back to time in the real world and ensure that calibration settings -+ * are sane to compensate for any horrible drift (on account of not being able -+ * to set the clock to anything). -+ * -+ * Days are semi-writeable. Namely, Retu will only track 255 days for us -+ * consecutively, after which the counter is explicitly stuck at 255 until -+ * someone comes along and clears it with a write. In the event that no one -+ * comes along and clears it, we no longer have any idea what day it is. -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/device.h> -+#include <linux/init.h> -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/completion.h> -+#include <linux/platform_device.h> -+#include <linux/mutex.h> -+#include <linux/workqueue.h> -+ -+#include "cbus.h" -+#include "retu.h" -+ -+static struct mutex retu_rtc_mutex; -+static u16 retu_rtc_alarm_expired; -+static u16 retu_rtc_reset_occurred; -+ -+static DECLARE_COMPLETION(retu_rtc_exited); -+static DECLARE_COMPLETION(retu_rtc_sync); -+ -+static void retu_rtc_barrier(void); -+ -+static void retu_rtc_device_release(struct device *dev) -+{ -+ complete(&retu_rtc_exited); -+} -+ -+static ssize_t retu_rtc_time_show(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ u16 dsr, hmr, dsr2; -+ -+ mutex_lock(&retu_rtc_mutex); -+ -+ do { -+ u16 dummy; -+ -+ /* -+ * Not being in_interrupt() for a retu rtc IRQ, we need to -+ * read twice for consistency.. -+ */ -+ dummy = retu_read_reg(RETU_REG_RTCDSR); -+ dsr = retu_read_reg(RETU_REG_RTCDSR); -+ -+ dummy = retu_read_reg(RETU_REG_RTCHMR); -+ hmr = retu_read_reg(RETU_REG_RTCHMR); -+ -+ dummy = retu_read_reg(RETU_REG_RTCDSR); -+ dsr2 = retu_read_reg(RETU_REG_RTCDSR); -+ } while ((dsr != dsr2)); -+ -+ mutex_unlock(&retu_rtc_mutex); -+ -+ /* -+ * Format a 32-bit date-string for userspace -+ * -+ * days | hours | minutes | seconds -+ * -+ * 8 bits for each. -+ * -+ * This mostly sucks because days and seconds are tracked in RTCDSR -+ * while hours and minutes are tracked in RTCHMR. And yes, there -+ * really are no words that can describe an 8 bit day register (or -+ * rather, none that will be reprinted here). -+ */ -+ return sprintf(buf, "0x%08x\n", (((dsr >> 8) & 0xff) << 24) | -+ (((hmr >> 8) & 0x1f) << 16) | -+ ((hmr & 0x3f) << 8) | (dsr & 0x3f)); -+} -+ -+static ssize_t retu_rtc_time_store(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ mutex_lock(&retu_rtc_mutex); -+ /* -+ * Writing anything to the day counter forces it to 0 -+ * The seconds counter would be cleared by resetting the minutes counter, -+ * however this won't happen, since we are using the hh:mm counters as -+ * a set of free running counters and the day counter as a multiple -+ * overflow holder. -+ */ -+ -+ /* Reset day counter, but keep Temperature Shutdown state */ -+ retu_write_reg(RETU_REG_RTCDSR, -+ retu_read_reg(RETU_REG_RTCDSR) & (1 << 6)); -+ -+ mutex_unlock(&retu_rtc_mutex); -+ -+ return count; -+} -+ -+static DEVICE_ATTR(time, S_IRUGO | S_IWUSR, retu_rtc_time_show, -+ retu_rtc_time_store); -+ -+ -+static ssize_t retu_rtc_reset_show(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ /* -+ * Returns the status of the rtc -+ * -+ * 0: no reset has occurred or the status has been cleared -+ * 1: a reset has occurred -+ * -+ * RTC needs to be reset only when both main battery -+ * _AND_ backup battery are discharged -+ */ -+ return sprintf(buf, "%u\n", retu_rtc_reset_occurred); -+} -+ -+static void retu_rtc_do_reset(void) -+{ -+ u16 ccr1; -+ -+ ccr1 = retu_read_reg(RETU_REG_CC1); -+ /* RTC in reset */ -+ retu_write_reg(RETU_REG_CC1, ccr1 | 0x0001); -+ /* RTC in normal operating mode */ -+ retu_write_reg(RETU_REG_CC1, ccr1 & ~0x0001); -+ -+ retu_rtc_barrier(); -+ /* Disable alarm and RTC WD */ -+ retu_write_reg(RETU_REG_RTCHMAR, 0x7f3f); -+ /* Set Calibration register to default value */ -+ retu_write_reg(RETU_REG_RTCCALR, 0x00c0); -+ -+ retu_rtc_alarm_expired = 0; -+ retu_rtc_reset_occurred = 1; -+} -+ -+static ssize_t retu_rtc_reset_store(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ unsigned choice; -+ -+ if(sscanf(buf, "%u", &choice) != 1) -+ return count; -+ mutex_lock(&retu_rtc_mutex); -+ if (choice == 0) -+ retu_rtc_reset_occurred = 0; -+ else if (choice == 1) -+ retu_rtc_do_reset(); -+ mutex_unlock(&retu_rtc_mutex); -+ return count; -+} -+ -+static DEVICE_ATTR(reset, S_IRUGO | S_IWUSR, retu_rtc_reset_show, -+ retu_rtc_reset_store); -+ -+static ssize_t retu_rtc_alarm_show(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ u16 chmar; -+ ssize_t retval; -+ -+ mutex_lock(&retu_rtc_mutex); -+ /* -+ * Format a 16-bit date-string for userspace -+ * -+ * hours | minutes -+ * 8 bits for each. -+ */ -+ chmar = retu_read_reg(RETU_REG_RTCHMAR); -+ /* No shifting needed, only masking unrelated bits */ -+ retval = sprintf(buf, "0x%04x\n", chmar & 0x1f3f); -+ mutex_unlock(&retu_rtc_mutex); -+ -+ return retval; -+} -+ -+static ssize_t retu_rtc_alarm_store(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ u16 chmar; -+ unsigned alrm; -+ unsigned hours; -+ unsigned minutes; -+ -+ mutex_lock(&retu_rtc_mutex); -+ -+ if(sscanf(buf, "%x", &alrm) != 1) -+ return count; -+ hours = (alrm >> 8) & 0x001f; -+ minutes = (alrm >> 0) & 0x003f; -+ if ((hours < 24 && minutes < 60) || (hours == 24 && minutes == 60)) { -+ /* -+ * OK, the time format for the alarm is valid (including the -+ * disabling values) -+ */ -+ /* Keeps the RTC watchdog status */ -+ chmar = retu_read_reg(RETU_REG_RTCHMAR) & 0x6000; -+ chmar |= alrm & 0x1f3f; /* Stores the requested alarm */ -+ retu_rtc_barrier(); -+ retu_write_reg(RETU_REG_RTCHMAR, chmar); -+ /* If the alarm is being disabled */ -+ if (hours == 24 && minutes == 60) { -+ /* disable the interrupt */ -+ retu_disable_irq(RETU_INT_RTCA); -+ retu_rtc_alarm_expired = 0; -+ } else -+ /* enable the interrupt */ -+ retu_enable_irq(RETU_INT_RTCA); -+ } -+ mutex_unlock(&retu_rtc_mutex); -+ -+ return count; -+} -+ -+static DEVICE_ATTR(alarm, S_IRUGO | S_IWUSR, retu_rtc_alarm_show, -+ retu_rtc_alarm_store); -+ -+static ssize_t retu_rtc_alarm_expired_show(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ ssize_t retval; -+ -+ retval = sprintf(buf, "%u\n", retu_rtc_alarm_expired); -+ -+ return retval; -+} -+ -+static ssize_t retu_rtc_alarm_expired_store(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ retu_rtc_alarm_expired = 0; -+ -+ return count; -+} -+ -+static DEVICE_ATTR(alarm_expired, S_IRUGO | S_IWUSR, retu_rtc_alarm_expired_show, -+ retu_rtc_alarm_expired_store); -+ -+ -+static ssize_t retu_rtc_cal_show(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ u16 rtccalr1; -+ -+ mutex_lock(&retu_rtc_mutex); -+ rtccalr1 = retu_read_reg(RETU_REG_RTCCALR); -+ mutex_unlock(&retu_rtc_mutex); -+ -+ /* -+ * Shows the status of the Calibration Register. -+ * -+ * Default, after power loss: 0x0000 -+ * Default, for R&D: 0x00C0 -+ * Default, for factory: 0x00?? -+ * -+ */ -+ return sprintf(buf, "0x%04x\n", rtccalr1 & 0x00ff); -+} -+ -+static ssize_t retu_rtc_cal_store(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ unsigned calibration_value; -+ -+ if (sscanf(buf, "%x", &calibration_value) != 1) -+ return count; -+ -+ mutex_lock(&retu_rtc_mutex); -+ retu_rtc_barrier(); -+ retu_write_reg(RETU_REG_RTCCALR, calibration_value & 0x00ff); -+ mutex_unlock(&retu_rtc_mutex); -+ -+ return count; -+} -+ -+static DEVICE_ATTR(cal, S_IRUGO | S_IWUSR, retu_rtc_cal_show, -+ retu_rtc_cal_store); -+ -+static struct platform_device retu_rtc_device; -+ -+static void retu_rtca_disable(void) -+{ -+ retu_disable_irq(RETU_INT_RTCA); -+ retu_rtc_alarm_expired = 1; -+ retu_rtc_barrier(); -+ retu_write_reg(RETU_REG_RTCHMAR, (24 << 8) | 60); -+} -+ -+static void retu_rtca_expired(struct work_struct *unused) -+{ -+ retu_rtca_disable(); -+ sysfs_notify(&retu_rtc_device.dev.kobj, NULL, "alarm_expired"); -+} -+ -+DECLARE_WORK(retu_rtca_work, retu_rtca_expired); -+ -+/* -+ * RTCHMR RTCHMAR RTCCAL must be accessed within 0.9 s since the seconds -+ * interrupt has been signaled in the IDR register -+ */ -+static void retu_rtcs_interrupt(unsigned long unused) -+{ -+ retu_ack_irq(RETU_INT_RTCS); -+ complete_all(&retu_rtc_sync); -+} -+ -+static void retu_rtca_interrupt(unsigned long unused) -+{ -+ retu_ack_irq(RETU_INT_RTCA); -+ schedule_work(&retu_rtca_work); -+} -+ -+static int retu_rtc_init_irq(void) -+{ -+ int ret; -+ -+ ret = retu_request_irq(RETU_INT_RTCS, retu_rtcs_interrupt, 0, "RTCS"); -+ if (ret != 0) -+ return ret; -+ /* -+ * We will take care of enabling and disabling the interrupt -+ * elsewhere, so leave it off by default.. -+ */ -+ retu_disable_irq(RETU_INT_RTCS); -+ -+ ret = retu_request_irq(RETU_INT_RTCA, retu_rtca_interrupt, 0, "RTCA"); -+ if (ret != 0) { -+ retu_free_irq(RETU_INT_RTCS); -+ return ret; -+ } -+ retu_disable_irq(RETU_INT_RTCA); -+ -+ return 0; -+} -+ -+ -+static int __devinit retu_rtc_probe(struct device *dev) -+{ -+ int r; -+ -+ retu_rtc_alarm_expired = retu_read_reg(RETU_REG_IDR) & -+ (0x1 << RETU_INT_RTCA); -+ -+ if ((r = retu_rtc_init_irq()) != 0) -+ return r; -+ -+ mutex_init(&retu_rtc_mutex); -+ -+ /* If the calibration register is zero, we've probably lost -+ * power */ -+ if (retu_read_reg(RETU_REG_RTCCALR) & 0x00ff) -+ retu_rtc_reset_occurred = 0; -+ else -+ retu_rtc_do_reset(); -+ -+ if ((r = device_create_file(dev, &dev_attr_time)) != 0) -+ return r; -+ else if ((r = device_create_file(dev, &dev_attr_reset)) != 0) -+ goto err_unregister_time; -+ else if ((r = device_create_file(dev, &dev_attr_alarm)) != 0) -+ goto err_unregister_reset; -+ else if ((r = device_create_file(dev, &dev_attr_alarm_expired)) != 0) -+ goto err_unregister_alarm; -+ else if ((r = device_create_file(dev, &dev_attr_cal)) != 0) -+ goto err_unregister_alarm_expired; -+ else -+ return r; -+ -+err_unregister_alarm_expired: -+ device_remove_file(dev, &dev_attr_alarm_expired); -+err_unregister_alarm: -+ device_remove_file(dev, &dev_attr_alarm); -+err_unregister_reset: -+ device_remove_file(dev, &dev_attr_reset); -+err_unregister_time: -+ device_remove_file(dev, &dev_attr_time); -+ return r; -+} -+ -+static int __devexit retu_rtc_remove(struct device *dev) -+{ -+ retu_disable_irq(RETU_INT_RTCS); -+ retu_free_irq(RETU_INT_RTCS); -+ retu_free_irq(RETU_INT_RTCA); -+ device_remove_file(dev, &dev_attr_cal); -+ device_remove_file(dev, &dev_attr_alarm_expired); -+ device_remove_file(dev, &dev_attr_alarm); -+ device_remove_file(dev, &dev_attr_reset); -+ device_remove_file(dev, &dev_attr_time); -+ return 0; -+} -+ -+static struct device_driver retu_rtc_driver = { -+ .name = "retu-rtc", -+ .bus = &platform_bus_type, -+ .probe = retu_rtc_probe, -+ .remove = __devexit_p(retu_rtc_remove), -+}; -+ -+static struct platform_device retu_rtc_device = { -+ .name = "retu-rtc", -+ .id = -1, -+ .dev = { -+ .release = retu_rtc_device_release, -+ }, -+}; -+ -+/* This function provides syncronization with the RTCS interrupt handler */ -+static void retu_rtc_barrier(void) -+{ -+ INIT_COMPLETION(retu_rtc_sync); -+ retu_ack_irq(RETU_INT_RTCS); -+ retu_enable_irq(RETU_INT_RTCS); -+ wait_for_completion(&retu_rtc_sync); -+ retu_disable_irq(RETU_INT_RTCS); -+} -+ -+static int __init retu_rtc_init(void) -+{ -+ int ret; -+ -+ init_completion(&retu_rtc_exited); -+ -+ if ((ret = driver_register(&retu_rtc_driver)) != 0) -+ return ret; -+ -+ if ((ret = platform_device_register(&retu_rtc_device)) != 0) -+ goto err_unregister_driver; -+ -+ return 0; -+ -+err_unregister_driver: -+ driver_unregister(&retu_rtc_driver); -+ return ret; -+} -+ -+static void __exit retu_rtc_exit(void) -+{ -+ platform_device_unregister(&retu_rtc_device); -+ driver_unregister(&retu_rtc_driver); -+ -+ wait_for_completion(&retu_rtc_exited); -+} -+ -+module_init(retu_rtc_init); -+module_exit(retu_rtc_exit); -+ -+MODULE_DESCRIPTION("Retu RTC"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Paul Mundt and Igor Stoppa"); ---- /dev/null -+++ b/drivers/cbus/retu-user.c -@@ -0,0 +1,423 @@ -+/** -+ * drivers/cbus/retu-user.c -+ * -+ * Retu user space interface functions -+ * -+ * Copyright (C) 2004, 2005 Nokia Corporation -+ * -+ * Written by Mikko Ylinen <mikko.k.ylinen@nokia.com> -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/types.h> -+#include <linux/kernel.h> -+#include <linux/interrupt.h> -+#include <linux/module.h> -+#include <linux/init.h> -+#include <linux/fs.h> -+#include <linux/miscdevice.h> -+#include <linux/poll.h> -+#include <linux/list.h> -+#include <linux/spinlock.h> -+#include <linux/mutex.h> -+ -+#include <asm/uaccess.h> -+ -+#include "retu.h" -+ -+#include "user_retu_tahvo.h" -+ -+/* Maximum size of IRQ node buffer/pool */ -+#define RETU_MAX_IRQ_BUF_LEN 16 -+ -+#define PFX "retu-user: " -+ -+/* Bitmap for marking the interrupt sources as having the handlers */ -+static u32 retu_irq_bits; -+ -+/* For allowing only one user process to subscribe to the retu interrupts */ -+static struct file *retu_irq_subscr = NULL; -+ -+/* For poll and IRQ passing */ -+struct retu_irq { -+ u32 id; -+ struct list_head node; -+}; -+ -+static spinlock_t retu_irqs_lock; -+static struct retu_irq *retu_irq_block; -+static LIST_HEAD(retu_irqs); -+static LIST_HEAD(retu_irqs_reserve); -+ -+/* Wait queue - used when user wants to read the device */ -+DECLARE_WAIT_QUEUE_HEAD(retu_user_waitqueue); -+ -+/* Semaphore to protect irq subscription sequence */ -+static struct mutex retu_mutex; -+ -+/* This array specifies RETU register types (read/write/toggle) */ -+static const u8 retu_access_bits[] = { -+ 1, -+ 4, -+ 3, -+ 3, -+ 1, -+ 3, -+ 3, -+ 0, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 4, -+ 4, -+ 3, -+ 0, -+ 0, -+ 0, -+ 0, -+ 1, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3 -+}; -+ -+/* -+ * The handler for all RETU interrupts. -+ * -+ * arg is the interrupt source in RETU. -+ */ -+static void retu_user_irq_handler(unsigned long arg) -+{ -+ struct retu_irq *irq; -+ -+ retu_ack_irq(arg); -+ -+ spin_lock(&retu_irqs_lock); -+ if (list_empty(&retu_irqs_reserve)) { -+ spin_unlock(&retu_irqs_lock); -+ return; -+ } -+ irq = list_entry((&retu_irqs_reserve)->next, struct retu_irq, node); -+ irq->id = arg; -+ list_move_tail(&irq->node, &retu_irqs); -+ spin_unlock(&retu_irqs_lock); -+ -+ /* wake up waiting thread */ -+ wake_up(&retu_user_waitqueue); -+} -+ -+/* -+ * This routine sets up the interrupt handler and marks an interrupt source -+ * in RETU as a candidate for signal delivery to the user process. -+ */ -+static int retu_user_subscribe_to_irq(int id, struct file *filp) -+{ -+ int ret; -+ -+ mutex_lock(&retu_mutex); -+ if ((retu_irq_subscr != NULL) && (retu_irq_subscr != filp)) { -+ mutex_unlock(&retu_mutex); -+ return -EBUSY; -+ } -+ /* Store the file pointer of the first user process registering IRQs */ -+ retu_irq_subscr = filp; -+ mutex_unlock(&retu_mutex); -+ -+ if (retu_irq_bits & (1 << id)) -+ return 0; -+ -+ ret = retu_request_irq(id, retu_user_irq_handler, id, ""); -+ if (ret < 0) -+ return ret; -+ -+ /* Mark that this interrupt has a handler */ -+ retu_irq_bits |= 1 << id; -+ -+ return 0; -+} -+ -+/* -+ * Unregisters all RETU interrupt handlers. -+ */ -+static void retu_unreg_irq_handlers(void) -+{ -+ int id; -+ -+ if (!retu_irq_bits) -+ return; -+ -+ for (id = 0; id < MAX_RETU_IRQ_HANDLERS; id++) -+ if (retu_irq_bits & (1 << id)) -+ retu_free_irq(id); -+ -+ retu_irq_bits = 0; -+} -+ -+/* -+ * Write to RETU register. -+ * Returns 0 upon success, a negative error value otherwise. -+ */ -+static int retu_user_write_with_mask(u32 field, u16 value) -+{ -+ u32 mask; -+ u32 reg; -+ u_short tmp; -+ unsigned long flags; -+ -+ mask = MASK(field); -+ reg = REG(field); -+ -+ /* Detect bad mask and reg */ -+ if (mask == 0 || reg > RETU_REG_MAX || -+ retu_access_bits[reg] == READ_ONLY) { -+ printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n", -+ reg, mask); -+ return -EINVAL; -+ } -+ -+ /* Justify value according to mask */ -+ while (!(mask & 1)) { -+ value = value << 1; -+ mask = mask >> 1; -+ } -+ -+ spin_lock_irqsave(&retu_lock, flags); -+ if (retu_access_bits[reg] == TOGGLE) { -+ /* No need to detect previous content of register */ -+ tmp = 0; -+ } else { -+ /* Read current value of register */ -+ tmp = retu_read_reg(reg); -+ } -+ -+ /* Generate new value */ -+ tmp = (tmp & ~MASK(field)) | (value & MASK(field)); -+ /* Write data to RETU */ -+ retu_write_reg(reg, tmp); -+ spin_unlock_irqrestore(&retu_lock, flags); -+ -+ return 0; -+} -+ -+/* -+ * Read RETU register. -+ */ -+static u32 retu_user_read_with_mask(u32 field) -+{ -+ u_short value; -+ u32 mask, reg; -+ -+ mask = MASK(field); -+ reg = REG(field); -+ -+ /* Detect bad mask and reg */ -+ if (mask == 0 || reg > RETU_REG_MAX) { -+ printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n", -+ reg, mask); -+ return -EINVAL; -+ } -+ -+ /* Read the register */ -+ value = retu_read_reg(reg) & mask; -+ -+ /* Right justify value */ -+ while (!(mask & 1)) { -+ value = value >> 1; -+ mask = mask >> 1; -+ } -+ -+ return value; -+} -+ -+/* -+ * Close device -+ */ -+static int retu_close(struct inode *inode, struct file *filp) -+{ -+ /* Unregister all interrupts that have been registered */ -+ if (retu_irq_subscr == filp) { -+ retu_unreg_irq_handlers(); -+ retu_irq_subscr = NULL; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Device control (ioctl) -+ */ -+static int retu_ioctl(struct inode *inode, struct file *filp, -+ unsigned int cmd, unsigned long arg) -+{ -+ struct retu_tahvo_write_parms par; -+ int ret; -+ -+ switch (cmd) { -+ case URT_IOCT_IRQ_SUBSCR: -+ return retu_user_subscribe_to_irq(arg, filp); -+ case RETU_IOCH_READ: -+ return retu_user_read_with_mask(arg); -+ case RETU_IOCX_WRITE: -+ ret = copy_from_user(&par, (void __user *) arg, sizeof(par)); -+ if (ret) -+ printk(KERN_ERR "copy_from_user failed: %d\n", ret); -+ par.result = retu_user_write_with_mask(par.field, par.value); -+ ret = copy_to_user((void __user *) arg, &par, sizeof(par)); -+ if (ret) -+ printk(KERN_ERR "copy_to_user failed: %d\n", ret); -+ break; -+ case RETU_IOCH_ADC_READ: -+ return retu_read_adc(arg); -+ default: -+ return -ENOIOCTLCMD; -+ } -+ return 0; -+} -+ -+/* -+ * Read from device -+ */ -+static ssize_t retu_read(struct file *filp, char *buf, size_t count, -+ loff_t * offp) -+{ -+ struct retu_irq *irq; -+ -+ u32 nr, i; -+ -+ /* read not permitted if neither filp nor anyone has registered IRQs */ -+ if (retu_irq_subscr != filp) -+ return -EPERM; -+ -+ if ((count < sizeof(u32)) || ((count % sizeof(u32)) != 0)) -+ return -EINVAL; -+ -+ nr = count / sizeof(u32); -+ -+ for (i = 0; i < nr; i++) { -+ unsigned long flags; -+ u32 irq_id; -+ int ret; -+ -+ ret = wait_event_interruptible(retu_user_waitqueue, -+ !list_empty(&retu_irqs)); -+ if (ret < 0) -+ return ret; -+ -+ spin_lock_irqsave(&retu_irqs_lock, flags); -+ irq = list_entry((&retu_irqs)->next, struct retu_irq, node); -+ irq_id = irq->id; -+ list_move(&irq->node, &retu_irqs_reserve); -+ spin_unlock_irqrestore(&retu_irqs_lock, flags); -+ -+ ret = copy_to_user(buf + i * sizeof(irq_id), &irq_id, -+ sizeof(irq_id)); -+ if (ret) -+ printk(KERN_ERR "copy_to_user failed: %d\n", ret); -+ } -+ -+ return count; -+} -+ -+/* -+ * Poll method -+ */ -+static unsigned retu_poll(struct file *filp, struct poll_table_struct *pt) -+{ -+ if (!list_empty(&retu_irqs)) -+ return POLLIN; -+ -+ poll_wait(filp, &retu_user_waitqueue, pt); -+ -+ if (!list_empty(&retu_irqs)) -+ return POLLIN; -+ else -+ return 0; -+} -+ -+static struct file_operations retu_user_fileops = { -+ .owner = THIS_MODULE, -+ .ioctl = retu_ioctl, -+ .read = retu_read, -+ .release = retu_close, -+ .poll = retu_poll -+}; -+ -+static struct miscdevice retu_device = { -+ .minor = MISC_DYNAMIC_MINOR, -+ .name = "retu", -+ .fops = &retu_user_fileops -+}; -+ -+/* -+ * Initialization -+ * -+ * @return 0 if successful, error value otherwise. -+ */ -+int retu_user_init(void) -+{ -+ struct retu_irq *irq; -+ int res, i; -+ -+ irq = kmalloc(sizeof(*irq) * RETU_MAX_IRQ_BUF_LEN, GFP_KERNEL); -+ if (irq == NULL) { -+ printk(KERN_ERR PFX "kmalloc failed\n"); -+ return -ENOMEM; -+ } -+ memset(irq, 0, sizeof(*irq) * RETU_MAX_IRQ_BUF_LEN); -+ for (i = 0; i < RETU_MAX_IRQ_BUF_LEN; i++) -+ list_add(&irq[i].node, &retu_irqs_reserve); -+ -+ retu_irq_block = irq; -+ -+ spin_lock_init(&retu_irqs_lock); -+ mutex_init(&retu_mutex); -+ -+ /* Request a misc device */ -+ res = misc_register(&retu_device); -+ if (res < 0) { -+ printk(KERN_ERR PFX "unable to register misc device for %s\n", -+ retu_device.name); -+ kfree(irq); -+ return res; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Cleanup. -+ */ -+void retu_user_cleanup(void) -+{ -+ /* Unregister our misc device */ -+ misc_deregister(&retu_device); -+ /* Unregister and disable all RETU interrupts used by this module */ -+ retu_unreg_irq_handlers(); -+ kfree(retu_irq_block); -+} -+ -+MODULE_DESCRIPTION("Retu ASIC user space functions"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Mikko Ylinen"); ---- /dev/null -+++ b/drivers/cbus/retu-wdt.c -@@ -0,0 +1,202 @@ -+/** -+ * drivers/cbus/retu-wdt.c -+ * -+ * Driver for Retu watchdog -+ * -+ * Copyright (C) 2004, 2005 Nokia Corporation -+ * -+ * Written by Amit Kucheria <amit.kucheria@nokia.com> -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/device.h> -+#include <linux/init.h> -+ -+#include <linux/completion.h> -+#include <linux/errno.h> -+#include <linux/moduleparam.h> -+#include <linux/platform_device.h> -+ -+#include "cbus.h" -+#include "retu.h" -+ -+/* Watchdog timeout in seconds */ -+#define RETU_WDT_MIN_TIMER 0 -+#define RETU_WDT_DEFAULT_TIMER 32 -+#define RETU_WDT_MAX_TIMER 63 -+ -+static struct completion retu_wdt_completion; -+static DEFINE_MUTEX(retu_wdt_mutex); -+ -+/* Current period of watchdog */ -+static unsigned int period_val = RETU_WDT_DEFAULT_TIMER; -+static int counter_param = RETU_WDT_MAX_TIMER; -+ -+static int retu_modify_counter(unsigned int new) -+{ -+ int ret = 0; -+ -+ if (new < RETU_WDT_MIN_TIMER || new > RETU_WDT_MAX_TIMER) -+ return -EINVAL; -+ -+ mutex_lock(&retu_wdt_mutex); -+ -+ period_val = new; -+ retu_write_reg(RETU_REG_WATCHDOG, (u16)period_val); -+ -+ mutex_unlock(&retu_wdt_mutex); -+ return ret; -+} -+ -+static ssize_t retu_wdt_period_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ /* Show current max counter */ -+ return sprintf(buf, "%u\n", (u16)period_val); -+} -+ -+static ssize_t retu_wdt_period_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ unsigned int new_period; -+ int ret; -+ -+ if (sscanf(buf, "%u", &new_period) != 1) { -+ printk(KERN_ALERT "retu_wdt_period_store: Invalid input\n"); -+ return -EINVAL; -+ } -+ -+ ret = retu_modify_counter(new_period); -+ if (ret < 0) -+ return ret; -+ -+ return strnlen(buf, count); -+} -+ -+static ssize_t retu_wdt_counter_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ u16 counter; -+ -+ /* Show current value in watchdog counter */ -+ counter = retu_read_reg(RETU_REG_WATCHDOG); -+ -+ /* Only the 5 LSB are important */ -+ return snprintf(buf, PAGE_SIZE, "%u\n", (counter & 0x3F)); -+} -+ -+static DEVICE_ATTR(period, S_IRUGO | S_IWUSR, retu_wdt_period_show, \ -+ retu_wdt_period_store); -+static DEVICE_ATTR(counter, S_IRUGO, retu_wdt_counter_show, NULL); -+ -+static int __devinit retu_wdt_probe(struct device *dev) -+{ -+ int ret; -+ -+ ret = device_create_file(dev, &dev_attr_period); -+ if (ret) { -+ printk(KERN_ERR "retu_wdt_probe: Error creating " -+ "sys device file: period\n"); -+ return ret; -+ } -+ -+ ret = device_create_file(dev, &dev_attr_counter); -+ if (ret) { -+ device_remove_file(dev, &dev_attr_period); -+ printk(KERN_ERR "retu_wdt_probe: Error creating " -+ "sys device file: counter\n"); -+ } -+ -+ return ret; -+} -+ -+static int __devexit retu_wdt_remove(struct device *dev) -+{ -+ device_remove_file(dev, &dev_attr_period); -+ device_remove_file(dev, &dev_attr_counter); -+ return 0; -+} -+ -+static void retu_wdt_device_release(struct device *dev) -+{ -+ complete(&retu_wdt_completion); -+} -+ -+static struct platform_device retu_wdt_device = { -+ .name = "retu-watchdog", -+ .id = -1, -+ .dev = { -+ .release = retu_wdt_device_release, -+ }, -+}; -+ -+static struct device_driver retu_wdt_driver = { -+ .name = "retu-watchdog", -+ .bus = &platform_bus_type, -+ .probe = retu_wdt_probe, -+ .remove = __devexit_p(retu_wdt_remove), -+}; -+ -+static int __init retu_wdt_init(void) -+{ -+ int ret; -+ -+ init_completion(&retu_wdt_completion); -+ -+ ret = driver_register(&retu_wdt_driver); -+ if (ret) -+ return ret; -+ -+ ret = platform_device_register(&retu_wdt_device); -+ if (ret) -+ goto exit1; -+ -+ /* passed as module parameter? */ -+ ret = retu_modify_counter(counter_param); -+ if (ret == -EINVAL) { -+ ret = retu_modify_counter(RETU_WDT_DEFAULT_TIMER); -+ printk(KERN_INFO -+ "retu_wdt_init: Intializing to default value\n"); -+ } -+ -+ printk(KERN_INFO "Retu watchdog driver initialized\n"); -+ return ret; -+ -+exit1: -+ driver_unregister(&retu_wdt_driver); -+ wait_for_completion(&retu_wdt_completion); -+ -+ return ret; -+} -+ -+static void __exit retu_wdt_exit(void) -+{ -+ platform_device_unregister(&retu_wdt_device); -+ driver_unregister(&retu_wdt_driver); -+ -+ wait_for_completion(&retu_wdt_completion); -+} -+ -+module_init(retu_wdt_init); -+module_exit(retu_wdt_exit); -+module_param(counter_param, int, 0); -+ -+MODULE_DESCRIPTION("Retu WatchDog"); -+MODULE_AUTHOR("Amit Kucheria"); -+MODULE_LICENSE("GPL"); -+ ---- /dev/null -+++ b/drivers/cbus/retu.c -@@ -0,0 +1,467 @@ -+/** -+ * drivers/cbus/retu.c -+ * -+ * Support functions for Retu ASIC -+ * -+ * Copyright (C) 2004, 2005 Nokia Corporation -+ * -+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>, -+ * David Weinehall <david.weinehall@nokia.com>, and -+ * Mikko Ylinen <mikko.k.ylinen@nokia.com> -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/module.h> -+#include <linux/init.h> -+ -+#include <linux/kernel.h> -+#include <linux/errno.h> -+#include <linux/device.h> -+#include <linux/miscdevice.h> -+#include <linux/poll.h> -+#include <linux/fs.h> -+#include <linux/irq.h> -+#include <linux/interrupt.h> -+#include <linux/platform_device.h> -+#include <linux/gpio.h> -+ -+#include <asm/uaccess.h> -+ -+#include <mach/mux.h> -+#include <mach/board.h> -+#include <mach/board-nokia.h> -+ -+#include "cbus.h" -+#include "retu.h" -+ -+#define RETU_ID 0x01 -+#define PFX "retu: " -+ -+static int retu_initialized; -+static int retu_irq_pin; -+static int retu_is_vilma; -+ -+static struct tasklet_struct retu_tasklet; -+spinlock_t retu_lock = SPIN_LOCK_UNLOCKED; -+ -+static struct completion device_release; -+ -+struct retu_irq_handler_desc { -+ int (*func)(unsigned long); -+ unsigned long arg; -+ char name[8]; -+}; -+ -+static struct retu_irq_handler_desc retu_irq_handlers[MAX_RETU_IRQ_HANDLERS]; -+ -+/** -+ * retu_read_reg - Read a value from a register in Retu -+ * @reg: the register to read from -+ * -+ * This function returns the contents of the specified register -+ */ -+int retu_read_reg(int reg) -+{ -+ BUG_ON(!retu_initialized); -+ return cbus_read_reg(cbus_host, RETU_ID, reg); -+} -+ -+/** -+ * retu_write_reg - Write a value to a register in Retu -+ * @reg: the register to write to -+ * @reg: the value to write to the register -+ * -+ * This function writes a value to the specified register -+ */ -+void retu_write_reg(int reg, u16 val) -+{ -+ BUG_ON(!retu_initialized); -+ cbus_write_reg(cbus_host, RETU_ID, reg, val); -+} -+ -+void retu_set_clear_reg_bits(int reg, u16 set, u16 clear) -+{ -+ unsigned long flags; -+ u16 w; -+ -+ spin_lock_irqsave(&retu_lock, flags); -+ w = retu_read_reg(reg); -+ w &= ~clear; -+ w |= set; -+ retu_write_reg(reg, w); -+ spin_unlock_irqrestore(&retu_lock, flags); -+} -+ -+#define ADC_MAX_CHAN_NUMBER 13 -+ -+int retu_read_adc(int channel) -+{ -+ unsigned long flags; -+ int res; -+ -+ if (channel < 0 || channel > ADC_MAX_CHAN_NUMBER) -+ return -EINVAL; -+ -+ spin_lock_irqsave(&retu_lock, flags); -+ -+ if ((channel == 8) && retu_is_vilma) { -+ int scr = retu_read_reg(RETU_REG_ADCSCR); -+ int ch = (retu_read_reg(RETU_REG_ADCR) >> 10) & 0xf; -+ if (((scr & 0xff) != 0) && (ch != 8)) -+ retu_write_reg (RETU_REG_ADCSCR, (scr & ~0xff)); -+ } -+ -+ /* Select the channel and read result */ -+ retu_write_reg(RETU_REG_ADCR, channel << 10); -+ res = retu_read_reg(RETU_REG_ADCR) & 0x3ff; -+ -+ if (retu_is_vilma) -+ retu_write_reg(RETU_REG_ADCR, (1 << 13)); -+ -+ /* Unlock retu */ -+ spin_unlock_irqrestore(&retu_lock, flags); -+ -+ return res; -+} -+ -+ -+static u16 retu_disable_bogus_irqs(u16 mask) -+{ -+ int i; -+ -+ for (i = 0; i < MAX_RETU_IRQ_HANDLERS; i++) { -+ if (mask & (1 << i)) -+ continue; -+ if (retu_irq_handlers[i].func != NULL) -+ continue; -+ /* an IRQ was enabled but we don't have a handler for it */ -+ printk(KERN_INFO PFX "disabling bogus IRQ %d\n", i); -+ mask |= (1 << i); -+ } -+ return mask; -+} -+ -+/* -+ * Disable given RETU interrupt -+ */ -+void retu_disable_irq(int id) -+{ -+ unsigned long flags; -+ u16 mask; -+ -+ spin_lock_irqsave(&retu_lock, flags); -+ mask = retu_read_reg(RETU_REG_IMR); -+ mask |= 1 << id; -+ mask = retu_disable_bogus_irqs(mask); -+ retu_write_reg(RETU_REG_IMR, mask); -+ spin_unlock_irqrestore(&retu_lock, flags); -+} -+ -+/* -+ * Enable given RETU interrupt -+ */ -+void retu_enable_irq(int id) -+{ -+ unsigned long flags; -+ u16 mask; -+ -+ if (id == 3) { -+ printk("Enabling Retu IRQ %d\n", id); -+ dump_stack(); -+ } -+ spin_lock_irqsave(&retu_lock, flags); -+ mask = retu_read_reg(RETU_REG_IMR); -+ mask &= ~(1 << id); -+ mask = retu_disable_bogus_irqs(mask); -+ retu_write_reg(RETU_REG_IMR, mask); -+ spin_unlock_irqrestore(&retu_lock, flags); -+} -+ -+/* -+ * Acknowledge given RETU interrupt -+ */ -+void retu_ack_irq(int id) -+{ -+ retu_write_reg(RETU_REG_IDR, 1 << id); -+} -+ -+/* -+ * RETU interrupt handler. Only schedules the tasklet. -+ */ -+static irqreturn_t retu_irq_handler(int irq, void *dev_id) -+{ -+ tasklet_schedule(&retu_tasklet); -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Tasklet handler -+ */ -+static void retu_tasklet_handler(unsigned long data) -+{ -+ struct retu_irq_handler_desc *hnd; -+ u16 id; -+ u16 im; -+ int i; -+ -+ for (;;) { -+ id = retu_read_reg(RETU_REG_IDR); -+ im = ~retu_read_reg(RETU_REG_IMR); -+ id &= im; -+ -+ if (!id) -+ break; -+ -+ for (i = 0; id != 0; i++, id >>= 1) { -+ if (!(id & 1)) -+ continue; -+ hnd = &retu_irq_handlers[i]; -+ if (hnd->func == NULL) { -+ /* Spurious retu interrupt - disable and ack it */ -+ printk(KERN_INFO "Spurious Retu interrupt " -+ "(id %d)\n", i); -+ retu_disable_irq(i); -+ retu_ack_irq(i); -+ continue; -+ } -+ hnd->func(hnd->arg); -+ /* -+ * Don't acknowledge the interrupt here -+ * It must be done explicitly -+ */ -+ } -+ } -+} -+ -+/* -+ * Register the handler for a given RETU interrupt source. -+ */ -+int retu_request_irq(int id, void *irq_handler, unsigned long arg, char *name) -+{ -+ struct retu_irq_handler_desc *hnd; -+ -+ if (irq_handler == NULL || id >= MAX_RETU_IRQ_HANDLERS || -+ name == NULL) { -+ printk(KERN_ERR PFX "Invalid arguments to %s\n", -+ __FUNCTION__); -+ return -EINVAL; -+ } -+ hnd = &retu_irq_handlers[id]; -+ if (hnd->func != NULL) { -+ printk(KERN_ERR PFX "IRQ %d already reserved\n", id); -+ return -EBUSY; -+ } -+ printk(KERN_INFO PFX "Registering interrupt %d for device %s\n", -+ id, name); -+ hnd->func = irq_handler; -+ hnd->arg = arg; -+ strlcpy(hnd->name, name, sizeof(hnd->name)); -+ -+ retu_ack_irq(id); -+ retu_enable_irq(id); -+ -+ return 0; -+} -+ -+/* -+ * Unregister the handler for a given RETU interrupt source. -+ */ -+void retu_free_irq(int id) -+{ -+ struct retu_irq_handler_desc *hnd; -+ -+ if (id >= MAX_RETU_IRQ_HANDLERS) { -+ printk(KERN_ERR PFX "Invalid argument to %s\n", -+ __FUNCTION__); -+ return; -+ } -+ hnd = &retu_irq_handlers[id]; -+ if (hnd->func == NULL) { -+ printk(KERN_ERR PFX "IRQ %d already freed\n", id); -+ return; -+ } -+ -+ retu_disable_irq(id); -+ hnd->func = NULL; -+} -+ -+/** -+ * retu_power_off - Shut down power to system -+ * -+ * This function puts the system in power off state -+ */ -+static void retu_power_off(void) -+{ -+ /* Ignore power button state */ -+ retu_write_reg(RETU_REG_CC1, retu_read_reg(RETU_REG_CC1) | 2); -+ /* Expire watchdog immediately */ -+ retu_write_reg(RETU_REG_WATCHDOG, 0); -+ /* Wait for poweroff*/ -+ for (;;); -+} -+ -+/** -+ * retu_probe - Probe for Retu ASIC -+ * @dev: the Retu device -+ * -+ * Probe for the Retu ASIC and allocate memory -+ * for its device-struct if found -+ */ -+static int __devinit retu_probe(struct device *dev) -+{ -+ const struct omap_em_asic_bb5_config * em_asic_config; -+ int rev, ret; -+ -+ /* Prepare tasklet */ -+ tasklet_init(&retu_tasklet, retu_tasklet_handler, 0); -+ -+ em_asic_config = omap_get_config(OMAP_TAG_EM_ASIC_BB5, -+ struct omap_em_asic_bb5_config); -+ if (em_asic_config == NULL) { -+ printk(KERN_ERR PFX "Unable to retrieve config data\n"); -+ return -ENODATA; -+ } -+ -+ retu_irq_pin = em_asic_config->retu_irq_gpio; -+ -+ if ((ret = gpio_request(retu_irq_pin, "RETU irq")) < 0) { -+ printk(KERN_ERR PFX "Unable to reserve IRQ GPIO\n"); -+ return ret; -+ } -+ -+ /* Set the pin as input */ -+ gpio_direction_input(retu_irq_pin); -+ -+ /* Rising edge triggers the IRQ */ -+ set_irq_type(gpio_to_irq(retu_irq_pin), IRQ_TYPE_EDGE_RISING); -+ -+ retu_initialized = 1; -+ -+ rev = retu_read_reg(RETU_REG_ASICR) & 0xff; -+ if (rev & (1 << 7)) -+ retu_is_vilma = 1; -+ -+ printk(KERN_INFO "%s v%d.%d found\n", retu_is_vilma ? "Vilma" : "Retu", -+ (rev >> 4) & 0x07, rev & 0x0f); -+ -+ /* Mask all RETU interrupts */ -+ retu_write_reg(RETU_REG_IMR, 0xffff); -+ -+ ret = request_irq(gpio_to_irq(retu_irq_pin), retu_irq_handler, 0, -+ "retu", 0); -+ if (ret < 0) { -+ printk(KERN_ERR PFX "Unable to register IRQ handler\n"); -+ gpio_free(retu_irq_pin); -+ return ret; -+ } -+ set_irq_wake(gpio_to_irq(retu_irq_pin), 1); -+ -+ /* Register power off function */ -+ pm_power_off = retu_power_off; -+ -+#ifdef CONFIG_CBUS_RETU_USER -+ /* Initialize user-space interface */ -+ if (retu_user_init() < 0) { -+ printk(KERN_ERR "Unable to initialize driver\n"); -+ free_irq(gpio_to_irq(retu_irq_pin), 0); -+ gpio_free(retu_irq_pin); -+ return ret; -+ } -+#endif -+ -+ return 0; -+} -+ -+static int retu_remove(struct device *dev) -+{ -+#ifdef CONFIG_CBUS_RETU_USER -+ retu_user_cleanup(); -+#endif -+ /* Mask all RETU interrupts */ -+ retu_write_reg(RETU_REG_IMR, 0xffff); -+ free_irq(gpio_to_irq(retu_irq_pin), 0); -+ gpio_free(retu_irq_pin); -+ tasklet_kill(&retu_tasklet); -+ -+ return 0; -+} -+ -+static void retu_device_release(struct device *dev) -+{ -+ complete(&device_release); -+} -+ -+static struct device_driver retu_driver = { -+ .name = "retu", -+ .bus = &platform_bus_type, -+ .probe = retu_probe, -+ .remove = retu_remove, -+}; -+ -+static struct platform_device retu_device = { -+ .name = "retu", -+ .id = -1, -+ .dev = { -+ .release = retu_device_release, -+ } -+}; -+ -+/** -+ * retu_init - initialise Retu driver -+ * -+ * Initialise the Retu driver and return 0 if everything worked ok -+ */ -+static int __init retu_init(void) -+{ -+ int ret = 0; -+ -+ printk(KERN_INFO "Retu/Vilma driver initialising\n"); -+ -+ init_completion(&device_release); -+ -+ if ((ret = driver_register(&retu_driver)) < 0) -+ return ret; -+ -+ if ((ret = platform_device_register(&retu_device)) < 0) { -+ driver_unregister(&retu_driver); -+ return ret; -+ } -+ return 0; -+} -+ -+/* -+ * Cleanup -+ */ -+static void __exit retu_exit(void) -+{ -+ platform_device_unregister(&retu_device); -+ driver_unregister(&retu_driver); -+ wait_for_completion(&device_release); -+} -+ -+EXPORT_SYMBOL(retu_request_irq); -+EXPORT_SYMBOL(retu_free_irq); -+EXPORT_SYMBOL(retu_enable_irq); -+EXPORT_SYMBOL(retu_disable_irq); -+EXPORT_SYMBOL(retu_ack_irq); -+EXPORT_SYMBOL(retu_read_reg); -+EXPORT_SYMBOL(retu_write_reg); -+ -+subsys_initcall(retu_init); -+module_exit(retu_exit); -+ -+MODULE_DESCRIPTION("Retu ASIC control"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Juha Yrjölä, David Weinehall, and Mikko Ylinen"); ---- /dev/null -+++ b/drivers/cbus/retu.h -@@ -0,0 +1,77 @@ -+/** -+ * drivers/cbus/retu.h -+ * -+ * Copyright (C) 2004, 2005 Nokia Corporation -+ * -+ * Written by Juha Yrjölä <juha.yrjola@nokia.com> and -+ * David Weinehall <david.weinehall@nokia.com> -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __DRIVERS_CBUS_RETU_H -+#define __DRIVERS_CBUS_RETU_H -+ -+#include <linux/types.h> -+ -+/* Registers */ -+#define RETU_REG_ASICR 0x00 /* ASIC ID & revision */ -+#define RETU_REG_IDR 0x01 /* Interrupt ID */ -+#define RETU_REG_IMR 0x02 /* Interrupt mask */ -+#define RETU_REG_RTCDSR 0x03 /* RTC seconds register */ -+#define RETU_REG_RTCHMR 0x04 /* RTC hours and minutes register */ -+#define RETU_REG_RTCHMAR 0x05 /* RTC hours and minutes alarm and time set register */ -+#define RETU_REG_RTCCALR 0x06 /* RTC calibration register */ -+#define RETU_REG_ADCR 0x08 /* ADC result */ -+#define RETU_REG_ADCSCR 0x09 /* ADC sample ctrl */ -+#define RETU_REG_CC1 0x0d /* Common control register 1 */ -+#define RETU_REG_CC2 0x0e /* Common control register 2 */ -+#define RETU_REG_CTRL_CLR 0x0f /* Regulator clear register */ -+#define RETU_REG_CTRL_SET 0x10 /* Regulator set register */ -+#define RETU_REG_STATUS 0x16 /* Status register */ -+#define RETU_REG_WATCHDOG 0x17 /* Watchdog register */ -+#define RETU_REG_AUDTXR 0x18 /* Audio Codec Tx register */ -+#define RETU_REG_MAX 0x1f -+ -+/* Interrupt sources */ -+#define RETU_INT_PWR 0 -+#define RETU_INT_CHAR 1 -+#define RETU_INT_RTCS 2 -+#define RETU_INT_RTCM 3 -+#define RETU_INT_RTCD 4 -+#define RETU_INT_RTCA 5 -+#define RETU_INT_HOOK 6 -+#define RETU_INT_HEAD 7 -+#define RETU_INT_ADCS 8 -+ -+#define MAX_RETU_IRQ_HANDLERS 16 -+ -+int retu_read_reg(int reg); -+void retu_write_reg(int reg, u16 val); -+void retu_set_clear_reg_bits(int reg, u16 set, u16 clear); -+int retu_read_adc(int channel); -+int retu_request_irq(int id, void *irq_handler, unsigned long arg, char *name); -+void retu_free_irq(int id); -+void retu_enable_irq(int id); -+void retu_disable_irq(int id); -+void retu_ack_irq(int id); -+ -+#ifdef CONFIG_CBUS_RETU_USER -+int retu_user_init(void); -+void retu_user_cleanup(void); -+#endif -+ -+extern spinlock_t retu_lock; -+ -+#endif /* __DRIVERS_CBUS_RETU_H */ ---- /dev/null -+++ b/drivers/cbus/tahvo-usb.c -@@ -0,0 +1,777 @@ -+/** -+ * drivers/cbus/tahvo-usb.c -+ * -+ * Tahvo USB transeiver -+ * -+ * Copyright (C) 2005-2006 Nokia Corporation -+ * -+ * Parts copied from drivers/i2c/chips/isp1301_omap.c -+ * Copyright (C) 2004 Texas Instruments -+ * Copyright (C) 2004 David Brownell -+ * -+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>, -+ * Tony Lindgren <tony@atomide.com>, and -+ * Timo Teräs <timo.teras@nokia.com> -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/module.h> -+#include <linux/init.h> -+#include <linux/slab.h> -+#include <linux/io.h> -+#include <linux/interrupt.h> -+#include <linux/platform_device.h> -+#include <linux/usb/ch9.h> -+#include <linux/usb/gadget.h> -+#include <linux/usb.h> -+#include <linux/usb/otg.h> -+#include <linux/i2c.h> -+#include <linux/workqueue.h> -+#include <linux/kobject.h> -+#include <linux/clk.h> -+#include <linux/mutex.h> -+ -+#include <asm/irq.h> -+#include <mach/usb.h> -+ -+#include "cbus.h" -+#include "tahvo.h" -+ -+#define DRIVER_NAME "tahvo-usb" -+ -+#define USBR_SLAVE_CONTROL (1 << 8) -+#define USBR_VPPVIO_SW (1 << 7) -+#define USBR_SPEED (1 << 6) -+#define USBR_REGOUT (1 << 5) -+#define USBR_MASTER_SW2 (1 << 4) -+#define USBR_MASTER_SW1 (1 << 3) -+#define USBR_SLAVE_SW (1 << 2) -+#define USBR_NSUSPEND (1 << 1) -+#define USBR_SEMODE (1 << 0) -+ -+/* bits in OTG_CTRL */ -+ -+/* Bits that are controlled by OMAP OTG and are read-only */ -+#define OTG_CTRL_OMAP_MASK (OTG_PULLDOWN|OTG_PULLUP|OTG_DRV_VBUS|\ -+ OTG_PD_VBUS|OTG_PU_VBUS|OTG_PU_ID) -+/* Bits that are controlled by transceiver */ -+#define OTG_CTRL_XCVR_MASK (OTG_ASESSVLD|OTG_BSESSEND|\ -+ OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID) -+/* Bits that are controlled by system */ -+#define OTG_CTRL_SYS_MASK (OTG_A_BUSREQ|OTG_A_SETB_HNPEN|OTG_B_BUSREQ|\ -+ OTG_B_HNPEN|OTG_BUSDROP) -+ -+#if defined(CONFIG_USB_OHCI_HCD) && !defined(CONFIG_USB_OTG) -+#error tahvo-otg.c does not work with OCHI yet! -+#endif -+ -+#define TAHVO_MODE_HOST 0 -+#define TAHVO_MODE_PERIPHERAL 1 -+ -+#ifdef CONFIG_USB_OTG -+#define TAHVO_MODE(tu) (tu)->tahvo_mode -+#elif defined(CONFIG_USB_GADGET_OMAP) -+#define TAHVO_MODE(tu) TAHVO_MODE_PERIPHERAL -+#else -+#define TAHVO_MODE(tu) TAHVO_MODE_HOST -+#endif -+ -+struct tahvo_usb { -+ struct platform_device *pt_dev; -+ struct otg_transceiver otg; -+ int vbus_state; -+ struct work_struct irq_work; -+ struct mutex serialize; -+#ifdef CONFIG_USB_OTG -+ int tahvo_mode; -+#endif -+}; -+static struct platform_device tahvo_usb_device; -+ -+/* -+ * --------------------------------------------------------------------------- -+ * OTG related functions -+ * -+ * These shoud be separated into omap-otg.c driver module, as they are used -+ * by various transceivers. These functions are needed in the UDC-only case -+ * as well. These functions are copied from GPL isp1301_omap.c -+ * --------------------------------------------------------------------------- -+ */ -+static struct platform_device *tahvo_otg_dev; -+ -+static irqreturn_t omap_otg_irq(int irq, void *arg) -+{ -+ struct platform_device *otg_dev = (struct platform_device *) arg; -+ struct tahvo_usb *tu = (struct tahvo_usb *) otg_dev->dev.driver_data; -+ u16 otg_irq; -+ -+ otg_irq = omap_readw(OTG_IRQ_SRC); -+ if (otg_irq & OPRT_CHG) { -+ omap_writew(OPRT_CHG, OTG_IRQ_SRC); -+ } else if (otg_irq & B_SRP_TMROUT) { -+ omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC); -+ } else if (otg_irq & B_HNP_FAIL) { -+ omap_writew(B_HNP_FAIL, OTG_IRQ_SRC); -+ } else if (otg_irq & A_SRP_DETECT) { -+ omap_writew(A_SRP_DETECT, OTG_IRQ_SRC); -+ } else if (otg_irq & A_REQ_TMROUT) { -+ omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC); -+ } else if (otg_irq & A_VBUS_ERR) { -+ omap_writew(A_VBUS_ERR, OTG_IRQ_SRC); -+ } else if (otg_irq & DRIVER_SWITCH) { -+ if ((!(omap_readl(OTG_CTRL) & OTG_DRIVER_SEL)) && -+ tu->otg.host && tu->otg.state == OTG_STATE_A_HOST) { -+ /* role is host */ -+ usb_bus_start_enum(tu->otg.host, -+ tu->otg.host->otg_port); -+ } -+ omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC); -+ } else -+ return IRQ_NONE; -+ -+ return IRQ_HANDLED; -+ -+} -+ -+static int omap_otg_init(void) -+{ -+ u32 l; -+ -+#ifdef CONFIG_USB_OTG -+ if (!tahvo_otg_dev) { -+ printk("tahvo-usb: no tahvo_otg_dev\n"); -+ return -ENODEV; -+ } -+#endif -+ -+ l = omap_readl(OTG_SYSCON_1); -+ l &= ~OTG_IDLE_EN; -+ omap_writel(l, OTG_SYSCON_1); -+ udelay(100); -+ -+ /* some of these values are board-specific... */ -+ l = omap_readl(OTG_SYSCON_2); -+ l |= OTG_EN -+ /* for B-device: */ -+ | SRP_GPDATA /* 9msec Bdev D+ pulse */ -+ | SRP_GPDVBUS /* discharge after VBUS pulse */ -+ // | (3 << 24) /* 2msec VBUS pulse */ -+ /* for A-device: */ -+ | (0 << 20) /* 200ms nominal A_WAIT_VRISE timer */ -+ | SRP_DPW /* detect 167+ns SRP pulses */ -+ | SRP_DATA | SRP_VBUS; /* accept both kinds of SRP pulse */ -+ omap_writel(l, OTG_SYSCON_2); -+ -+ omap_writew(DRIVER_SWITCH | OPRT_CHG -+ | B_SRP_TMROUT | B_HNP_FAIL -+ | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT, -+ OTG_IRQ_EN); -+ l = omap_readl(OTG_SYSCON_2); -+ l |= OTG_EN; -+ omap_writel(l, OTG_SYSCON_2); -+ -+ return 0; -+} -+ -+static int omap_otg_probe(struct device *dev) -+{ -+ int ret; -+ -+ tahvo_otg_dev = to_platform_device(dev); -+ ret = omap_otg_init(); -+ if (ret != 0) { -+ printk(KERN_ERR "tahvo-usb: omap_otg_init failed\n"); -+ return ret; -+ } -+ -+ return request_irq(tahvo_otg_dev->resource[1].start, -+ omap_otg_irq, IRQF_DISABLED, DRIVER_NAME, -+ &tahvo_usb_device); -+} -+ -+static int omap_otg_remove(struct device *dev) -+{ -+ free_irq(tahvo_otg_dev->resource[1].start, &tahvo_usb_device); -+ tahvo_otg_dev = NULL; -+ -+ return 0; -+} -+ -+struct device_driver omap_otg_driver = { -+ .name = "omap_otg", -+ .bus = &platform_bus_type, -+ .probe = omap_otg_probe, -+ .remove = omap_otg_remove, -+}; -+ -+/* -+ * --------------------------------------------------------------------------- -+ * Tahvo related functions -+ * These are Nokia proprietary code, except for the OTG register settings, -+ * which are copied from isp1301.c -+ * --------------------------------------------------------------------------- -+ */ -+static ssize_t vbus_state_show(struct device *device, -+ struct device_attribute *attr, char *buf) -+{ -+ struct tahvo_usb *tu = (struct tahvo_usb*) device->driver_data; -+ return sprintf(buf, "%d\n", tu->vbus_state); -+} -+static DEVICE_ATTR(vbus_state, 0444, vbus_state_show, NULL); -+ -+int vbus_active = 0; -+ -+#if 0 -+ -+static int host_suspend(struct tahvo_usb *tu) -+{ -+ struct device *dev; -+ -+ if (!tu->otg.host) -+ return -ENODEV; -+ -+ /* Currently ASSUMES only the OTG port matters; -+ * other ports could be active... -+ */ -+ dev = tu->otg.host->controller; -+ return dev->driver->suspend(dev, PMSG_SUSPEND); -+} -+ -+static int host_resume(struct tahvo_usb *tu) -+{ -+ struct device *dev; -+ -+ if (!tu->otg.host) -+ return -ENODEV; -+ -+ dev = tu->otg.host->controller; -+ return dev->driver->resume(dev); -+} -+ -+#else -+ -+static int host_suspend(struct tahvo_usb *tu) -+{ -+ return 0; -+} -+ -+static int host_resume(struct tahvo_usb *tu) -+{ -+ return 0; -+} -+ -+#endif -+ -+static void check_vbus_state(struct tahvo_usb *tu) -+{ -+ int reg, prev_state; -+ -+ reg = tahvo_read_reg(TAHVO_REG_IDSR); -+ if (reg & 0x01) { -+ u32 l; -+ -+ vbus_active = 1; -+ switch (tu->otg.state) { -+ case OTG_STATE_B_IDLE: -+ /* Enable the gadget driver */ -+ if (tu->otg.gadget) -+ usb_gadget_vbus_connect(tu->otg.gadget); -+ /* Set B-session valid and not B-sessio ended to indicate -+ * Vbus to be ok. */ -+ l = omap_readl(OTG_CTRL); -+ l &= ~OTG_BSESSEND; -+ l |= OTG_BSESSVLD; -+ omap_writel(l, OTG_CTRL); -+ -+ tu->otg.state = OTG_STATE_B_PERIPHERAL; -+ break; -+ case OTG_STATE_A_IDLE: -+ /* Session is now valid assuming the USB hub is driving Vbus */ -+ tu->otg.state = OTG_STATE_A_HOST; -+ host_resume(tu); -+ break; -+ default: -+ break; -+ } -+ printk("USB cable connected\n"); -+ } else { -+ switch (tu->otg.state) { -+ case OTG_STATE_B_PERIPHERAL: -+ if (tu->otg.gadget) -+ usb_gadget_vbus_disconnect(tu->otg.gadget); -+ tu->otg.state = OTG_STATE_B_IDLE; -+ break; -+ case OTG_STATE_A_HOST: -+ tu->otg.state = OTG_STATE_A_IDLE; -+ break; -+ default: -+ break; -+ } -+ printk("USB cable disconnected\n"); -+ vbus_active = 0; -+ } -+ -+ prev_state = tu->vbus_state; -+ tu->vbus_state = reg & 0x01; -+ if (prev_state != tu->vbus_state) -+ sysfs_notify(&tu->pt_dev->dev.kobj, NULL, "vbus_state"); -+} -+ -+static void tahvo_usb_become_host(struct tahvo_usb *tu) -+{ -+ u32 l; -+ -+ /* Clear system and transceiver controlled bits -+ * also mark the A-session is always valid */ -+ omap_otg_init(); -+ -+ l = omap_readl(OTG_CTRL); -+ l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK); -+ l |= OTG_ASESSVLD; -+ omap_writel(l, OTG_CTRL); -+ -+ /* Power up the transceiver in USB host mode */ -+ tahvo_write_reg(TAHVO_REG_USBR, USBR_REGOUT | USBR_NSUSPEND | -+ USBR_MASTER_SW2 | USBR_MASTER_SW1); -+ tu->otg.state = OTG_STATE_A_IDLE; -+ -+ check_vbus_state(tu); -+} -+ -+static void tahvo_usb_stop_host(struct tahvo_usb *tu) -+{ -+ host_suspend(tu); -+ tu->otg.state = OTG_STATE_A_IDLE; -+} -+ -+static void tahvo_usb_become_peripheral(struct tahvo_usb *tu) -+{ -+ u32 l; -+ -+ /* Clear system and transceiver controlled bits -+ * and enable ID to mark peripheral mode and -+ * BSESSEND to mark no Vbus */ -+ omap_otg_init(); -+ l = omap_readl(OTG_CTRL); -+ l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD); -+ l |= OTG_ID | OTG_BSESSEND; -+ omap_writel(l, OTG_CTRL); -+ -+ /* Power up transceiver and set it in USB perhiperal mode */ -+ tahvo_write_reg(TAHVO_REG_USBR, USBR_SLAVE_CONTROL | USBR_REGOUT | USBR_NSUSPEND | USBR_SLAVE_SW); -+ tu->otg.state = OTG_STATE_B_IDLE; -+ -+ check_vbus_state(tu); -+} -+ -+static void tahvo_usb_stop_peripheral(struct tahvo_usb *tu) -+{ -+ u32 l; -+ -+ l = omap_readl(OTG_CTRL); -+ l &= ~OTG_BSESSVLD; -+ l |= OTG_BSESSEND; -+ omap_writel(l, OTG_CTRL); -+ -+ if (tu->otg.gadget) -+ usb_gadget_vbus_disconnect(tu->otg.gadget); -+ tu->otg.state = OTG_STATE_B_IDLE; -+ -+} -+ -+static void tahvo_usb_power_off(struct tahvo_usb *tu) -+{ -+ u32 l; -+ int id; -+ -+ /* Disable gadget controller if any */ -+ if (tu->otg.gadget) -+ usb_gadget_vbus_disconnect(tu->otg.gadget); -+ -+ host_suspend(tu); -+ -+ /* Disable OTG and interrupts */ -+ if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL) -+ id = OTG_ID; -+ else -+ id = 0; -+ l = omap_readl(OTG_CTRL); -+ l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD); -+ l |= id | OTG_BSESSEND; -+ omap_writel(l, OTG_CTRL); -+ omap_writew(0, OTG_IRQ_EN); -+ -+ l = omap_readl(OTG_SYSCON_2); -+ l &= ~OTG_EN; -+ omap_writel(l, OTG_SYSCON_2); -+ -+ l = omap_readl(OTG_SYSCON_1); -+ l |= OTG_IDLE_EN; -+ omap_writel(l, OTG_SYSCON_1); -+ -+ /* Power off transceiver */ -+ tahvo_write_reg(TAHVO_REG_USBR, 0); -+ tu->otg.state = OTG_STATE_UNDEFINED; -+} -+ -+ -+static int tahvo_usb_set_power(struct otg_transceiver *dev, unsigned mA) -+{ -+ struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg); -+ -+ dev_dbg(&tu->pt_dev->dev, "set_power %d mA\n", mA); -+ -+ if (dev->state == OTG_STATE_B_PERIPHERAL) { -+ /* REVISIT: Can Tahvo charge battery from VBUS? */ -+ } -+ return 0; -+} -+ -+static int tahvo_usb_set_suspend(struct otg_transceiver *dev, int suspend) -+{ -+ struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg); -+ u16 w; -+ -+ dev_dbg(&tu->pt_dev->dev, "set_suspend\n"); -+ -+ w = tahvo_read_reg(TAHVO_REG_USBR); -+ if (suspend) -+ w &= ~USBR_NSUSPEND; -+ else -+ w |= USBR_NSUSPEND; -+ tahvo_write_reg(TAHVO_REG_USBR, w); -+ -+ return 0; -+} -+ -+static int tahvo_usb_start_srp(struct otg_transceiver *dev) -+{ -+ struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg); -+ u32 otg_ctrl; -+ -+ dev_dbg(&tu->pt_dev->dev, "start_srp\n"); -+ -+ if (!dev || tu->otg.state != OTG_STATE_B_IDLE) -+ return -ENODEV; -+ -+ otg_ctrl = omap_readl(OTG_CTRL); -+ if (!(otg_ctrl & OTG_BSESSEND)) -+ return -EINVAL; -+ -+ otg_ctrl |= OTG_B_BUSREQ; -+ otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_SYS_MASK; -+ omap_writel(otg_ctrl, OTG_CTRL); -+ tu->otg.state = OTG_STATE_B_SRP_INIT; -+ -+ return 0; -+} -+ -+static int tahvo_usb_start_hnp(struct otg_transceiver *otg) -+{ -+ struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg); -+ -+ dev_dbg(&tu->pt_dev->dev, "start_hnp\n"); -+#ifdef CONFIG_USB_OTG -+ /* REVISIT: Add this for OTG */ -+#endif -+ return -EINVAL; -+} -+ -+static int tahvo_usb_set_host(struct otg_transceiver *otg, struct usb_bus *host) -+{ -+ struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg); -+ u32 l; -+ -+ dev_dbg(&tu->pt_dev->dev, "set_host %p\n", host); -+ -+ if (otg == NULL) -+ return -ENODEV; -+ -+#if defined(CONFIG_USB_OTG) || !defined(CONFIG_USB_GADGET_OMAP) -+ -+ mutex_lock(&tu->serialize); -+ -+ if (host == NULL) { -+ if (TAHVO_MODE(tu) == TAHVO_MODE_HOST) -+ tahvo_usb_power_off(tu); -+ tu->otg.host = NULL; -+ mutex_unlock(&tu->serialize); -+ return 0; -+ } -+ -+ l = omap_readl(OTG_SYSCON_1); -+ l &= ~(OTG_IDLE_EN | HST_IDLE_EN | DEV_IDLE_EN); -+ omap_writel(l, OTG_SYSCON_1); -+ -+ if (TAHVO_MODE(tu) == TAHVO_MODE_HOST) { -+ tu->otg.host = NULL; -+ tahvo_usb_become_host(tu); -+ } else -+ host_suspend(tu); -+ -+ tu->otg.host = host; -+ -+ mutex_unlock(&tu->serialize); -+#else -+ /* No host mode configured, so do not allow host controlled to be set */ -+ return -EINVAL; -+#endif -+ -+ return 0; -+} -+ -+static int tahvo_usb_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget) -+{ -+ struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg); -+ -+ dev_dbg(&tu->pt_dev->dev, "set_peripheral %p\n", gadget); -+ -+ if (!otg) -+ return -ENODEV; -+ -+#if defined(CONFIG_USB_OTG) || defined(CONFIG_USB_GADGET_OMAP) -+ -+ mutex_lock(&tu->serialize); -+ -+ if (!gadget) { -+ if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL) -+ tahvo_usb_power_off(tu); -+ tu->otg.gadget = NULL; -+ mutex_unlock(&tu->serialize); -+ return 0; -+ } -+ -+ tu->otg.gadget = gadget; -+ if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL) -+ tahvo_usb_become_peripheral(tu); -+ -+ mutex_unlock(&tu->serialize); -+#else -+ /* No gadget mode configured, so do not allow host controlled to be set */ -+ return -EINVAL; -+#endif -+ -+ return 0; -+} -+ -+static void tahvo_usb_irq_work(struct work_struct *work) -+{ -+ struct tahvo_usb *tu = container_of(work, struct tahvo_usb, irq_work); -+ -+ mutex_lock(&tu->serialize); -+ check_vbus_state(tu); -+ mutex_unlock(&tu->serialize); -+} -+ -+static void tahvo_usb_vbus_interrupt(unsigned long arg) -+{ -+ struct tahvo_usb *tu = (struct tahvo_usb *) arg; -+ -+ tahvo_ack_irq(TAHVO_INT_VBUSON); -+ /* Seems we need this to acknowledge the interrupt */ -+ tahvo_read_reg(TAHVO_REG_IDSR); -+ schedule_work(&tu->irq_work); -+} -+ -+#ifdef CONFIG_USB_OTG -+static ssize_t otg_mode_show(struct device *device, -+ struct device_attribute *attr, char *buf) -+{ -+ struct tahvo_usb *tu = (struct tahvo_usb*) device->driver_data; -+ switch (tu->tahvo_mode) { -+ case TAHVO_MODE_HOST: -+ return sprintf(buf, "host\n"); -+ case TAHVO_MODE_PERIPHERAL: -+ return sprintf(buf, "peripheral\n"); -+ } -+ return sprintf(buf, "unknown\n"); -+} -+ -+static ssize_t otg_mode_store(struct device *device, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct tahvo_usb *tu = (struct tahvo_usb*) device->driver_data; -+ int r; -+ -+ r = strlen(buf); -+ mutex_lock(&tu->serialize); -+ if (strncmp(buf, "host", 4) == 0) { -+ if (tu->tahvo_mode == TAHVO_MODE_PERIPHERAL) -+ tahvo_usb_stop_peripheral(tu); -+ tu->tahvo_mode = TAHVO_MODE_HOST; -+ if (tu->otg.host) { -+ printk(KERN_INFO "Selected HOST mode: host controller present.\n"); -+ tahvo_usb_become_host(tu); -+ } else { -+ printk(KERN_INFO "Selected HOST mode: no host controller, powering off.\n"); -+ tahvo_usb_power_off(tu); -+ } -+ } else if (strncmp(buf, "peripheral", 10) == 0) { -+ if (tu->tahvo_mode == TAHVO_MODE_HOST) -+ tahvo_usb_stop_host(tu); -+ tu->tahvo_mode = TAHVO_MODE_PERIPHERAL; -+ if (tu->otg.gadget) { -+ printk(KERN_INFO "Selected PERIPHERAL mode: gadget driver present.\n"); -+ tahvo_usb_become_peripheral(tu); -+ } else { -+ printk(KERN_INFO "Selected PERIPHERAL mode: no gadget driver, powering off.\n"); -+ tahvo_usb_power_off(tu); -+ } -+ } else -+ r = -EINVAL; -+ -+ mutex_unlock(&tu->serialize); -+ return r; -+} -+ -+static DEVICE_ATTR(otg_mode, 0644, otg_mode_show, otg_mode_store); -+#endif -+ -+static int tahvo_usb_probe(struct device *dev) -+{ -+ struct tahvo_usb *tu; -+ int ret; -+ -+ dev_dbg(dev, "probe\n"); -+ -+ /* Create driver data */ -+ tu = kmalloc(sizeof(*tu), GFP_KERNEL); -+ if (!tu) -+ return -ENOMEM; -+ memset(tu, 0, sizeof(*tu)); -+ tu->pt_dev = container_of(dev, struct platform_device, dev); -+#ifdef CONFIG_USB_OTG -+ /* Default mode */ -+#ifdef CONFIG_CBUS_TAHVO_USB_HOST_BY_DEFAULT -+ tu->tahvo_mode = TAHVO_MODE_HOST; -+#else -+ tu->tahvo_mode = TAHVO_MODE_PERIPHERAL; -+#endif -+#endif -+ -+ INIT_WORK(&tu->irq_work, tahvo_usb_irq_work); -+ mutex_init(&tu->serialize); -+ -+ /* Set initial state, so that we generate kevents only on -+ * state changes */ -+ tu->vbus_state = tahvo_read_reg(TAHVO_REG_IDSR) & 0x01; -+ -+ /* We cannot enable interrupt until omap_udc is initialized */ -+ ret = tahvo_request_irq(TAHVO_INT_VBUSON, tahvo_usb_vbus_interrupt, -+ (unsigned long) tu, "vbus_interrupt"); -+ if (ret != 0) { -+ kfree(tu); -+ printk(KERN_ERR "Could not register Tahvo interrupt for VBUS\n"); -+ return ret; -+ } -+ -+ /* Attributes */ -+ ret = device_create_file(dev, &dev_attr_vbus_state); -+#ifdef CONFIG_USB_OTG -+ ret |= device_create_file(dev, &dev_attr_otg_mode); -+#endif -+ if (ret) -+ printk(KERN_ERR "attribute creation failed: %d\n", ret); -+ -+ /* Create OTG interface */ -+ tahvo_usb_power_off(tu); -+ tu->otg.state = OTG_STATE_UNDEFINED; -+ tu->otg.label = DRIVER_NAME; -+ tu->otg.set_host = tahvo_usb_set_host; -+ tu->otg.set_peripheral = tahvo_usb_set_peripheral; -+ tu->otg.set_power = tahvo_usb_set_power; -+ tu->otg.set_suspend = tahvo_usb_set_suspend; -+ tu->otg.start_srp = tahvo_usb_start_srp; -+ tu->otg.start_hnp = tahvo_usb_start_hnp; -+ -+ ret = otg_set_transceiver(&tu->otg); -+ if (ret < 0) { -+ printk(KERN_ERR "Cannot register USB transceiver\n"); -+ kfree(tu); -+ tahvo_free_irq(TAHVO_INT_VBUSON); -+ return ret; -+ } -+ -+ dev->driver_data = tu; -+ -+ /* Act upon current vbus state once at startup. A vbus state irq may or -+ * may not be generated in addition to this. */ -+ schedule_work(&tu->irq_work); -+ return 0; -+} -+ -+static int tahvo_usb_remove(struct device *dev) -+{ -+ dev_dbg(dev, "remove\n"); -+ -+ tahvo_free_irq(TAHVO_INT_VBUSON); -+ flush_scheduled_work(); -+ otg_set_transceiver(0); -+ device_remove_file(dev, &dev_attr_vbus_state); -+#ifdef CONFIG_USB_OTG -+ device_remove_file(dev, &dev_attr_otg_mode); -+#endif -+ return 0; -+} -+ -+static struct device_driver tahvo_usb_driver = { -+ .name = "tahvo-usb", -+ .bus = &platform_bus_type, -+ .probe = tahvo_usb_probe, -+ .remove = tahvo_usb_remove, -+}; -+ -+static struct platform_device tahvo_usb_device = { -+ .name = "tahvo-usb", -+ .id = -1, -+}; -+ -+static int __init tahvo_usb_init(void) -+{ -+ int ret = 0; -+ -+ printk(KERN_INFO "Tahvo USB transceiver driver initializing\n"); -+ ret = driver_register(&tahvo_usb_driver); -+ if (ret) -+ return ret; -+ ret = platform_device_register(&tahvo_usb_device); -+ if (ret < 0) { -+ driver_unregister(&tahvo_usb_driver); -+ return ret; -+ } -+ ret = driver_register(&omap_otg_driver); -+ if (ret) { -+ platform_device_unregister(&tahvo_usb_device); -+ driver_unregister(&tahvo_usb_driver); -+ return ret; -+ } -+ return 0; -+} -+ -+subsys_initcall(tahvo_usb_init); -+ -+static void __exit tahvo_usb_exit(void) -+{ -+ driver_unregister(&omap_otg_driver); -+ platform_device_unregister(&tahvo_usb_device); -+ driver_unregister(&tahvo_usb_driver); -+} -+module_exit(tahvo_usb_exit); -+ -+MODULE_DESCRIPTION("Tahvo USB OTG Transceiver Driver"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Juha Yrjölä, Tony Lindgren, and Timo Teräs"); ---- /dev/null -+++ b/drivers/cbus/tahvo-user.c -@@ -0,0 +1,405 @@ -+/** -+ * drivers/cbus/tahvo-user.c -+ * -+ * Tahvo user space interface functions -+ * -+ * Copyright (C) 2004, 2005 Nokia Corporation -+ * -+ * Written by Mikko Ylinen <mikko.k.ylinen@nokia.com> -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/types.h> -+#include <linux/kernel.h> -+#include <linux/interrupt.h> -+#include <linux/module.h> -+#include <linux/init.h> -+#include <linux/fs.h> -+#include <linux/miscdevice.h> -+#include <linux/poll.h> -+#include <linux/list.h> -+#include <linux/spinlock.h> -+#include <linux/mutex.h> -+ -+#include <asm/uaccess.h> -+ -+#include "tahvo.h" -+ -+#include "user_retu_tahvo.h" -+ -+/* Maximum size of IRQ node buffer/pool */ -+#define TAHVO_MAX_IRQ_BUF_LEN 16 -+ -+#define PFX "tahvo-user: " -+ -+/* Bitmap for marking the interrupt sources as having the handlers */ -+static u32 tahvo_irq_bits; -+ -+/* For allowing only one user process to subscribe to the tahvo interrupts */ -+static struct file *tahvo_irq_subscr = NULL; -+ -+/* For poll and IRQ passing */ -+struct tahvo_irq { -+ u32 id; -+ struct list_head node; -+}; -+ -+static spinlock_t tahvo_irqs_lock; -+static struct tahvo_irq *tahvo_irq_block; -+static LIST_HEAD(tahvo_irqs); -+static LIST_HEAD(tahvo_irqs_reserve); -+ -+/* Wait queue - used when user wants to read the device */ -+DECLARE_WAIT_QUEUE_HEAD(tahvo_user_waitqueue); -+ -+/* Semaphore to protect irq subscription sequence */ -+static struct mutex tahvo_mutex; -+ -+/* This array specifies TAHVO register types (read/write/toggle) */ -+static const u8 tahvo_access_bits[] = { -+ 1, -+ 4, -+ 1, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 3, -+ 1 -+}; -+ -+/* -+ * The handler for all TAHVO interrupts. -+ * -+ * arg is the interrupt source in TAHVO. -+ */ -+static void tahvo_user_irq_handler(unsigned long arg) -+{ -+ struct tahvo_irq *irq; -+ -+ /* user has to re-enable the interrupt once ready -+ * for receiving them again */ -+ tahvo_disable_irq(arg); -+ tahvo_ack_irq(arg); -+ -+ spin_lock(&tahvo_irqs_lock); -+ if (list_empty(&tahvo_irqs_reserve)) { -+ spin_unlock(&tahvo_irqs_lock); -+ return; -+ } -+ irq = list_entry((&tahvo_irqs_reserve)->next, struct tahvo_irq, node); -+ irq->id = arg; -+ list_move_tail(&irq->node, &tahvo_irqs); -+ spin_unlock(&tahvo_irqs_lock); -+ -+ /* wake up waiting thread */ -+ wake_up(&tahvo_user_waitqueue); -+} -+ -+/* -+ * This routine sets up the interrupt handler and marks an interrupt source -+ * in TAHVO as a candidate for signal delivery to the user process. -+ */ -+static int tahvo_user_subscribe_to_irq(int id, struct file *filp) -+{ -+ int ret; -+ -+ mutex_lock(&tahvo_mutex); -+ if ((tahvo_irq_subscr != NULL) && (tahvo_irq_subscr != filp)) { -+ mutex_unlock(&tahvo_mutex); -+ return -EBUSY; -+ } -+ /* Store the file pointer of the first user process registering IRQs */ -+ tahvo_irq_subscr = filp; -+ mutex_unlock(&tahvo_mutex); -+ -+ if (tahvo_irq_bits & (1 << id)) -+ return 0; -+ -+ ret = tahvo_request_irq(id, tahvo_user_irq_handler, id, ""); -+ if (ret < 0) -+ return ret; -+ -+ /* Mark that this interrupt has a handler */ -+ tahvo_irq_bits |= 1 << id; -+ -+ return 0; -+} -+ -+/* -+ * Unregister all TAHVO interrupt handlers -+ */ -+static void tahvo_unreg_irq_handlers(void) -+{ -+ int id; -+ -+ if (!tahvo_irq_bits) -+ return; -+ -+ for (id = 0; id < MAX_TAHVO_IRQ_HANDLERS; id++) -+ if (tahvo_irq_bits & (1 << id)) -+ tahvo_free_irq(id); -+ -+ tahvo_irq_bits = 0; -+} -+ -+/* -+ * Write to TAHVO register. -+ * Returns 0 upon success, a negative error value otherwise. -+ */ -+static int tahvo_user_write_with_mask(u32 field, u16 value) -+{ -+ u32 mask; -+ u32 reg; -+ u_short tmp; -+ unsigned long flags; -+ -+ mask = MASK(field); -+ reg = REG(field); -+ -+ /* Detect bad mask and reg */ -+ if (mask == 0 || reg > TAHVO_REG_MAX || -+ tahvo_access_bits[reg] == READ_ONLY) { -+ printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n", -+ reg, mask); -+ return -EINVAL; -+ } -+ -+ /* Justify value according to mask */ -+ while (!(mask & 1)) { -+ value = value << 1; -+ mask = mask >> 1; -+ } -+ -+ spin_lock_irqsave(&tahvo_lock, flags); -+ if (tahvo_access_bits[reg] == TOGGLE) { -+ /* No need to detect previous content of register */ -+ tmp = 0; -+ } else { -+ /* Read current value of register */ -+ tmp = tahvo_read_reg(reg); -+ } -+ /* Generate a new value */ -+ tmp = (tmp & ~MASK(field)) | (value & MASK(field)); -+ /* Write data to TAHVO */ -+ tahvo_write_reg(reg, tmp); -+ spin_unlock_irqrestore(&tahvo_lock, flags); -+ -+ return 0; -+} -+ -+/* -+ * Read TAHVO register. -+ */ -+static u32 tahvo_user_read_with_mask(u32 field) -+{ -+ u_short value; -+ u32 mask, reg; -+ -+ mask = MASK(field); -+ reg = REG(field); -+ -+ /* Detect bad mask and reg */ -+ if (mask == 0 || reg > TAHVO_REG_MAX) { -+ printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n", -+ reg, mask); -+ return -EINVAL; -+ } -+ -+ /* Read the register */ -+ value = tahvo_read_reg(reg) & mask; -+ -+ /* Right justify value */ -+ while (!(mask & 1)) { -+ value = value >> 1; -+ mask = mask >> 1; -+ } -+ -+ return value; -+} -+ -+/* -+ * Close device -+ */ -+static int tahvo_close(struct inode *inode, struct file *filp) -+{ -+ /* Unregister all interrupts that have been registered */ -+ if (tahvo_irq_subscr == filp) { -+ tahvo_unreg_irq_handlers(); -+ tahvo_irq_subscr = NULL; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Device control (ioctl) -+ */ -+static int tahvo_ioctl(struct inode *inode, struct file *filp, -+ unsigned int cmd, unsigned long arg) -+{ -+ struct retu_tahvo_write_parms par; -+ int ret; -+ -+ switch (cmd) { -+ case URT_IOCT_IRQ_SUBSCR: -+ return tahvo_user_subscribe_to_irq(arg, filp); -+ case TAHVO_IOCH_READ: -+ return tahvo_user_read_with_mask(arg); -+ case TAHVO_IOCX_WRITE: -+ ret = copy_from_user(&par, (void __user *) arg, sizeof(par)); -+ if (ret) -+ printk(KERN_ERR "copy_from_user failed: %d\n", ret); -+ par.result = tahvo_user_write_with_mask(par.field, par.value); -+ ret = copy_to_user((void __user *) arg, &par, sizeof(par)); -+ if (ret) -+ printk(KERN_ERR "copy_to_user failed: %d\n", ret); -+ break; -+ default: -+ return -ENOIOCTLCMD; -+ } -+ return 0; -+} -+ -+/* -+ * Read from device -+ */ -+static ssize_t tahvo_read(struct file *filp, char *buf, size_t count, -+ loff_t * offp) -+{ -+ struct tahvo_irq *irq; -+ -+ u32 nr, i; -+ -+ /* read not permitted if neither filp nor anyone has registered IRQs */ -+ if (tahvo_irq_subscr != filp) -+ return -EPERM; -+ -+ if ((count < sizeof(u32)) || ((count % sizeof(u32)) != 0)) -+ return -EINVAL; -+ -+ nr = count / sizeof(u32); -+ -+ for (i = 0; i < nr; i++) { -+ unsigned long flags; -+ u32 irq_id; -+ int ret; -+ -+ ret = wait_event_interruptible(tahvo_user_waitqueue, -+ !list_empty(&tahvo_irqs)); -+ if (ret < 0) -+ return ret; -+ -+ spin_lock_irqsave(&tahvo_irqs_lock, flags); -+ irq = list_entry((&tahvo_irqs)->next, struct tahvo_irq, node); -+ irq_id = irq->id; -+ list_move(&irq->node, &tahvo_irqs_reserve); -+ spin_unlock_irqrestore(&tahvo_irqs_lock, flags); -+ -+ ret = copy_to_user(buf + i * sizeof(irq_id), &irq_id, -+ sizeof(irq_id)); -+ if (ret) -+ printk(KERN_ERR "copy_to_user failed: %d\n", ret); -+ } -+ -+ return count; -+} -+ -+/* -+ * Poll method -+ */ -+static unsigned tahvo_poll(struct file *filp, struct poll_table_struct *pt) -+{ -+ if (!list_empty(&tahvo_irqs)) -+ return POLLIN; -+ -+ poll_wait(filp, &tahvo_user_waitqueue, pt); -+ -+ if (!list_empty(&tahvo_irqs)) -+ return POLLIN; -+ else -+ return 0; -+} -+ -+static struct file_operations tahvo_user_fileops = { -+ .owner = THIS_MODULE, -+ .ioctl = tahvo_ioctl, -+ .read = tahvo_read, -+ .release = tahvo_close, -+ .poll = tahvo_poll -+}; -+ -+static struct miscdevice tahvo_device = { -+ .minor = MISC_DYNAMIC_MINOR, -+ .name = "tahvo", -+ .fops = &tahvo_user_fileops -+}; -+ -+/* -+ * Initialization -+ * -+ * @return 0 if successful, error value otherwise. -+ */ -+int tahvo_user_init(void) -+{ -+ struct tahvo_irq *irq; -+ int res, i; -+ -+ irq = kmalloc(sizeof(*irq) * TAHVO_MAX_IRQ_BUF_LEN, GFP_KERNEL); -+ if (irq == NULL) { -+ printk(KERN_ERR PFX "kmalloc failed\n"); -+ return -ENOMEM; -+ } -+ memset(irq, 0, sizeof(*irq) * TAHVO_MAX_IRQ_BUF_LEN); -+ for (i = 0; i < TAHVO_MAX_IRQ_BUF_LEN; i++) -+ list_add(&irq[i].node, &tahvo_irqs_reserve); -+ -+ tahvo_irq_block = irq; -+ -+ spin_lock_init(&tahvo_irqs_lock); -+ mutex_init(&tahvo_mutex); -+ -+ /* Request a misc device */ -+ res = misc_register(&tahvo_device); -+ if (res < 0) { -+ printk(KERN_ERR PFX "unable to register misc device for %s\n", -+ tahvo_device.name); -+ kfree(irq); -+ return res; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Cleanup. -+ */ -+void tahvo_user_cleanup(void) -+{ -+ /* Unregister our misc device */ -+ misc_deregister(&tahvo_device); -+ /* Unregister and disable all TAHVO interrupts */ -+ tahvo_unreg_irq_handlers(); -+ kfree(tahvo_irq_block); -+} -+ -+MODULE_DESCRIPTION("Tahvo ASIC user space functions"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Mikko Ylinen"); ---- /dev/null -+++ b/drivers/cbus/tahvo.c -@@ -0,0 +1,442 @@ -+/** -+ * drivers/cbus/tahvo.c -+ * -+ * Support functions for Tahvo ASIC -+ * -+ * Copyright (C) 2004, 2005 Nokia Corporation -+ * -+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>, -+ * David Weinehall <david.weinehall@nokia.com>, and -+ * Mikko Ylinen <mikko.k.ylinen@nokia.com> -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include <linux/module.h> -+#include <linux/init.h> -+ -+#include <linux/kernel.h> -+#include <linux/errno.h> -+#include <linux/device.h> -+#include <linux/miscdevice.h> -+#include <linux/poll.h> -+#include <linux/fs.h> -+#include <linux/irq.h> -+#include <linux/interrupt.h> -+#include <linux/platform_device.h> -+#include <linux/gpio.h> -+ -+#include <asm/uaccess.h> -+ -+#include <mach/mux.h> -+#include <mach/board.h> -+#include <mach/board-nokia.h> -+ -+#include "cbus.h" -+#include "tahvo.h" -+ -+#define TAHVO_ID 0x02 -+#define PFX "tahvo: " -+ -+static int tahvo_initialized; -+static int tahvo_irq_pin; -+static int tahvo_is_betty; -+ -+static struct tasklet_struct tahvo_tasklet; -+spinlock_t tahvo_lock = SPIN_LOCK_UNLOCKED; -+ -+static struct completion device_release; -+ -+struct tahvo_irq_handler_desc { -+ int (*func)(unsigned long); -+ unsigned long arg; -+ char name[8]; -+}; -+ -+static struct tahvo_irq_handler_desc tahvo_irq_handlers[MAX_TAHVO_IRQ_HANDLERS]; -+ -+/** -+ * tahvo_read_reg - Read a value from a register in Tahvo -+ * @reg: the register to read from -+ * -+ * This function returns the contents of the specified register -+ */ -+int tahvo_read_reg(int reg) -+{ -+ BUG_ON(!tahvo_initialized); -+ return cbus_read_reg(cbus_host, TAHVO_ID, reg); -+} -+ -+/** -+ * tahvo_write_reg - Write a value to a register in Tahvo -+ * @reg: the register to write to -+ * @reg: the value to write to the register -+ * -+ * This function writes a value to the specified register -+ */ -+void tahvo_write_reg(int reg, u16 val) -+{ -+ BUG_ON(!tahvo_initialized); -+ cbus_write_reg(cbus_host, TAHVO_ID, reg, val); -+} -+ -+/** -+ * tahvo_set_clear_reg_bits - set and clear register bits atomically -+ * @reg: the register to write to -+ * @bits: the bits to set -+ * -+ * This function sets and clears the specified Tahvo register bits atomically -+ */ -+void tahvo_set_clear_reg_bits(int reg, u16 set, u16 clear) -+{ -+ unsigned long flags; -+ u16 w; -+ -+ spin_lock_irqsave(&tahvo_lock, flags); -+ w = tahvo_read_reg(reg); -+ w &= ~clear; -+ w |= set; -+ tahvo_write_reg(reg, w); -+ spin_unlock_irqrestore(&tahvo_lock, flags); -+} -+ -+/* -+ * Disable given TAHVO interrupt -+ */ -+void tahvo_disable_irq(int id) -+{ -+ unsigned long flags; -+ u16 mask; -+ -+ spin_lock_irqsave(&tahvo_lock, flags); -+ mask = tahvo_read_reg(TAHVO_REG_IMR); -+ mask |= 1 << id; -+ tahvo_write_reg(TAHVO_REG_IMR, mask); -+ spin_unlock_irqrestore(&tahvo_lock, flags); -+} -+ -+/* -+ * Enable given TAHVO interrupt -+ */ -+void tahvo_enable_irq(int id) -+{ -+ unsigned long flags; -+ u16 mask; -+ -+ spin_lock_irqsave(&tahvo_lock, flags); -+ mask = tahvo_read_reg(TAHVO_REG_IMR); -+ mask &= ~(1 << id); -+ tahvo_write_reg(TAHVO_REG_IMR, mask); -+ spin_unlock_irqrestore(&tahvo_lock, flags); -+} -+ -+/* -+ * Acknowledge given TAHVO interrupt -+ */ -+void tahvo_ack_irq(int id) -+{ -+ tahvo_write_reg(TAHVO_REG_IDR, 1 << id); -+} -+ -+static int tahvo_7bit_backlight; -+ -+int tahvo_get_backlight_level(void) -+{ -+ int mask; -+ -+ if (tahvo_7bit_backlight) -+ mask = 0x7f; -+ else -+ mask = 0x0f; -+ return tahvo_read_reg(TAHVO_REG_LEDPWMR) & mask; -+} -+ -+int tahvo_get_max_backlight_level(void) -+{ -+ if (tahvo_7bit_backlight) -+ return 0x7f; -+ else -+ return 0x0f; -+} -+ -+void tahvo_set_backlight_level(int level) -+{ -+ int max_level; -+ -+ max_level = tahvo_get_max_backlight_level(); -+ if (level > max_level) -+ level = max_level; -+ tahvo_write_reg(TAHVO_REG_LEDPWMR, level); -+} -+ -+/* -+ * TAHVO interrupt handler. Only schedules the tasklet. -+ */ -+static irqreturn_t tahvo_irq_handler(int irq, void *dev_id) -+{ -+ tasklet_schedule(&tahvo_tasklet); -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Tasklet handler -+ */ -+static void tahvo_tasklet_handler(unsigned long data) -+{ -+ struct tahvo_irq_handler_desc *hnd; -+ u16 id; -+ u16 im; -+ int i; -+ -+ for (;;) { -+ id = tahvo_read_reg(TAHVO_REG_IDR); -+ im = ~tahvo_read_reg(TAHVO_REG_IMR); -+ id &= im; -+ -+ if (!id) -+ break; -+ -+ for (i = 0; id != 0; i++, id >>= 1) { -+ if (!(id & 1)) -+ continue; -+ hnd = &tahvo_irq_handlers[i]; -+ if (hnd->func == NULL) { -+ /* Spurious tahvo interrupt - just ack it */ -+ printk(KERN_INFO "Spurious Tahvo interrupt " -+ "(id %d)\n", i); -+ tahvo_disable_irq(i); -+ tahvo_ack_irq(i); -+ continue; -+ } -+ hnd->func(hnd->arg); -+ /* -+ * Don't acknowledge the interrupt here -+ * It must be done explicitly -+ */ -+ } -+ } -+} -+ -+/* -+ * Register the handler for a given TAHVO interrupt source. -+ */ -+int tahvo_request_irq(int id, void *irq_handler, unsigned long arg, char *name) -+{ -+ struct tahvo_irq_handler_desc *hnd; -+ -+ if (irq_handler == NULL || id >= MAX_TAHVO_IRQ_HANDLERS || -+ name == NULL) { -+ printk(KERN_ERR PFX "Invalid arguments to %s\n", -+ __FUNCTION__); -+ return -EINVAL; -+ } -+ hnd = &tahvo_irq_handlers[id]; -+ if (hnd->func != NULL) { -+ printk(KERN_ERR PFX "IRQ %d already reserved\n", id); -+ return -EBUSY; -+ } -+ printk(KERN_INFO PFX "Registering interrupt %d for device %s\n", -+ id, name); -+ hnd->func = irq_handler; -+ hnd->arg = arg; -+ strlcpy(hnd->name, name, sizeof(hnd->name)); -+ -+ tahvo_ack_irq(id); -+ tahvo_enable_irq(id); -+ -+ return 0; -+} -+ -+/* -+ * Unregister the handler for a given TAHVO interrupt source. -+ */ -+void tahvo_free_irq(int id) -+{ -+ struct tahvo_irq_handler_desc *hnd; -+ -+ if (id >= MAX_TAHVO_IRQ_HANDLERS) { -+ printk(KERN_ERR PFX "Invalid argument to %s\n", -+ __FUNCTION__); -+ return; -+ } -+ hnd = &tahvo_irq_handlers[id]; -+ if (hnd->func == NULL) { -+ printk(KERN_ERR PFX "IRQ %d already freed\n", id); -+ return; -+ } -+ -+ tahvo_disable_irq(id); -+ hnd->func = NULL; -+} -+ -+/** -+ * tahvo_probe - Probe for Tahvo ASIC -+ * @dev: the Tahvo device -+ * -+ * Probe for the Tahvo ASIC and allocate memory -+ * for its device-struct if found -+ */ -+static int __devinit tahvo_probe(struct device *dev) -+{ -+ const struct omap_em_asic_bb5_config * em_asic_config; -+ int rev, id, ret; -+ -+ /* Prepare tasklet */ -+ tasklet_init(&tahvo_tasklet, tahvo_tasklet_handler, 0); -+ -+ em_asic_config = omap_get_config(OMAP_TAG_EM_ASIC_BB5, -+ struct omap_em_asic_bb5_config); -+ if (em_asic_config == NULL) { -+ printk(KERN_ERR PFX "Unable to retrieve config data\n"); -+ return -ENODATA; -+ } -+ -+ tahvo_initialized = 1; -+ -+ rev = tahvo_read_reg(TAHVO_REG_ASICR); -+ -+ id = (rev >> 8) & 0xff; -+ if (id == 0x03) { -+ if ((rev & 0xff) >= 0x50) -+ tahvo_7bit_backlight = 1; -+ } else if (id == 0x0b) { -+ tahvo_is_betty = 1; -+ tahvo_7bit_backlight = 1; -+ } else { -+ printk(KERN_ERR "Tahvo/Betty chip not found"); -+ return -ENODEV; -+ } -+ -+ printk(KERN_INFO "%s v%d.%d found\n", tahvo_is_betty ? "Betty" : "Tahvo", -+ (rev >> 4) & 0x0f, rev & 0x0f); -+ -+ tahvo_irq_pin = em_asic_config->tahvo_irq_gpio; -+ -+ if ((ret = gpio_request(tahvo_irq_pin, "TAHVO irq")) < 0) { -+ printk(KERN_ERR PFX "Unable to reserve IRQ GPIO\n"); -+ return ret; -+ } -+ -+ /* Set the pin as input */ -+ gpio_direction_input(tahvo_irq_pin); -+ -+ /* Rising edge triggers the IRQ */ -+ set_irq_type(gpio_to_irq(tahvo_irq_pin), IRQ_TYPE_EDGE_RISING); -+ -+ /* Mask all TAHVO interrupts */ -+ tahvo_write_reg(TAHVO_REG_IMR, 0xffff); -+ -+ ret = request_irq(gpio_to_irq(tahvo_irq_pin), tahvo_irq_handler, 0, -+ "tahvo", 0); -+ if (ret < 0) { -+ printk(KERN_ERR PFX "Unable to register IRQ handler\n"); -+ gpio_free(tahvo_irq_pin); -+ return ret; -+ } -+#ifdef CONFIG_CBUS_TAHVO_USER -+ /* Initialize user-space interface */ -+ if (tahvo_user_init() < 0) { -+ printk(KERN_ERR "Unable to initialize driver\n"); -+ free_irq(gpio_to_irq(tahvo_irq_pin), 0); -+ gpio_free(tahvo_irq_pin); -+ return ret; -+ } -+#endif -+ return 0; -+} -+ -+static int tahvo_remove(struct device *dev) -+{ -+#ifdef CONFIG_CBUS_TAHVO_USER -+ tahvo_user_cleanup(); -+#endif -+ /* Mask all TAHVO interrupts */ -+ tahvo_write_reg(TAHVO_REG_IMR, 0xffff); -+ free_irq(gpio_to_irq(tahvo_irq_pin), 0); -+ gpio_free(tahvo_irq_pin); -+ tasklet_kill(&tahvo_tasklet); -+ -+ return 0; -+} -+ -+static void tahvo_device_release(struct device *dev) -+{ -+ complete(&device_release); -+} -+ -+static struct device_driver tahvo_driver = { -+ .name = "tahvo", -+ .bus = &platform_bus_type, -+ .probe = tahvo_probe, -+ .remove = tahvo_remove, -+}; -+ -+static struct platform_device tahvo_device = { -+ .name = "tahvo", -+ .id = -1, -+ .dev = { -+ .release = tahvo_device_release, -+ } -+}; -+ -+/** -+ * tahvo_init - initialise Tahvo driver -+ * -+ * Initialise the Tahvo driver and return 0 if everything worked ok -+ */ -+static int __init tahvo_init(void) -+{ -+ int ret = 0; -+ -+ printk(KERN_INFO "Tahvo/Betty driver initialising\n"); -+ -+ init_completion(&device_release); -+ -+ if ((ret = driver_register(&tahvo_driver)) < 0) -+ return ret; -+ -+ if ((ret = platform_device_register(&tahvo_device)) < 0) { -+ driver_unregister(&tahvo_driver); -+ return ret; -+ } -+ return 0; -+} -+ -+/* -+ * Cleanup -+ */ -+static void __exit tahvo_exit(void) -+{ -+ platform_device_unregister(&tahvo_device); -+ driver_unregister(&tahvo_driver); -+ wait_for_completion(&device_release); -+} -+ -+EXPORT_SYMBOL(tahvo_request_irq); -+EXPORT_SYMBOL(tahvo_free_irq); -+EXPORT_SYMBOL(tahvo_enable_irq); -+EXPORT_SYMBOL(tahvo_disable_irq); -+EXPORT_SYMBOL(tahvo_ack_irq); -+EXPORT_SYMBOL(tahvo_read_reg); -+EXPORT_SYMBOL(tahvo_write_reg); -+EXPORT_SYMBOL(tahvo_get_backlight_level); -+EXPORT_SYMBOL(tahvo_get_max_backlight_level); -+EXPORT_SYMBOL(tahvo_set_backlight_level); -+ -+subsys_initcall(tahvo_init); -+module_exit(tahvo_exit); -+ -+MODULE_DESCRIPTION("Tahvo ASIC control"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Juha Yrjölä, David Weinehall, and Mikko Ylinen"); ---- /dev/null -+++ b/drivers/cbus/tahvo.h -@@ -0,0 +1,61 @@ -+/* -+ * drivers/cbus/tahvo.h -+ * -+ * Copyright (C) 2004, 2005 Nokia Corporation -+ * -+ * Written by Juha Yrjölä <juha.yrjola@nokia.com> and -+ * David Weinehall <david.weinehall@nokia.com> -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __DRIVERS_CBUS_TAHVO_H -+#define __DRIVERS_CBUS_TAHVO_H -+ -+#include <linux/types.h> -+ -+/* Registers */ -+#define TAHVO_REG_ASICR 0x00 /* ASIC ID & revision */ -+#define TAHVO_REG_IDR 0x01 /* Interrupt ID */ -+#define TAHVO_REG_IDSR 0x02 /* Interrupt status */ -+#define TAHVO_REG_IMR 0x03 /* Interrupt mask */ -+#define TAHVO_REG_LEDPWMR 0x05 /* LED PWM */ -+#define TAHVO_REG_USBR 0x06 /* USB control */ -+#define TAHVO_REG_MAX 0x0d -+ -+/* Interrupt sources */ -+#define TAHVO_INT_VBUSON 0 -+ -+#define MAX_TAHVO_IRQ_HANDLERS 8 -+ -+int tahvo_read_reg(int reg); -+void tahvo_write_reg(int reg, u16 val); -+void tahvo_set_clear_reg_bits(int reg, u16 set, u16 clear); -+int tahvo_request_irq(int id, void *irq_handler, unsigned long arg, char *name); -+void tahvo_free_irq(int id); -+void tahvo_enable_irq(int id); -+void tahvo_disable_irq(int id); -+void tahvo_ack_irq(int id); -+int tahvo_get_backlight_level(void); -+int tahvo_get_max_backlight_level(void); -+void tahvo_set_backlight_level(int level); -+ -+#ifdef CONFIG_CBUS_TAHVO_USER -+int tahvo_user_init(void); -+void tahvo_user_cleanup(void); -+#endif -+ -+extern spinlock_t tahvo_lock; -+ -+#endif /* __DRIVERS_CBUS_TAHVO_H */ ---- /dev/null -+++ b/drivers/cbus/user_retu_tahvo.h -@@ -0,0 +1,75 @@ -+/** -+ * drivers/cbus/user_retu_tahvo.h -+ * -+ * Copyright (C) 2004, 2005 Nokia Corporation -+ * -+ * Written by Mikko Ylinen <mikko.k.ylinen@nokia.com> -+ * -+ * Definitions and types used by both retu-user and tahvo-user. -+ * -+ * This file is subject to the terms and conditions of the GNU General -+ * Public License. See the file "COPYING" in the main directory of this -+ * archive for more details. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _USER_RETU_TAHVO_H -+#define _USER_RETU_TAHVO_H -+ -+/* Chip IDs */ -+#define CHIP_RETU 1 -+#define CHIP_TAHVO 2 -+ -+/* Register access type bits */ -+#define READ_ONLY 1 -+#define WRITE_ONLY 2 -+#define READ_WRITE 3 -+#define TOGGLE 4 -+ -+#define MASK(field) ((u16)(field & 0xFFFF)) -+#define REG(field) ((u16)((field >> 16) & 0x3F)) -+ -+/*** IOCTL definitions. These should be kept in sync with user space **********/ -+ -+#define URT_IOC_MAGIC '`' -+ -+/* -+ * IOCTL function naming conventions: -+ * ================================== -+ * 0 -- No argument and return value -+ * S -- Set through a pointer -+ * T -- Tell directly with the argument value -+ * G -- Reply by setting through a pointer -+ * Q -- response is on the return value -+ * X -- S and G atomically -+ * H -- T and Q atomically -+ */ -+ -+/* General */ -+#define URT_IOCT_IRQ_SUBSCR _IO(URT_IOC_MAGIC, 0) -+ -+/* RETU */ -+#define RETU_IOCH_READ _IO(URT_IOC_MAGIC, 1) -+#define RETU_IOCX_WRITE _IO(URT_IOC_MAGIC, 2) -+#define RETU_IOCH_ADC_READ _IO(URT_IOC_MAGIC, 3) -+ -+/* TAHVO */ -+#define TAHVO_IOCH_READ _IO(URT_IOC_MAGIC, 4) -+#define TAHVO_IOCX_WRITE _IO(URT_IOC_MAGIC, 5) -+ -+/* This structure is used for writing RETU/TAHVO registers */ -+struct retu_tahvo_write_parms { -+ u32 field; -+ u16 value; -+ u8 result; -+}; -+ -+#endif ---- a/drivers/spi/omap_uwire.c -+++ b/drivers/spi/omap_uwire.c -@@ -52,7 +52,7 @@ - #include <asm/mach-types.h> - - #include <mach/mux.h> --#include <mach/omap730.h> /* OMAP730_IO_CONF registers */ -+#include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */ - - - /* FIXME address is now a platform device resource, -@@ -504,7 +504,7 @@ static int __init uwire_probe(struct pla - } - clk_enable(uwire->ck); - -- if (cpu_is_omap730()) -+ if (cpu_is_omap7xx()) - uwire_idx_shift = 1; - else - uwire_idx_shift = 2; -@@ -573,8 +573,8 @@ static int __init omap_uwire_init(void) - } - if (machine_is_omap_perseus2()) { - /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */ -- int val = omap_readl(OMAP730_IO_CONF_9) & ~0x00EEE000; -- omap_writel(val | 0x00AAA000, OMAP730_IO_CONF_9); -+ int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000; -+ omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9); - } - - return platform_driver_probe(&uwire_driver, uwire_probe); ---- a/drivers/usb/Kconfig -+++ b/drivers/usb/Kconfig -@@ -60,6 +60,7 @@ config USB_ARCH_HAS_EHCI - default y if ARCH_IXP4XX - default y if ARCH_W90X900 - default y if ARCH_AT91SAM9G45 -+ default y if ARCH_OMAP34XX - default PCI - - # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface. ---- a/drivers/usb/host/ehci-hcd.c -+++ b/drivers/usb/host/ehci-hcd.c -@@ -1111,6 +1111,11 @@ MODULE_LICENSE ("GPL"); - #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver - #endif - -+#ifdef CONFIG_ARCH_OMAP34XX -+#include "ehci-omap.c" -+#define PLATFORM_DRIVER ehci_hcd_omap_driver -+#endif -+ - #ifdef CONFIG_PPC_PS3 - #include "ehci-ps3.c" - #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver ---- /dev/null -+++ b/drivers/usb/host/ehci-omap.c -@@ -0,0 +1,755 @@ -+/* -+ * ehci-omap.c - driver for USBHOST on OMAP 34xx processor -+ * -+ * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller -+ * Tested on OMAP3430 ES2.0 SDP -+ * -+ * Copyright (C) 2007-2008 Texas Instruments, Inc. -+ * Author: Vikram Pandita <vikram.pandita@ti.com> -+ * -+ * Copyright (C) 2009 Nokia Corporation -+ * Contact: Felipe Balbi <felipe.balbi@nokia.com> -+ * -+ * Based on "ehci-fsl.c" and "ehci-au1xxx.c" ehci glue layers -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ * TODO (last updated Feb 23rd, 2009): -+ * - add kernel-doc -+ * - enable AUTOIDLE -+ * - move DPLL5 programming to clock fw -+ * - add suspend/resume -+ * - move workarounds to board-files -+ */ -+ -+#include <linux/platform_device.h> -+#include <linux/clk.h> -+#include <linux/gpio.h> -+#include <mach/usb.h> -+ -+/* -+ * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES -+ * Use ehci_omap_readl()/ehci_omap_writel() functions -+ */ -+ -+/* TLL Register Set */ -+#define OMAP_USBTLL_REVISION (0x00) -+#define OMAP_USBTLL_SYSCONFIG (0x10) -+#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) -+#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) -+#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) -+#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) -+#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0) -+ -+#define OMAP_USBTLL_SYSSTATUS (0x14) -+#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) -+ -+#define OMAP_USBTLL_IRQSTATUS (0x18) -+#define OMAP_USBTLL_IRQENABLE (0x1C) -+ -+#define OMAP_TLL_SHARED_CONF (0x30) -+#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6) -+#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5) -+#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2) -+#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1) -+#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0) -+ -+#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num) -+#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) -+#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10) -+#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9) -+#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8) -+#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0) -+ -+#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num) -+#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num) -+#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num) -+#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num) -+#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num) -+#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num) -+#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num) -+#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num) -+#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num) -+ -+#define OMAP_TLL_CHANNEL_COUNT 3 -+#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 1) -+#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 2) -+#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 4) -+ -+/* UHH Register Set */ -+#define OMAP_UHH_REVISION (0x00) -+#define OMAP_UHH_SYSCONFIG (0x10) -+#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) -+#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) -+#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) -+#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) -+#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) -+#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0) -+ -+#define OMAP_UHH_SYSSTATUS (0x14) -+#define OMAP_UHH_HOSTCONFIG (0x40) -+#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0) -+#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0) -+#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) -+#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) -+#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) -+#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) -+#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) -+#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) -+#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8) -+#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9) -+#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10) -+ -+#define OMAP_UHH_DEBUG_CSR (0x44) -+ -+/* EHCI Register Set */ -+#define EHCI_INSNREG05_ULPI (0xA4) -+#define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31 -+#define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24 -+#define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22 -+#define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16 -+#define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8 -+#define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0 -+ -+/*-------------------------------------------------------------------------*/ -+ -+static inline void ehci_omap_writel(void __iomem *base, u32 reg, u32 val) -+{ -+ __raw_writel(val, base + reg); -+} -+ -+static inline u32 ehci_omap_readl(void __iomem *base, u32 reg) -+{ -+ return __raw_readl(base + reg); -+} -+ -+static inline void ehci_omap_writeb(void __iomem *base, u8 reg, u8 val) -+{ -+ __raw_writeb(val, base + reg); -+} -+ -+static inline u8 ehci_omap_readb(void __iomem *base, u8 reg) -+{ -+ return __raw_readb(base + reg); -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+struct ehci_hcd_omap { -+ struct ehci_hcd *ehci; -+ struct device *dev; -+ -+ struct clk *usbhost_ick; -+ struct clk *usbhost2_120m_fck; -+ struct clk *usbhost1_48m_fck; -+ struct clk *usbtll_fck; -+ struct clk *usbtll_ick; -+ -+ /* FIXME the following two workarounds are -+ * board specific not silicon-specific so these -+ * should be moved to board-file instead. -+ * -+ * Maybe someone from TI will know better which -+ * board is affected and needs the workarounds -+ * to be applied -+ */ -+ -+ /* gpio for resetting phy */ -+ int reset_gpio_port[OMAP3_HS_USB_PORTS]; -+ -+ /* phy reset workaround */ -+ int phy_reset; -+ -+ /* desired phy_mode: TLL, PHY */ -+ enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS]; -+ -+ void __iomem *uhh_base; -+ void __iomem *tll_base; -+ void __iomem *ehci_base; -+}; -+ -+/*-------------------------------------------------------------------------*/ -+ -+static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask) -+{ -+ unsigned reg; -+ int i; -+ -+ /* Program the 3 TLL channels upfront */ -+ for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) { -+ reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i)); -+ -+ /* Disable AutoIdle, BitStuffing and use SDR Mode */ -+ reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE -+ | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF -+ | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE); -+ ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg); -+ } -+ -+ /* Program Common TLL register */ -+ reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF); -+ reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON -+ | OMAP_TLL_SHARED_CONF_USB_DIVRATION -+ | OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN); -+ reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; -+ -+ ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg); -+ -+ /* Enable channels now */ -+ for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) { -+ reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i)); -+ -+ /* Enable only the reg that is needed */ -+ if (!(tll_channel_mask & 1<<i)) -+ continue; -+ -+ reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; -+ ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg); -+ -+ ehci_omap_writeb(omap->tll_base, -+ OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe); -+ dev_dbg(omap->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n", -+ i+1, ehci_omap_readb(omap->tll_base, -+ OMAP_TLL_ULPI_SCRATCH_REGISTER(i))); -+ } -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* omap_start_ehc -+ * - Start the TI USBHOST controller -+ */ -+static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) -+{ -+ unsigned long timeout = jiffies + msecs_to_jiffies(1000); -+ u8 tll_ch_mask = 0; -+ unsigned reg = 0; -+ int ret = 0; -+ -+ dev_dbg(omap->dev, "starting TI EHCI USB Controller\n"); -+ -+ /* Enable Clocks for USBHOST */ -+ omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick"); -+ if (IS_ERR(omap->usbhost_ick)) { -+ ret = PTR_ERR(omap->usbhost_ick); -+ goto err_host_ick; -+ } -+ clk_enable(omap->usbhost_ick); -+ -+ omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck"); -+ if (IS_ERR(omap->usbhost2_120m_fck)) { -+ ret = PTR_ERR(omap->usbhost2_120m_fck); -+ goto err_host_120m_fck; -+ } -+ clk_enable(omap->usbhost2_120m_fck); -+ -+ omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck"); -+ if (IS_ERR(omap->usbhost1_48m_fck)) { -+ ret = PTR_ERR(omap->usbhost1_48m_fck); -+ goto err_host_48m_fck; -+ } -+ clk_enable(omap->usbhost1_48m_fck); -+ -+ if (omap->phy_reset) { -+ /* Refer: ISSUE1 */ -+ if (gpio_is_valid(omap->reset_gpio_port[0])) { -+ gpio_request(omap->reset_gpio_port[0], -+ "USB1 PHY reset"); -+ gpio_direction_output(omap->reset_gpio_port[0], 0); -+ } -+ -+ if (gpio_is_valid(omap->reset_gpio_port[1])) { -+ gpio_request(omap->reset_gpio_port[1], -+ "USB2 PHY reset"); -+ gpio_direction_output(omap->reset_gpio_port[1], 0); -+ } -+ -+ /* Hold the PHY in RESET for enough time till DIR is high */ -+ udelay(10); -+ } -+ -+ /* Configure TLL for 60Mhz clk for ULPI */ -+ omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck"); -+ if (IS_ERR(omap->usbtll_fck)) { -+ ret = PTR_ERR(omap->usbtll_fck); -+ goto err_tll_fck; -+ } -+ clk_enable(omap->usbtll_fck); -+ -+ omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick"); -+ if (IS_ERR(omap->usbtll_ick)) { -+ ret = PTR_ERR(omap->usbtll_ick); -+ goto err_tll_ick; -+ } -+ clk_enable(omap->usbtll_ick); -+ -+ /* perform TLL soft reset, and wait until reset is complete */ -+ ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, -+ OMAP_USBTLL_SYSCONFIG_SOFTRESET); -+ -+ /* Wait for TLL reset to complete */ -+ while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS) -+ & OMAP_USBTLL_SYSSTATUS_RESETDONE)) { -+ cpu_relax(); -+ -+ if (time_after(jiffies, timeout)) { -+ dev_dbg(omap->dev, "operation timed out\n"); -+ ret = -EINVAL; -+ goto err_sys_status; -+ } -+ } -+ -+ dev_dbg(omap->dev, "TLL RESET DONE\n"); -+ -+ /* (1<<3) = no idle mode only for initial debugging */ -+ ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, -+ OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | -+ OMAP_USBTLL_SYSCONFIG_SIDLEMODE | -+ OMAP_USBTLL_SYSCONFIG_CACTIVITY); -+ -+ -+ /* Put UHH in NoIdle/NoStandby mode */ -+ reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG); -+ reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP -+ | OMAP_UHH_SYSCONFIG_SIDLEMODE -+ | OMAP_UHH_SYSCONFIG_CACTIVITY -+ | OMAP_UHH_SYSCONFIG_MIDLEMODE); -+ reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE; -+ -+ ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg); -+ -+ reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG); -+ -+ /* setup ULPI bypass and burst configurations */ -+ reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN -+ | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN -+ | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); -+ reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; -+ -+ if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN) -+ reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; -+ if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN) -+ reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; -+ if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN) -+ reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; -+ -+ /* Bypass the TLL module for PHY mode operation */ -+ if (omap_rev() <= OMAP3430_REV_ES2_1) { -+ dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1 \n"); -+ if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) || -+ (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) || -+ (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)) -+ reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; -+ else -+ reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; -+ } else { -+ dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n"); -+ if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) -+ reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; -+ else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) -+ reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; -+ -+ if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) -+ reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; -+ else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) -+ reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; -+ -+ if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY) -+ reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; -+ else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL) -+ reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; -+ -+ } -+ ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); -+ dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg); -+ -+ -+ if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) || -+ (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) || -+ (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) { -+ -+ if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) -+ tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK; -+ if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) -+ tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK; -+ if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL) -+ tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK; -+ -+ /* Enable UTMI mode for required TLL channels */ -+ omap_usb_utmi_init(omap, tll_ch_mask); -+ } -+ -+ if (omap->phy_reset) { -+ /* Refer ISSUE1: -+ * Hold the PHY in RESET for enough time till -+ * PHY is settled and ready -+ */ -+ udelay(10); -+ -+ if (gpio_is_valid(omap->reset_gpio_port[0])) -+ gpio_set_value(omap->reset_gpio_port[0], 1); -+ -+ if (gpio_is_valid(omap->reset_gpio_port[1])) -+ gpio_set_value(omap->reset_gpio_port[1], 1); -+ } -+ -+ return 0; -+ -+err_sys_status: -+ clk_disable(omap->usbtll_ick); -+ clk_put(omap->usbtll_ick); -+ -+err_tll_ick: -+ clk_disable(omap->usbtll_fck); -+ clk_put(omap->usbtll_fck); -+ -+err_tll_fck: -+ clk_disable(omap->usbhost1_48m_fck); -+ clk_put(omap->usbhost1_48m_fck); -+ -+ if (omap->phy_reset) { -+ if (gpio_is_valid(omap->reset_gpio_port[0])) -+ gpio_free(omap->reset_gpio_port[0]); -+ -+ if (gpio_is_valid(omap->reset_gpio_port[1])) -+ gpio_free(omap->reset_gpio_port[1]); -+ } -+ -+err_host_48m_fck: -+ clk_disable(omap->usbhost2_120m_fck); -+ clk_put(omap->usbhost2_120m_fck); -+ -+err_host_120m_fck: -+ clk_disable(omap->usbhost_ick); -+ clk_put(omap->usbhost_ick); -+ -+err_host_ick: -+ return ret; -+} -+ -+static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) -+{ -+ unsigned long timeout = jiffies + msecs_to_jiffies(100); -+ -+ dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n"); -+ -+ /* Reset OMAP modules for insmod/rmmod to work */ -+ ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, -+ OMAP_UHH_SYSCONFIG_SOFTRESET); -+ while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) -+ & (1 << 0))) { -+ cpu_relax(); -+ -+ if (time_after(jiffies, timeout)) -+ dev_dbg(omap->dev, "operation timed out\n"); -+ } -+ -+ while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) -+ & (1 << 1))) { -+ cpu_relax(); -+ -+ if (time_after(jiffies, timeout)) -+ dev_dbg(omap->dev, "operation timed out\n"); -+ } -+ -+ while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) -+ & (1 << 2))) { -+ cpu_relax(); -+ -+ if (time_after(jiffies, timeout)) -+ dev_dbg(omap->dev, "operation timed out\n"); -+ } -+ -+ ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1)); -+ -+ while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS) -+ & (1 << 0))) { -+ cpu_relax(); -+ -+ if (time_after(jiffies, timeout)) -+ dev_dbg(omap->dev, "operation timed out\n"); -+ } -+ -+ if (omap->usbtll_fck != NULL) { -+ clk_disable(omap->usbtll_fck); -+ clk_put(omap->usbtll_fck); -+ omap->usbtll_fck = NULL; -+ } -+ -+ if (omap->usbhost_ick != NULL) { -+ clk_disable(omap->usbhost_ick); -+ clk_put(omap->usbhost_ick); -+ omap->usbhost_ick = NULL; -+ } -+ -+ if (omap->usbhost1_48m_fck != NULL) { -+ clk_disable(omap->usbhost1_48m_fck); -+ clk_put(omap->usbhost1_48m_fck); -+ omap->usbhost1_48m_fck = NULL; -+ } -+ -+ if (omap->usbhost2_120m_fck != NULL) { -+ clk_disable(omap->usbhost2_120m_fck); -+ clk_put(omap->usbhost2_120m_fck); -+ omap->usbhost2_120m_fck = NULL; -+ } -+ -+ if (omap->usbtll_ick != NULL) { -+ clk_disable(omap->usbtll_ick); -+ clk_put(omap->usbtll_ick); -+ omap->usbtll_ick = NULL; -+ } -+ -+ if (omap->phy_reset) { -+ if (gpio_is_valid(omap->reset_gpio_port[0])) -+ gpio_free(omap->reset_gpio_port[0]); -+ -+ if (gpio_is_valid(omap->reset_gpio_port[1])) -+ gpio_free(omap->reset_gpio_port[1]); -+ } -+ -+ dev_dbg(omap->dev, "Clock to USB host has been disabled\n"); -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+static const struct hc_driver ehci_omap_hc_driver; -+ -+/* configure so an HC device and id are always provided */ -+/* always called with process context; sleeping is OK */ -+ -+/** -+ * ehci_hcd_omap_probe - initialize TI-based HCDs -+ * -+ * Allocates basic resources for this USB host controller, and -+ * then invokes the start() method for the HCD associated with it -+ * through the hotplug entry's driver_data. -+ */ -+static int ehci_hcd_omap_probe(struct platform_device *pdev) -+{ -+ struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data; -+ struct ehci_hcd_omap *omap; -+ struct resource *res; -+ struct usb_hcd *hcd; -+ -+ int irq = platform_get_irq(pdev, 0); -+ int ret = -ENODEV; -+ -+ if (!pdata) { -+ dev_dbg(&pdev->dev, "missing platform_data\n"); -+ goto err_pdata; -+ } -+ -+ if (usb_disabled()) -+ goto err_disabled; -+ -+ omap = kzalloc(sizeof(*omap), GFP_KERNEL); -+ if (!omap) { -+ ret = -ENOMEM; -+ goto err_create_hcd; -+ } -+ -+ hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev, -+ dev_name(&pdev->dev)); -+ if (!hcd) { -+ dev_dbg(&pdev->dev, "failed to create hcd with err %d\n", ret); -+ ret = -ENOMEM; -+ goto err_create_hcd; -+ } -+ -+ platform_set_drvdata(pdev, omap); -+ omap->dev = &pdev->dev; -+ omap->phy_reset = pdata->phy_reset; -+ omap->reset_gpio_port[0] = pdata->reset_gpio_port[0]; -+ omap->reset_gpio_port[1] = pdata->reset_gpio_port[1]; -+ omap->reset_gpio_port[2] = pdata->reset_gpio_port[2]; -+ omap->port_mode[0] = pdata->port_mode[0]; -+ omap->port_mode[1] = pdata->port_mode[1]; -+ omap->port_mode[2] = pdata->port_mode[2]; -+ omap->ehci = hcd_to_ehci(hcd); -+ omap->ehci->sbrn = 0x20; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ hcd->rsrc_start = res->start; -+ hcd->rsrc_len = resource_size(res); -+ -+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); -+ if (!hcd->regs) { -+ dev_err(&pdev->dev, "EHCI ioremap failed\n"); -+ ret = -ENOMEM; -+ goto err_ioremap; -+ } -+ -+ /* we know this is the memory we want, no need to ioremap again */ -+ omap->ehci->caps = hcd->regs; -+ omap->ehci_base = hcd->regs; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); -+ omap->uhh_base = ioremap(res->start, resource_size(res)); -+ if (!omap->uhh_base) { -+ dev_err(&pdev->dev, "UHH ioremap failed\n"); -+ ret = -ENOMEM; -+ goto err_uhh_ioremap; -+ } -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2); -+ omap->tll_base = ioremap(res->start, resource_size(res)); -+ if (!omap->tll_base) { -+ dev_err(&pdev->dev, "TLL ioremap failed\n"); -+ ret = -ENOMEM; -+ goto err_tll_ioremap; -+ } -+ -+ ret = omap_start_ehc(omap, hcd); -+ if (ret) { -+ dev_dbg(&pdev->dev, "failed to start ehci\n"); -+ goto err_start; -+ } -+ -+ omap->ehci->regs = hcd->regs -+ + HC_LENGTH(readl(&omap->ehci->caps->hc_capbase)); -+ -+ /* cache this readonly data; minimize chip reads */ -+ omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params); -+ -+ /* SET 1 micro-frame Interrupt interval */ -+ writel(readl(&omap->ehci->regs->command) | (1 << 16), -+ &omap->ehci->regs->command); -+ -+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); -+ if (ret) { -+ dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret); -+ goto err_add_hcd; -+ } -+ -+ return 0; -+ -+err_add_hcd: -+ omap_stop_ehc(omap, hcd); -+ -+err_start: -+ iounmap(omap->tll_base); -+ -+err_tll_ioremap: -+ iounmap(omap->uhh_base); -+ -+err_uhh_ioremap: -+ iounmap(hcd->regs); -+ -+err_ioremap: -+ usb_put_hcd(hcd); -+ -+err_create_hcd: -+err_disabled: -+err_pdata: -+ return ret; -+} -+ -+/* may be called without controller electrically present */ -+/* may be called with controller, bus, and devices active */ -+ -+/** -+ * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs -+ * @pdev: USB Host Controller being removed -+ * -+ * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking -+ * the HCD's stop() method. It is always called from a thread -+ * context, normally "rmmod", "apmd", or something similar. -+ */ -+static int ehci_hcd_omap_remove(struct platform_device *pdev) -+{ -+ struct ehci_hcd_omap *omap = platform_get_drvdata(pdev); -+ struct usb_hcd *hcd = ehci_to_hcd(omap->ehci); -+ -+ usb_remove_hcd(hcd); -+ omap_stop_ehc(omap, hcd); -+ iounmap(hcd->regs); -+ iounmap(omap->tll_base); -+ iounmap(omap->uhh_base); -+ usb_put_hcd(hcd); -+ -+ return 0; -+} -+ -+static void ehci_hcd_omap_shutdown(struct platform_device *pdev) -+{ -+ struct ehci_hcd_omap *omap = platform_get_drvdata(pdev); -+ struct usb_hcd *hcd = ehci_to_hcd(omap->ehci); -+ -+ if (hcd->driver->shutdown) -+ hcd->driver->shutdown(hcd); -+} -+ -+static struct platform_driver ehci_hcd_omap_driver = { -+ .probe = ehci_hcd_omap_probe, -+ .remove = ehci_hcd_omap_remove, -+ .shutdown = ehci_hcd_omap_shutdown, -+ /*.suspend = ehci_hcd_omap_suspend, */ -+ /*.resume = ehci_hcd_omap_resume, */ -+ .driver = { -+ .name = "ehci-omap", -+ } -+}; -+ -+/*-------------------------------------------------------------------------*/ -+ -+static const struct hc_driver ehci_omap_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "OMAP-EHCI Host Controller", -+ .hcd_priv_size = sizeof(struct ehci_hcd), -+ -+ /* -+ * generic hardware linkage -+ */ -+ .irq = ehci_irq, -+ .flags = HCD_MEMORY | HCD_USB2, -+ -+ /* -+ * basic lifecycle operations -+ */ -+ .reset = ehci_init, -+ .start = ehci_run, -+ .stop = ehci_stop, -+ .shutdown = ehci_shutdown, -+ -+ /* -+ * managing i/o requests and associated device resources -+ */ -+ .urb_enqueue = ehci_urb_enqueue, -+ .urb_dequeue = ehci_urb_dequeue, -+ .endpoint_disable = ehci_endpoint_disable, -+ .endpoint_reset = ehci_endpoint_reset, -+ -+ /* -+ * scheduling support -+ */ -+ .get_frame_number = ehci_get_frame, -+ -+ /* -+ * root hub support -+ */ -+ .hub_status_data = ehci_hub_status_data, -+ .hub_control = ehci_hub_control, -+ .bus_suspend = ehci_bus_suspend, -+ .bus_resume = ehci_bus_resume, -+ -+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, -+}; -+ -+MODULE_ALIAS("platform:omap-ehci"); -+MODULE_AUTHOR("Texas Instruments, Inc."); -+MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>"); -+ ---- a/drivers/video/omap/dispc.c -+++ b/drivers/video/omap/dispc.c -@@ -210,6 +210,7 @@ static u32 inline dispc_read_reg(int idx - /* Select RFBI or bypass mode */ - static void enable_rfbi_mode(int enable) - { -+ void __iomem *rfbi_control; - u32 l; - - l = dispc_read_reg(DISPC_CONTROL); -@@ -222,9 +223,15 @@ static void enable_rfbi_mode(int enable) - dispc_write_reg(DISPC_CONTROL, l); - - /* Set bypass mode in RFBI module */ -- l = __raw_readl(OMAP2_IO_ADDRESS(RFBI_CONTROL)); -+ rfbi_control = ioremap(RFBI_CONTROL, SZ_1K); -+ if (!rfbi_control) { -+ pr_err("Unable to ioremap rfbi_control\n"); -+ return; -+ } -+ l = __raw_readl(rfbi_control); - l |= enable ? 0 : (1 << 1); -- __raw_writel(l, OMAP2_IO_ADDRESS(RFBI_CONTROL)); -+ __raw_writel(l, rfbi_control); -+ iounmap(rfbi_control); - } - - static void set_lcd_data_lines(int data_lines) -@@ -1373,6 +1380,7 @@ static int omap_dispc_init(struct omapfb - int r; - u32 l; - struct lcd_panel *panel = fbdev->panel; -+ void __iomem *ram_fw_base; - int tmo = 10000; - int skip_init = 0; - int i; -@@ -1453,7 +1461,13 @@ static int omap_dispc_init(struct omapfb - } - - /* L3 firewall setting: enable access to OCM RAM */ -- __raw_writel(0x402000b0, OMAP2_IO_ADDRESS(0x680050a0)); -+ ram_fw_base = ioremap(0x68005000, SZ_1K); -+ if (!ram_fw_base) { -+ dev_err(dispc.fbdev->dev, "Cannot ioremap to enable OCM RAM\n"); -+ goto fail1; -+ } -+ __raw_writel(0x402000b0, ram_fw_base + 0xa0); -+ iounmap(ram_fw_base); - - if ((r = alloc_palette_ram()) < 0) - goto fail2; diff --git a/target/linux/omap35xx/patches-2.6.32/003-enable_dss2_beagleboard.patch b/target/linux/omap35xx/patches-2.6.32/003-enable_dss2_beagleboard.patch deleted file mode 100644 index fb89a90..0000000 --- a/target/linux/omap35xx/patches-2.6.32/003-enable_dss2_beagleboard.patch +++ /dev/null @@ -1,195 +0,0 @@ ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -23,6 +23,7 @@ - #include <linux/gpio.h> - #include <linux/input.h> - #include <linux/gpio_keys.h> -+#include <linux/omapfb.h> - - #include <linux/mtd/mtd.h> - #include <linux/mtd/partitions.h> -@@ -44,6 +45,7 @@ - #include <mach/mux.h> - #include <mach/usb.h> - #include <mach/timer-gp.h> -+#include <mach/display.h> - - #include "mmc-twl4030.h" - -@@ -106,6 +108,92 @@ static struct platform_device omap3beagl - .resource = &omap3beagle_nand_resource, - }; - -+/* DSS */ -+ -+static int beagle_enable_dvi(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->reset_gpio != -1) -+ gpio_set_value(dssdev->reset_gpio, 1); -+ -+ return 0; -+} -+ -+static void beagle_disable_dvi(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->reset_gpio != -1) -+ gpio_set_value(dssdev->reset_gpio, 0); -+} -+ -+static struct omap_dss_device beagle_dvi_device = { -+ .type = OMAP_DISPLAY_TYPE_DPI, -+ .name = "dvi", -+ .driver_name = "generic_panel", -+ .phy.dpi.data_lines = 24, -+ .reset_gpio = 170, -+ .platform_enable = beagle_enable_dvi, -+ .platform_disable = beagle_disable_dvi, -+}; -+ -+static int beagle_panel_enable_tv(struct omap_dss_device *dssdev) -+{ -+ return 0; -+} -+ -+static void beagle_panel_disable_tv(struct omap_dss_device *dssdev) -+{ -+} -+ -+static struct omap_dss_device beagle_tv_device = { -+ .name = "tv", -+ .driver_name = "venc", -+ .type = OMAP_DISPLAY_TYPE_VENC, -+ .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, -+ .platform_enable = beagle_panel_enable_tv, -+ .platform_disable = beagle_panel_disable_tv, -+}; -+ -+static struct omap_dss_device *beagle_dss_devices[] = { -+ &beagle_dvi_device, -+ &beagle_tv_device, -+}; -+ -+static struct omap_dss_board_info beagle_dss_data = { -+ .num_devices = ARRAY_SIZE(beagle_dss_devices), -+ .devices = beagle_dss_devices, -+ .default_device = &beagle_dvi_device, -+}; -+ -+static struct platform_device beagle_dss_device = { -+ .name = "omapdss", -+ .id = -1, -+ .dev = { -+ .platform_data = &beagle_dss_data, -+ }, -+}; -+ -+static struct regulator_consumer_supply beagle_vdda_dac_supply = { -+ .supply = "vdda_dac", -+ .dev = &beagle_dss_device.dev, -+}; -+ -+static struct regulator_consumer_supply beagle_vdds_dsi_supply = { -+ .supply = "vdds_dsi", -+ .dev = &beagle_dss_device.dev, -+}; -+ -+static void __init beagle_display_init(void) -+{ -+ int r; -+ -+ r = gpio_request(beagle_dvi_device.reset_gpio, "DVI reset"); -+ if (r < 0) { -+ printk(KERN_ERR "Unable to get DVI reset GPIO\n"); -+ return; -+ } -+ -+ gpio_direction_output(beagle_dvi_device.reset_gpio, 0); -+} -+ - #include "sdram-micron-mt46h32m32lf-6.h" - - static struct twl4030_hsmmc_info mmc[] = { -@@ -117,15 +205,6 @@ static struct twl4030_hsmmc_info mmc[] = - {} /* Terminator */ - }; - --static struct platform_device omap3_beagle_lcd_device = { -- .name = "omap3beagle_lcd", -- .id = -1, --}; -- --static struct omap_lcd_config omap3_beagle_lcd_config __initdata = { -- .ctrl_name = "internal", --}; -- - static struct regulator_consumer_supply beagle_vmmc1_supply = { - .supply = "vmmc", - }; -@@ -181,15 +260,6 @@ static struct twl4030_gpio_platform_data - .setup = beagle_twl_gpio_setup, - }; - --static struct regulator_consumer_supply beagle_vdac_supply = { -- .supply = "vdac", -- .dev = &omap3_beagle_lcd_device.dev, --}; -- --static struct regulator_consumer_supply beagle_vdvi_supply = { -- .supply = "vdvi", -- .dev = &omap3_beagle_lcd_device.dev, --}; - - /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ - static struct regulator_init_data beagle_vmmc1 = { -@@ -226,13 +296,14 @@ static struct regulator_init_data beagle - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, -+ .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, -- .consumer_supplies = &beagle_vdac_supply, -+ .consumer_supplies = &beagle_vdda_dac_supply, - }; - - /* VPLL2 for digital video outputs */ -@@ -247,7 +318,7 @@ static struct regulator_init_data beagle - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, -- .consumer_supplies = &beagle_vdvi_supply, -+ .consumer_supplies = &beagle_vdds_dsi_supply, - }; - - static struct twl4030_usb_data beagle_usb_data = { -@@ -340,7 +411,6 @@ static struct platform_device keys_gpio - }; - - static struct omap_board_config_kernel omap3_beagle_config[] __initdata = { -- { OMAP_TAG_LCD, &omap3_beagle_lcd_config }, - }; - - static void __init omap3_beagle_init_irq(void) -@@ -357,7 +427,7 @@ static void __init omap3_beagle_init_irq - } - - static struct platform_device *omap3_beagle_devices[] __initdata = { -- &omap3_beagle_lcd_device, -+ &beagle_dss_device, - &leds_gpio, - &keys_gpio, - }; -@@ -420,9 +490,6 @@ static void __init omap3_beagle_init(voi - omap_serial_init(); - - omap_cfg_reg(J25_34XX_GPIO170); -- gpio_request(170, "DVI_nPD"); -- /* REVISIT leave DVI powered down until it's needed ... */ -- gpio_direction_output(170, true); - - usb_musb_init(); - usb_ehci_init(&ehci_pdata); diff --git a/target/linux/omap35xx/patches-2.6.32/004-compile_fix_dispc.patch b/target/linux/omap35xx/patches-2.6.32/004-compile_fix_dispc.patch deleted file mode 100644 index ab76ee2..0000000 --- a/target/linux/omap35xx/patches-2.6.32/004-compile_fix_dispc.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/drivers/video/omap2/dss/dispc.c -+++ b/drivers/video/omap2/dss/dispc.c -@@ -3077,8 +3077,8 @@ static void _omap_dispc_initial_config(v - REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); - - /* L3 firewall setting: enable access to OCM RAM */ -- if (cpu_is_omap24xx()) -- __raw_writel(0x402000b0, OMAP2_IO_ADDRESS(0x680050a0)); -+// if (cpu_is_omap24xx()) -+// __raw_writel(0x402000b0, OMAP2_IO_ADDRESS(0x680050a0)); - - _dispc_setup_color_conv_coef(); - diff --git a/target/linux/omap35xx/patches-2.6.36/001-expose_omap3_die_id.patch b/target/linux/omap35xx/patches-2.6.36/001-expose_omap3_die_id.patch deleted file mode 100644 index 6d3bed4..0000000 --- a/target/linux/omap35xx/patches-2.6.36/001-expose_omap3_die_id.patch +++ /dev/null @@ -1,48 +0,0 @@ -diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c -index 9a879f9..9cefef4 100644 ---- a/arch/arm/mach-omap2/id.c -+++ b/arch/arm/mach-omap2/id.c -@@ -85,6 +85,9 @@ EXPORT_SYMBOL(omap_type); - - #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) - -+static ssize_t die_id_show(struct kobject *, struct kobj_attribute *, char *); -+static struct kobj_attribute die_id_attr = __ATTR(die_id, 0444, die_id_show, NULL); -+ - struct omap_id { - u16 hawkeye; /* Silicon type (Hawkeye id) */ - u8 dev; /* Device type from production_id reg */ -@@ -104,6 +107,17 @@ static struct omap_id omap_ids[] __initdata = { - static void __iomem *tap_base; - static u16 tap_prod_id; - -+static ssize_t die_id_show(struct kobject *kobj, struct kobj_attribute *attr, -+ char *buf) -+{ -+ return sprintf(buf, "Die ID: %08x%08x%08x%08x\n", -+ read_tap_reg(OMAP_TAP_DIE_ID_0), -+ read_tap_reg(OMAP_TAP_DIE_ID_1), -+ read_tap_reg(OMAP_TAP_DIE_ID_2), -+ read_tap_reg(OMAP_TAP_DIE_ID_3)); -+ -+} -+ - void omap_get_die_id(struct omap_die_id *odi) - { - odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); -@@ -457,3 +471,15 @@ void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) - else - tap_prod_id = 0x0208; - } -+ -+int __init export_omap_die_id(void) -+{ -+ int error; -+ -+ error = sysfs_create_file(power_kobj, &die_id_attr.attr); -+ if (error) -+ printk(KERN_ERR "sysfs_create_file failed: %d\n", error); -+ return error; -+} -+ -+late_initcall(export_omap_die_id); diff --git a/target/linux/omap35xx/patches-2.6.36/002-omap-nand-remove-hardware-ECC-as-default.patch b/target/linux/omap35xx/patches-2.6.36/002-omap-nand-remove-hardware-ECC-as-default.patch deleted file mode 100644 index 038c1af..0000000 --- a/target/linux/omap35xx/patches-2.6.36/002-omap-nand-remove-hardware-ECC-as-default.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 859158bfab7e72af440622fb9731bcaef4e7d6dc Mon Sep 17 00:00:00 2001 -From: Sukumar Ghorai <s-ghorai@ti.com> -Date: Fri, 19 Nov 2010 14:45:26 +0000 -Subject: [PATCH] omap: nand: remove hardware ECC as default - -Commit 2c01946c6b9ebaa5a89710bc42ca224a7f52f227 (omap3 nand: cleanup -virtual address usages) wrongly enabled CONFIG_MTD_NAND_OMAP_HWECC -which breaks boards like beagle and pandora that use software ECC -for write. - -Boards like beagle and pandora uses sw ecc for write (e.g. binary flushed -from u-boot) and read from kernel. - -Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> -Acked-by: David Woodhouse <David.Woodhouse@intel.com> -[tony@atomide.com: updated comments] -Signed-off-by: Tony Lindgren <tony@atomide.com> ---- - drivers/mtd/nand/omap2.c | 1 - - 1 files changed, 0 insertions(+), 1 deletions(-) - -diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c -index cd41c58..15682ec 100644 ---- a/drivers/mtd/nand/omap2.c -+++ b/drivers/mtd/nand/omap2.c -@@ -7,7 +7,6 @@ - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ --#define CONFIG_MTD_NAND_OMAP_HWECC - - #include <linux/platform_device.h> - #include <linux/dma-mapping.h> --- -1.7.0.4 - diff --git a/target/linux/omap35xx/patches-2.6.36/003-change_partition_table.patch b/target/linux/omap35xx/patches-2.6.36/003-change_partition_table.patch deleted file mode 100644 index 65ba45a..0000000 --- a/target/linux/omap35xx/patches-2.6.36/003-change_partition_table.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- linux-2.6.36.1/arch/arm/mach-omap2/board-overo.c.old 2011-02-18 12:24:24.000000000 +0100 -+++ linux-2.6.36.1/arch/arm/mach-omap2/board-overo.c 2011-02-18 12:38:40.000000000 +0100 -@@ -250,13 +250,28 @@ - .size = 2 * NAND_BLOCK_SIZE, - }, - { -- .name = "linux", -+ .name = "kernel 0", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ -- .size = 32 * NAND_BLOCK_SIZE, -+ .size = 16 * NAND_BLOCK_SIZE, - }, - { -- .name = "rootfs", -+ .name = "kernel 1", -+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x480000 */ -+ .size = 16 * NAND_BLOCK_SIZE, -+ }, -+ { -+ .name = "rootfs 0", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ -+ .size = 512 * NAND_BLOCK_SIZE, -+ }, -+ { -+ .name = "rootfs 1", -+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x2e80000 */ -+ .size = 512 * NAND_BLOCK_SIZE, -+ }, -+ { -+ .name = "data", -+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x5680000 */ - .size = MTDPART_SIZ_FULL, - }, - }; diff --git a/target/linux/omap35xx/patches-2.6.36/004-nand_subpage_align.patch b/target/linux/omap35xx/patches-2.6.36/004-nand_subpage_align.patch deleted file mode 100644 index 4bb854d..0000000 --- a/target/linux/omap35xx/patches-2.6.36/004-nand_subpage_align.patch +++ /dev/null @@ -1,22 +0,0 @@ -diff -urN linux-2.6.38.old/drivers/mtd/nand/omap2.c linux-2.6.38/drivers/mtd/nand/omap2.c ---- linux-2.6.38.old/drivers/mtd/nand/omap2.c 2011-03-15 02:20:32.000000000 +0100 -+++ linux-2.6.38/drivers/mtd/nand/omap2.c 2011-03-21 15:05:21.000000000 +0100 -@@ -245,6 +245,18 @@ - int ret = 0; - u32 *p = (u32 *)buf; - -+ /* u32 align the buffer and read */ -+ /* NB: This assumes the buf ptr can be aligned *down* which is a valid. -+ * Assumption when dealing with ecc buffers etc. -+ */ -+ u32 addr = (u32)p; -+ -+ int diff = addr & 3; -+ addr -= diff; -+ len += diff; -+ len = (len + 3) & ~3; -+ p = (u32 *)addr; -+ - /* take care of subpage reads */ - if (len % 4) { - if (info->nand.options & NAND_BUSWIDTH_16) diff --git a/target/linux/omap35xx/patches-2.6.36/005-add_cti_usbids.patch b/target/linux/omap35xx/patches-2.6.36/005-add_cti_usbids.patch deleted file mode 100644 index 3ff9c6b..0000000 --- a/target/linux/omap35xx/patches-2.6.36/005-add_cti_usbids.patch +++ /dev/null @@ -1,24 +0,0 @@ -diff -urN linux-2.6.36.1.old/drivers/usb/serial/ftdi_sio.c linux-2.6.36.1/drivers/usb/serial/ftdi_sio.c ---- linux-2.6.36.1.old/drivers/usb/serial/ftdi_sio.c 2010-11-22 20:03:49.000000000 +0100 -+++ linux-2.6.36.1/drivers/usb/serial/ftdi_sio.c 2011-03-23 11:23:23.000000000 +0100 -@@ -794,6 +794,9 @@ - { USB_DEVICE(FTDI_VID, FTDI_SCIENCESCOPE_LOGBOOKML_PID) }, - { USB_DEVICE(FTDI_VID, FTDI_SCIENCESCOPE_LS_LOGBOOK_PID) }, - { USB_DEVICE(FTDI_VID, FTDI_SCIENCESCOPE_HS_LOGBOOK_PID) }, -+ /* CTI Devices */ -+ { USB_DEVICE(FTDI_VID, FTDI_CTI_Mini_PID) }, -+ { USB_DEVICE(FTDI_VID, FTDI_CTI_Nano_PID) }, - { }, /* Optional parameter entry */ - { } /* Terminating entry */ - }; -diff -urN linux-2.6.36.1.old/drivers/usb/serial/ftdi_sio_ids.h linux-2.6.36.1/drivers/usb/serial/ftdi_sio_ids.h ---- linux-2.6.36.1.old/drivers/usb/serial/ftdi_sio_ids.h 2010-11-22 20:03:49.000000000 +0100 -+++ linux-2.6.36.1/drivers/usb/serial/ftdi_sio_ids.h 2011-03-23 11:20:57.000000000 +0100 -@@ -1100,3 +1100,7 @@ - #define FTDI_SCIENCESCOPE_LOGBOOKML_PID 0xFF18 - #define FTDI_SCIENCESCOPE_LS_LOGBOOK_PID 0xFF1C - #define FTDI_SCIENCESCOPE_HS_LOGBOOK_PID 0xFF1D -+ -+/* www.cti-lean.com RS485 converter */ -+#define FTDI_CTI_Mini_PID 0xF608 /* USB-485 Mini */ -+#define FTDI_CTI_Nano_PID 0xF60B /* USB-Nano-485 */ diff --git a/target/linux/omap35xx/patches-3.0/001-change_partition_table.patch b/target/linux/omap35xx/patches-3.0/001-change_partition_table.patch deleted file mode 100644 index 65ba45a..0000000 --- a/target/linux/omap35xx/patches-3.0/001-change_partition_table.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- linux-2.6.36.1/arch/arm/mach-omap2/board-overo.c.old 2011-02-18 12:24:24.000000000 +0100 -+++ linux-2.6.36.1/arch/arm/mach-omap2/board-overo.c 2011-02-18 12:38:40.000000000 +0100 -@@ -250,13 +250,28 @@ - .size = 2 * NAND_BLOCK_SIZE, - }, - { -- .name = "linux", -+ .name = "kernel 0", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ -- .size = 32 * NAND_BLOCK_SIZE, -+ .size = 16 * NAND_BLOCK_SIZE, - }, - { -- .name = "rootfs", -+ .name = "kernel 1", -+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x480000 */ -+ .size = 16 * NAND_BLOCK_SIZE, -+ }, -+ { -+ .name = "rootfs 0", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ -+ .size = 512 * NAND_BLOCK_SIZE, -+ }, -+ { -+ .name = "rootfs 1", -+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x2e80000 */ -+ .size = 512 * NAND_BLOCK_SIZE, -+ }, -+ { -+ .name = "data", -+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x5680000 */ - .size = MTDPART_SIZ_FULL, - }, - }; diff --git a/target/linux/omap35xx/patches-3.0/002-fix_twl_rtc.patch b/target/linux/omap35xx/patches-3.0/002-fix_twl_rtc.patch deleted file mode 100644 index ef243ea..0000000 --- a/target/linux/omap35xx/patches-3.0/002-fix_twl_rtc.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/rtc/rtc-twl.c -+++ b/drivers/rtc/rtc-twl.c -@@ -362,14 +362,6 @@ static irqreturn_t twl_rtc_interrupt(int - int res; - u8 rd_reg; - --#ifdef CONFIG_LOCKDEP -- /* WORKAROUND for lockdep forcing IRQF_DISABLED on us, which -- * we don't want and can't tolerate. Although it might be -- * friendlier not to borrow this thread context... -- */ -- local_irq_enable(); --#endif -- - res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG); - if (res) - goto out; -@@ -462,7 +454,7 @@ static int __devinit twl_rtc_probe(struc - if (ret < 0) - goto out1; - -- ret = request_irq(irq, twl_rtc_interrupt, -+ ret = request_threaded_irq(irq, NULL, twl_rtc_interrupt, - IRQF_TRIGGER_RISING, - dev_name(&rtc->dev), rtc); - if (ret < 0) { |