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Diffstat (limited to 'target/linux/ramips/patches-3.18/0015-MIPS-ralink-cleanup-early_printk.patch')
-rw-r--r--target/linux/ramips/patches-3.18/0015-MIPS-ralink-cleanup-early_printk.patch104
1 files changed, 0 insertions, 104 deletions
diff --git a/target/linux/ramips/patches-3.18/0015-MIPS-ralink-cleanup-early_printk.patch b/target/linux/ramips/patches-3.18/0015-MIPS-ralink-cleanup-early_printk.patch
deleted file mode 100644
index 1e5c90b..0000000
--- a/target/linux/ramips/patches-3.18/0015-MIPS-ralink-cleanup-early_printk.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From e410b0069ee7c318a5b556f39b8b16814330a208 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 24 Jan 2014 17:01:17 +0100
-Subject: [PATCH 15/57] MIPS: ralink: cleanup early_printk
-
-Add support for the new MT7621/8 SoC and kill ifdefs.
-Cleanup some whitespace error while we are at it.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/early_printk.c | 45 ++++++++++++++++++++++++++-------------
- 1 file changed, 30 insertions(+), 15 deletions(-)
-
---- a/arch/mips/ralink/early_printk.c
-+++ b/arch/mips/ralink/early_printk.c
-@@ -12,21 +12,26 @@
- #include <asm/addrspace.h>
-
- #ifdef CONFIG_SOC_RT288X
--#define EARLY_UART_BASE 0x300c00
-+#define EARLY_UART_BASE 0x300c00
-+#define CHIPID_BASE 0x300004
-+#elif defined(CONFIG_SOC_MT7621)
-+#define EARLY_UART_BASE 0x1E000c00
-+#define CHIPID_BASE 0x1E000004
- #else
--#define EARLY_UART_BASE 0x10000c00
-+#define EARLY_UART_BASE 0x10000c00
-+#define CHIPID_BASE 0x10000004
- #endif
-
--#define UART_REG_RX 0x00
--#define UART_REG_TX 0x04
--#define UART_REG_IER 0x08
--#define UART_REG_IIR 0x0c
--#define UART_REG_FCR 0x10
--#define UART_REG_LCR 0x14
--#define UART_REG_MCR 0x18
--#define UART_REG_LSR 0x1c
-+#define MT7628_CHIP_NAME1 0x20203832
-+
-+#define UART_REG_TX 0x04
-+#define UART_REG_LCR 0x0c
-+#define UART_REG_LSR 0x14
-+#define UART_REG_LSR_RT2880 0x1c
-
- static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
-+static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
-+static int init_complete;
-
- static inline void uart_w32(u32 val, unsigned reg)
- {
-@@ -38,11 +43,46 @@ static inline u32 uart_r32(unsigned reg)
- return __raw_readl(uart_membase + reg);
- }
-
-+static inline int soc_is_mt7628(void)
-+{
-+ return IS_ENABLED(CONFIG_SOC_MT7620) &&
-+ (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
-+}
-+
-+static inline void find_uart_base(void)
-+{
-+ int i;
-+
-+ if (!soc_is_mt7628())
-+ return;
-+
-+ for (i = 0; i < 3; i++) {
-+ u32 reg = uart_r32(UART_REG_LCR + (0x100 * i));
-+
-+ if (!reg)
-+ continue;
-+
-+ uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE + (0x100 * i));
-+ break;
-+ }
-+}
-+
- void prom_putchar(unsigned char ch)
- {
-- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
-- ;
-- uart_w32(ch, UART_REG_TX);
-- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
-- ;
-+ if (!init_complete) {
-+ find_uart_base();
-+ init_complete = 1;
-+ }
-+
-+ if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
-+ uart_w32(ch, UART_TX);
-+ while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
-+ ;
-+ } else {
-+ while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
-+ ;
-+ uart_w32(ch, UART_REG_TX);
-+ while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
-+ ;
-+ }
- }