diff options
Diffstat (limited to 'target/linux/ramips/patches-3.9/0159-NET-MIPS-add-ralink-SoC-ethernet-driver.patch')
| -rw-r--r-- | target/linux/ramips/patches-3.9/0159-NET-MIPS-add-ralink-SoC-ethernet-driver.patch | 4732 |
1 files changed, 4732 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.9/0159-NET-MIPS-add-ralink-SoC-ethernet-driver.patch b/target/linux/ramips/patches-3.9/0159-NET-MIPS-add-ralink-SoC-ethernet-driver.patch new file mode 100644 index 0000000..4f894e8 --- /dev/null +++ b/target/linux/ramips/patches-3.9/0159-NET-MIPS-add-ralink-SoC-ethernet-driver.patch @@ -0,0 +1,4732 @@ +From 12ea1efe1496e936d1cecc4de97ee55321aceee9 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Mon, 22 Apr 2013 23:20:03 +0200 +Subject: [PATCH 159/164] NET: MIPS: add ralink SoC ethernet driver + +Add support for Ralink FE and ESW. + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 + + arch/mips/ralink/rt305x.c | 1 + + drivers/net/ethernet/Kconfig | 1 + + drivers/net/ethernet/Makefile | 1 + + drivers/net/ethernet/ralink/Kconfig | 31 + + drivers/net/ethernet/ralink/Makefile | 18 + + drivers/net/ethernet/ralink/esw_rt3052.c | 1463 ++++++++++++++++++++ + drivers/net/ethernet/ralink/esw_rt3052.h | 32 + + drivers/net/ethernet/ralink/gsw_mt7620a.c | 1027 ++++++++++++++ + drivers/net/ethernet/ralink/gsw_mt7620a.h | 29 + + drivers/net/ethernet/ralink/mdio.c | 245 ++++ + drivers/net/ethernet/ralink/mdio.h | 29 + + drivers/net/ethernet/ralink/mdio_rt2880.c | 163 +++ + drivers/net/ethernet/ralink/mdio_rt2880.h | 25 + + drivers/net/ethernet/ralink/ralink_soc_eth.c | 759 ++++++++++ + drivers/net/ethernet/ralink/ralink_soc_eth.h | 372 +++++ + drivers/net/ethernet/ralink/soc_mt7620.c | 111 ++ + drivers/net/ethernet/ralink/soc_rt2880.c | 51 + + drivers/net/ethernet/ralink/soc_rt305x.c | 102 ++ + drivers/net/ethernet/ralink/soc_rt3883.c | 59 + + 20 files changed, 4546 insertions(+) + create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h + create mode 100644 drivers/net/ethernet/ralink/Kconfig + create mode 100644 drivers/net/ethernet/ralink/Makefile + create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c + create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h + create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c + create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h + create mode 100644 drivers/net/ethernet/ralink/mdio.c + create mode 100644 drivers/net/ethernet/ralink/mdio.h + create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c + create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h + create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c + create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h + create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c + create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c + create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c + create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c + +diff --git a/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h +new file mode 100644 +index 0000000..2098c5c +--- /dev/null ++++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h +@@ -0,0 +1,27 @@ ++/* ++ * Ralink RT305x SoC platform device registration ++ * ++ * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef _RT305X_ESW_PLATFORM_H ++#define _RT305X_ESW_PLATFORM_H ++ ++enum { ++ RT305X_ESW_VLAN_CONFIG_NONE = 0, ++ RT305X_ESW_VLAN_CONFIG_LLLLW, ++ RT305X_ESW_VLAN_CONFIG_WLLLL, ++}; ++ ++struct rt305x_esw_platform_data ++{ ++ u8 vlan_config; ++ u32 reg_initval_fct2; ++ u32 reg_initval_fpa2; ++}; ++ ++#endif /* _RT305X_ESW_PLATFORM_H */ +diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c +index ca7ee3a..1a6b458 100644 +--- a/arch/mips/ralink/rt305x.c ++++ b/arch/mips/ralink/rt305x.c +@@ -221,6 +221,7 @@ void __init ralink_clk_init(void) + } + + ralink_clk_add("cpu", cpu_rate); ++ ralink_clk_add("sys", sys_rate); + ralink_clk_add("10000b00.spi", sys_rate); + ralink_clk_add("10000100.timer", wdt_rate); + ralink_clk_add("10000120.watchdog", wdt_rate); +diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig +index ed956e0..0b3caa1 100644 +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -135,6 +135,7 @@ config ETHOC + source "drivers/net/ethernet/packetengines/Kconfig" + source "drivers/net/ethernet/pasemi/Kconfig" + source "drivers/net/ethernet/qlogic/Kconfig" ++source "drivers/net/ethernet/ralink/Kconfig" + source "drivers/net/ethernet/realtek/Kconfig" + source "drivers/net/ethernet/renesas/Kconfig" + source "drivers/net/ethernet/rdc/Kconfig" +diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile +index 8268d85..508c494 100644 +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -53,6 +53,7 @@ obj-$(CONFIG_ETHOC) += ethoc.o + obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/ + obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/ + obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/ ++obj-$(CONFIG_NET_RALINK) += ralink/ + obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/ + obj-$(CONFIG_SH_ETH) += renesas/ + obj-$(CONFIG_NET_VENDOR_RDC) += rdc/ +diff --git a/drivers/net/ethernet/ralink/Kconfig b/drivers/net/ethernet/ralink/Kconfig +new file mode 100644 +index 0000000..ca2c9ad +--- /dev/null ++++ b/drivers/net/ethernet/ralink/Kconfig +@@ -0,0 +1,31 @@ ++config NET_RALINK ++ tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver" ++ depends on RALINK ++ help ++ This driver supports the ethernet mac inside the ralink wisocs ++ ++if NET_RALINK ++ ++config NET_RALINK_MDIO ++ def_bool NET_RALINK ++ depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620) ++ select PHYLIB ++ ++config NET_RALINK_MDIO_RT2880 ++ def_bool NET_RALINK ++ depends on (SOC_RT288X || SOC_RT3883) ++ select NET_RALINK_MDIO ++ ++config NET_RALINK_ESW_RT3052 ++ def_bool NET_RALINK ++ depends on SOC_RT305X ++ select PHYLIB ++ select SWCONFIG ++ ++config NET_RALINK_GSW_MT7620 ++ def_bool NET_RALINK ++ depends on SOC_MT7620 ++ select NET_RALINK_MDIO ++ select PHYLIB ++ select SWCONFIG ++endif +diff --git a/drivers/net/ethernet/ralink/Makefile b/drivers/net/ethernet/ralink/Makefile +new file mode 100644 +index 0000000..a38fa21 +--- /dev/null ++++ b/drivers/net/ethernet/ralink/Makefile +@@ -0,0 +1,18 @@ ++# ++# Makefile for the Ralink SoCs built-in ethernet macs ++# ++ ++ralink-eth-y += ralink_soc_eth.o ++ ++ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o ++ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o ++ ++ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052) += esw_rt3052.o ++ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620a.o ++ ++ralink-eth-$(CONFIG_SOC_RT288X) += soc_rt2880.o ++ralink-eth-$(CONFIG_SOC_RT305X) += soc_rt305x.o ++ralink-eth-$(CONFIG_SOC_RT3883) += soc_rt3883.o ++ralink-eth-$(CONFIG_SOC_MT7620) += soc_mt7620.o ++ ++obj-$(CONFIG_NET_RALINK) += ralink-eth.o +diff --git a/drivers/net/ethernet/ralink/esw_rt3052.c b/drivers/net/ethernet/ralink/esw_rt3052.c +new file mode 100644 +index 0000000..b937062 +--- /dev/null ++++ b/drivers/net/ethernet/ralink/esw_rt3052.c +@@ -0,0 +1,1463 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/dma-mapping.h> ++#include <linux/init.h> ++#include <linux/skbuff.h> ++#include <linux/etherdevice.h> ++#include <linux/ethtool.h> ++#include <linux/platform_device.h> ++#include <linux/of_device.h> ++#include <linux/clk.h> ++#include <linux/of_net.h> ++#include <linux/of_mdio.h> ++ ++#include <asm/mach-ralink/ralink_regs.h> ++ ++#include "ralink_soc_eth.h" ++ ++#include <linux/ioport.h> ++#include <linux/switch.h> ++#include <linux/mii.h> ++ ++#include <ralink_regs.h> ++#include <asm/mach-ralink/rt305x.h> ++#include <asm/mach-ralink/rt305x_esw_platform.h> ++ ++/* ++ * HW limitations for this switch: ++ * - No large frame support (PKT_MAX_LEN at most 1536) ++ * - Can't have untagged vlan and tagged vlan on one port at the same time, ++ * though this might be possible using the undocumented PPE. ++ */ ++ ++#define RT305X_ESW_REG_ISR 0x00 ++#define RT305X_ESW_REG_IMR 0x04 ++#define RT305X_ESW_REG_FCT0 0x08 ++#define RT305X_ESW_REG_PFC1 0x14 ++#define RT305X_ESW_REG_ATS 0x24 ++#define RT305X_ESW_REG_ATS0 0x28 ++#define RT305X_ESW_REG_ATS1 0x2c ++#define RT305X_ESW_REG_ATS2 0x30 ++#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n)) ++#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n)) ++#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n)) ++#define RT305X_ESW_REG_POA 0x80 ++#define RT305X_ESW_REG_FPA 0x84 ++#define RT305X_ESW_REG_SOCPC 0x8c ++#define RT305X_ESW_REG_POC0 0x90 ++#define RT305X_ESW_REG_POC1 0x94 ++#define RT305X_ESW_REG_POC2 0x98 ++#define RT305X_ESW_REG_SGC 0x9c ++#define RT305X_ESW_REG_STRT 0xa0 ++#define RT305X_ESW_REG_PCR0 0xc0 ++#define RT305X_ESW_REG_PCR1 0xc4 ++#define RT305X_ESW_REG_FPA2 0xc8 ++#define RT305X_ESW_REG_FCT2 0xcc ++#define RT305X_ESW_REG_SGC2 0xe4 ++#define RT305X_ESW_REG_P0LED 0xa4 ++#define RT305X_ESW_REG_P1LED 0xa8 ++#define RT305X_ESW_REG_P2LED 0xac ++#define RT305X_ESW_REG_P3LED 0xb0 ++#define RT305X_ESW_REG_P4LED 0xb4 ++#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x)) ++#define RT305X_ESW_REG_P1PC 0xec ++#define RT305X_ESW_REG_P2PC 0xf0 ++#define RT305X_ESW_REG_P3PC 0xf4 ++#define RT305X_ESW_REG_P4PC 0xf8 ++#define RT305X_ESW_REG_P5PC 0xfc ++ ++#define RT305X_ESW_LED_LINK 0 ++#define RT305X_ESW_LED_100M 1 ++#define RT305X_ESW_LED_DUPLEX 2 ++#define RT305X_ESW_LED_ACTIVITY 3 ++#define RT305X_ESW_LED_COLLISION 4 ++#define RT305X_ESW_LED_LINKACT 5 ++#define RT305X_ESW_LED_DUPLCOLL 6 ++#define RT305X_ESW_LED_10MACT 7 ++#define RT305X_ESW_LED_100MACT 8 ++/* Additional led states not in datasheet: */ ++#define RT305X_ESW_LED_BLINK 10 ++#define RT305X_ESW_LED_ON 12 ++ ++#define RT305X_ESW_LINK_S 25 ++#define RT305X_ESW_DUPLEX_S 9 ++#define RT305X_ESW_SPD_S 0 ++ ++#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16 ++#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13) ++#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8 ++ ++#define RT305X_ESW_PCR1_WT_DONE BIT(0) ++ ++#define RT305X_ESW_ATS_TIMEOUT (5 * HZ) ++#define RT305X_ESW_PHY_TIMEOUT (5 * HZ) ++ ++#define RT305X_ESW_PVIDC_PVID_M 0xfff ++#define RT305X_ESW_PVIDC_PVID_S 12 ++ ++#define RT305X_ESW_VLANI_VID_M 0xfff ++#define RT305X_ESW_VLANI_VID_S 12 ++ ++#define RT305X_ESW_VMSC_MSC_M 0xff ++#define RT305X_ESW_VMSC_MSC_S 8 ++ ++#define RT305X_ESW_SOCPC_DISUN2CPU_S 0 ++#define RT305X_ESW_SOCPC_DISMC2CPU_S 8 ++#define RT305X_ESW_SOCPC_DISBC2CPU_S 16 ++#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25) ++ ++#define RT305X_ESW_POC0_EN_BP_S 0 ++#define RT305X_ESW_POC0_EN_FC_S 8 ++#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16 ++#define RT305X_ESW_POC0_DIS_PORT_M 0x7f ++#define RT305X_ESW_POC0_DIS_PORT_S 23 ++ ++#define RT305X_ESW_POC2_UNTAG_EN_M 0xff ++#define RT305X_ESW_POC2_UNTAG_EN_S 0 ++#define RT305X_ESW_POC2_ENAGING_S 8 ++#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16 ++ ++#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f ++#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0 ++#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f ++#define RT305X_ESW_SGC2_LAN_PMAP_S 24 ++ ++#define RT305X_ESW_PFC1_EN_VLAN_M 0xff ++#define RT305X_ESW_PFC1_EN_VLAN_S 16 ++#define RT305X_ESW_PFC1_EN_TOS_S 24 ++ ++#define RT305X_ESW_VLAN_NONE 0xfff ++ ++#define RT305X_ESW_GSC_BC_STROM_MASK 0x3 ++#define RT305X_ESW_GSC_BC_STROM_SHIFT 4 ++ ++#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3 ++#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23 ++ ++#define RT305X_ESW_POA_LINK_MASK 0x1f ++#define RT305X_ESW_POA_LINK_SHIFT 25 ++ ++#define RT305X_ESW_PORT_ST_CHG BIT(26) ++#define RT305X_ESW_PORT0 0 ++#define RT305X_ESW_PORT1 1 ++#define RT305X_ESW_PORT2 2 ++#define RT305X_ESW_PORT3 3 ++#define RT305X_ESW_PORT4 4 ++#define RT305X_ESW_PORT5 5 ++#define RT305X_ESW_PORT6 6 ++ ++#define RT305X_ESW_PORTS_NONE 0 ++ ++#define RT305X_ESW_PMAP_LLLLLL 0x3f ++#define RT305X_ESW_PMAP_LLLLWL 0x2f ++#define RT305X_ESW_PMAP_WLLLLL 0x3e ++ ++#define RT305X_ESW_PORTS_INTERNAL \ ++ (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \ ++ BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \ ++ BIT(RT305X_ESW_PORT4)) ++ ++#define RT305X_ESW_PORTS_NOCPU \ ++ (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5)) ++ ++#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6) ++ ++#define RT305X_ESW_PORTS_ALL \ ++ (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU) ++ ++#define RT305X_ESW_NUM_VLANS 16 ++#define RT305X_ESW_NUM_VIDS 4096 ++#define RT305X_ESW_NUM_PORTS 7 ++#define RT305X_ESW_NUM_LANWAN 6 ++#define RT305X_ESW_NUM_LEDS 5 ++ ++#define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x)) ++#define RT5350_EWS_REG_LED_POLARITY 0x168 ++#define RT5350_RESET_EPHY BIT(24) ++#define SYSC_REG_RESET_CTRL 0x34 ++ ++enum { ++ /* Global attributes. */ ++ RT305X_ESW_ATTR_ENABLE_VLAN, ++ RT305X_ESW_ATTR_ALT_VLAN_DISABLE, ++ RT305X_ESW_ATTR_BC_STATUS, ++ RT305X_ESW_ATTR_LED_FREQ, ++ /* Port attributes. */ ++ RT305X_ESW_ATTR_PORT_DISABLE, ++ RT305X_ESW_ATTR_PORT_DOUBLETAG, ++ RT305X_ESW_ATTR_PORT_UNTAG, ++ RT305X_ESW_ATTR_PORT_LED, ++ RT305X_ESW_ATTR_PORT_LAN, ++ RT305X_ESW_ATTR_PORT_RECV_BAD, ++ RT305X_ESW_ATTR_PORT_RECV_GOOD, ++ RT5350_ESW_ATTR_PORT_TR_BAD, ++ RT5350_ESW_ATTR_PORT_TR_GOOD, ++}; ++ ++struct esw_port { ++ bool disable; ++ bool doubletag; ++ bool untag; ++ u8 led; ++ u16 pvid; ++}; ++ ++struct esw_vlan { ++ u8 ports; ++ u16 vid; ++}; ++ ++struct rt305x_esw { ++ struct device *dev; ++ void __iomem *base; ++ int irq; ++ const struct rt305x_esw_platform_data *pdata; ++ /* Protects against concurrent register rmw operations. */ ++ spinlock_t reg_rw_lock; ++ ++ unsigned char port_map; ++ unsigned int reg_initval_fct2; ++ unsigned int reg_initval_fpa2; ++ unsigned int reg_led_polarity; ++ ++ ++ struct switch_dev swdev; ++ bool global_vlan_enable; ++ bool alt_vlan_disable; ++ int bc_storm_protect; ++ int led_frequency; ++ struct esw_vlan vlans[RT305X_ESW_NUM_VLANS]; ++ struct esw_port ports[RT305X_ESW_NUM_PORTS]; ++ ++}; ++ ++static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg) ++{ ++ __raw_writel(val, esw->base + reg); ++} ++ ++static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg) ++{ ++ return __raw_readl(esw->base + reg); ++} ++ ++static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask, ++ unsigned long val) ++{ ++ unsigned long t; ++ ++ t = __raw_readl(esw->base + reg) & ~mask; ++ __raw_writel(t | val, esw->base + reg); ++} ++ ++static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask, ++ unsigned long val) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&esw->reg_rw_lock, flags); ++ esw_rmw_raw(esw, reg, mask, val); ++ spin_unlock_irqrestore(&esw->reg_rw_lock, flags); ++} ++ ++static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register, ++ u32 write_data) ++{ ++ unsigned long t_start = jiffies; ++ int ret = 0; ++ ++ while (1) { ++ if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) & ++ RT305X_ESW_PCR1_WT_DONE)) ++ break; ++ if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) { ++ ret = 1; ++ goto out; ++ } ++ } ++ ++ write_data &= 0xffff; ++ esw_w32(esw, ++ (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) | ++ (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) | ++ (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD, ++ RT305X_ESW_REG_PCR0); ++ ++ t_start = jiffies; ++ while (1) { ++ if (esw_r32(esw, RT305X_ESW_REG_PCR1) & ++ RT305X_ESW_PCR1_WT_DONE) ++ break; ++ ++ if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) { ++ ret = 1; ++ break; ++ } ++ } ++out: ++ if (ret) ++ printk(KERN_ERR "ramips_eth: MDIO timeout\n"); ++ return ret; ++} ++ ++static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan) ++{ ++ unsigned s; ++ unsigned val; ++ ++ s = RT305X_ESW_VLANI_VID_S * (vlan % 2); ++ val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2)); ++ val = (val >> s) & RT305X_ESW_VLANI_VID_M; ++ ++ return val; ++} ++ ++static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid) ++{ ++ unsigned s; ++ ++ s = RT305X_ESW_VLANI_VID_S * (vlan % 2); ++ esw_rmw(esw, ++ RT305X_ESW_REG_VLANI(vlan / 2), ++ RT305X_ESW_VLANI_VID_M << s, ++ (vid & RT305X_ESW_VLANI_VID_M) << s); ++} ++ ++static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port) ++{ ++ unsigned s, val; ++ ++ s = RT305X_ESW_PVIDC_PVID_S * (port % 2); ++ val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2)); ++ return (val >> s) & RT305X_ESW_PVIDC_PVID_M; ++} ++ ++static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid) ++{ ++ unsigned s; ++ ++ s = RT305X_ESW_PVIDC_PVID_S * (port % 2); ++ esw_rmw(esw, ++ RT305X_ESW_REG_PVIDC(port / 2), ++ RT305X_ESW_PVIDC_PVID_M << s, ++ (pvid & RT305X_ESW_PVIDC_PVID_M) << s); ++} ++ ++static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan) ++{ ++ unsigned s, val; ++ ++ s = RT305X_ESW_VMSC_MSC_S * (vlan % 4); ++ val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4)); ++ val = (val >> s) & RT305X_ESW_VMSC_MSC_M; ++ ++ return val; ++} ++ ++static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc) ++{ ++ unsigned s; ++ ++ s = RT305X_ESW_VMSC_MSC_S * (vlan % 4); ++ esw_rmw(esw, ++ RT305X_ESW_REG_VMSC(vlan / 4), ++ RT305X_ESW_VMSC_MSC_M << s, ++ (msc & RT305X_ESW_VMSC_MSC_M) << s); ++} ++ ++static unsigned esw_get_port_disable(struct rt305x_esw *esw) ++{ ++ unsigned reg; ++ reg = esw_r32(esw, RT305X_ESW_REG_POC0); ++ return (reg >> RT305X_ESW_POC0_DIS_PORT_S) & ++ RT305X_ESW_POC0_DIS_PORT_M; ++} ++ ++static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask) ++{ ++ unsigned old_mask; ++ unsigned enable_mask; ++ unsigned changed; ++ int i; ++ ++ old_mask = esw_get_port_disable(esw); ++ changed = old_mask ^ disable_mask; ++ enable_mask = old_mask & disable_mask; ++ ++ /* enable before writing to MII */ ++ esw_rmw(esw, RT305X_ESW_REG_POC0, ++ (RT305X_ESW_POC0_DIS_PORT_M << ++ RT305X_ESW_POC0_DIS_PORT_S), ++ enable_mask << RT305X_ESW_POC0_DIS_PORT_S); ++ ++ for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) { ++ if (!(changed & (1 << i))) ++ continue; ++ if (disable_mask & (1 << i)) { ++ /* disable */ ++ rt305x_mii_write(esw, i, MII_BMCR, ++ BMCR_PDOWN); ++ } else { ++ /* enable */ ++ rt305x_mii_write(esw, i, MII_BMCR, ++ BMCR_FULLDPLX | ++ BMCR_ANENABLE | ++ BMCR_ANRESTART | ++ BMCR_SPEED100); ++ } ++ } ++ ++ /* disable after writing to MII */ ++ esw_rmw(esw, RT305X_ESW_REG_POC0, ++ (RT305X_ESW_POC0_DIS_PORT_M << ++ RT305X_ESW_POC0_DIS_PORT_S), ++ disable_mask << RT305X_ESW_POC0_DIS_PORT_S); ++} ++ ++static void esw_set_gsc(struct rt305x_esw *esw) ++{ ++ esw_rmw(esw, RT305X_ESW_REG_SGC, ++ RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT, ++ esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT); ++ esw_rmw(esw, RT305X_ESW_REG_SGC, ++ RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT, ++ esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT); ++} ++ ++static int esw_apply_config(struct switch_dev *dev); ++ ++static void esw_hw_init(struct rt305x_esw *esw) ++{ ++ int i; ++ u8 port_disable = 0; ++ u8 port_map = RT305X_ESW_PMAP_LLLLLL; ++ ++ /* vodoo from original driver */ ++ esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0); ++ esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2); ++ /* Port priority 1 for all ports, vlan enabled. */ ++ esw_w32(esw, 0x00005555 | ++ (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S), ++ RT305X_ESW_REG_PFC1); ++ ++ /* Enable Back Pressure, and Flow Control */ ++ esw_w32(esw, ++ ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) | ++ (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)), ++ RT305X_ESW_REG_POC0); ++ ++ /* Enable Aging, and VLAN TAG removal */ ++ esw_w32(esw, ++ ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) | ++ (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)), ++ RT305X_ESW_REG_POC2); ++ ++ if (esw->reg_initval_fct2) ++ esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2); ++ else ++ esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2); ++ ++ /* ++ * 300s aging timer, max packet len 1536, broadcast storm prevention ++ * disabled, disable collision abort, mac xor48 hash, 10 packet back ++ * pressure jam, GMII disable was_transmit, back pressure disabled, ++ * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all ++ * ports. ++ */ ++ esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC); ++ ++ /* Setup SoC Port control register */ ++ esw_w32(esw, ++ (RT305X_ESW_SOCPC_CRC_PADDING | ++ (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) | ++ (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) | ++ (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)), ++ RT305X_ESW_REG_SOCPC); ++ ++ if (esw->reg_initval_fpa2) ++ esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2); ++ else ++ esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2); ++ esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA); ++ ++ /* Force Link/Activity on ports */ ++ esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED); ++ esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED); ++ esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED); ++ esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED); ++ esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED); ++ ++ /* Copy disabled port configuration from bootloader setup */ ++ port_disable = esw_get_port_disable(esw); ++ for (i = 0; i < 6; i++) ++ esw->ports[i].disable = (port_disable & (1 << i)) != 0; ++ ++ if (soc_is_rt3352()) { ++ /* reset EPHY */ ++ u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); ++ rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL); ++ rt_sysc_w32(val, SYSC_REG_RESET_CTRL); ++ ++ rt305x_mii_write(esw, 0, 31, 0x8000); ++ for (i = 0; i < 5; i++) { ++ if (esw->ports[i].disable) { ++ rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN); ++ } else { ++ rt305x_mii_write(esw, i, MII_BMCR, ++ BMCR_FULLDPLX | ++ BMCR_ANENABLE | ++ BMCR_SPEED100); ++ } ++ /* TX10 waveform coefficient LSB=0 disable PHY */ ++ rt305x_mii_write(esw, i, 26, 0x1601); ++ /* TX100/TX10 AD/DA current bias */ ++ rt305x_mii_write(esw, i, 29, 0x7016); ++ /* TX100 slew rate control */ ++ rt305x_mii_write(esw, i, 30, 0x0038); ++ } ++ ++ /* select global register */ ++ rt305x_mii_write(esw, 0, 31, 0x0); ++ /* enlarge agcsel threshold 3 and threshold 2 */ ++ rt305x_mii_write(esw, 0, 1, 0x4a40); ++ /* enlarge agcsel threshold 5 and threshold 4 */ ++ rt305x_mii_write(esw, 0, 2, 0x6254); ++ /* enlarge agcsel threshold */ ++ rt305x_mii_write(esw, 0, 3, 0xa17f); ++ rt305x_mii_write(esw, 0,12, 0x7eaa); ++ /* longer TP_IDL tail length */ ++ rt305x_mii_write(esw, 0, 14, 0x65); ++ /* increased squelch pulse count threshold. */ ++ rt305x_mii_write(esw, 0, 16, 0x0684); ++ /* set TX10 signal amplitude threshold to minimum */ ++ rt305x_mii_write(esw, 0, 17, 0x0fe0); ++ /* set squelch amplitude to higher threshold */ ++ rt305x_mii_write(esw, 0, 18, 0x40ba); ++ /* tune TP_IDL tail and head waveform, enable power down slew rate control */ ++ rt305x_mii_write(esw, 0, 22, 0x253f); ++ /* set PLL/Receive bias current are calibrated */ ++ rt305x_mii_write(esw, 0, 27, 0x2fda); ++ /* change PLL/Receive bias current to internal(RT3350) */ ++ rt305x_mii_write(esw, 0, 28, 0xc410); ++ /* change PLL bias current to internal(RT3052_MP3) */ ++ rt305x_mii_write(esw, 0, 29, 0x598b); ++ /* select local register */ ++ rt305x_mii_write(esw, 0, 31, 0x8000); ++ } else if (soc_is_rt5350()) { ++ /* reset EPHY */ ++ u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); ++ rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL); ++ rt_sysc_w32(val, SYSC_REG_RESET_CTRL); ++ ++ /* set the led polarity */ ++ esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY); ++ ++ /* local registers */ ++ rt305x_mii_write(esw, 0, 31, 0x8000); ++ for (i = 0; i < 5; i++) { ++ if (esw->ports[i].disable) { ++ rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN); ++ } else { ++ rt305x_mii_write(esw, i, MII_BMCR, ++ BMCR_FULLDPLX | ++ BMCR_ANENABLE | ++ BMCR_SPEED100); ++ } ++ /* TX10 waveform coefficient LSB=0 disable PHY */ ++ rt305x_mii_write(esw, i, 26, 0x1601); ++ /* TX100/TX10 AD/DA current bias */ ++ rt305x_mii_write(esw, i, 29, 0x7015); ++ /* TX100 slew rate control */ ++ rt305x_mii_write(esw, i, 30, 0x0038); ++ } ++ ++ /* global registers */ ++ rt305x_mii_write(esw, 0, 31, 0x0); ++ /* enlarge agcsel threshold 3 and threshold 2 */ ++ rt305x_mii_write(esw, 0, 1, 0x4a40); ++ /* enlarge agcsel threshold 5 and threshold 4 */ ++ rt305x_mii_write(esw, 0, 2, 0x6254); ++ /* enlarge agcsel threshold 6 */ ++ rt305x_mii_write(esw, 0, 3, 0xa17f); ++ rt305x_mii_write(esw, 0, 12, 0x7eaa); ++ /* longer TP_IDL tail length */ ++ rt305x_mii_write(esw, 0, 14, 0x65); ++ /* increased squelch pulse count threshold. */ ++ rt305x_mii_write(esw, 0, 16, 0x0684); ++ /* set TX10 signal amplitude threshold to minimum */ ++ rt305x_mii_write(esw, 0, 17, 0x0fe0); ++ /* set squelch amplitude to higher threshold */ ++ rt305x_mii_write(esw, 0, 18, 0x40ba); ++ /* tune TP_IDL tail and head waveform, enable power down slew rate control */ ++ rt305x_mii_write(esw, 0, 22, 0x253f); ++ /* set PLL/Receive bias current are calibrated */ ++ rt305x_mii_write(esw, 0, 27, 0x2fda); ++ /* change PLL/Receive bias current to internal(RT3350) */ ++ rt305x_mii_write(esw, 0, 28, 0xc410); ++ /* change PLL bias current to internal(RT3052_MP3) */ ++ rt305x_mii_write(esw, 0, 29, 0x598b); ++ /* select local register */ ++ rt305x_mii_write(esw, 0, 31, 0x8000); ++ } else { ++ rt305x_mii_write(esw, 0, 31, 0x8000); ++ for (i = 0; i < 5; i++) { ++ if (esw->ports[i].disable) { ++ rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN); ++ } else { ++ rt305x_mii_write(esw, i, MII_BMCR, ++ BMCR_FULLDPLX | ++ BMCR_ANENABLE | ++ BMCR_SPEED100); ++ } ++ /* TX10 waveform coefficient */ ++ rt305x_mii_write(esw, i, 26, 0x1601); ++ /* TX100/TX10 AD/DA current bias */ ++ rt305x_mii_write(esw, i, 29, 0x7058); ++ /* TX100 slew rate control */ ++ rt305x_mii_write(esw, i, 30, 0x0018); ++ } ++ ++ /* PHY IOT */ ++ /* select global register */ ++ rt305x_mii_write(esw, 0, 31, 0x0); ++ /* tune TP_IDL tail and head waveform */ ++ rt305x_mii_write(esw, 0, 22, 0x052f); ++ /* set TX10 signal amplitude threshold to minimum */ ++ rt305x_mii_write(esw, 0, 17, 0x0fe0); ++ /* set squelch amplitude to higher threshold */ ++ rt305x_mii_write(esw, 0, 18, 0x40ba); ++ /* longer TP_IDL tail length */ ++ rt305x_mii_write(esw, 0, 14, 0x65); ++ /* select local register */ ++ rt305x_mii_write(esw, 0, 31, 0x8000); ++ } ++ ++ if (esw->port_map) ++ port_map = esw->port_map; ++ else ++ port_map = RT305X_ESW_PMAP_LLLLLL; ++ ++ /* ++ * Unused HW feature, but still nice to be consistent here... ++ * This is also exported to userspace ('lan' attribute) so it's ++ * conveniently usable to decide which ports go into the wan vlan by ++ * default. ++ */ ++ esw_rmw(esw, RT305X_ESW_REG_SGC2, ++ RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S, ++ port_map << RT305X_ESW_SGC2_LAN_PMAP_S); ++ ++ /* make the switch leds blink */ ++ for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) ++ esw->ports[i].led = 0x05; ++ ++ /* Apply the empty config. */ ++ esw_apply_config(&esw->swdev); ++ ++ /* Only unmask the port change interrupt */ ++ esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR); ++} ++ ++static irqreturn_t esw_interrupt(int irq, void *_esw) ++{ ++ struct rt305x_esw *esw = (struct rt305x_esw *) _esw; ++ u32 status; ++ ++ status = esw_r32(esw, RT305X_ESW_REG_ISR); ++ if (status & RT305X_ESW_PORT_ST_CHG) { ++ u32 link = esw_r32(esw, RT305X_ESW_REG_POA); ++ link >>= RT305X_ESW_POA_LINK_SHIFT; ++ link &= RT305X_ESW_POA_LINK_MASK; ++ dev_info(esw->dev, "link changed 0x%02X\n", link); ++ } ++ esw_w32(esw, status, RT305X_ESW_REG_ISR); ++ ++ return IRQ_HANDLED; ++} ++ ++static int esw_apply_config(struct switch_dev *dev) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ int i; ++ u8 disable = 0; ++ u8 doubletag = 0; ++ u8 en_vlan = 0; ++ u8 untag = 0; ++ ++ for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) { ++ u32 vid, vmsc; ++ if (esw->global_vlan_enable) { ++ vid = esw->vlans[i].vid; ++ vmsc = esw->vlans[i].ports; ++ } else { ++ vid = RT305X_ESW_VLAN_NONE; ++ vmsc = RT305X_ESW_PORTS_NONE; ++ } ++ esw_set_vlan_id(esw, i, vid); ++ esw_set_vmsc(esw, i, vmsc); ++ } ++ ++ for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) { ++ u32 pvid; ++ disable |= esw->ports[i].disable << i; ++ if (esw->global_vlan_enable) { ++ doubletag |= esw->ports[i].doubletag << i; ++ en_vlan |= 1 << i; ++ untag |= esw->ports[i].untag << i; ++ pvid = esw->ports[i].pvid; ++ } else { ++ int x = esw->alt_vlan_disable ? 0 : 1; ++ doubletag |= x << i; ++ en_vlan |= x << i; ++ untag |= x << i; ++ pvid = 0; ++ } ++ esw_set_pvid(esw, i, pvid); ++ if (i < RT305X_ESW_NUM_LEDS) ++ esw_w32(esw, esw->ports[i].led, ++ RT305X_ESW_REG_P0LED + 4*i); ++ } ++ ++ esw_set_gsc(esw); ++ esw_set_port_disable(esw, disable); ++ esw_rmw(esw, RT305X_ESW_REG_SGC2, ++ (RT305X_ESW_SGC2_DOUBLE_TAG_M << ++ RT305X_ESW_SGC2_DOUBLE_TAG_S), ++ doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S); ++ esw_rmw(esw, RT305X_ESW_REG_PFC1, ++ RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S, ++ en_vlan << RT305X_ESW_PFC1_EN_VLAN_S); ++ esw_rmw(esw, RT305X_ESW_REG_POC2, ++ RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S, ++ untag << RT305X_ESW_POC2_UNTAG_EN_S); ++ ++ if (!esw->global_vlan_enable) { ++ /* ++ * Still need to put all ports into vlan 0 or they'll be ++ * isolated. ++ * NOTE: vlan 0 is special, no vlan tag is prepended ++ */ ++ esw_set_vlan_id(esw, 0, 0); ++ esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL); ++ } ++ ++ return 0; ++} ++ ++static int esw_reset_switch(struct switch_dev *dev) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ ++ esw->global_vlan_enable = 0; ++ memset(esw->ports, 0, sizeof(esw->ports)); ++ memset(esw->vlans, 0, sizeof(esw->vlans)); ++ esw_hw_init(esw); ++ ++ return 0; ++} ++ ++static int esw_get_vlan_enable(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ ++ val->value.i = esw->global_vlan_enable; ++ ++ return 0; ++} ++ ++static int esw_set_vlan_enable(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ ++ esw->global_vlan_enable = val->value.i != 0; ++ ++ return 0; ++} ++ ++static int esw_get_alt_vlan_disable(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ ++ val->value.i = esw->alt_vlan_disable; ++ ++ return 0; ++} ++ ++static int esw_set_alt_vlan_disable(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ ++ esw->alt_vlan_disable = val->value.i != 0; ++ ++ return 0; ++} ++ ++static int ++rt305x_esw_set_bc_status(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ ++ esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK; ++ ++ return 0; ++} ++ ++static int ++rt305x_esw_get_bc_status(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ ++ val->value.i = esw->bc_storm_protect; ++ ++ return 0; ++} ++ ++static int ++rt305x_esw_set_led_freq(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ ++ esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK; ++ ++ return 0; ++} ++ ++static int ++rt305x_esw_get_led_freq(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ ++ val->value.i = esw->led_frequency; ++ ++ return 0; ++} ++ ++static int esw_get_port_link(struct switch_dev *dev, ++ int port, ++ struct switch_port_link *link) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ u32 speed, poa; ++ ++ if (port < 0 || port >= RT305X_ESW_NUM_PORTS) ++ return -EINVAL; ++ ++ poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port; ++ ++ link->link = (poa >> RT305X_ESW_LINK_S) & 1; ++ link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1; ++ if (port < RT305X_ESW_NUM_LEDS) { ++ speed = (poa >> RT305X_ESW_SPD_S) & 1; ++ } else { ++ if (port == RT305X_ESW_NUM_PORTS - 1) ++ poa >>= 1; ++ speed = (poa >> RT305X_ESW_SPD_S) & 3; ++ } ++ switch (speed) { ++ case 0: ++ link->speed = SWITCH_PORT_SPEED_10; ++ break; ++ case 1: ++ link->speed = SWITCH_PORT_SPEED_100; ++ break; ++ case 2: ++ case 3: /* forced gige speed can be 2 or 3 */ ++ link->speed = SWITCH_PORT_SPEED_1000; ++ break; ++ default: ++ link->speed = SWITCH_PORT_SPEED_UNKNOWN; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int esw_get_port_bool(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ int idx = val->port_vlan; ++ u32 x, reg, shift; ++ ++ if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS) ++ return -EINVAL; ++ ++ switch (attr->id) { ++ case RT305X_ESW_ATTR_PORT_DISABLE: ++ reg = RT305X_ESW_REG_POC0; ++ shift = RT305X_ESW_POC0_DIS_PORT_S; ++ break; ++ case RT305X_ESW_ATTR_PORT_DOUBLETAG: ++ reg = RT305X_ESW_REG_SGC2; ++ shift = RT305X_ESW_SGC2_DOUBLE_TAG_S; ++ break; ++ case RT305X_ESW_ATTR_PORT_UNTAG: ++ reg = RT305X_ESW_REG_POC2; ++ shift = RT305X_ESW_POC2_UNTAG_EN_S; ++ break; ++ case RT305X_ESW_ATTR_PORT_LAN: ++ reg = RT305X_ESW_REG_SGC2; ++ shift = RT305X_ESW_SGC2_LAN_PMAP_S; ++ if (idx >= RT305X_ESW_NUM_LANWAN) ++ return -EINVAL; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ x = esw_r32(esw, reg); ++ val->value.i = (x >> (idx + shift)) & 1; ++ ++ return 0; ++} ++ ++static int esw_set_port_bool(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ int idx = val->port_vlan; ++ ++ if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS || ++ val->value.i < 0 || val->value.i > 1) ++ return -EINVAL; ++ ++ switch (attr->id) { ++ case RT305X_ESW_ATTR_PORT_DISABLE: ++ esw->ports[idx].disable = val->value.i; ++ break; ++ case RT305X_ESW_ATTR_PORT_DOUBLETAG: ++ esw->ports[idx].doubletag = val->value.i; ++ break; ++ case RT305X_ESW_ATTR_PORT_UNTAG: ++ esw->ports[idx].untag = val->value.i; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int esw_get_port_recv_badgood(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ int idx = val->port_vlan; ++ int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16; ++ u32 reg; ++ ++ if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN) ++ return -EINVAL; ++ reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx)); ++ val->value.i = (reg >> shift) & 0xffff; ++ ++ return 0; ++} ++ ++static int ++esw_get_port_tr_badgood(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ ++ int idx = val->port_vlan; ++ int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16; ++ u32 reg; ++ ++ if (!soc_is_rt5350()) ++ return -EINVAL; ++ ++ if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN) ++ return -EINVAL; ++ ++ reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx)); ++ val->value.i = (reg >> shift) & 0xffff; ++ ++ return 0; ++} ++ ++static int esw_get_port_led(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ int idx = val->port_vlan; ++ ++ if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS || ++ idx >= RT305X_ESW_NUM_LEDS) ++ return -EINVAL; ++ ++ val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx); ++ ++ return 0; ++} ++ ++static int esw_set_port_led(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ int idx = val->port_vlan; ++ ++ if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS) ++ return -EINVAL; ++ ++ esw->ports[idx].led = val->value.i; ++ ++ return 0; ++} ++ ++static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ ++ if (port >= RT305X_ESW_NUM_PORTS) ++ return -EINVAL; ++ ++ *val = esw_get_pvid(esw, port); ++ ++ return 0; ++} ++ ++static int esw_set_port_pvid(struct switch_dev *dev, int port, int val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ ++ if (port >= RT305X_ESW_NUM_PORTS) ++ return -EINVAL; ++ ++ esw->ports[port].pvid = val; ++ ++ return 0; ++} ++ ++static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ u32 vmsc, poc2; ++ int vlan_idx = -1; ++ int i; ++ ++ val->len = 0; ++ ++ if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS) ++ return -EINVAL; ++ ++ /* valid vlan? */ ++ for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) { ++ if (esw_get_vlan_id(esw, i) == val->port_vlan && ++ esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) { ++ vlan_idx = i; ++ break; ++ } ++ } ++ ++ if (vlan_idx == -1) ++ return -EINVAL; ++ ++ vmsc = esw_get_vmsc(esw, vlan_idx); ++ poc2 = esw_r32(esw, RT305X_ESW_REG_POC2); ++ ++ for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) { ++ struct switch_port *p; ++ int port_mask = 1 << i; ++ ++ if (!(vmsc & port_mask)) ++ continue; ++ ++ p = &val->value.ports[val->len++]; ++ p->id = i; ++ if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S)) ++ p->flags = 0; ++ else ++ p->flags = 1 << SWITCH_PORT_FLAG_TAGGED; ++ } ++ ++ return 0; ++} ++ ++static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev); ++ int ports; ++ int vlan_idx = -1; ++ int i; ++ ++ if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS || ++ val->len > RT305X_ESW_NUM_PORTS) ++ return -EINVAL; ++ ++ /* one of the already defined vlans? */ ++ for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) { ++ if (esw->vlans[i].vid == val->port_vlan && ++ esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) { ++ vlan_idx = i; ++ break; ++ } ++ } ++ ++ /* select a free slot */ ++ for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) { ++ if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE) ++ vlan_idx = i; ++ } ++ ++ /* bail if all slots are in use */ ++ if (vlan_idx == -1) ++ return -EINVAL; ++ ++ ports = RT305X_ESW_PORTS_NONE; ++ for (i = 0; i < val->len; i++) { ++ struct switch_port *p = &val->value.ports[i]; ++ int port_mask = 1 << p->id; ++ bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)); ++ ++ if (p->id >= RT305X_ESW_NUM_PORTS) ++ return -EINVAL; ++ ++ ports |= port_mask; ++ esw->ports[p->id].untag = untagged; ++ } ++ esw->vlans[vlan_idx].ports = ports; ++ if (ports == RT305X_ESW_PORTS_NONE) ++ esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE; ++ else ++ esw->vlans[vlan_idx].vid = val->port_vlan; ++ ++ return 0; ++} ++ ++static const struct switch_attr esw_global[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "enable_vlan", ++ .description = "VLAN mode (1:enabled)", ++ .max = 1, ++ .id = RT305X_ESW_ATTR_ENABLE_VLAN, ++ .get = esw_get_vlan_enable, ++ .set = esw_set_vlan_enable, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "alternate_vlan_disable", ++ .description = "Use en_vlan instead of doubletag to disable" ++ " VLAN mode", ++ .max = 1, ++ .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE, ++ .get = esw_get_alt_vlan_disable, ++ .set = esw_set_alt_vlan_disable, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "bc_storm_protect", ++ .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)", ++ .max = 3, ++ .id = RT305X_ESW_ATTR_BC_STATUS, ++ .get = rt305x_esw_get_bc_status, ++ .set = rt305x_esw_set_bc_status, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "led_frequency", ++ .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)", ++ .max = 3, ++ .id = RT305X_ESW_ATTR_LED_FREQ, ++ .get = rt305x_esw_get_led_freq, ++ .set = rt305x_esw_set_led_freq, ++ } ++}; ++ ++static const struct switch_attr esw_port[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "disable", ++ .description = "Port state (1:disabled)", ++ .max = 1, ++ .id = RT305X_ESW_ATTR_PORT_DISABLE, ++ .get = esw_get_port_bool, ++ .set = esw_set_port_bool, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "doubletag", ++ .description = "Double tagging for incoming vlan packets " ++ "(1:enabled)", ++ .max = 1, ++ .id = RT305X_ESW_ATTR_PORT_DOUBLETAG, ++ .get = esw_get_port_bool, ++ .set = esw_set_port_bool, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "untag", ++ .description = "Untag (1:strip outgoing vlan tag)", ++ .max = 1, ++ .id = RT305X_ESW_ATTR_PORT_UNTAG, ++ .get = esw_get_port_bool, ++ .set = esw_set_port_bool, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "led", ++ .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity," ++ " 4:collision, 5:linkact, 6:duplcoll, 7:10mact," ++ " 8:100mact, 10:blink, 11:off, 12:on)", ++ .max = 15, ++ .id = RT305X_ESW_ATTR_PORT_LED, ++ .get = esw_get_port_led, ++ .set = esw_set_port_led, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "lan", ++ .description = "HW port group (0:wan, 1:lan)", ++ .max = 1, ++ .id = RT305X_ESW_ATTR_PORT_LAN, ++ .get = esw_get_port_bool, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "recv_bad", ++ .description = "Receive bad packet counter", ++ .id = RT305X_ESW_ATTR_PORT_RECV_BAD, ++ .get = esw_get_port_recv_badgood, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "recv_good", ++ .description = "Receive good packet counter", ++ .id = RT305X_ESW_ATTR_PORT_RECV_GOOD, ++ .get = esw_get_port_recv_badgood, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "tr_bad", ++ ++ .description = "Transmit bad packet counter. rt5350 only", ++ .id = RT5350_ESW_ATTR_PORT_TR_BAD, ++ .get = esw_get_port_tr_badgood, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "tr_good", ++ ++ .description = "Transmit good packet counter. rt5350 only", ++ .id = RT5350_ESW_ATTR_PORT_TR_GOOD, ++ .get = esw_get_port_tr_badgood, ++ }, ++}; ++ ++static const struct switch_attr esw_vlan[] = { ++}; ++ ++static const struct switch_dev_ops esw_ops = { ++ .attr_global = { ++ .attr = esw_global, ++ .n_attr = ARRAY_SIZE(esw_global), ++ }, ++ .attr_port = { ++ .attr = esw_port, ++ .n_attr = ARRAY_SIZE(esw_port), ++ }, ++ .attr_vlan = { ++ .attr = esw_vlan, ++ .n_attr = ARRAY_SIZE(esw_vlan), ++ }, ++ .get_vlan_ports = esw_get_vlan_ports, ++ .set_vlan_ports = esw_set_vlan_ports, ++ .get_port_pvid = esw_get_port_pvid, ++ .set_port_pvid = esw_set_port_pvid, ++ .get_port_link = esw_get_port_link, ++ .apply_config = esw_apply_config, ++ .reset_switch = esw_reset_switch, ++}; ++ ++static struct rt305x_esw_platform_data rt3050_esw_data = { ++ /* All ports are LAN ports. */ ++ .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE, ++ .reg_initval_fct2 = 0x00d6500c, ++ /* ++ * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1, ++ * turbo mii off, rgmi 3.3v off ++ * port5: disabled ++ * port6: enabled, gige, full-duplex, rx/tx-flow-control ++ */ ++ .reg_initval_fpa2 = 0x3f502b28, ++}; ++ ++static const struct of_device_id ralink_esw_match[] = { ++ { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ralink_esw_match); ++ ++static int esw_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ const struct rt305x_esw_platform_data *pdata; ++ const __be32 *port_map, *reg_init; ++ struct rt305x_esw *esw; ++ struct switch_dev *swdev; ++ struct resource *res, *irq; ++ int err; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) { ++ const struct of_device_id *match; ++ match = of_match_device(ralink_esw_match, &pdev->dev); ++ if (match) ++ pdata = (struct rt305x_esw_platform_data *) match->data; ++ } ++ if (!pdata) ++ return -EINVAL; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "no memory resource found\n"); ++ return -ENOMEM; ++ } ++ ++ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!irq) { ++ dev_err(&pdev->dev, "no irq resource found\n"); ++ return -ENOMEM; ++ } ++ ++ esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL); ++ if (!esw) { ++ dev_err(&pdev->dev, "no memory for private data\n"); ++ return -ENOMEM; ++ } ++ ++ esw->dev = &pdev->dev; ++ esw->irq = irq->start; ++ esw->base = ioremap(res->start, resource_size(res)); ++ if (!esw->base) { ++ dev_err(&pdev->dev, "ioremap failed\n"); ++ err = -ENOMEM; ++ goto free_esw; ++ } ++ ++ port_map = of_get_property(np, "ralink,portmap", NULL); ++ if (port_map) ++ esw->port_map = be32_to_cpu(*port_map); ++ ++ reg_init = of_get_property(np, "ralink,fct2", NULL); ++ if (reg_init) ++ esw->reg_initval_fct2 = be32_to_cpu(*reg_init); ++ ++ reg_init = of_get_property(np, "ralink,fpa2", NULL); ++ if (reg_init) ++ esw->reg_initval_fpa2 = be32_to_cpu(*reg_init); ++ ++ reg_init = of_get_property(np, "ralink,led_polarity", NULL); ++ if (reg_init) ++ esw->reg_led_polarity = be32_to_cpu(*reg_init); ++ ++ swdev = &esw->swdev; ++ swdev->of_node = pdev->dev.of_node; ++ swdev->name = "rt305x-esw"; ++ swdev->alias = "rt305x"; ++ swdev->cpu_port = RT305X_ESW_PORT6; ++ swdev->ports = RT305X_ESW_NUM_PORTS; ++ swdev->vlans = RT305X_ESW_NUM_VIDS; ++ swdev->ops = &esw_ops; ++ ++ err = register_switch(swdev, NULL); ++ if (err < 0) { ++ dev_err(&pdev->dev, "register_switch failed\n"); ++ goto unmap_base; ++ } ++ ++ platform_set_drvdata(pdev, esw); ++ ++ esw->pdata = pdata; ++ spin_lock_init(&esw->reg_rw_lock); ++ ++ esw_hw_init(esw); ++ ++ esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR); ++ esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR); ++ request_irq(esw->irq, esw_interrupt, 0, "esw", esw); ++ ++ return 0; ++ ++unmap_base: ++ iounmap(esw->base); ++free_esw: ++ kfree(esw); ++ return err; ++} ++ ++static int esw_remove(struct platform_device *pdev) ++{ ++ struct rt305x_esw *esw; ++ ++ esw = platform_get_drvdata(pdev); ++ if (esw) { ++ unregister_switch(&esw->swdev); ++ platform_set_drvdata(pdev, NULL); ++ iounmap(esw->base); ++ kfree(esw); ++ } ++ ++ return 0; ++} ++ ++static struct platform_driver esw_driver = { ++ .probe = esw_probe, ++ .remove = esw_remove, ++ .driver = { ++ .name = "rt305x-esw", ++ .owner = THIS_MODULE, ++ .of_match_table = ralink_esw_match, ++ }, ++}; ++ ++int __init rtesw_init(void) ++{ ++ return platform_driver_register(&esw_driver); ++} ++ ++void rtesw_exit(void) ++{ ++ platform_driver_unregister(&esw_driver); ++} +diff --git a/drivers/net/ethernet/ralink/esw_rt3052.h b/drivers/net/ethernet/ralink/esw_rt3052.h +new file mode 100644 +index 0000000..2ced3dff +--- /dev/null ++++ b/drivers/net/ethernet/ralink/esw_rt3052.h +@@ -0,0 +1,32 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#ifndef _RALINK_ESW_RT3052_H__ ++#define _RALINK_ESW_RT3052_H__ ++ ++#ifdef CONFIG_NET_RALINK_ESW_RT3052 ++ ++int __init rtesw_init(void); ++void rtesw_exit(void); ++ ++#else ++ ++static inline int __init rtesw_init(void) { return 0; } ++static inline void rtesw_exit(void) { } ++ ++#endif ++#endif +diff --git a/drivers/net/ethernet/ralink/gsw_mt7620a.c b/drivers/net/ethernet/ralink/gsw_mt7620a.c +new file mode 100644 +index 0000000..9fa6a54 +--- /dev/null ++++ b/drivers/net/ethernet/ralink/gsw_mt7620a.c +@@ -0,0 +1,1027 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/dma-mapping.h> ++#include <linux/init.h> ++#include <linux/skbuff.h> ++#include <linux/etherdevice.h> ++#include <linux/ethtool.h> ++#include <linux/platform_device.h> ++#include <linux/of_device.h> ++#include <linux/clk.h> ++#include <linux/of_net.h> ++#include <linux/of_mdio.h> ++#include <linux/of_irq.h> ++#include <linux/of_address.h> ++#include <linux/switch.h> ++ ++#include <asm/mach-ralink/ralink_regs.h> ++ ++#include "ralink_soc_eth.h" ++ ++#include <linux/ioport.h> ++#include <linux/switch.h> ++#include <linux/mii.h> ++ ++#include <ralink_regs.h> ++#include <asm/mach-ralink/mt7620.h> ++ ++#include "ralink_soc_eth.h" ++#include "gsw_mt7620a.h" ++#include "mdio.h" ++ ++#define GSW_REG_PHY_TIMEOUT (5 * HZ) ++ ++#define MT7620A_GSW_REG_PIAC 0x7004 ++ ++#define GSW_NUM_VLANS 16 ++#define GSW_NUM_VIDS 4096 ++#define GSW_NUM_PORTS 7 ++#define GSW_PORT6 6 ++ ++#define GSW_MDIO_ACCESS BIT(31) ++#define GSW_MDIO_READ BIT(19) ++#define GSW_MDIO_WRITE BIT(18) ++#define GSW_MDIO_START BIT(16) ++#define GSW_MDIO_ADDR_SHIFT 20 ++#define GSW_MDIO_REG_SHIFT 25 ++ ++#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100)) ++#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100)) ++#define GSW_REG_SMACCR0 0x3fE4 ++#define GSW_REG_SMACCR1 0x3fE8 ++#define GSW_REG_CKGCR 0x3ff0 ++ ++#define GSW_REG_IMR 0x7008 ++#define GSW_REG_ISR 0x700c ++ ++#define SYSC_REG_CFG1 0x14 ++ ++#define PORT_IRQ_ST_CHG 0x7f ++ ++#define GSW_VLAN_VTCR 0x90 ++#define GSW_VLAN_VTCR_VID_M 0xfff ++#define GSW_VLAN_ID(_x) (0x100 + (4 * (_x))) ++#define GSW_VLAN_ID_VID_S 12 ++#define GSW_VLAN_ID_VID_M 0xfff ++ ++#define GSW_VAWD1 0x94 ++#define GSW_VAWD1_VTAG_EN BIT(28) ++#define GSW_VAWD1_PORTM_S 16 ++#define GSW_VAWD1_PORTM_M 0xff ++ ++#define GSW_VAWD2 0x98 ++#define GSW_VAWD2_PORTT_S 16 ++#define GSW_VAWD2_PORTT_M 0xff ++ ++#define GSW_VTIM(_x) (0x100 + (4 * (_x))) ++#define GSW_VTIM_M 0xfff ++#define GSW_VTIM_S 12 ++ ++#define GSW_REG_PCR(x) (0x2004 + (x * 0x100)) ++#define GSW_REG_PCR_EG_TAG_S 28 ++#define GSW_REG_PCR_EG_TAG_M 0x3 ++ ++#define SYSCFG1 0x14 ++ ++#define ESW_PHY_POLLING 0x7000 ++ ++#define PMCR_IPG BIT(18) ++#define PMCR_MAC_MODE BIT(16) ++#define PMCR_FORCE BIT(15) ++#define PMCR_TX_EN BIT(14) ++#define PMCR_RX_EN BIT(13) ++#define PMCR_BACKOFF BIT(9) ++#define PMCR_BACKPRES BIT(8) ++#define PMCR_RX_FC BIT(5) ++#define PMCR_TX_FC BIT(4) ++#define PMCR_SPEED(_x) (_x << 2) ++#define PMCR_DUPLEX BIT(1) ++#define PMCR_LINK BIT(0) ++ ++#define PHY_AN_EN BIT(31) ++#define PHY_PRE_EN BIT(30) ++#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24) ++ ++enum { ++ /* Global attributes. */ ++ GSW_ATTR_ENABLE_VLAN, ++ /* Port attributes. */ ++ GSW_ATTR_PORT_UNTAG, ++}; ++ ++enum { ++ PORT4_EPHY = 0, ++ PORT4_EXT, ++}; ++ ++struct gsw_port { ++ bool disable; ++ bool untag; ++ u16 pvid; ++}; ++ ++struct gsw_vlan { ++ u8 ports; ++ u16 vid; ++}; ++ ++struct mt7620_gsw { ++ struct device *dev; ++ void __iomem *base; ++ int irq; ++ ++ struct switch_dev swdev; ++ bool global_vlan_enable; ++ struct gsw_vlan vlans[GSW_NUM_VLANS]; ++ struct gsw_port ports[GSW_NUM_PORTS]; ++ long unsigned int autopoll; ++ int port4; ++}; ++ ++static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg) ++{ ++ iowrite32(val, gsw->base + reg); ++} ++ ++static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg) ++{ ++ return ioread32(gsw->base + reg); ++} ++ ++static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw) ++{ ++ unsigned long t_start = jiffies; ++ ++ while (1) { ++ if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS)) ++ return 0; ++ if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) { ++ break; ++ } ++ } ++ ++ printk(KERN_ERR "mdio: MDIO timeout\n"); ++ return -1; ++} ++ ++static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register, ++ u32 write_data) ++{ ++ if (mt7620_mii_busy_wait(gsw)) ++ return -1; ++ ++ write_data &= 0xffff; ++ ++ gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE | ++ (phy_register << GSW_MDIO_REG_SHIFT) | ++ (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data, ++ MT7620A_GSW_REG_PIAC); ++ ++ if (mt7620_mii_busy_wait(gsw)) ++ return -1; ++ ++ return 0; ++} ++ ++int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val) ++{ ++ struct fe_priv *priv = bus->priv; ++ struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv; ++ ++ return _mt7620_mii_write(gsw, phy_addr, phy_reg, val); ++} ++ ++int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) ++{ ++ struct fe_priv *priv = bus->priv; ++ struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv; ++ u32 d; ++ ++ if (mt7620_mii_busy_wait(gsw)) ++ return 0xffff; ++ ++ gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ | ++ (phy_reg << GSW_MDIO_REG_SHIFT) | ++ (phy_addr << GSW_MDIO_ADDR_SHIFT), ++ MT7620A_GSW_REG_PIAC); ++ ++ if (mt7620_mii_busy_wait(gsw)) ++ return 0xffff; ++ ++ d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff; ++ ++ return d; ++} ++ ++static unsigned char *fe_speed_str(int speed) ++{ ++ switch (speed) { ++ case 2: ++ case SPEED_1000: ++ return "1000"; ++ case 1: ++ case SPEED_100: ++ return "100"; ++ case 0: ++ case SPEED_10: ++ return "10"; ++ } ++ ++ return "? "; ++} ++ ++int mt7620a_has_carrier(struct fe_priv *priv) ++{ ++ struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv; ++ int i; ++ ++ for (i = 0; i < GSW_PORT6; i++) ++ if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1) ++ return 1; ++ return 0; ++} ++ ++static void mt7620a_handle_carrier(struct fe_priv *priv) ++{ ++ if (!priv->phy) ++ return; ++ ++ if (mt7620a_has_carrier(priv)) ++ netif_carrier_on(priv->netdev); ++ else ++ netif_carrier_off(priv->netdev); ++} ++ ++void mt7620_mdio_link_adjust(struct fe_priv *priv, int port) ++{ ++ if (priv->link[port]) ++ netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n", ++ port, fe_speed_str(priv->phy->speed[port]), ++ (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half"); ++ else ++ netdev_info(priv->netdev, "port %d link down\n", port); ++ mt7620a_handle_carrier(priv); ++} ++ ++static irqreturn_t gsw_interrupt(int irq, void *_priv) ++{ ++ struct fe_priv *priv = (struct fe_priv *) _priv; ++ struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv; ++ u32 status; ++ int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3); ++ ++ status = gsw_r32(gsw, GSW_REG_ISR); ++ if (status & PORT_IRQ_ST_CHG) ++ for (i = 0; i <= max; i++) { ++ u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i)); ++ int link = status & 0x1; ++ ++ if (link != priv->link[i]) { ++ if (link) ++ netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n", ++ i, fe_speed_str((status >> 2) & 3), ++ (status & 0x2) ? "Full" : "Half"); ++ else ++ netdev_info(priv->netdev, "port %d link down\n", i); ++ } ++ ++ priv->link[i] = link; ++ } ++ mt7620a_handle_carrier(priv); ++ ++ gsw_w32(gsw, status, GSW_REG_ISR); ++ ++ return IRQ_HANDLED; ++} ++ ++static int mt7620_is_bga(void) ++{ ++ u32 bga = rt_sysc_r32(0x0c); ++ ++ return (bga >> 16) & 1; ++} ++ ++static void gsw_auto_poll(struct mt7620_gsw *gsw) ++{ ++ int phy; ++ int lsb = -1, msb = 0; ++ ++ for_each_set_bit(phy, &gsw->autopoll, 32) { ++ if (lsb < 0) ++ lsb = phy; ++ msb = phy; ++ } ++ ++ gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING); ++} ++ ++void mt7620_port_init(struct fe_priv *priv, struct device_node *np) ++{ ++ struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv; ++ const __be32 *_id = of_get_property(np, "reg", NULL); ++ int phy_mode, size, id; ++ int shift = 12; ++ u32 val, mask = 0; ++ int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4); ++ ++ if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) { ++ if (_id) ++ pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id)); ++ else ++ pr_err("%s: invalid port id\n", np->name); ++ return; ++ } ++ ++ id = be32_to_cpu(*_id); ++ ++ if (id == 4) ++ shift = 14; ++ ++ priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size); ++ if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) { ++ pr_err("%s: invalid fixed link property\n", np->name); ++ priv->phy->phy_fixed[id] = NULL; ++ return; ++ } ++ ++ phy_mode = of_get_phy_mode(np); ++ switch (phy_mode) { ++ case PHY_INTERFACE_MODE_RGMII: ++ mask = 0; ++ break; ++ case PHY_INTERFACE_MODE_MII: ++ mask = 1; ++ break; ++ case PHY_INTERFACE_MODE_RMII: ++ mask = 2; ++ break; ++ default: ++ dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[id]); ++ return; ++ } ++ ++ priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0); ++ if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id]) ++ return; ++ ++ val = rt_sysc_r32(SYSCFG1); ++ val &= ~(3 << shift); ++ val |= mask << shift; ++ rt_sysc_w32(val, SYSCFG1); ++ ++ if (priv->phy->phy_fixed[id]) { ++ const __be32 *link = priv->phy->phy_fixed[id]; ++ int tx_fc = be32_to_cpup(link++); ++ int rx_fc = be32_to_cpup(link++); ++ u32 val = 0; ++ ++ priv->phy->speed[id] = be32_to_cpup(link++); ++ priv->phy->duplex[id] = be32_to_cpup(link++); ++ priv->link[id] = 1; ++ ++ switch (priv->phy->speed[id]) { ++ case SPEED_10: ++ val = 0; ++ break; ++ case SPEED_100: ++ val = 1; ++ break; ++ case SPEED_1000: ++ val = 2; ++ break; ++ default: ++ dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]); ++ priv->phy->phy_fixed[id] = 0; ++ return; ++ } ++ val = PMCR_SPEED(val); ++ val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN | ++ PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG; ++ if (tx_fc) ++ val |= PMCR_TX_FC; ++ if (rx_fc) ++ val |= PMCR_RX_FC; ++ if (priv->phy->duplex[id]) ++ val |= PMCR_DUPLEX; ++ gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id)); ++ dev_info(priv->device, "using fixed link parameters\n"); ++ return; ++ } ++ ++ if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) { ++ u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN | ++ PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG; ++ ++ gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id)); ++ fe_connect_phy_node(priv, priv->phy->phy_node[id]); ++ gsw->autopoll |= BIT(id); ++ gsw_auto_poll(gsw); ++ return; ++ } ++} ++ ++static void gsw_hw_init(struct mt7620_gsw *gsw) ++{ ++ u32 is_BGA = mt7620_is_bga(); ++ ++ rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1); ++ gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR); ++ ++ /*correct PHY setting L3.0 BGA*/ ++ _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4 ++ ++ _mt7620_mii_write(gsw, 1, 17, 0x7444); ++ if (is_BGA) ++ _mt7620_mii_write(gsw, 1, 19, 0x0114); ++ else ++ _mt7620_mii_write(gsw, 1, 19, 0x0117); ++ ++ _mt7620_mii_write(gsw, 1, 22, 0x10cf); ++ _mt7620_mii_write(gsw, 1, 25, 0x6212); ++ _mt7620_mii_write(gsw, 1, 26, 0x0777); ++ _mt7620_mii_write(gsw, 1, 29, 0x4000); ++ _mt7620_mii_write(gsw, 1, 28, 0xc077); ++ _mt7620_mii_write(gsw, 1, 24, 0x0000); ++ ++ _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3 ++ _mt7620_mii_write(gsw, 1, 17, 0x4838); ++ ++ _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2 ++ if (is_BGA) { ++ _mt7620_mii_write(gsw, 1, 21, 0x0515); ++ _mt7620_mii_write(gsw, 1, 22, 0x0053); ++ _mt7620_mii_write(gsw, 1, 23, 0x00bf); ++ _mt7620_mii_write(gsw, 1, 24, 0x0aaf); ++ _mt7620_mii_write(gsw, 1, 25, 0x0fad); ++ _mt7620_mii_write(gsw, 1, 26, 0x0fc1); ++ } else { ++ _mt7620_mii_write(gsw, 1, 21, 0x0517); ++ _mt7620_mii_write(gsw, 1, 22, 0x0fd2); ++ _mt7620_mii_write(gsw, 1, 23, 0x00bf); ++ _mt7620_mii_write(gsw, 1, 24, 0x0aab); ++ _mt7620_mii_write(gsw, 1, 25, 0x00ae); ++ _mt7620_mii_write(gsw, 1, 26, 0x0fff); ++ } ++ _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1 ++ _mt7620_mii_write(gsw, 1, 17, 0xe7f8); ++ ++ _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0 ++ _mt7620_mii_write(gsw, 0, 30, 0xa000); ++ _mt7620_mii_write(gsw, 1, 30, 0xa000); ++ _mt7620_mii_write(gsw, 2, 30, 0xa000); ++ _mt7620_mii_write(gsw, 3, 30, 0xa000); ++ ++ _mt7620_mii_write(gsw, 0, 4, 0x05e1); ++ _mt7620_mii_write(gsw, 1, 4, 0x05e1); ++ _mt7620_mii_write(gsw, 2, 4, 0x05e1); ++ _mt7620_mii_write(gsw, 3, 4, 0x05e1); ++ _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2 ++ _mt7620_mii_write(gsw, 0, 16, 0x1111); ++ _mt7620_mii_write(gsw, 1, 16, 0x1010); ++ _mt7620_mii_write(gsw, 2, 16, 0x1515); ++ _mt7620_mii_write(gsw, 3, 16, 0x0f0f); ++ ++ /* CPU Port6 Force Link 1G, FC ON */ ++ gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6)); ++ /* Set Port6 CPU Port */ ++ gsw_w32(gsw, 0x7f7f7fe0, 0x0010); ++ ++// GSW_VAWD2 ++ ++ /* setup port 4 */ ++ if (gsw->port4 == PORT4_EPHY) { ++ u32 val = rt_sysc_r32(SYSCFG1); ++ val |= 3 << 14; ++ rt_sysc_w32(val, SYSCFG1); ++ _mt7620_mii_write(gsw, 4, 30, 0xa000); ++ _mt7620_mii_write(gsw, 4, 4, 0x05e1); ++ _mt7620_mii_write(gsw, 4, 16, 0x1313); ++ pr_info("gsw: setting port4 to ephy mode\n"); ++ } ++} ++ ++static int gsw_reset_switch(struct switch_dev *dev) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ ++ gsw->global_vlan_enable = 0; ++ memset(gsw->ports, 0, sizeof(gsw->ports)); ++ memset(gsw->vlans, 0, sizeof(gsw->vlans)); ++ gsw_hw_init(gsw); ++ ++ return 0; ++} ++ ++static int gsw_get_vlan_enable(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ ++ val->value.i = gsw->global_vlan_enable; ++ ++ return 0; ++} ++ ++static int gsw_set_vlan_enable(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ ++ gsw->global_vlan_enable = val->value.i != 0; ++ ++ return 0; ++} ++ ++static unsigned gsw_get_pvid(struct mt7620_gsw *gsw, unsigned port) ++{ ++ unsigned s, val; ++ ++ s = GSW_VTIM_S * (port % 2); ++ val = gsw_r32(gsw, GSW_VTIM(port / 2)); ++ ++ return (val >> s) & GSW_VTIM_M; ++} ++ ++static void gsw_set_pvid(struct mt7620_gsw *gsw, unsigned port, unsigned pvid) ++{ ++ unsigned s, val; ++ ++ s = GSW_VTIM_S * (port % 2); ++ val = gsw_r32(gsw, GSW_VTIM(port / 2)); ++ val &= ~(GSW_VTIM_M << s); ++ val |= (pvid && GSW_VTIM_M) << s; ++ gsw_w32(gsw, val, GSW_VTIM(port / 2)); ++} ++ ++static int gsw_get_port_bool(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ int idx = val->port_vlan; ++ ++ if (idx < 0 || idx >= GSW_NUM_PORTS) ++ return -EINVAL; ++ ++ switch (attr->id) { ++ case GSW_ATTR_PORT_UNTAG: ++ return gsw->ports[idx].untag; ++ } ++ ++ return -EINVAL; ++} ++ ++static int gsw_get_port_pvid(struct switch_dev *dev, int port, int *val) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ ++ if (port >= GSW_NUM_PORTS) ++ return -EINVAL; ++ ++ *val = gsw_get_pvid(gsw, port); ++ ++ return 0; ++} ++ ++static int gsw_set_port_pvid(struct switch_dev *dev, int port, int val) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ ++ if (port >= GSW_NUM_PORTS) ++ return -EINVAL; ++ ++ gsw->ports[port].pvid = val; ++ ++ return 0; ++} ++ ++static void gsw_set_vtcr(struct switch_dev *dev, u32 vid) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ int retry = 1000; ++ ++ gsw_w32(gsw, 0x80000000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR); ++ while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000)) ++ ; ++} ++ ++static void gsw_apply_vtcr(struct switch_dev *dev, u32 vid) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ int retry = 1000; ++ ++ gsw_w32(gsw, 0x80001000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR); ++ while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000)) ++ ; ++} ++ ++static unsigned gsw_get_vlan_id(struct mt7620_gsw *gsw, unsigned vlan) ++{ ++ unsigned s; ++ unsigned val; ++ ++ s = GSW_VLAN_ID_VID_S * (vlan % 2); ++ val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2)); ++ val = (val >> s) & GSW_VLAN_ID_VID_M; ++ ++ return val; ++} ++ ++static void gsw_set_vlan_id(struct mt7620_gsw *gsw, unsigned vlan, unsigned vid) ++{ ++ unsigned s; ++ unsigned val; ++ ++ s = GSW_VLAN_ID_VID_S * (vlan % 2); ++ val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2)); ++ val &= ~(GSW_VLAN_ID_VID_M << s); ++ val |= (vid << s); ++ gsw_w32(gsw, val, GSW_VLAN_ID(vlan / 2)); ++} ++ ++static void gsw_vlan_tagging_enable(struct mt7620_gsw *gsw, unsigned vlan, unsigned enable) ++{ ++ unsigned val; ++ ++ val = gsw_r32(gsw, GSW_VAWD1); ++ if (enable) ++ val |= GSW_VAWD1_VTAG_EN; ++ else ++ val &= ~GSW_VAWD1_VTAG_EN; ++ gsw_w32(gsw, val, GSW_VAWD1); ++} ++ ++static unsigned gsw_get_port_member(struct mt7620_gsw *gsw, unsigned vlan) ++{ ++ unsigned val; ++ ++ gsw_set_vtcr(&gsw->swdev, vlan); ++ ++ val = gsw_r32(gsw, GSW_VAWD1); ++ val = (val >> GSW_VAWD1_PORTM_S) & GSW_VAWD1_PORTM_M; ++ ++ return val; ++} ++ ++static void gsw_set_port_member(struct mt7620_gsw *gsw, unsigned vlan, unsigned member) ++{ ++ unsigned val; ++ ++ val = gsw_r32(gsw, GSW_VAWD1); ++ val = ~(GSW_VAWD1_PORTM_M << GSW_VAWD1_PORTM_S); ++ val |= (member & GSW_VAWD1_PORTM_M) << GSW_VAWD1_PORTM_S; ++ gsw_w32(gsw, val, GSW_VAWD1); ++} ++ ++static unsigned gsw_get_port_tag(struct mt7620_gsw *gsw, unsigned port) ++{ ++ unsigned val; ++ ++ val = gsw_r32(gsw, GSW_REG_PCR(port)); ++ val >>= GSW_REG_PCR_EG_TAG_S; ++ val &= GSW_REG_PCR_EG_TAG_M; ++ ++ return !!val; ++} ++ ++static void gsw_set_port_untag(struct mt7620_gsw *gsw, unsigned port, unsigned untag) ++{ ++ unsigned val; ++ ++ val = gsw_r32(gsw, GSW_REG_PCR(port)); ++ if (!untag) ++ untag = 0x2; ++ else ++ untag = 0; ++ val &= ~(GSW_REG_PCR_EG_TAG_M << GSW_REG_PCR_EG_TAG_S); ++ val |= (untag & GSW_REG_PCR_EG_TAG_M) << GSW_REG_PCR_EG_TAG_S; ++ gsw_w32(gsw, val, GSW_REG_PCR(port)); ++} ++ ++static int gsw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ int vlan_idx = -1; ++ u32 member; ++ int i; ++ ++ val->len = 0; ++ ++ if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS) ++ return -EINVAL; ++ ++ /* valid vlan? */ ++ for (i = 0; i < GSW_NUM_VLANS; i++) { ++ if (gsw_get_vlan_id(gsw, i) != val->port_vlan) ++ continue; ++ member = gsw_get_port_member(gsw, i); ++ vlan_idx = i; ++ break; ++ } ++ ++ if (vlan_idx == -1) ++ return -EINVAL; ++ ++ for (i = 0; i < GSW_NUM_PORTS; i++) { ++ struct switch_port *p; ++ int port_mask = 1 << i; ++ ++ if (!(member & port_mask)) ++ continue; ++ ++ p = &val->value.ports[val->len++]; ++ p->id = i; ++ if (gsw_get_port_tag(gsw, i)) ++ p->flags = 1 << SWITCH_PORT_FLAG_TAGGED; ++ else ++ p->flags = 0; ++ } ++ ++ return 0; ++} ++ ++static int gsw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ int ports; ++ int vlan_idx = -1; ++ int i; ++ ++ if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS || ++ val->len > GSW_NUM_PORTS) ++ return -EINVAL; ++ ++ /* one of the already defined vlans? */ ++ for (i = 0; i < GSW_NUM_VLANS; i++) { ++ if (gsw->vlans[i].vid == val->port_vlan && ++ gsw->vlans[i].ports) { ++ vlan_idx = i; ++ break; ++ } ++ } ++ ++ /* select a free slot */ ++ for (i = 0; vlan_idx == -1 && i < GSW_NUM_VLANS; i++) { ++ if (!gsw->vlans[i].ports) ++ vlan_idx = i; ++ } ++ ++ /* bail if all slots are in use */ ++ if (vlan_idx == -1) ++ return -EINVAL; ++ ++ ports = 0; ++ for (i = 0; i < val->len; i++) { ++ struct switch_port *p = &val->value.ports[i]; ++ int port_mask = 1 << p->id; ++ bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)); ++ ++ if (p->id >= GSW_NUM_PORTS) ++ return -EINVAL; ++ ++ ports |= port_mask; ++ gsw->ports[p->id].untag = untagged; ++ } ++ gsw->vlans[vlan_idx].ports = ports; ++ if (!ports) ++ gsw->vlans[vlan_idx].vid = 0xfff; ++ else ++ gsw->vlans[vlan_idx].vid = val->port_vlan; ++ ++ return 0; ++} ++ ++static int gsw_apply_config(struct switch_dev *dev) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ int i; ++ ++ for (i = 0; i < GSW_NUM_VLANS; i++) { ++ gsw_set_vtcr(&gsw->swdev, i); ++ if (gsw->global_vlan_enable) { ++ gsw_set_vlan_id(gsw, i, gsw->vlans[i].vid); ++ gsw_set_port_member(gsw, i, gsw->vlans[i].ports); ++ gsw_vlan_tagging_enable(gsw, i, 1); ++ } else { ++ gsw_set_vlan_id(gsw, i, 0xfff); ++ gsw_set_port_member(gsw, i, 0); ++ gsw_vlan_tagging_enable(gsw, i, 0); ++ } ++ gsw_apply_vtcr(&gsw->swdev, i); ++ } ++ ++ for (i = 0; i < GSW_NUM_PORTS; i++) { ++ if (gsw->global_vlan_enable) { ++ gsw_set_port_untag(gsw, i, !gsw->ports[i].untag); ++ gsw_set_pvid(gsw, i, gsw->ports[i].pvid); ++ } else { ++ gsw_set_port_untag(gsw, i, 0); ++ gsw_set_pvid(gsw, i, 0); ++ } ++ } ++ ++ if (!gsw->global_vlan_enable) ++ gsw_set_vlan_id(gsw, 0, 0); ++ ++ return 0; ++} ++ ++static int gsw_get_port_link(struct switch_dev *dev, ++ int port, ++ struct switch_port_link *link) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ u32 status; ++ ++ if (port < 0 || port >= GSW_NUM_PORTS) ++ return -EINVAL; ++ ++ status = gsw_r32(gsw, GSW_REG_PORT_STATUS(port)); ++ link->link = status & 0x1; ++ link->duplex = (status >> 1) & 1; ++ ++ switch ((status >> 2) & 0x3) { ++ case 0: ++ link->speed = SWITCH_PORT_SPEED_10; ++ break; ++ case 1: ++ link->speed = SWITCH_PORT_SPEED_100; ++ break; ++ case 2: ++ case 3: // forced gige speed can be 2 or 3 ++ link->speed = SWITCH_PORT_SPEED_1000; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int gsw_set_port_bool(struct switch_dev *dev, ++ const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev); ++ int idx = val->port_vlan; ++ ++ if (idx < 0 || idx >= GSW_NUM_PORTS || ++ val->value.i < 0 || val->value.i > 1) ++ return -EINVAL; ++ ++ switch (attr->id) { ++ case GSW_ATTR_PORT_UNTAG: ++ gsw->ports[idx].untag = val->value.i; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static const struct switch_attr gsw_global[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "enable_vlan", ++ .description = "VLAN mode (1:enabled)", ++ .max = 1, ++ .id = GSW_ATTR_ENABLE_VLAN, ++ .get = gsw_get_vlan_enable, ++ .set = gsw_set_vlan_enable, ++ }, ++}; ++ ++static const struct switch_attr gsw_port[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "untag", ++ .description = "Untag (1:strip outgoing vlan tag)", ++ .max = 1, ++ .id = GSW_ATTR_PORT_UNTAG, ++ .get = gsw_get_port_bool, ++ .set = gsw_set_port_bool, ++ }, ++}; ++ ++static const struct switch_attr gsw_vlan[] = { ++}; ++ ++static const struct switch_dev_ops gsw_ops = { ++ .attr_global = { ++ .attr = gsw_global, ++ .n_attr = ARRAY_SIZE(gsw_global), ++ }, ++ .attr_port = { ++ .attr = gsw_port, ++ .n_attr = ARRAY_SIZE(gsw_port), ++ }, ++ .attr_vlan = { ++ .attr = gsw_vlan, ++ .n_attr = ARRAY_SIZE(gsw_vlan), ++ }, ++ .get_vlan_ports = gsw_get_vlan_ports, ++ .set_vlan_ports = gsw_set_vlan_ports, ++ .get_port_pvid = gsw_get_port_pvid, ++ .set_port_pvid = gsw_set_port_pvid, ++ .get_port_link = gsw_get_port_link, ++ .apply_config = gsw_apply_config, ++ .reset_switch = gsw_reset_switch, ++}; ++ ++void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac) ++{ ++ struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->page_lock, flags); ++ gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1); ++ gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], ++ GSW_REG_SMACCR0); ++ spin_unlock_irqrestore(&priv->page_lock, flags); ++} ++ ++static struct of_device_id gsw_match[] = { ++ { .compatible = "ralink,mt7620a-gsw" }, ++ {} ++}; ++ ++int mt7620_gsw_probe(struct fe_priv *priv) ++{ ++ struct mt7620_gsw *gsw; ++ struct device_node *np; ++ struct switch_dev *swdev; ++ const char *port4 = NULL; ++ ++ np = of_find_matching_node(NULL, gsw_match); ++ if (!np) { ++ dev_err(priv->device, "no gsw node found\n"); ++ return -EINVAL; ++ } ++ np = of_node_get(np); ++ ++ gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL); ++ if (!gsw) { ++ dev_err(priv->device, "no gsw memory for private data\n"); ++ return -ENOMEM; ++ } ++ ++ gsw->irq = irq_of_parse_and_map(np, 0); ++ if (!gsw->irq) { ++ dev_err(priv->device, "no gsw irq resource found\n"); ++ return -ENOMEM; ++ } ++ ++ gsw->base = of_iomap(np, 0); ++ if (!gsw->base) { ++ dev_err(priv->device, "gsw ioremap failed\n"); ++ } ++ ++ gsw->dev = priv->device; ++ priv->soc->swpriv = gsw; ++ ++ swdev = &gsw->swdev; ++ swdev->of_node = np; ++ swdev->name = "mt7620a-gsw"; ++ swdev->alias = "mt7620x"; ++ swdev->cpu_port = GSW_PORT6; ++ swdev->ports = GSW_NUM_PORTS; ++ swdev->vlans = GSW_NUM_VLANS; ++ swdev->ops = &gsw_ops; ++ ++ if (register_switch(swdev, NULL)) ++ dev_err(priv->device, "register_switch failed\n"); ++ ++ of_property_read_string(np, "ralink,port4", &port4); ++ if (port4 && !strcmp(port4, "ephy")) ++ gsw->port4 = PORT4_EPHY; ++ else if (port4 && !strcmp(port4, "gmac")) ++ gsw->port4 = PORT4_EXT; ++ else ++ WARN_ON(port4); ++ ++ gsw_hw_init(gsw); ++ ++ gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR); ++ request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv); ++ ++ return 0; ++} +diff --git a/drivers/net/ethernet/ralink/gsw_mt7620a.h b/drivers/net/ethernet/ralink/gsw_mt7620a.h +new file mode 100644 +index 0000000..fd4add5 +--- /dev/null ++++ b/drivers/net/ethernet/ralink/gsw_mt7620a.h +@@ -0,0 +1,29 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#ifndef _RALINK_GSW_MT7620_H__ ++#define _RALINK_GSW_MT7620_H__ ++ ++extern int mt7620_gsw_probe(struct fe_priv *priv); ++extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac); ++extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val); ++extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg); ++extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port); ++extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np); ++extern int mt7620a_has_carrier(struct fe_priv *priv); ++ ++#endif +diff --git a/drivers/net/ethernet/ralink/mdio.c b/drivers/net/ethernet/ralink/mdio.c +new file mode 100644 +index 0000000..b265c75 +--- /dev/null ++++ b/drivers/net/ethernet/ralink/mdio.c +@@ -0,0 +1,245 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/dma-mapping.h> ++#include <linux/init.h> ++#include <linux/skbuff.h> ++#include <linux/etherdevice.h> ++#include <linux/ethtool.h> ++#include <linux/platform_device.h> ++#include <linux/phy.h> ++#include <linux/of_device.h> ++#include <linux/clk.h> ++#include <linux/of_net.h> ++#include <linux/of_mdio.h> ++ ++#include "ralink_soc_eth.h" ++#include "mdio.h" ++ ++static int fe_mdio_reset(struct mii_bus *bus) ++{ ++ /* TODO */ ++ return 0; ++} ++ ++static void fe_phy_link_adjust(struct net_device *dev) ++{ ++ struct fe_priv *priv = netdev_priv(dev); ++ unsigned long flags; ++ int i; ++ ++ spin_lock_irqsave(&priv->phy->lock, flags); ++ for (i = 0; i < 8; i++) { ++ if (priv->phy->phy_node[i]) { ++ struct phy_device *phydev = priv->phy->phy[i]; ++ int status_change = 0; ++ ++ if (phydev->link) ++ if (priv->phy->duplex[i] != phydev->duplex || ++ priv->phy->speed[i] != phydev->speed) ++ status_change = 1; ++ ++ if (phydev->link != priv->link[i]) ++ status_change = 1; ++ ++ switch (phydev->speed) { ++ case SPEED_1000: ++ case SPEED_100: ++ case SPEED_10: ++ priv->link[i] = phydev->link; ++ priv->phy->duplex[i] = phydev->duplex; ++ priv->phy->speed[i] = phydev->speed; ++ ++ if (status_change && priv->soc->mdio_adjust_link) ++ priv->soc->mdio_adjust_link(priv, i); ++ break; ++ } ++ } ++ } ++ spin_unlock_irqrestore(&priv->phy->lock, flags); ++} ++ ++int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node) ++{ ++ const __be32 *_port = NULL; ++ struct phy_device *phydev; ++ int phy_mode, port; ++ ++ _port = of_get_property(phy_node, "reg", NULL); ++ ++ if (!_port || (be32_to_cpu(*_port) >= 8)) { ++ pr_err("%s: invalid port id\n", phy_node->name); ++ return -EINVAL; ++ } ++ port = be32_to_cpu(*_port); ++ phy_mode = of_get_phy_mode(phy_node); ++ if (phy_mode < 0) { ++ dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode); ++ priv->phy->phy_node[port] = NULL; ++ return -EINVAL; ++ } ++ ++ phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust, ++ 0, phy_mode); ++ if (IS_ERR(phydev)) { ++ dev_err(priv->device, "could not connect to PHY\n"); ++ priv->phy->phy_node[port] = NULL; ++ return PTR_ERR(phydev); ++ } ++ ++ phydev->supported &= PHY_GBIT_FEATURES; ++ phydev->advertising = phydev->supported; ++ phydev->no_auto_carrier_off = 1; ++ ++ dev_info(priv->device, ++ "connected port %d to PHY at %s [uid=%08x, driver=%s]\n", ++ port, dev_name(&phydev->dev), phydev->phy_id, ++ phydev->drv->name); ++ ++ priv->phy->phy[port] = phydev; ++ priv->link[port] = 0; ++ ++ return 0; ++} ++ ++static int fe_phy_connect(struct fe_priv *priv) ++{ ++ return 0; ++} ++ ++static void fe_phy_disconnect(struct fe_priv *priv) ++{ ++ unsigned long flags; ++ int i; ++ ++ for (i = 0; i < 8; i++) ++ if (priv->phy->phy_fixed[i]) { ++ spin_lock_irqsave(&priv->phy->lock, flags); ++ priv->link[i] = 0; ++ if (priv->soc->mdio_adjust_link) ++ priv->soc->mdio_adjust_link(priv, i); ++ spin_unlock_irqrestore(&priv->phy->lock, flags); ++ } else if (priv->phy->phy[i]) { ++ phy_disconnect(priv->phy->phy[i]); ++ } ++} ++ ++static void fe_phy_start(struct fe_priv *priv) ++{ ++ unsigned long flags; ++ int i; ++ ++ for (i = 0; i < 8; i++) { ++ if (priv->phy->phy_fixed[i]) { ++ spin_lock_irqsave(&priv->phy->lock, flags); ++ priv->link[i] = 1; ++ if (priv->soc->mdio_adjust_link) ++ priv->soc->mdio_adjust_link(priv, i); ++ spin_unlock_irqrestore(&priv->phy->lock, flags); ++ } else if (priv->phy->phy[i]) { ++ phy_start(priv->phy->phy[i]); ++ } ++ } ++} ++ ++static void fe_phy_stop(struct fe_priv *priv) ++{ ++ unsigned long flags; ++ int i; ++ ++ for (i = 0; i < 8; i++) ++ if (priv->phy->phy_fixed[i]) { ++ spin_lock_irqsave(&priv->phy->lock, flags); ++ priv->link[i] = 0; ++ if (priv->soc->mdio_adjust_link) ++ priv->soc->mdio_adjust_link(priv, i); ++ spin_unlock_irqrestore(&priv->phy->lock, flags); ++ } else if (priv->phy->phy[i]) { ++ phy_stop(priv->phy->phy[i]); ++ } ++} ++ ++static struct fe_phy phy_ralink = { ++ .connect = fe_phy_connect, ++ .disconnect = fe_phy_disconnect, ++ .start = fe_phy_start, ++ .stop = fe_phy_stop, ++}; ++ ++int fe_mdio_init(struct fe_priv *priv) ++{ ++ struct device_node *mii_np; ++ int err; ++ ++ if (!priv->soc->mdio_read || !priv->soc->mdio_write) ++ return 0; ++ ++ spin_lock_init(&phy_ralink.lock); ++ priv->phy = &phy_ralink; ++ ++ mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus"); ++ if (!mii_np) { ++ dev_err(priv->device, "no %s child node found", "mdio-bus"); ++ return -ENODEV; ++ } ++ ++ if (!of_device_is_available(mii_np)) { ++ err = 0; ++ goto err_put_node; ++ } ++ ++ priv->mii_bus = mdiobus_alloc(); ++ if (priv->mii_bus == NULL) { ++ err = -ENOMEM; ++ goto err_put_node; ++ } ++ ++ priv->mii_bus->name = "mdio"; ++ priv->mii_bus->read = priv->soc->mdio_read; ++ priv->mii_bus->write = priv->soc->mdio_write; ++ priv->mii_bus->reset = fe_mdio_reset; ++ priv->mii_bus->irq = priv->mii_irq; ++ priv->mii_bus->priv = priv; ++ priv->mii_bus->parent = priv->device; ++ ++ snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name); ++ err = of_mdiobus_register(priv->mii_bus, mii_np); ++ if (err) ++ goto err_free_bus; ++ ++ return 0; ++ ++err_free_bus: ++ kfree(priv->mii_bus); ++err_put_node: ++ of_node_put(mii_np); ++ priv->mii_bus = NULL; ++ return err; ++} ++ ++void fe_mdio_cleanup(struct fe_priv *priv) ++{ ++ if (!priv->mii_bus) ++ return; ++ ++ mdiobus_unregister(priv->mii_bus); ++ of_node_put(priv->mii_bus->dev.of_node); ++ kfree(priv->mii_bus); ++} +diff --git a/drivers/net/ethernet/ralink/mdio.h b/drivers/net/ethernet/ralink/mdio.h +new file mode 100644 +index 0000000..c3910a0 +--- /dev/null ++++ b/drivers/net/ethernet/ralink/mdio.h +@@ -0,0 +1,29 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#ifndef _RALINK_MDIO_H__ ++#define _RALINK_MDIO_H__ ++ ++#ifdef CONFIG_NET_RALINK_MDIO ++extern int fe_mdio_init(struct fe_priv *priv); ++extern void fe_mdio_cleanup(struct fe_priv *priv); ++extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node); ++#else ++static inline int fe_mdio_init(struct fe_priv *priv) { return 0; } ++static inline void fe_mdio_cleanup(struct fe_priv *priv) {} ++#endif ++#endif +diff --git a/drivers/net/ethernet/ralink/mdio_rt2880.c b/drivers/net/ethernet/ralink/mdio_rt2880.c +new file mode 100644 +index 0000000..54dbc53 +--- /dev/null ++++ b/drivers/net/ethernet/ralink/mdio_rt2880.c +@@ -0,0 +1,163 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/dma-mapping.h> ++#include <linux/init.h> ++#include <linux/skbuff.h> ++#include <linux/etherdevice.h> ++#include <linux/ethtool.h> ++#include <linux/platform_device.h> ++#include <linux/phy.h> ++#include <linux/of_device.h> ++#include <linux/clk.h> ++#include <linux/of_net.h> ++#include <linux/of_mdio.h> ++ ++#include "ralink_soc_eth.h" ++#include "mdio_rt2880.h" ++ ++#define FE_MDIO_RETRY 1000 ++ ++static unsigned char *rt2880_speed_str(struct fe_priv *priv) ++{ ++ switch (priv->phy->speed[0]) { ++ case SPEED_1000: ++ return "1000"; ++ case SPEED_100: ++ return "100"; ++ case SPEED_10: ++ return "10"; ++ } ++ ++ return "?"; ++} ++ ++void rt2880_mdio_link_adjust(struct fe_priv *priv) ++{ ++ u32 mdio_cfg; ++ ++ if (!priv->link[0]) { ++ netif_carrier_off(priv->netdev); ++ netdev_info(priv->netdev, "link down\n"); ++ return; ++ } ++ ++ mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 | ++ FE_MDIO_CFG_RX_CLK_SKEW_200 | ++ FE_MDIO_CFG_GP1_FRC_EN; ++ ++ if (priv->phy->duplex[0] == DUPLEX_FULL) ++ mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX; ++ ++ if (priv->phy->tx_fc) ++ mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX; ++ ++ if (priv->phy->rx_fc) ++ mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX; ++ ++ switch (priv->phy->speed[0]) { ++ case SPEED_10: ++ mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10; ++ break; ++ case SPEED_100: ++ mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100; ++ break; ++ case SPEED_1000: ++ mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000; ++ break; ++ default: ++ BUG(); ++ } ++ ++ fe_w32(mdio_cfg, FE_MDIO_CFG); ++ ++ netif_carrier_on(priv->netdev); ++ netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n", ++ rt2880_speed_str(priv), ++ (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half"); ++} ++ ++static int rt2880_mdio_wait_ready(struct fe_priv *priv) ++{ ++ int retries; ++ ++ retries = FE_MDIO_RETRY; ++ while (1) { ++ u32 t; ++ ++ t = fe_r32(FE_MDIO_ACCESS); ++ if ((t & (0x1 << 31)) == 0) ++ return 0; ++ ++ if (retries-- == 0) ++ break; ++ ++ udelay(1); ++ } ++ ++ dev_err(priv->device, "MDIO operation timed out\n"); ++ return -ETIMEDOUT; ++} ++ ++int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) ++{ ++ struct fe_priv *priv = bus->priv; ++ int err; ++ u32 t; ++ ++ err = rt2880_mdio_wait_ready(priv); ++ if (err) ++ return 0xffff; ++ ++ t = (phy_addr << 24) | (phy_reg << 16); ++ fe_w32(t, FE_MDIO_ACCESS); ++ t |= (1 << 31); ++ fe_w32(t, FE_MDIO_ACCESS); ++ ++ err = rt2880_mdio_wait_ready(priv); ++ if (err) ++ return 0xffff; ++ ++ pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__, ++ phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff); ++ ++ return fe_r32(FE_MDIO_ACCESS) & 0xffff; ++} ++ ++int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val) ++{ ++ struct fe_priv *priv = bus->priv; ++ int err; ++ u32 t; ++ ++ pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__, ++ phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff); ++ ++ err = rt2880_mdio_wait_ready(priv); ++ if (err) ++ return err; ++ ++ t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val; ++ fe_w32(t, FE_MDIO_ACCESS); ++ t |= (1 << 31); ++ fe_w32(t, FE_MDIO_ACCESS); ++ ++ return rt2880_mdio_wait_ready(priv); ++} +diff --git a/drivers/net/ethernet/ralink/mdio_rt2880.h b/drivers/net/ethernet/ralink/mdio_rt2880.h +new file mode 100644 +index 0000000..c9ac0fe +--- /dev/null ++++ b/drivers/net/ethernet/ralink/mdio_rt2880.h +@@ -0,0 +1,25 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#ifndef _RALINK_MDIO_RT2880_H__ ++#define _RALINK_MDIO_RT2880_H__ ++ ++void rt2880_mdio_link_adjust(struct fe_priv *priv); ++int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg); ++int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val); ++ ++#endif +diff --git a/drivers/net/ethernet/ralink/ralink_soc_eth.c b/drivers/net/ethernet/ralink/ralink_soc_eth.c +new file mode 100644 +index 0000000..04e82eb +--- /dev/null ++++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c +@@ -0,0 +1,759 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/dma-mapping.h> ++#include <linux/init.h> ++#include <linux/skbuff.h> ++#include <linux/etherdevice.h> ++#include <linux/ethtool.h> ++#include <linux/platform_device.h> ++#include <linux/of_device.h> ++#include <linux/clk.h> ++#include <linux/of_net.h> ++#include <linux/of_mdio.h> ++#include <linux/if_vlan.h> ++ ++#include <asm/mach-ralink/ralink_regs.h> ++ ++#include "ralink_soc_eth.h" ++#include "esw_rt3052.h" ++#include "mdio.h" ++ ++#define TX_TIMEOUT (20 * HZ / 100) ++#define MAX_RX_LENGTH 1536 ++ ++static const u32 fe_reg_table_default[FE_REG_COUNT] = { ++ [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG, ++ [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG, ++ [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG, ++ [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0, ++ [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0, ++ [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0, ++ [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0, ++ [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0, ++ [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0, ++ [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE, ++ [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS, ++ [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0, ++}; ++ ++static const u32 *fe_reg_table = fe_reg_table_default; ++ ++static void __iomem *fe_base = 0; ++ ++void fe_w32(u32 val, unsigned reg) ++{ ++ __raw_writel(val, fe_base + reg); ++} ++ ++u32 fe_r32(unsigned reg) ++{ ++ return __raw_readl(fe_base + reg); ++} ++ ++static inline void fe_reg_w32(u32 val, enum fe_reg reg) ++{ ++ fe_w32(val, fe_reg_table[reg]); ++} ++ ++static inline u32 fe_reg_r32(enum fe_reg reg) ++{ ++ return fe_r32(fe_reg_table[reg]); ++} ++ ++static inline void fe_int_disable(u32 mask) ++{ ++ fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask, ++ FE_REG_FE_INT_ENABLE); ++ /* flush write */ ++ fe_reg_r32(FE_REG_FE_INT_ENABLE); ++} ++ ++static inline void fe_int_enable(u32 mask) ++{ ++ fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask, ++ FE_REG_FE_INT_ENABLE); ++ /* flush write */ ++ fe_reg_r32(FE_REG_FE_INT_ENABLE); ++} ++ ++static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->page_lock, flags); ++ fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH); ++ fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], ++ FE_GDMA1_MAC_ADRL); ++ spin_unlock_irqrestore(&priv->page_lock, flags); ++} ++ ++static int fe_set_mac_address(struct net_device *dev, void *p) ++{ ++ int ret = eth_mac_addr(dev, p); ++ ++ if (!ret) { ++ struct fe_priv *priv = netdev_priv(dev); ++ ++ if (priv->soc->set_mac) ++ priv->soc->set_mac(priv, dev->dev_addr); ++ else ++ fe_hw_set_macaddr(priv, p); ++ } ++ ++ return ret; ++} ++ ++static struct sk_buff* fe_alloc_skb(struct fe_priv *priv) ++{ ++ struct sk_buff *skb; ++ ++ skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN); ++ if (!skb) ++ return NULL; ++ ++ skb_reserve(skb, NET_IP_ALIGN); ++ ++ return skb; ++} ++ ++static int fe_alloc_rx(struct fe_priv *priv) ++{ ++ int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma); ++ int i; ++ ++ priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size, ++ &priv->rx_phys, GFP_ATOMIC); ++ if (!priv->rx_dma) ++ return -ENOMEM; ++ ++ memset(priv->rx_dma, 0, size); ++ ++ for (i = 0; i < NUM_DMA_DESC; i++) { ++ priv->rx_skb[i] = fe_alloc_skb(priv); ++ if (!priv->rx_skb[i]) ++ return -ENOMEM; ++ } ++ ++ for (i = 0; i < NUM_DMA_DESC; i++) { ++ dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev, ++ priv->rx_skb[i]->data, ++ MAX_RX_LENGTH, ++ DMA_FROM_DEVICE); ++ priv->rx_dma[i].rxd1 = (unsigned int) dma_addr; ++ ++ if (priv->soc->rx_dma) ++ priv->soc->rx_dma(priv, i, MAX_RX_LENGTH); ++ else ++ priv->rx_dma[i].rxd2 = RX_DMA_LSO; ++ } ++ wmb(); ++ ++ fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0); ++ fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0); ++ fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0); ++ fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG); ++ ++ return 0; ++} ++ ++static int fe_alloc_tx(struct fe_priv *priv) ++{ ++ int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma); ++ int i; ++ ++ priv->tx_free_idx = 0; ++ ++ priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size, ++ &priv->tx_phys, GFP_ATOMIC); ++ if (!priv->tx_dma) ++ return -ENOMEM; ++ ++ memset(priv->tx_dma, 0, size); ++ ++ for (i = 0; i < NUM_DMA_DESC; i++) { ++ if (priv->soc->tx_dma) { ++ priv->soc->tx_dma(priv, i, 0); ++ continue; ++ } ++ ++ priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE; ++ priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1); ++ } ++ ++ fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0); ++ fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0); ++ fe_reg_w32(0, FE_REG_TX_CTX_IDX0); ++ fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG); ++ ++ return 0; ++} ++ ++static void fe_free_dma(struct fe_priv *priv) ++{ ++ int i; ++ ++ for (i = 0; i < NUM_DMA_DESC; i++) { ++ if (priv->rx_skb[i]) { ++ dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1, ++ MAX_RX_LENGTH, DMA_FROM_DEVICE); ++ dev_kfree_skb_any(priv->rx_skb[i]); ++ priv->rx_skb[i] = NULL; ++ } ++ ++ if (priv->tx_skb[i]) { ++ dev_kfree_skb_any(priv->tx_skb[i]); ++ priv->tx_skb[i] = NULL; ++ } ++ } ++ ++ if (priv->rx_dma) { ++ int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma); ++ dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma, ++ priv->rx_phys); ++ } ++ ++ if (priv->tx_dma) { ++ int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma); ++ dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma, ++ priv->tx_phys); ++ } ++ ++ netdev_reset_queue(priv->netdev); ++} ++ ++static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct fe_priv *priv = netdev_priv(dev); ++ dma_addr_t mapped_addr; ++ u32 tx_next; ++ u32 tx; ++ ++ if (priv->soc->min_pkt_len) { ++ if (skb->len < priv->soc->min_pkt_len) { ++ if (skb_padto(skb, priv->soc->min_pkt_len)) { ++ printk(KERN_ERR ++ "fe_eth: skb_padto failed\n"); ++ kfree_skb(skb); ++ return 0; ++ } ++ skb_put(skb, priv->soc->min_pkt_len - skb->len); ++ } ++ } ++ ++ dev->trans_start = jiffies; ++ mapped_addr = dma_map_single(&priv->netdev->dev, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ ++ spin_lock(&priv->page_lock); ++ ++ tx = fe_reg_r32(FE_REG_TX_CTX_IDX0); ++ tx_next = (tx + 1) % NUM_DMA_DESC; ++ ++ if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) || ++ !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) || ++ !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE)) ++ { ++ spin_unlock(&priv->page_lock); ++ dev->stats.tx_dropped++; ++ kfree_skb(skb); ++ ++ return NETDEV_TX_OK; ++ } ++ ++ priv->tx_skb[tx] = skb; ++ priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr; ++ wmb(); ++ if (priv->soc->tx_dma) ++ priv->soc->tx_dma(priv, tx, skb->len); ++ else ++ priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len); ++ ++ if (skb->ip_summed == CHECKSUM_PARTIAL) ++ priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM; ++ else ++ priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM; ++ ++ if (fe_reg_table[FE_REG_FE_DMA_VID_BASE] && vlan_tx_tag_present(skb)) ++ priv->tx_dma[tx].txd4 |= 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF); ++ else ++ priv->tx_dma[tx].txd4 &= ~0x80; ++ ++ dev->stats.tx_packets++; ++ dev->stats.tx_bytes += skb->len; ++ ++ fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0); ++ netdev_sent_queue(dev, skb->len); ++ ++ spin_unlock(&priv->page_lock); ++ ++ return NETDEV_TX_OK; ++} ++ ++static int fe_poll_rx(struct napi_struct *napi, int budget) ++{ ++ struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi); ++ int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0); ++ unsigned long flags; ++ int complete = 0; ++ int rx = 0; ++ ++ while ((rx < budget) && !complete) { ++ ++ idx = (idx + 1) % NUM_DMA_DESC; ++ ++ if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) { ++ struct sk_buff *new_skb = fe_alloc_skb(priv); ++ ++ if (new_skb) { ++ int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2); ++ dma_addr_t dma_addr; ++ ++ dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1, ++ MAX_RX_LENGTH, DMA_FROM_DEVICE); ++ ++ skb_put(priv->rx_skb[idx], pktlen); ++ priv->rx_skb[idx]->dev = priv->netdev; ++ priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev); ++ if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit) ++ priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY; ++ else ++ priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE; ++ priv->netdev->stats.rx_packets++; ++ priv->netdev->stats.rx_bytes += pktlen; ++ netif_rx(priv->rx_skb[idx]); ++ ++ priv->rx_skb[idx] = new_skb; ++ ++ dma_addr = dma_map_single(&priv->netdev->dev, ++ new_skb->data, ++ MAX_RX_LENGTH, ++ DMA_FROM_DEVICE); ++ priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr; ++ wmb(); ++ } else { ++ priv->netdev->stats.rx_dropped++; ++ } ++ ++ if (priv->soc->rx_dma) ++ priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH); ++ else ++ priv->rx_dma[idx].rxd2 = RX_DMA_LSO; ++ fe_reg_w32(idx, FE_REG_RX_CALC_IDX0); ++ rx++; ++ } else { ++ complete = 1; ++ } ++ } ++ ++ if (complete || !rx) { ++ napi_complete(&priv->rx_napi); ++ spin_lock_irqsave(&priv->page_lock, flags); ++ fe_int_enable(priv->soc->rx_dly_int); ++ spin_unlock_irqrestore(&priv->page_lock, flags); ++ } ++ ++ return rx; ++} ++ ++static int fe_poll_tx(struct napi_struct *napi, int budget) ++{ ++ struct fe_priv *priv = container_of(napi, struct fe_priv, tx_napi); ++ unsigned int bytes_compl = 0; ++ unsigned int pkts_compl = 0; ++ struct netdev_queue *txq; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->page_lock, flags); ++ while (pkts_compl < budget) { ++ struct fe_tx_dma *txd; ++ ++ txd = &priv->tx_dma[priv->tx_free_idx]; ++ ++ if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx])) ++ break; ++ ++ bytes_compl += priv->tx_skb[priv->tx_free_idx]->len; ++ pkts_compl++; ++ ++ dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]); ++ priv->tx_skb[priv->tx_free_idx] = NULL; ++ priv->tx_free_idx++; ++ if (priv->tx_free_idx >= NUM_DMA_DESC) ++ priv->tx_free_idx = 0; ++ } ++ spin_unlock_irqrestore(&priv->page_lock, flags); ++ ++ txq = netdev_get_tx_queue(priv->netdev, 0); ++ if (netif_tx_queue_stopped(txq)) ++ netif_tx_start_queue(txq); ++ ++ napi_complete(napi); ++ netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl); ++ ++ spin_lock_irqsave(&priv->page_lock, flags); ++ fe_int_enable(priv->soc->tx_dly_int); ++ spin_unlock_irqrestore(&priv->page_lock, flags); ++ ++ return pkts_compl; ++} ++ ++static void fe_tx_timeout(struct net_device *dev) ++{ ++ struct fe_priv *priv = netdev_priv(dev); ++ ++ priv->netdev->stats.tx_errors++; ++ netdev_err(dev, "transmit timed out, waking up the queue\n"); ++ netif_wake_queue(dev); ++} ++ ++static irqreturn_t fe_handle_irq(int irq, void *dev) ++{ ++ struct fe_priv *priv = netdev_priv(dev); ++ unsigned int status; ++ unsigned int mask; ++ ++ status = fe_reg_r32(FE_REG_FE_INT_STATUS); ++ mask = fe_reg_r32(FE_REG_FE_INT_ENABLE); ++ ++ if (!(status & mask)) ++ return IRQ_NONE; ++ ++ if (status & priv->soc->rx_dly_int) { ++ fe_int_disable(priv->soc->rx_dly_int); ++ napi_schedule(&priv->rx_napi); ++ } ++ ++ if (status & priv->soc->tx_dly_int) { ++ fe_int_disable(priv->soc->tx_dly_int); ++ napi_schedule(&priv->tx_napi); ++ } ++ ++ fe_reg_w32(status, FE_REG_FE_INT_STATUS); ++ ++ return IRQ_HANDLED; ++} ++ ++static int fe_hw_init(struct net_device *dev) ++{ ++ struct fe_priv *priv = netdev_priv(dev); ++ int err, i; ++ ++ err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0, ++ dev_name(priv->device), dev); ++ if (err) ++ return err; ++ ++ err = fe_alloc_rx(priv); ++ if (!err) ++ err = fe_alloc_tx(priv); ++ if (err) ++ return err; ++ ++ if (priv->soc->set_mac) ++ priv->soc->set_mac(priv, dev->dev_addr); ++ else ++ fe_hw_set_macaddr(priv, dev->dev_addr); ++ ++ fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG); ++ ++ fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int); ++ ++ ++ if (fe_reg_table[FE_REG_FE_DMA_VID_BASE]) ++ for (i = 0; i < 16; i += 2) ++ fe_w32((i + 1) << 16 | i, fe_reg_table[FE_REG_FE_DMA_VID_BASE] + (i * 4)); ++ ++ if (priv->soc->fwd_config) { ++ priv->soc->fwd_config(priv); ++ } else { ++ unsigned long sysclk = priv->sysclk; ++ ++ if (!sysclk) { ++ netdev_err(dev, "unable to get clock\n"); ++ return -EINVAL; ++ } ++ ++ sysclk /= FE_US_CYC_CNT_DIVISOR; ++ sysclk <<= FE_US_CYC_CNT_SHIFT; ++ ++ fe_w32((fe_r32(FE_FE_GLO_CFG) & ++ ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | priv->sysclk, ++ FE_FE_GLO_CFG); ++ ++ fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG); ++ fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN), ++ FE_GDMA1_FWD_CFG); ++ fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN), ++ FE_CDMA_CSG_CFG); ++ fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG); ++ } ++ ++ fe_w32(1, FE_FE_RST_GL); ++ fe_w32(0, FE_FE_RST_GL); ++ ++ return 0; ++} ++ ++static int fe_open(struct net_device *dev) ++{ ++ struct fe_priv *priv = netdev_priv(dev); ++ unsigned long flags; ++ u32 val; ++ ++ spin_lock_irqsave(&priv->page_lock, flags); ++ napi_enable(&priv->rx_napi); ++ napi_enable(&priv->tx_napi); ++ ++ val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN; ++ val |= priv->soc->pdma_glo_cfg; ++ fe_reg_w32(val, FE_REG_PDMA_GLO_CFG); ++ ++ spin_unlock_irqrestore(&priv->page_lock, flags); ++ ++ if (priv->phy) ++ priv->phy->start(priv); ++ ++ if (priv->soc->has_carrier && priv->soc->has_carrier(priv)) ++ netif_carrier_on(dev); ++ ++ netif_start_queue(dev); ++ fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int); ++ ++ return 0; ++} ++ ++static int fe_stop(struct net_device *dev) ++{ ++ struct fe_priv *priv = netdev_priv(dev); ++ unsigned long flags; ++ ++ fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int); ++ ++ netif_stop_queue(dev); ++ ++ if (priv->phy) ++ priv->phy->stop(priv); ++ ++ spin_lock_irqsave(&priv->page_lock, flags); ++ napi_disable(&priv->rx_napi); ++ napi_disable(&priv->tx_napi); ++ ++ fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) & ++ ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN), ++ FE_REG_PDMA_GLO_CFG); ++ spin_unlock_irqrestore(&priv->page_lock, flags); ++ ++ return 0; ++} ++ ++static int __init fe_init(struct net_device *dev) ++{ ++ struct fe_priv *priv = netdev_priv(dev); ++ struct device_node *port; ++ int err; ++ ++ BUG_ON(!priv->soc->reset_fe); ++ priv->soc->reset_fe(); ++ ++ if (priv->soc->switch_init) ++ priv->soc->switch_init(priv); ++ ++ net_srandom(jiffies); ++ memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN); ++ of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr); ++ ++ err = fe_mdio_init(priv); ++ if (err) ++ return err; ++ ++ if (priv->phy) { ++ err = priv->phy->connect(priv); ++ if (err) ++ goto err_mdio_cleanup; ++ } ++ ++ if (priv->soc->port_init) ++ for_each_child_of_node(priv->device->of_node, port) ++ if (of_device_is_compatible(port, "ralink,eth-port")) ++ priv->soc->port_init(priv, port); ++ ++ err = fe_hw_init(dev); ++ if (err) ++ goto err_phy_disconnect; ++ ++ return 0; ++ ++err_phy_disconnect: ++ if (priv->phy) ++ priv->phy->disconnect(priv); ++err_mdio_cleanup: ++ fe_mdio_cleanup(priv); ++ ++ return err; ++} ++ ++static void fe_uninit(struct net_device *dev) ++{ ++ struct fe_priv *priv = netdev_priv(dev); ++ ++ if (priv->phy) ++ priv->phy->disconnect(priv); ++ fe_mdio_cleanup(priv); ++ ++ fe_reg_w32(0, FE_REG_FE_INT_ENABLE); ++ free_irq(dev->irq, dev); ++ ++ fe_free_dma(priv); ++} ++ ++static const struct net_device_ops fe_netdev_ops = { ++ .ndo_init = fe_init, ++ .ndo_uninit = fe_uninit, ++ .ndo_open = fe_open, ++ .ndo_stop = fe_stop, ++ .ndo_start_xmit = fe_start_xmit, ++ .ndo_tx_timeout = fe_tx_timeout, ++ .ndo_set_mac_address = fe_set_mac_address, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_validate_addr = eth_validate_addr, ++}; ++ ++static int fe_probe(struct platform_device *pdev) ++{ ++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ const struct of_device_id *match; ++ struct fe_soc_data *soc = NULL; ++ struct net_device *netdev; ++ struct fe_priv *priv; ++ struct clk *sysclk; ++ int err; ++ ++ match = of_match_device(of_fe_match, &pdev->dev); ++ soc = (struct fe_soc_data *) match->data; ++ if (soc->reg_table) ++ fe_reg_table = soc->reg_table; ++ ++ fe_base = devm_request_and_ioremap(&pdev->dev, res); ++ if (!fe_base) ++ return -ENOMEM; ++ ++ netdev = alloc_etherdev(sizeof(struct fe_priv)); ++ if (!netdev) { ++ dev_err(&pdev->dev, "alloc_etherdev failed\n"); ++ return -ENOMEM; ++ } ++ ++ strcpy(netdev->name, "eth%d"); ++ netdev->netdev_ops = &fe_netdev_ops; ++ netdev->base_addr = (unsigned long) fe_base; ++ netdev->watchdog_timeo = TX_TIMEOUT; ++ netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; ++ if (fe_reg_table[FE_REG_FE_DMA_VID_BASE]) ++ netdev->features |= NETIF_F_HW_VLAN_TX; ++ ++ netdev->irq = platform_get_irq(pdev, 0); ++ if (netdev->irq < 0) { ++ dev_err(&pdev->dev, "no IRQ resource found\n"); ++ kfree(netdev); ++ return -ENXIO; ++ } ++ ++ priv = netdev_priv(netdev); ++ memset(priv, 0, sizeof(struct fe_priv)); ++ spin_lock_init(&priv->page_lock); ++ ++ sysclk = devm_clk_get(&pdev->dev, NULL); ++ if (!IS_ERR(sysclk)) ++ priv->sysclk = clk_get_rate(sysclk); ++ ++ priv->netdev = netdev; ++ priv->device = &pdev->dev; ++ priv->soc = soc; ++ ++ err = register_netdev(netdev); ++ if (err) { ++ dev_err(&pdev->dev, "error bringing up device\n"); ++ kfree(netdev); ++ return err; ++ } ++ ++ netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32); ++ netif_napi_add(netdev, &priv->tx_napi, fe_poll_tx, 8); ++ ++ platform_set_drvdata(pdev, netdev); ++ ++ netdev_info(netdev, "done loading\n"); ++ ++ return 0; ++} ++ ++static int fe_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct fe_priv *priv = netdev_priv(dev); ++ ++ netif_stop_queue(dev); ++ netif_napi_del(&priv->rx_napi); ++ netif_napi_del(&priv->tx_napi); ++ ++ unregister_netdev(dev); ++ free_netdev(dev); ++ ++ return 0; ++} ++ ++static struct platform_driver fe_driver = { ++ .probe = fe_probe, ++ .remove = fe_remove, ++ .driver = { ++ .name = "ralink_soc_eth", ++ .owner = THIS_MODULE, ++ .of_match_table = of_fe_match, ++ }, ++}; ++ ++static int __init init_rtfe(void) ++{ ++ int ret; ++ ++ ret = rtesw_init(); ++ if (ret) ++ return ret; ++ ++ ret = platform_driver_register(&fe_driver); ++ if (ret) ++ rtesw_exit(); ++ ++ return ret; ++} ++ ++static void __exit exit_rtfe(void) ++{ ++ platform_driver_unregister(&fe_driver); ++ rtesw_exit(); ++} ++ ++module_init(init_rtfe); ++module_exit(exit_rtfe); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); ++MODULE_DESCRIPTION("Ethernet driver for Ralink SoC"); +diff --git a/drivers/net/ethernet/ralink/ralink_soc_eth.h b/drivers/net/ethernet/ralink/ralink_soc_eth.h +new file mode 100644 +index 0000000..0c769ef +--- /dev/null ++++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h +@@ -0,0 +1,372 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * based on Ralink SDK3.3 ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#ifndef FE_ETH_H ++#define FE_ETH_H ++ ++#include <linux/mii.h> ++#include <linux/interrupt.h> ++#include <linux/netdevice.h> ++#include <linux/dma-mapping.h> ++#include <linux/phy.h> ++ ++ ++enum fe_reg { ++ FE_REG_PDMA_GLO_CFG = 0, ++ FE_REG_PDMA_RST_CFG, ++ FE_REG_DLY_INT_CFG, ++ FE_REG_TX_BASE_PTR0, ++ FE_REG_TX_MAX_CNT0, ++ FE_REG_TX_CTX_IDX0, ++ FE_REG_RX_BASE_PTR0, ++ FE_REG_RX_MAX_CNT0, ++ FE_REG_RX_CALC_IDX0, ++ FE_REG_FE_INT_ENABLE, ++ FE_REG_FE_INT_STATUS, ++ FE_REG_FE_DMA_VID_BASE, ++ FE_REG_COUNT ++}; ++ ++#define NUM_DMA_DESC 0x100 ++ ++#define FE_DELAY_EN_INT 0x80 ++#define FE_DELAY_MAX_INT 0x04 ++#define FE_DELAY_MAX_TOUT 0x04 ++#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT) ++#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN) ++#define FE_PSE_FQFC_CFG_INIT 0x80504000 ++ ++/* interrupt bits */ ++#define FE_CNT_PPE_AF BIT(31) ++#define FE_CNT_GDM_AF BIT(29) ++#define FE_PSE_P2_FC BIT(26) ++#define FE_PSE_BUF_DROP BIT(24) ++#define FE_GDM_OTHER_DROP BIT(23) ++#define FE_PSE_P1_FC BIT(22) ++#define FE_PSE_P0_FC BIT(21) ++#define FE_PSE_FQ_EMPTY BIT(20) ++#define FE_GE1_STA_CHG BIT(18) ++#define FE_TX_COHERENT BIT(17) ++#define FE_RX_COHERENT BIT(16) ++#define FE_TX_DONE_INT3 BIT(11) ++#define FE_TX_DONE_INT2 BIT(10) ++#define FE_TX_DONE_INT1 BIT(9) ++#define FE_TX_DONE_INT0 BIT(8) ++#define FE_RX_DONE_INT0 BIT(2) ++#define FE_TX_DLY_INT BIT(1) ++#define FE_RX_DLY_INT BIT(0) ++ ++#define RT5350_RX_DLY_INT BIT(30) ++#define RT5350_TX_DLY_INT BIT(28) ++ ++/* registers */ ++#define FE_FE_OFFSET 0x0000 ++#define FE_GDMA_OFFSET 0x0020 ++#define FE_PSE_OFFSET 0x0040 ++#define FE_GDMA2_OFFSET 0x0060 ++#define FE_CDMA_OFFSET 0x0080 ++#define FE_DMA_VID0 0x00a8 ++#define FE_PDMA_OFFSET 0x0100 ++#define FE_PPE_OFFSET 0x0200 ++#define FE_CMTABLE_OFFSET 0x0400 ++#define FE_POLICYTABLE_OFFSET 0x1000 ++ ++#define RT5350_PDMA_OFFSET 0x0800 ++#define RT5350_SDM_OFFSET 0x0c00 ++ ++#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00) ++#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04) ++#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08) ++#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C) ++#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10) ++#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14) ++#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18) ++#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C) ++ ++#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00) ++#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04) ++#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08) ++#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C) ++#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10) ++ ++#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00) ++#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04) ++#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08) ++#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C) ++#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10) ++ ++#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00) ++#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04) ++#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08) ++#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C) ++ ++#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00) ++#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04) ++ ++#define MT7620A_GDMA_OFFSET 0x0600 ++#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00) ++#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04) ++#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08) ++#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C) ++#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10) ++ ++#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00) ++#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04) ++#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08) ++#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C) ++#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10) ++#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14) ++#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18) ++#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C) ++#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20) ++#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24) ++#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28) ++#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C) ++#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30) ++#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34) ++#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38) ++#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C) ++#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100) ++#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104) ++#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108) ++#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C) ++#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110) ++#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114) ++#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118) ++#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C) ++#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204) ++#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208) ++#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c) ++#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220) ++#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228) ++#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280) ++ ++#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00) ++#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04) ++#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08) ++#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C) ++#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10) ++#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14) ++#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18) ++#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C) ++#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20) ++#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24) ++#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28) ++#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C) ++#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30) ++#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34) ++#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38) ++#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C) ++#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40) ++#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44) ++#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48) ++#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C) ++#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50) ++#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54) ++#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58) ++#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C) ++#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60) ++#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64) ++#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68) ++#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C) ++ ++#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration ++#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring ++#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring ++#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB ++#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB ++#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count ++#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count ++#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count ++#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count ++#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count ++ ++#define RT5350_SDM_ICS_EN BIT(16) ++#define RT5350_SDM_TCS_EN BIT(17) ++#define RT5350_SDM_UCS_EN BIT(18) ++ ++ ++/* MDIO_CFG register bits */ ++#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29) ++#define FE_MDIO_CFG_GP1_BP_EN BIT(16) ++#define FE_MDIO_CFG_GP1_FRC_EN BIT(15) ++#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13) ++#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13) ++#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13) ++#define FE_MDIO_CFG_GP1_DUPLEX BIT(12) ++#define FE_MDIO_CFG_GP1_FC_TX BIT(11) ++#define FE_MDIO_CFG_GP1_FC_RX BIT(10) ++#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9) ++#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8) ++#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6) ++#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6) ++#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6) ++#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6) ++#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5) ++#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4) ++#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2) ++#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2) ++#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2) ++#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2) ++#define FE_MDIO_CFG_TX_CLK_SKEW_0 0 ++#define FE_MDIO_CFG_TX_CLK_SKEW_200 1 ++#define FE_MDIO_CFG_TX_CLK_SKEW_400 2 ++#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3 ++ ++/* uni-cast port */ ++#define FE_GDM1_ICS_EN BIT(22) ++#define FE_GDM1_TCS_EN BIT(21) ++#define FE_GDM1_UCS_EN BIT(20) ++#define FE_GDM1_JMB_EN BIT(19) ++#define FE_GDM1_STRPCRC BIT(16) ++#define FE_GDM1_UFRC_P_CPU (0 << 12) ++#define FE_GDM1_UFRC_P_GDMA1 (1 << 12) ++#define FE_GDM1_UFRC_P_PPE (6 << 12) ++ ++/* checksums */ ++#define FE_ICS_GEN_EN BIT(2) ++#define FE_UCS_GEN_EN BIT(1) ++#define FE_TCS_GEN_EN BIT(0) ++ ++/* dma ring */ ++#define FE_PST_DRX_IDX0 BIT(16) ++#define FE_PST_DTX_IDX3 BIT(3) ++#define FE_PST_DTX_IDX2 BIT(2) ++#define FE_PST_DTX_IDX1 BIT(1) ++#define FE_PST_DTX_IDX0 BIT(0) ++ ++#define FE_TX_WB_DDONE BIT(6) ++#define FE_RX_DMA_BUSY BIT(3) ++#define FE_TX_DMA_BUSY BIT(1) ++#define FE_RX_DMA_EN BIT(2) ++#define FE_TX_DMA_EN BIT(0) ++ ++#define FE_PDMA_SIZE_4DWORDS (0 << 4) ++#define FE_PDMA_SIZE_8DWORDS (1 << 4) ++#define FE_PDMA_SIZE_16DWORDS (2 << 4) ++ ++#define FE_US_CYC_CNT_MASK 0xff ++#define FE_US_CYC_CNT_SHIFT 0x8 ++#define FE_US_CYC_CNT_DIVISOR 1000000 ++ ++#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff) ++#define RX_DMA_LSO BIT(30) ++#define RX_DMA_DONE BIT(31) ++#define RX_DMA_L4VALID BIT(30) ++ ++struct fe_rx_dma { ++ unsigned int rxd1; ++ unsigned int rxd2; ++ unsigned int rxd3; ++ unsigned int rxd4; ++} __packed __aligned(4); ++ ++#define TX_DMA_PLEN0_MASK ((0x3fff) << 16) ++#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) ++#define TX_DMA_LSO BIT(30) ++#define TX_DMA_DONE BIT(31) ++#define TX_DMA_QN(_x) ((_x) << 16) ++#define TX_DMA_PN(_x) ((_x) << 24) ++#define TX_DMA_QN_MASK TX_DMA_QN(0x7) ++#define TX_DMA_PN_MASK TX_DMA_PN(0x7) ++#define TX_DMA_CHKSUM (0x7 << 29) ++ ++struct fe_tx_dma { ++ unsigned int txd1; ++ unsigned int txd2; ++ unsigned int txd3; ++ unsigned int txd4; ++} __packed __aligned(4); ++ ++struct fe_priv; ++ ++struct fe_phy { ++ struct phy_device *phy[8]; ++ struct device_node *phy_node[8]; ++ const __be32 *phy_fixed[8]; ++ int duplex[8]; ++ int speed[8]; ++ spinlock_t lock; ++ ++ int (*connect)(struct fe_priv *priv); ++ void (*disconnect)(struct fe_priv *priv); ++ void (*start)(struct fe_priv *priv); ++ void (*stop)(struct fe_priv *priv); ++}; ++ ++struct fe_soc_data ++{ ++ unsigned char mac[6]; ++ const u32 *reg_table; ++ ++ void (*reset_fe)(void); ++ void (*set_mac)(struct fe_priv *priv, unsigned char *mac); ++ void (*fwd_config)(struct fe_priv *priv); ++ void (*tx_dma)(struct fe_priv *priv, int idx, int len); ++ void (*rx_dma)(struct fe_priv *priv, int idx, int len); ++ int (*switch_init)(struct fe_priv *priv); ++ void (*port_init)(struct fe_priv *priv, struct device_node *port); ++ int (*has_carrier)(struct fe_priv *priv); ++ int (*mdio_init)(struct fe_priv *priv); ++ void (*mdio_cleanup)(struct fe_priv *priv); ++ int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val); ++ int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg); ++ void (*mdio_adjust_link)(struct fe_priv *priv, int port); ++ ++ void *swpriv; ++ u32 pdma_glo_cfg; ++ u32 rx_dly_int; ++ u32 tx_dly_int; ++ u32 checksum_bit; ++ ++ int min_pkt_len; ++}; ++ ++struct fe_priv ++{ ++ spinlock_t page_lock; ++ ++ struct fe_soc_data *soc; ++ struct net_device *netdev; ++ struct device *device; ++ unsigned long sysclk; ++ ++ struct fe_rx_dma *rx_dma; ++ struct sk_buff *rx_skb[NUM_DMA_DESC]; ++ struct napi_struct rx_napi; ++ dma_addr_t rx_phys; ++ ++ struct fe_tx_dma *tx_dma; ++ struct sk_buff *tx_skb[NUM_DMA_DESC]; ++ struct napi_struct tx_napi; ++ dma_addr_t tx_phys; ++ unsigned int tx_free_idx; ++ ++ struct fe_phy *phy; ++ struct mii_bus *mii_bus; ++ int mii_irq[PHY_MAX_ADDR]; ++ ++ int link[8]; ++}; ++ ++extern const struct of_device_id of_fe_match[]; ++ ++void fe_w32(u32 val, unsigned reg); ++u32 fe_r32(unsigned reg); ++ ++#endif /* FE_ETH_H */ +diff --git a/drivers/net/ethernet/ralink/soc_mt7620.c b/drivers/net/ethernet/ralink/soc_mt7620.c +new file mode 100644 +index 0000000..55e303f +--- /dev/null ++++ b/drivers/net/ethernet/ralink/soc_mt7620.c +@@ -0,0 +1,111 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++#include <linux/platform_device.h> ++ ++#include <asm/mach-ralink/ralink_regs.h> ++ ++#include "ralink_soc_eth.h" ++#include "gsw_mt7620a.h" ++ ++#define MT7620A_CDMA_CSG_CFG 0x400 ++#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30) ++#define MT7620A_DMA_2B_OFFSET BIT(31) ++#define MT7620A_RESET_FE BIT(21) ++#define MT7620A_RESET_ESW BIT(23) ++#define MT7620_L4_VALID BIT(23) ++ ++#define SYSC_REG_RESET_CTRL 0x34 ++#define MAX_RX_LENGTH 1536 ++ ++#define CDMA_ICS_EN BIT(2) ++#define CDMA_UCS_EN BIT(1) ++#define CDMA_TCS_EN BIT(0) ++ ++#define GDMA_ICS_EN BIT(22) ++#define GDMA_TCS_EN BIT(21) ++#define GDMA_UCS_EN BIT(20) ++ ++static const u32 rt5350_reg_table[FE_REG_COUNT] = { ++ [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, ++ [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, ++ [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, ++ [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0, ++ [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0, ++ [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0, ++ [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0, ++ [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0, ++ [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0, ++ [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE, ++ [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS, ++ [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID, ++}; ++ ++static void mt7620_fe_reset(void) ++{ ++ rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL); ++ rt_sysc_w32(0, SYSC_REG_RESET_CTRL); ++} ++ ++static void mt7620_fwd_config(struct fe_priv *priv) ++{ ++ fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG); ++ fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG); ++ fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG); ++} ++ ++static void mt7620_tx_dma(struct fe_priv *priv, int idx, int len) ++{ ++ if (len) ++ priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len); ++ else ++ priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE; ++} ++ ++static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len) ++{ ++ priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len); ++} ++ ++static struct fe_soc_data mt7620_data = { ++ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 }, ++ .reset_fe = mt7620_fe_reset, ++ .set_mac = mt7620_set_mac, ++ .fwd_config = mt7620_fwd_config, ++ .tx_dma = mt7620_tx_dma, ++ .rx_dma = mt7620_rx_dma, ++ .switch_init = mt7620_gsw_probe, ++ .port_init = mt7620_port_init, ++ .min_pkt_len = 0, ++ .reg_table = rt5350_reg_table, ++ .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET, ++ .rx_dly_int = RT5350_RX_DLY_INT, ++ .tx_dly_int = RT5350_TX_DLY_INT, ++ .checksum_bit = MT7620_L4_VALID, ++ .has_carrier = mt7620a_has_carrier, ++ .mdio_read = mt7620_mdio_read, ++ .mdio_write = mt7620_mdio_write, ++ .mdio_adjust_link = mt7620_mdio_link_adjust, ++}; ++ ++const struct of_device_id of_fe_match[] = { ++ { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, of_fe_match); +diff --git a/drivers/net/ethernet/ralink/soc_rt2880.c b/drivers/net/ethernet/ralink/soc_rt2880.c +new file mode 100644 +index 0000000..fdbd118 +--- /dev/null ++++ b/drivers/net/ethernet/ralink/soc_rt2880.c +@@ -0,0 +1,51 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++ ++#include <asm/mach-ralink/ralink_regs.h> ++ ++#include "ralink_soc_eth.h" ++#include "mdio_rt2880.h" ++ ++#define SYSC_REG_RESET_CTRL 0x034 ++#define RT2880_RESET_FE BIT(18) ++ ++void rt2880_fe_reset(void) ++{ ++ rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL); ++} ++ ++struct fe_soc_data rt2880_data = { ++ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 }, ++ .reset_fe = rt2880_fe_reset, ++ .min_pkt_len = 64, ++ .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS, ++ .checksum_bit = RX_DMA_L4VALID, ++ .rx_dly_int = FE_RX_DLY_INT, ++ .tx_dly_int = FE_TX_DLY_INT, ++ .mdio_read = rt2880_mdio_read, ++ .mdio_write = rt2880_mdio_write, ++ .mdio_link_adjust = rt2880_mdio_link_adjust, ++}; ++ ++const struct of_device_id of_fe_match[] = { ++ { .compatible = "ralink,rt2880-eth", .data = &rt2880_data }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, of_fe_match); +diff --git a/drivers/net/ethernet/ralink/soc_rt305x.c b/drivers/net/ethernet/ralink/soc_rt305x.c +new file mode 100644 +index 0000000..c43d3f9 +--- /dev/null ++++ b/drivers/net/ethernet/ralink/soc_rt305x.c +@@ -0,0 +1,102 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++ ++#include <asm/mach-ralink/ralink_regs.h> ++ ++#include "ralink_soc_eth.h" ++ ++#define RT305X_RESET_FE BIT(21) ++#define RT305X_RESET_ESW BIT(23) ++#define SYSC_REG_RESET_CTRL 0x034 ++ ++static const u32 rt5350_reg_table[FE_REG_COUNT] = { ++ [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, ++ [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, ++ [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, ++ [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0, ++ [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0, ++ [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0, ++ [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0, ++ [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0, ++ [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0, ++ [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE, ++ [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS, ++ [FE_REG_FE_DMA_VID_BASE] = 0, ++}; ++ ++static void rt305x_fe_reset(void) ++{ ++ rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL); ++ rt_sysc_w32(0, SYSC_REG_RESET_CTRL); ++} ++ ++static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->page_lock, flags); ++ fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH); ++ fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], ++ RT5350_SDM_MAC_ADRL); ++ spin_unlock_irqrestore(&priv->page_lock, flags); ++} ++ ++static void rt5350_fwd_config(struct fe_priv *priv) ++{ ++ fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG); ++ fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN, ++ RT5350_SDM_CFG); ++} ++ ++static void rt5350_fe_reset(void) ++{ ++ rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL); ++ rt_sysc_w32(0, SYSC_REG_RESET_CTRL); ++} ++ ++static struct fe_soc_data rt3050_data = { ++ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 }, ++ .reset_fe = rt305x_fe_reset, ++ .min_pkt_len = 64, ++ .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS, ++ .checksum_bit = RX_DMA_L4VALID, ++ .rx_dly_int = FE_RX_DLY_INT, ++ .tx_dly_int = FE_TX_DLY_INT, ++}; ++ ++static struct fe_soc_data rt5350_data = { ++ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 }, ++ .reg_table = rt5350_reg_table, ++ .reset_fe = rt5350_fe_reset, ++ .set_mac = rt5350_set_mac, ++ .fwd_config = rt5350_fwd_config, ++ .min_pkt_len = 64, ++ .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS, ++ .checksum_bit = RX_DMA_L4VALID, ++ .rx_dly_int = RT5350_RX_DLY_INT, ++ .tx_dly_int = RT5350_TX_DLY_INT, ++}; ++ ++const struct of_device_id of_fe_match[] = { ++ { .compatible = "ralink,rt3050-eth", .data = &rt3050_data }, ++ { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, of_fe_match); +diff --git a/drivers/net/ethernet/ralink/soc_rt3883.c b/drivers/net/ethernet/ralink/soc_rt3883.c +new file mode 100644 +index 0000000..3886be1 +--- /dev/null ++++ b/drivers/net/ethernet/ralink/soc_rt3883.c +@@ -0,0 +1,59 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++ ++#include <asm/mach-ralink/ralink_regs.h> ++ ++#include "ralink_soc_eth.h" ++#include "mdio_rt2880.h" ++ ++#define RT3883_SYSC_REG_RSTCTRL 0x34 ++#define RT3883_RSTCTRL_FE BIT(21) ++ ++static void rt3883_fe_reset(void) ++{ ++ u32 t; ++ ++ t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); ++ t |= RT3883_RSTCTRL_FE; ++ rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL); ++ ++ t &= ~RT3883_RSTCTRL_FE; ++ rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); ++} ++ ++static struct fe_soc_data rt3883_data = { ++ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 }, ++ .reset_fe = rt3883_fe_reset, ++ .min_pkt_len = 64, ++ .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS, ++ .rx_dly_int = FE_RX_DLY_INT, ++ .tx_dly_int = FE_TX_DLY_INT, ++ .checksum_bit = RX_DMA_L4VALID, ++ .mdio_read = rt2880_mdio_read, ++ .mdio_write = rt2880_mdio_write, ++ .mdio_link_adjust = rt2880_mdio_link_adjust, ++}; ++ ++const struct of_device_id of_fe_match[] = { ++ { .compatible = "ralink,rt3883-eth", .data = &rt3883_data }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, of_fe_match); ++ +-- +1.7.10.4 + |