1 files changed, 80 insertions, 0 deletions
diff --git a/target/linux/sibyte/patches-3.3/104-sibyte_rtc_cleanup.patch b/target/linux/sibyte/patches-3.3/104-sibyte_rtc_cleanup.patch
new file mode 100644
index 0000000..0483142
--- /dev/null
+++ b/target/linux/sibyte/patches-3.3/104-sibyte_rtc_cleanup.patch
@@ -0,0 +1,80 @@
+--- a/arch/mips/sibyte/swarm/setup.c
++++ b/arch/mips/sibyte/swarm/setup.c
+@@ -56,14 +56,6 @@ extern void sb1250_setup(void);
+ #error invalid SiByte board configuration
+ #endif
+ 
+-extern int xicor_probe(void);
+-extern int xicor_set_time(unsigned long);
+-extern unsigned long xicor_get_time(void);
+-
+-extern int m41t81_probe(void);
+-extern int m41t81_set_time(unsigned long);
+-extern unsigned long m41t81_get_time(void);
+-
+ const char *get_system_type(void)
+ {
+ 	return "SiByte " SIBYTE_BOARD_NAME;
+@@ -79,49 +71,18 @@ int swarm_be_handler(struct pt_regs *reg
+ 	return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
+ }
+ 
+-enum swarm_rtc_type {
+-	RTC_NONE,
+-	RTC_XICOR,
+-	RTC_M41T81,
+-};
+-
+-enum swarm_rtc_type swarm_rtc_type;
+-
+ void read_persistent_clock(struct timespec *ts)
+ {
+ 	unsigned long sec;
+ 
+-	switch (swarm_rtc_type) {
+-	case RTC_XICOR:
+-		sec = xicor_get_time();
+-		break;
+-
+-	case RTC_M41T81:
+-		sec = m41t81_get_time();
+-		break;
+-
+-	case RTC_NONE:
+-	default:
+-		sec = mktime(2000, 1, 1, 0, 0, 0);
+-		break;
+-	}
++	sec = mktime(2000, 1, 1, 0, 0, 0);
+ 	ts->tv_sec = sec;
+ 	ts->tv_nsec = 0;
+ }
+ 
+ int rtc_mips_set_time(unsigned long sec)
+ {
+-	switch (swarm_rtc_type) {
+-	case RTC_XICOR:
+-		return xicor_set_time(sec);
+-
+-	case RTC_M41T81:
+-		return m41t81_set_time(sec);
+-
+-	case RTC_NONE:
+-	default:
+ 		return -1;
+-	}
+ }
+ 
+ void __init plat_mem_setup(void)
+@@ -138,11 +99,6 @@ void __init plat_mem_setup(void)
+ 
+ 	board_be_handler = swarm_be_handler;
+ 
+-	if (xicor_probe())
+-		swarm_rtc_type = RTC_XICOR;
+-	if (m41t81_probe())
+-		swarm_rtc_type = RTC_M41T81;
+-
+ #ifdef CONFIG_VT
+ 	screen_info = (struct screen_info) {
+ 		.orig_video_page	= 52,