diff options
Diffstat (limited to 'target/linux/sunxi/patches-3.13/126-dt-sun7i-add-external-clock-outputs.patch')
| -rw-r--r-- | target/linux/sunxi/patches-3.13/126-dt-sun7i-add-external-clock-outputs.patch | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-3.13/126-dt-sun7i-add-external-clock-outputs.patch b/target/linux/sunxi/patches-3.13/126-dt-sun7i-add-external-clock-outputs.patch new file mode 100644 index 0000000..84ca843 --- /dev/null +++ b/target/linux/sunxi/patches-3.13/126-dt-sun7i-add-external-clock-outputs.patch @@ -0,0 +1,58 @@ +From 0aff0370cbffeadc14456556b904c80e30b3717e Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai <wens@csie.org> +Date: Wed, 1 Jan 2014 10:30:48 +0800 +Subject: [PATCH] ARM: dts: sun7i: external clock outputs + +This commit adds the two external clock outputs available on A20 to +its device tree. A dummy fixed factor clock is also added to serve as +the first input of the clock outputs, which according to AW's A20 user +manual, is the 24MHz oscillator divided by 750. + +Signed-off-by: Chen-Yu Tsai <wens@csie.org> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi +index edad6f1..0d54998 100644 +--- a/arch/arm/boot/dts/sun7i-a20.dtsi ++++ b/arch/arm/boot/dts/sun7i-a20.dtsi +@@ -303,6 +303,34 @@ + clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; + clock-output-names = "mbus"; + }; ++ ++ /* ++ * Dummy clock used by output clocks ++ */ ++ osc24M_32k: clk@1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clock-div = <750>; ++ clock-mult = <1>; ++ clocks = <&osc24M>; ++ clock-output-names = "osc24M_32k"; ++ }; ++ ++ clk_out_a: clk@01c201f0 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun7i-a20-out-clk"; ++ reg = <0x01c201f0 0x4>; ++ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; ++ clock-output-names = "clk_out_a"; ++ }; ++ ++ clk_out_b: clk@01c201f4 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun7i-a20-out-clk"; ++ reg = <0x01c201f4 0x4>; ++ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; ++ clock-output-names = "clk_out_b"; ++ }; + }; + + soc@01c00000 { +-- +1.8.5.5 + |