diff options
Diffstat (limited to 'target/linux')
38 files changed, 3769 insertions, 1463 deletions
diff --git a/target/linux/brcm47xx/config-3.6 b/target/linux/brcm47xx/config-3.6 index ae56ccf..7f1ea7d 100644 --- a/target/linux/brcm47xx/config-3.6 +++ b/target/linux/brcm47xx/config-3.6 @@ -3,9 +3,9 @@ CONFIG_ARCH_DISCARD_MEMBLOCK=y CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y # CONFIG_ARPD is not set CONFIG_BCM47XX=y CONFIG_BCM47XX_BCMA=y @@ -15,6 +15,7 @@ CONFIG_BCMA=y CONFIG_BCMA_BLOCKIO=y CONFIG_BCMA_DEBUG=y CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y CONFIG_BCMA_DRIVER_MIPS=y CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y CONFIG_BCMA_HOST_PCI=y @@ -120,6 +121,7 @@ CONFIG_SSB_BLOCKIO=y CONFIG_SSB_DEBUG=y CONFIG_SSB_DRIVER_EXTIF=y CONFIG_SSB_DRIVER_GIGE=y +CONFIG_SSB_DRIVER_GPIO=y CONFIG_SSB_DRIVER_MIPS=y CONFIG_SSB_DRIVER_PCICORE=y CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y diff --git a/target/linux/brcm47xx/patches-3.6/015-MIPS-BCM47XX-remove-GPIO-driver.patch b/target/linux/brcm47xx/patches-3.6/015-MIPS-BCM47XX-remove-GPIO-driver.patch new file mode 100644 index 0000000..b39bdc4 --- /dev/null +++ b/target/linux/brcm47xx/patches-3.6/015-MIPS-BCM47XX-remove-GPIO-driver.patch @@ -0,0 +1,360 @@ +commit 2da4c74dc3711275e82856e62884c99f7a45f541 +Author: Hauke Mehrtens <hauke@hauke-m.de> +Date: Tue Nov 20 22:24:34 2012 +0000 + + MIPS: BCM47XX: remove GPIO driver + + Instated of providing an own GPIO driver use the one provided by ssb and + bcma. + + Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> + Patchwork: http://patchwork.linux-mips.org/patch/4592 + Acked-by: Florian Fainelli <florian@openwrt.org> + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -101,6 +101,7 @@ config ATH79 + + config BCM47XX + bool "Broadcom BCM47XX based boards" ++ select ARCH_WANT_OPTIONAL_GPIOLIB + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT +@@ -108,7 +109,6 @@ config BCM47XX + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN +- select GENERIC_GPIO + select SYS_HAS_EARLY_PRINTK + select CFE + help +--- a/arch/mips/bcm47xx/Kconfig ++++ b/arch/mips/bcm47xx/Kconfig +@@ -9,6 +9,7 @@ config BCM47XX_SSB + select SSB_EMBEDDED + select SSB_B43_PCI_BRIDGE if PCI + select SSB_PCICORE_HOSTMODE if PCI ++ select SSB_DRIVER_GPIO + default y + help + Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support. +@@ -23,6 +24,7 @@ config BCM47XX_BCMA + select BCMA_DRIVER_MIPS + select BCMA_HOST_PCI if PCI + select BCMA_DRIVER_PCI_HOSTMODE if PCI ++ select BCMA_DRIVER_GPIO + default y + help + Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus. +--- a/arch/mips/bcm47xx/Makefile ++++ b/arch/mips/bcm47xx/Makefile +@@ -3,5 +3,5 @@ + # under Linux. + # + +-obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o sprom.o ++obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o + obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o +--- a/arch/mips/bcm47xx/gpio.c ++++ /dev/null +@@ -1,102 +0,0 @@ +-/* +- * This file is subject to the terms and conditions of the GNU General Public +- * License. See the file "COPYING" in the main directory of this archive +- * for more details. +- * +- * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net> +- */ +- +-#include <linux/export.h> +-#include <linux/ssb/ssb.h> +-#include <linux/ssb/ssb_driver_chipcommon.h> +-#include <linux/ssb/ssb_driver_extif.h> +-#include <asm/mach-bcm47xx/bcm47xx.h> +-#include <asm/mach-bcm47xx/gpio.h> +- +-#if (BCM47XX_CHIPCO_GPIO_LINES > BCM47XX_EXTIF_GPIO_LINES) +-static DECLARE_BITMAP(gpio_in_use, BCM47XX_CHIPCO_GPIO_LINES); +-#else +-static DECLARE_BITMAP(gpio_in_use, BCM47XX_EXTIF_GPIO_LINES); +-#endif +- +-int gpio_request(unsigned gpio, const char *tag) +-{ +- switch (bcm47xx_bus_type) { +-#ifdef CONFIG_BCM47XX_SSB +- case BCM47XX_BUS_TYPE_SSB: +- if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && +- ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) +- return -EINVAL; +- +- if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && +- ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) +- return -EINVAL; +- +- if (test_and_set_bit(gpio, gpio_in_use)) +- return -EBUSY; +- +- return 0; +-#endif +-#ifdef CONFIG_BCM47XX_BCMA +- case BCM47XX_BUS_TYPE_BCMA: +- if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) +- return -EINVAL; +- +- if (test_and_set_bit(gpio, gpio_in_use)) +- return -EBUSY; +- +- return 0; +-#endif +- } +- return -EINVAL; +-} +-EXPORT_SYMBOL(gpio_request); +- +-void gpio_free(unsigned gpio) +-{ +- switch (bcm47xx_bus_type) { +-#ifdef CONFIG_BCM47XX_SSB +- case BCM47XX_BUS_TYPE_SSB: +- if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && +- ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) +- return; +- +- if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && +- ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) +- return; +- +- clear_bit(gpio, gpio_in_use); +- return; +-#endif +-#ifdef CONFIG_BCM47XX_BCMA +- case BCM47XX_BUS_TYPE_BCMA: +- if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) +- return; +- +- clear_bit(gpio, gpio_in_use); +- return; +-#endif +- } +-} +-EXPORT_SYMBOL(gpio_free); +- +-int gpio_to_irq(unsigned gpio) +-{ +- switch (bcm47xx_bus_type) { +-#ifdef CONFIG_BCM47XX_SSB +- case BCM47XX_BUS_TYPE_SSB: +- if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco)) +- return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2; +- else if (ssb_extif_available(&bcm47xx_bus.ssb.extif)) +- return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2; +- else +- return -EINVAL; +-#endif +-#ifdef CONFIG_BCM47XX_BCMA +- case BCM47XX_BUS_TYPE_BCMA: +- return bcma_core_mips_irq(bcm47xx_bus.bcma.bus.drv_cc.core) + 2; +-#endif +- } +- return -EINVAL; +-} +-EXPORT_SYMBOL_GPL(gpio_to_irq); +--- a/arch/mips/bcm47xx/wgt634u.c ++++ b/arch/mips/bcm47xx/wgt634u.c +@@ -11,6 +11,7 @@ + #include <linux/leds.h> + #include <linux/mtd/physmap.h> + #include <linux/ssb/ssb.h> ++#include <linux/ssb/ssb_embedded.h> + #include <linux/interrupt.h> + #include <linux/reboot.h> + #include <linux/gpio.h> +@@ -116,7 +117,8 @@ static irqreturn_t gpio_interrupt(int ir + + /* Interrupt are level triggered, revert the interrupt polarity + to clear the interrupt. */ +- gpio_polarity(WGT634U_GPIO_RESET, state); ++ ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << WGT634U_GPIO_RESET, ++ state ? 1 << WGT634U_GPIO_RESET : 0); + + if (!state) { + printk(KERN_INFO "Reset button pressed"); +@@ -150,7 +152,9 @@ static int __init wgt634u_init(void) + gpio_interrupt, IRQF_SHARED, + "WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) { + gpio_direction_input(WGT634U_GPIO_RESET); +- gpio_intmask(WGT634U_GPIO_RESET, 1); ++ ssb_gpio_intmask(&bcm47xx_bus.ssb, ++ 1 << WGT634U_GPIO_RESET, ++ 1 << WGT634U_GPIO_RESET); + ssb_chipco_irq_mask(&bcm47xx_bus.ssb.chipco, + SSB_CHIPCO_IRQ_GPIO, + SSB_CHIPCO_IRQ_GPIO); +--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h ++++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h +@@ -1,155 +1,17 @@ +-/* +- * This file is subject to the terms and conditions of the GNU General Public +- * License. See the file "COPYING" in the main directory of this archive +- * for more details. +- * +- * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net> +- */ ++#ifndef __ASM_MIPS_MACH_BCM47XX_GPIO_H ++#define __ASM_MIPS_MACH_BCM47XX_GPIO_H + +-#ifndef __BCM47XX_GPIO_H +-#define __BCM47XX_GPIO_H ++#include <asm-generic/gpio.h> + +-#include <linux/ssb/ssb_embedded.h> +-#include <linux/bcma/bcma.h> +-#include <asm/mach-bcm47xx/bcm47xx.h> ++#define gpio_get_value __gpio_get_value ++#define gpio_set_value __gpio_set_value + +-#define BCM47XX_EXTIF_GPIO_LINES 5 +-#define BCM47XX_CHIPCO_GPIO_LINES 16 ++#define gpio_cansleep __gpio_cansleep ++#define gpio_to_irq __gpio_to_irq + +-extern int gpio_request(unsigned gpio, const char *label); +-extern void gpio_free(unsigned gpio); +-extern int gpio_to_irq(unsigned gpio); +- +-static inline int gpio_get_value(unsigned gpio) ++static inline int irq_to_gpio(unsigned int irq) + { +- switch (bcm47xx_bus_type) { +-#ifdef CONFIG_BCM47XX_SSB +- case BCM47XX_BUS_TYPE_SSB: +- return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio); +-#endif +-#ifdef CONFIG_BCM47XX_BCMA +- case BCM47XX_BUS_TYPE_BCMA: +- return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, +- 1 << gpio); +-#endif +- } + return -EINVAL; + } + +-#define gpio_get_value_cansleep gpio_get_value +- +-static inline void gpio_set_value(unsigned gpio, int value) +-{ +- switch (bcm47xx_bus_type) { +-#ifdef CONFIG_BCM47XX_SSB +- case BCM47XX_BUS_TYPE_SSB: +- ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio, +- value ? 1 << gpio : 0); +- return; +-#endif +-#ifdef CONFIG_BCM47XX_BCMA +- case BCM47XX_BUS_TYPE_BCMA: +- bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, +- value ? 1 << gpio : 0); +- return; + #endif +- } +-} +- +-#define gpio_set_value_cansleep gpio_set_value +- +-static inline int gpio_cansleep(unsigned gpio) +-{ +- return 0; +-} +- +-static inline int gpio_is_valid(unsigned gpio) +-{ +- return gpio < (BCM47XX_EXTIF_GPIO_LINES + BCM47XX_CHIPCO_GPIO_LINES); +-} +- +- +-static inline int gpio_direction_input(unsigned gpio) +-{ +- switch (bcm47xx_bus_type) { +-#ifdef CONFIG_BCM47XX_SSB +- case BCM47XX_BUS_TYPE_SSB: +- ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0); +- return 0; +-#endif +-#ifdef CONFIG_BCM47XX_BCMA +- case BCM47XX_BUS_TYPE_BCMA: +- bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, +- 0); +- return 0; +-#endif +- } +- return -EINVAL; +-} +- +-static inline int gpio_direction_output(unsigned gpio, int value) +-{ +- switch (bcm47xx_bus_type) { +-#ifdef CONFIG_BCM47XX_SSB +- case BCM47XX_BUS_TYPE_SSB: +- /* first set the gpio out value */ +- ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio, +- value ? 1 << gpio : 0); +- /* then set the gpio mode */ +- ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio); +- return 0; +-#endif +-#ifdef CONFIG_BCM47XX_BCMA +- case BCM47XX_BUS_TYPE_BCMA: +- /* first set the gpio out value */ +- bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, +- value ? 1 << gpio : 0); +- /* then set the gpio mode */ +- bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, +- 1 << gpio); +- return 0; +-#endif +- } +- return -EINVAL; +-} +- +-static inline int gpio_intmask(unsigned gpio, int value) +-{ +- switch (bcm47xx_bus_type) { +-#ifdef CONFIG_BCM47XX_SSB +- case BCM47XX_BUS_TYPE_SSB: +- ssb_gpio_intmask(&bcm47xx_bus.ssb, 1 << gpio, +- value ? 1 << gpio : 0); +- return 0; +-#endif +-#ifdef CONFIG_BCM47XX_BCMA +- case BCM47XX_BUS_TYPE_BCMA: +- bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc, +- 1 << gpio, value ? 1 << gpio : 0); +- return 0; +-#endif +- } +- return -EINVAL; +-} +- +-static inline int gpio_polarity(unsigned gpio, int value) +-{ +- switch (bcm47xx_bus_type) { +-#ifdef CONFIG_BCM47XX_SSB +- case BCM47XX_BUS_TYPE_SSB: +- ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << gpio, +- value ? 1 << gpio : 0); +- return 0; +-#endif +-#ifdef CONFIG_BCM47XX_BCMA +- case BCM47XX_BUS_TYPE_BCMA: +- bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc, +- 1 << gpio, value ? 1 << gpio : 0); +- return 0; +-#endif +- } +- return -EINVAL; +-} +- +- +-#endif /* __BCM47XX_GPIO_H */ diff --git a/target/linux/brcm47xx/patches-3.6/016-MIPS-BCM47XX-select-GPIOLIB-for-BCMA-on-bcm47xx-platform.patch b/target/linux/brcm47xx/patches-3.6/016-MIPS-BCM47XX-select-GPIOLIB-for-BCMA-on-bcm47xx-platform.patch new file mode 100644 index 0000000..dba65de --- /dev/null +++ b/target/linux/brcm47xx/patches-3.6/016-MIPS-BCM47XX-select-GPIOLIB-for-BCMA-on-bcm47xx-platform.patch @@ -0,0 +1,21 @@ +--- a/arch/mips/bcm47xx/Kconfig ++++ b/arch/mips/bcm47xx/Kconfig +@@ -8,8 +8,10 @@ config BCM47XX_SSB + select SSB_DRIVER_EXTIF + select SSB_EMBEDDED + select SSB_B43_PCI_BRIDGE if PCI ++ select SSB_DRIVER_PCICORE if PCI + select SSB_PCICORE_HOSTMODE if PCI + select SSB_DRIVER_GPIO ++ select GPIOLIB + default y + help + Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support. +@@ -25,6 +27,7 @@ config BCM47XX_BCMA + select BCMA_HOST_PCI if PCI + select BCMA_DRIVER_PCI_HOSTMODE if PCI + select BCMA_DRIVER_GPIO ++ select GPIOLIB + default y + help + Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus. diff --git a/target/linux/brcm47xx/patches-3.6/060-ssb-add-serial-flash-driver.patch b/target/linux/brcm47xx/patches-3.6/060-ssb-add-serial-flash-driver.patch index 8b218f3..c40a58e 100644 --- a/target/linux/brcm47xx/patches-3.6/060-ssb-add-serial-flash-driver.patch +++ b/target/linux/brcm47xx/patches-3.6/060-ssb-add-serial-flash-driver.patch @@ -1,47 +1,36 @@ --- a/drivers/ssb/Kconfig +++ b/drivers/ssb/Kconfig -@@ -143,6 +143,11 @@ config SSB_EMBEDDED - depends on SSB_DRIVER_MIPS - default y +@@ -139,7 +139,7 @@ config SSB_DRIVER_MIPS -+config SSB_SFLASH -+ bool + config SSB_SFLASH + bool "SSB serial flash support" +- depends on SSB_DRIVER_MIPS && BROKEN + depends on SSB_DRIVER_MIPS -+ default y -+ - config SSB_DRIVER_EXTIF - bool "SSB Broadcom EXTIF core driver" - depends on SSB_DRIVER_MIPS ---- a/drivers/ssb/Makefile -+++ b/drivers/ssb/Makefile -@@ -11,6 +11,7 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o - # built-in drivers - ssb-y += driver_chipcommon.o - ssb-y += driver_chipcommon_pmu.o -+ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o - ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o - ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o - ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o ---- /dev/null + default y + + # Assumption: We are on embedded, if we compile the MIPS core. +--- a/drivers/ssb/driver_chipcommon_sflash.c +++ b/drivers/ssb/driver_chipcommon_sflash.c -@@ -0,0 +1,395 @@ -+/* -+ * Broadcom specific AMBA -+ * ChipCommon serial flash interface +@@ -1,18 +1,395 @@ + /* + * Sonics Silicon Backplane + * ChipCommon serial flash interface + * Copyright 2011, Jonas Gorski <jonas.gorski@gmail.com> + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> + * Copyright 2010, Broadcom Corporation -+ * -+ * Licensed under the GNU/GPL. See COPYING for details. -+ */ -+ + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +#include <linux/platform_device.h> +#include <linux/delay.h> -+#include <linux/ssb/ssb.h> + #include <linux/ssb/ssb.h> +#include <linux/ssb/ssb_driver_chipcommon.h> -+ -+#include "ssb_private.h" -+ + + #include "ssb_private.h" + +-/* Initialize serial flash access */ +-int ssb_sflash_init(struct ssb_chipcommon *cc) +#define NUM_RETRIES 3 + +static struct resource ssb_sflash_resource = { @@ -169,7 +158,8 @@ + +/* Poll for command completion. Returns zero when complete. */ +static int ssb_sflash_poll(struct bcm47xx_sflash *dev, u32 offset) -+{ + { +- pr_err("Serial flash support is not implemented yet!\n"); + struct ssb_chipcommon *chipco = dev->scc; + + if (offset >= chipco->sflash.size) @@ -417,21 +407,10 @@ + ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start + + sflash->size; + ssb_sflash_dev.dev.platform_data = sflash; -+ + +- return -ENOTSUPP; + return 0; -+} ---- a/drivers/ssb/driver_mipscore.c -+++ b/drivers/ssb/driver_mipscore.c -@@ -203,7 +203,8 @@ static void ssb_mips_flash_detect(struct - switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) { - case SSB_CHIPCO_FLASHT_STSER: - case SSB_CHIPCO_FLASHT_ATSER: -- pr_err("Serial flash not supported\n"); -+ pr_debug("Found serial flash\n"); -+ ssb_sflash_init(&bus->chipco); - break; - case SSB_CHIPCO_FLASHT_PARA: - pr_debug("Found parallel flash\n"); + } --- a/drivers/ssb/main.c +++ b/drivers/ssb/main.c @@ -19,6 +19,7 @@ @@ -460,23 +439,14 @@ /* Unwind the already registered devices. */ --- a/drivers/ssb/ssb_private.h +++ b/drivers/ssb/ssb_private.h -@@ -242,4 +242,16 @@ static inline int ssb_watchdog_register( - } - #endif /* CONFIG_SSB_EMBEDDED */ - -+#ifdef CONFIG_SSB_SFLASH -+/* driver_chipcommon_sflash.c */ -+int ssb_sflash_init(struct ssb_chipcommon *chipco); +@@ -220,6 +220,7 @@ extern u32 ssb_chipco_watchdog_timer_set + /* driver_chipcommon_sflash.c */ + #ifdef CONFIG_SSB_SFLASH + int ssb_sflash_init(struct ssb_chipcommon *cc); +extern struct platform_device ssb_sflash_dev; -+#else -+static inline int ssb_sflash_init(struct ssb_chipcommon *chipco) -+{ -+ pr_err("Serial flash not supported\n"); -+ return 0; -+} -+#endif /* CONFIG_SSB_SFLASH */ -+ - #endif /* LINUX_SSB_PRIVATE_H_ */ + #else + static inline int ssb_sflash_init(struct ssb_chipcommon *cc) + { --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h @@ -13,6 +13,8 @@ @@ -515,7 +485,7 @@ #define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */ #define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */ #define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */ -@@ -593,6 +606,9 @@ struct ssb_chipcommon { +@@ -594,6 +607,9 @@ struct ssb_chipcommon { struct ssb_chipcommon_pmu pmu; u32 ticks_per_ms; u32 max_timer_ms; diff --git a/target/linux/brcm47xx/patches-3.6/061-ssb-register-parallel-flash-device.patch b/target/linux/brcm47xx/patches-3.6/061-ssb-register-parallel-flash-device.patch index b2f85ae..3c90013 100644 --- a/target/linux/brcm47xx/patches-3.6/061-ssb-register-parallel-flash-device.patch +++ b/target/linux/brcm47xx/patches-3.6/061-ssb-register-parallel-flash-device.patch @@ -67,9 +67,9 @@ error: --- a/drivers/ssb/ssb_private.h +++ b/drivers/ssb/ssb_private.h -@@ -254,4 +254,6 @@ static inline int ssb_sflash_init(struct +@@ -271,4 +271,6 @@ static inline int ssb_gpio_init(struct s } - #endif /* CONFIG_SSB_SFLASH */ + #endif /* CONFIG_SSB_DRIVER_GPIO */ +extern struct platform_device ssb_pflash_dev; + diff --git a/target/linux/brcm47xx/patches-3.6/070-bcma-add-functions-to-write-to-serial-flash.patch b/target/linux/brcm47xx/patches-3.6/070-bcma-add-functions-to-write-to-serial-flash.patch index 5acc2cf..98cd795 100644 --- a/target/linux/brcm47xx/patches-3.6/070-bcma-add-functions-to-write-to-serial-flash.patch +++ b/target/linux/brcm47xx/patches-3.6/070-bcma-add-functions-to-write-to-serial-flash.patch @@ -307,16 +307,16 @@ e->name, sflash->size / 1024, sflash->blocksize, --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h -@@ -3,6 +3,8 @@ - +@@ -4,6 +4,8 @@ #include <linux/platform_device.h> + #include <linux/gpio.h> +#include <linux/mtd/bcm47xx_sflash.h> + /** ChipCommon core registers. **/ #define BCMA_CC_ID 0x0000 #define BCMA_CC_ID_ID 0x0000FFFF -@@ -518,17 +520,6 @@ struct bcma_pflash { +@@ -519,17 +521,6 @@ struct bcma_pflash { u32 window_size; }; @@ -334,7 +334,7 @@ #ifdef CONFIG_BCMA_NFLASH struct mtd_info; -@@ -563,7 +554,7 @@ struct bcma_drv_cc { +@@ -564,7 +555,7 @@ struct bcma_drv_cc { #ifdef CONFIG_BCMA_DRIVER_MIPS struct bcma_pflash pflash; #ifdef CONFIG_BCMA_SFLASH diff --git a/target/linux/brcm47xx/patches-3.6/071-bcma-add-functions-to-write-to-nand-flash.patch b/target/linux/brcm47xx/patches-3.6/071-bcma-add-functions-to-write-to-nand-flash.patch index f1b4f7f..7a21298 100644 --- a/target/linux/brcm47xx/patches-3.6/071-bcma-add-functions-to-write-to-nand-flash.patch +++ b/target/linux/brcm47xx/patches-3.6/071-bcma-add-functions-to-write-to-nand-flash.patch @@ -181,15 +181,15 @@ +} --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h -@@ -4,6 +4,7 @@ - #include <linux/platform_device.h> +@@ -5,6 +5,7 @@ + #include <linux/gpio.h> #include <linux/mtd/bcm47xx_sflash.h> +#include <linux/mtd/bcm47xx_nand.h> /** ChipCommon core registers. **/ #define BCMA_CC_ID 0x0000 -@@ -521,17 +522,6 @@ struct bcma_pflash { +@@ -522,17 +523,6 @@ struct bcma_pflash { }; @@ -207,7 +207,7 @@ struct bcma_serial_port { void *regs; unsigned long clockspeed; -@@ -557,7 +547,7 @@ struct bcma_drv_cc { +@@ -558,7 +548,7 @@ struct bcma_drv_cc { struct bcm47xx_sflash sflash; #endif #ifdef CONFIG_BCMA_NFLASH @@ -216,7 +216,7 @@ #endif int nr_serial_ports; -@@ -616,4 +606,13 @@ extern void bcma_chipco_regctl_maskset(s +@@ -625,4 +615,13 @@ extern void bcma_chipco_regctl_maskset(s u32 offset, u32 mask, u32 set); extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid); diff --git a/target/linux/brcm47xx/patches-3.6/072-bcma-register-parallel-flash-device.patch b/target/linux/brcm47xx/patches-3.6/072-bcma-register-parallel-flash-device.patch index cacb903..f21608b 100644 --- a/target/linux/brcm47xx/patches-3.6/072-bcma-register-parallel-flash-device.patch +++ b/target/linux/brcm47xx/patches-3.6/072-bcma-register-parallel-flash-device.patch @@ -1,6 +1,6 @@ --- a/drivers/bcma/bcma_private.h +++ b/drivers/bcma/bcma_private.h -@@ -45,6 +45,7 @@ int bcma_sprom_get(struct bcma_bus *bus) +@@ -47,6 +47,7 @@ int bcma_sprom_get(struct bcma_bus *bus) /* driver_chipcommon.c */ #ifdef CONFIG_BCMA_DRIVER_MIPS void bcma_chipco_serial_init(struct bcma_drv_cc *cc); @@ -18,7 +18,7 @@ /* The 47162a0 hangs when reading MIPS DMP registers registers */ static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev) -@@ -178,6 +179,19 @@ u32 bcma_cpu_clock(struct bcma_drv_mips +@@ -201,6 +202,19 @@ u32 bcma_cpu_clock(struct bcma_drv_mips } EXPORT_SYMBOL(bcma_cpu_clock); @@ -38,7 +38,7 @@ static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore) { struct bcma_bus *bus = mcore->core->bus; -@@ -200,6 +214,9 @@ static void bcma_core_mips_flash_detect( +@@ -223,6 +237,9 @@ static void bcma_core_mips_flash_detect( cc->pflash.buswidth = 1; else cc->pflash.buswidth = 2; diff --git a/target/linux/brcm47xx/patches-3.6/080-MIPS-BCM47XX-rewrite-nvram-probing.patch b/target/linux/brcm47xx/patches-3.6/080-MIPS-BCM47XX-rewrite-nvram-probing.patch index ecc9e04..1e75b10 100644 --- a/target/linux/brcm47xx/patches-3.6/080-MIPS-BCM47XX-rewrite-nvram-probing.patch +++ b/target/linux/brcm47xx/patches-3.6/080-MIPS-BCM47XX-rewrite-nvram-probing.patch @@ -9,7 +9,7 @@ * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the -@@ -18,83 +18,166 @@ +@@ -18,83 +18,168 @@ #include <linux/kernel.h> #include <linux/string.h> #include <asm/addrspace.h> @@ -122,14 +122,15 @@ + memset(dst, 0x0, NVRAM_SPACE - i); + + return 0; - } - --int nvram_getenv(char *name, char *val, size_t val_len) ++} ++ +#ifdef CONFIG_BCM47XX_SSB +static int nvram_init_ssb(void) +{ + struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore; ++#ifdef CONFIG_SSB_SFLASH + struct ssb_chipcommon *chipco = &bcm47xx_bus.ssb.chipco; ++#endif + u32 base; + u32 lim; + @@ -177,9 +178,10 @@ + } + + return nvram_find_and_copy(base, lim); -+} + } +#endif -+ + +-int nvram_getenv(char *name, char *val, size_t val_len) +static int nvram_init(void) +{ + switch (bcm47xx_bus_type) { @@ -214,7 +216,7 @@ /* Look for name=value and return value */ var = &nvram_buf[sizeof(struct nvram_header)]; -@@ -110,6 +193,6 @@ int nvram_getenv(char *name, char *val, +@@ -110,6 +195,6 @@ int nvram_getenv(char *name, char *val, return snprintf(val, val_len, "%s", value); } } diff --git a/target/linux/brcm47xx/patches-3.6/116-MIPS-BCM47xx-Remove-CFE-console.patch b/target/linux/brcm47xx/patches-3.6/116-MIPS-BCM47xx-Remove-CFE-console.patch index f068ac8..f7ace42 100644 --- a/target/linux/brcm47xx/patches-3.6/116-MIPS-BCM47xx-Remove-CFE-console.patch +++ b/target/linux/brcm47xx/patches-3.6/116-MIPS-BCM47xx-Remove-CFE-console.patch @@ -17,9 +17,9 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -109,7 +109,6 @@ config BCM47XX + select IRQ_CPU select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_GPIO - select SYS_HAS_EARLY_PRINTK select CFE help diff --git a/target/linux/brcm47xx/patches-3.6/119-fix-boot.patch b/target/linux/brcm47xx/patches-3.6/119-fix-boot.patch index 6abfd8d..db9883b 100644 --- a/target/linux/brcm47xx/patches-3.6/119-fix-boot.patch +++ b/target/linux/brcm47xx/patches-3.6/119-fix-boot.patch @@ -1,9 +1,9 @@ --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -101,11 +101,13 @@ config ATH79 - +@@ -102,11 +102,13 @@ config ATH79 config BCM47XX bool "Broadcom BCM47XX based boards" + select ARCH_WANT_OPTIONAL_GPIOLIB + select BOOT_RAW select CEVT_R4K select CSRC_R4K @@ -13,4 +13,4 @@ + select NO_EXCEPT_FILL select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_GPIO + select CFE diff --git a/target/linux/brcm47xx/patches-3.6/180-bcma-make-bcma_find_core_unit-accessible-by-other-pa.patch b/target/linux/brcm47xx/patches-3.6/180-bcma-make-bcma_find_core_unit-accessible-by-other-pa.patch deleted file mode 100644 index 147ac34..0000000 --- a/target/linux/brcm47xx/patches-3.6/180-bcma-make-bcma_find_core_unit-accessible-by-other-pa.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/bcma/bcma_private.h -+++ b/drivers/bcma/bcma_private.h -@@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc - int bcma_bus_suspend(struct bcma_bus *bus); - int bcma_bus_resume(struct bcma_bus *bus); - #endif -+struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, -+ u8 unit); - - /* scan.c */ - int bcma_bus_scan(struct bcma_bus *bus); ---- a/drivers/bcma/main.c -+++ b/drivers/bcma/main.c -@@ -81,8 +81,8 @@ struct bcma_device *bcma_find_core(struc - } - EXPORT_SYMBOL_GPL(bcma_find_core); - --static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, -- u8 unit) -+struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, -+ u8 unit) - { - struct bcma_device *core; - diff --git a/target/linux/brcm47xx/patches-3.6/181-bcma-explicit-assigne-irq-numbers.patch b/target/linux/brcm47xx/patches-3.6/181-bcma-explicit-assigne-irq-numbers.patch deleted file mode 100644 index 501f8d6..0000000 --- a/target/linux/brcm47xx/patches-3.6/181-bcma-explicit-assigne-irq-numbers.patch +++ /dev/null @@ -1,101 +0,0 @@ ---- a/drivers/bcma/driver_mips.c -+++ b/drivers/bcma/driver_mips.c -@@ -148,6 +148,22 @@ static void bcma_core_mips_set_irq(struc - dev->id.id, oldirq + 2, irq + 2); - } - -+static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq, -+ u16 coreid, u8 unit) -+{ -+ struct bcma_device *core; -+ -+ core = bcma_find_core_unit(bus, coreid, unit); -+ if (!core) { -+ bcma_warn(bus, -+ "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n", -+ coreid, unit); -+ return; -+ } -+ -+ bcma_core_mips_set_irq(core, irq); -+} -+ - static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq) - { - int i; -@@ -259,35 +275,47 @@ void bcma_core_mips_init(struct bcma_drv - - mcore->assigned_irqs = 1; - -- /* Assign IRQs to all cores on the bus */ -- list_for_each_entry(core, &bus->cores, list) { -- int mips_irq; -- if (core->irq) -- continue; -- -- mips_irq = bcma_core_mips_irq(core); -- if (mips_irq > 4) -- core->irq = 0; -- else -- core->irq = mips_irq + 2; -- if (core->irq > 5) -- continue; -- switch (core->id.id) { -- case BCMA_CORE_PCI: -- case BCMA_CORE_PCIE: -- case BCMA_CORE_ETHERNET: -- case BCMA_CORE_ETHERNET_GBIT: -- case BCMA_CORE_MAC_GBIT: -- case BCMA_CORE_80211: -- case BCMA_CORE_USB20_HOST: -- /* These devices get their own IRQ line if available, -- * the rest goes on IRQ0 -- */ -- if (mcore->assigned_irqs <= 4) -- bcma_core_mips_set_irq(core, -- mcore->assigned_irqs++); -- break; -+ switch (bus->chipinfo.id) { -+ case BCMA_CHIP_ID_BCM4716: -+ case BCMA_CHIP_ID_BCM4748: -+ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); -+ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); -+ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); -+ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0); -+ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); -+ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); -+ break; -+ case BCMA_CHIP_ID_BCM5356: -+ case BCMA_CHIP_ID_BCM47162: -+ case BCMA_CHIP_ID_BCM53572: -+ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); -+ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); -+ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); -+ break; -+ case BCMA_CHIP_ID_BCM5357: -+ case BCMA_CHIP_ID_BCM4749: -+ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); -+ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); -+ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); -+ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); -+ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); -+ break; -+ case BCMA_CHIP_ID_BCM4706: -+ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0); -+ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT, -+ 0); -+ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1); -+ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0); -+ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON, -+ 0); -+ break; -+ default: -+ list_for_each_entry(core, &bus->cores, list) { -+ core->irq = bcma_core_irq(core); - } -+ bcma_err(bus, -+ "Unknown device (0x%x) found, can not configure IRQs\n", -+ bus->chipinfo.id); - } - bcma_info(bus, "IRQ reconfiguration done\n"); - bcma_core_mips_dump_irq(bus); diff --git a/target/linux/brcm47xx/patches-3.6/182-bcma-make-some-info-messages-debug.patch b/target/linux/brcm47xx/patches-3.6/182-bcma-make-some-info-messages-debug.patch deleted file mode 100644 index 4250216..0000000 --- a/target/linux/brcm47xx/patches-3.6/182-bcma-make-some-info-messages-debug.patch +++ /dev/null @@ -1,40 +0,0 @@ ---- a/drivers/bcma/driver_mips.c -+++ b/drivers/bcma/driver_mips.c -@@ -144,8 +144,8 @@ static void bcma_core_mips_set_irq(struc - 1 << irqflag); - } - -- bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n", -- dev->id.id, oldirq + 2, irq + 2); -+ bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n", -+ dev->id.id, oldirq + 2, irq + 2); - } - - static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq, -@@ -168,7 +168,7 @@ static void bcma_core_mips_print_irq(str - { - int i; - static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; -- printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); -+ printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); - for (i = 0; i <= 6; i++) - printk(" %s%s", irq_name[i], i == irq ? "*" : " "); - printk("\n"); -@@ -269,7 +269,7 @@ void bcma_core_mips_init(struct bcma_drv - if (mcore->setup_done) - return; - -- bcma_info(bus, "Initializing MIPS core...\n"); -+ bcma_debug(bus, "Initializing MIPS core...\n"); - - bcma_core_mips_early_init(mcore); - -@@ -317,7 +317,7 @@ void bcma_core_mips_init(struct bcma_drv - "Unknown device (0x%x) found, can not configure IRQs\n", - bus->chipinfo.id); - } -- bcma_info(bus, "IRQ reconfiguration done\n"); -+ bcma_debug(bus, "IRQ reconfiguration done\n"); - bcma_core_mips_dump_irq(bus); - - mcore->setup_done = true; diff --git a/target/linux/brcm47xx/patches-3.6/183-bcma-mips-show-also-disabled-irqs.patch b/target/linux/brcm47xx/patches-3.6/183-bcma-mips-show-also-disabled-irqs.patch deleted file mode 100644 index d44b306..0000000 --- a/target/linux/brcm47xx/patches-3.6/183-bcma-mips-show-also-disabled-irqs.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/drivers/bcma/driver_mips.c -+++ b/drivers/bcma/driver_mips.c -@@ -75,11 +75,16 @@ static u32 bcma_core_mips_irqflag(struct - return dev->core_index; - flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30); - -- return flag & 0x1F; -+ if (flag) -+ return flag & 0x1F; -+ else -+ return 0x3f; - } - - /* Get the MIPS IRQ assignment for a specified device. - * If unassigned, 0 is returned. -+ * If disabled, 5 is returned. -+ * If not supported, 6 is returned. - */ - unsigned int bcma_core_mips_irq(struct bcma_device *dev) - { -@@ -88,13 +93,15 @@ unsigned int bcma_core_mips_irq(struct b - unsigned int irq; - - irqflag = bcma_core_mips_irqflag(dev); -+ if (irqflag == 0x3f) -+ return 6; - -- for (irq = 1; irq <= 4; irq++) -+ for (irq = 0; irq <= 4; irq++) - if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) & - (1 << irqflag)) - return irq; - -- return 0; -+ return 5; - } - EXPORT_SYMBOL(bcma_core_mips_irq); - -@@ -115,7 +122,7 @@ static void bcma_core_mips_set_irq(struc - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0), - bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) & - ~(1 << irqflag)); -- else -+ else if (oldirq != 5) - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0); - - /* assign the new one */ -@@ -145,7 +152,7 @@ static void bcma_core_mips_set_irq(struc - } - - bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n", -- dev->id.id, oldirq + 2, irq + 2); -+ dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2); - } - - static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq, diff --git a/target/linux/brcm47xx/patches-3.6/184-bcma-mips-remove-assigned_irqs.patch b/target/linux/brcm47xx/patches-3.6/184-bcma-mips-remove-assigned_irqs.patch deleted file mode 100644 index c402e11..0000000 --- a/target/linux/brcm47xx/patches-3.6/184-bcma-mips-remove-assigned_irqs.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/bcma/driver_mips.c -+++ b/drivers/bcma/driver_mips.c -@@ -280,8 +280,6 @@ void bcma_core_mips_init(struct bcma_drv - - bcma_core_mips_early_init(mcore); - -- mcore->assigned_irqs = 1; -- - switch (bus->chipinfo.id) { - case BCMA_CHIP_ID_BCM4716: - case BCMA_CHIP_ID_BCM4748: ---- a/include/linux/bcma/bcma_driver_mips.h -+++ b/include/linux/bcma/bcma_driver_mips.h -@@ -36,7 +36,6 @@ struct bcma_drv_mips { - struct bcma_device *core; - u8 setup_done:1; - u8 early_setup_done:1; -- unsigned int assigned_irqs; - }; - - #ifdef CONFIG_BCMA_DRIVER_MIPS diff --git a/target/linux/brcm47xx/patches-3.6/185-bcma-rename-oldirqflag-to-irqinitmask-to-better-matc.patch b/target/linux/brcm47xx/patches-3.6/185-bcma-rename-oldirqflag-to-irqinitmask-to-better-matc.patch deleted file mode 100644 index 5fb952f..0000000 --- a/target/linux/brcm47xx/patches-3.6/185-bcma-rename-oldirqflag-to-irqinitmask-to-better-matc.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/bcma/driver_mips.c -+++ b/drivers/bcma/driver_mips.c -@@ -131,9 +131,9 @@ static void bcma_core_mips_set_irq(struc - bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) | - (1 << irqflag)); - } else { -- u32 oldirqflag = bcma_read32(mdev, -- BCMA_MIPS_MIPS74K_INTMASK(irq)); -- if (oldirqflag) { -+ u32 irqinitmask = bcma_read32(mdev, -+ BCMA_MIPS_MIPS74K_INTMASK(irq)); -+ if (irqinitmask) { - struct bcma_device *core; - - /* backplane irq line is in use, find out who uses -@@ -141,7 +141,7 @@ static void bcma_core_mips_set_irq(struc - */ - list_for_each_entry(core, &bus->cores, list) { - if ((1 << bcma_core_mips_irqflag(core)) == -- oldirqflag) { -+ irqinitmask) { - bcma_core_mips_set_irq(core, 0); - break; - } diff --git a/target/linux/brcm47xx/patches-3.6/220-bcma-fix-detection-of-serial-flash-chips.patch b/target/linux/brcm47xx/patches-3.6/220-bcma-fix-detection-of-serial-flash-chips.patch deleted file mode 100644 index 1567712..0000000 --- a/target/linux/brcm47xx/patches-3.6/220-bcma-fix-detection-of-serial-flash-chips.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/drivers/bcma/driver_chipcommon_sflash.c -+++ b/drivers/bcma/driver_chipcommon_sflash.c -@@ -42,7 +42,7 @@ static const struct bcma_sflash_tbl_e bc - { "M25P40", 0x12, 0x10000, 8, }, - - { "M25P16", 0x14, 0x10000, 32, }, -- { "M25P32", 0x14, 0x10000, 64, }, -+ { "M25P32", 0x15, 0x10000, 64, }, - { "M25P64", 0x16, 0x10000, 128, }, - { "M25FL128", 0x17, 0x10000, 256, }, - { 0 }, diff --git a/target/linux/brcm47xx/patches-3.6/235-bcma-dont-expose-mips-irq.patch b/target/linux/brcm47xx/patches-3.6/235-bcma-dont-expose-mips-irq.patch index 5df8636..b7cf0bc 100644 --- a/target/linux/brcm47xx/patches-3.6/235-bcma-dont-expose-mips-irq.patch +++ b/target/linux/brcm47xx/patches-3.6/235-bcma-dont-expose-mips-irq.patch @@ -10,7 +10,7 @@ #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */ --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c -@@ -258,7 +258,7 @@ void bcma_chipco_serial_init(struct bcma +@@ -329,7 +329,7 @@ void bcma_chipco_serial_init(struct bcma return; } @@ -64,17 +64,6 @@ + return bcma_core_irq(pc_host->pdev->core); } EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq); ---- a/arch/mips/bcm47xx/gpio.c -+++ b/arch/mips/bcm47xx/gpio.c -@@ -94,7 +94,7 @@ int gpio_to_irq(unsigned gpio) - #endif - #ifdef CONFIG_BCM47XX_BCMA - case BCM47XX_BUS_TYPE_BCMA: -- return bcma_core_mips_irq(bcm47xx_bus.bcma.bus.drv_cc.core) + 2; -+ return bcma_core_irq(bcm47xx_bus.bcma.bus.drv_cc.core); - #endif - } - return -EINVAL; --- a/arch/mips/bcm47xx/serial.c +++ b/arch/mips/bcm47xx/serial.c @@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi diff --git a/target/linux/brcm47xx/patches-3.6/280-activate_ssb_support_in_usb.patch b/target/linux/brcm47xx/patches-3.6/280-activate_ssb_support_in_usb.patch index 8b858e1..c4382ed 100644 --- a/target/linux/brcm47xx/patches-3.6/280-activate_ssb_support_in_usb.patch +++ b/target/linux/brcm47xx/patches-3.6/280-activate_ssb_support_in_usb.patch @@ -15,8 +15,8 @@ This prevents the options from being delete with make kernel_oldconfig. bool "BCMA Broadcom MIPS core driver" --- a/drivers/ssb/Kconfig +++ b/drivers/ssb/Kconfig -@@ -146,6 +146,7 @@ config SSB_EMBEDDED - config SSB_SFLASH +@@ -146,6 +146,7 @@ config SSB_SFLASH + config SSB_EMBEDDED bool depends on SSB_DRIVER_MIPS + select USB_HCD_SSB if USB_EHCI_HCD || USB_OHCI_HCD diff --git a/target/linux/brcm47xx/patches-3.6/400-arch-bcm47xx.patch b/target/linux/brcm47xx/patches-3.6/400-arch-bcm47xx.patch index 1ed0b8a..c8c3158 100644 --- a/target/linux/brcm47xx/patches-3.6/400-arch-bcm47xx.patch +++ b/target/linux/brcm47xx/patches-3.6/400-arch-bcm47xx.patch @@ -1,6 +1,6 @@ --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c -@@ -196,3 +196,30 @@ int bcm47xx_nvram_getenv(char *name, cha +@@ -198,3 +198,30 @@ int bcm47xx_nvram_getenv(char *name, cha return -ENOENT; } EXPORT_SYMBOL(bcm47xx_nvram_getenv); @@ -31,3 +31,147 @@ + return NULL; +} +EXPORT_SYMBOL(nvram_get); +--- a/arch/mips/bcm47xx/Makefile ++++ b/arch/mips/bcm47xx/Makefile +@@ -4,4 +4,5 @@ + # + + obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o ++obj-y += gpio.o + obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o +--- /dev/null ++++ b/arch/mips/bcm47xx/gpio.c +@@ -0,0 +1,119 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net> ++ * Copyright (C) 2012 Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * Parts of this file are based on Atheros AR71XX/AR724X/AR913X GPIO ++ */ ++ ++#include <linux/export.h> ++#include <linux/gpio.h> ++#include <linux/ssb/ssb_embedded.h> ++#include <linux/bcma/bcma.h> ++ ++#include <bcm47xx.h> ++ ++/* low level BCM47xx gpio api */ ++u32 bcm47xx_gpio_in(u32 mask) ++{ ++ switch (bcm47xx_bus_type) { ++#ifdef CONFIG_BCM47XX_SSB ++ case BCM47XX_BUS_TYPE_SSB: ++ return ssb_gpio_in(&bcm47xx_bus.ssb, mask); ++#endif ++#ifdef CONFIG_BCM47XX_BCMA ++ case BCM47XX_BUS_TYPE_BCMA: ++ return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, mask); ++#endif ++ } ++ return -EINVAL; ++} ++EXPORT_SYMBOL(bcm47xx_gpio_in); ++ ++u32 bcm47xx_gpio_out(u32 mask, u32 value) ++{ ++ switch (bcm47xx_bus_type) { ++#ifdef CONFIG_BCM47XX_SSB ++ case BCM47XX_BUS_TYPE_SSB: ++ return ssb_gpio_out(&bcm47xx_bus.ssb, mask, value); ++#endif ++#ifdef CONFIG_BCM47XX_BCMA ++ case BCM47XX_BUS_TYPE_BCMA: ++ return bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, mask, ++ value); ++#endif ++ } ++ return -EINVAL; ++} ++EXPORT_SYMBOL(bcm47xx_gpio_out); ++ ++u32 bcm47xx_gpio_outen(u32 mask, u32 value) ++{ ++ switch (bcm47xx_bus_type) { ++#ifdef CONFIG_BCM47XX_SSB ++ case BCM47XX_BUS_TYPE_SSB: ++ return ssb_gpio_outen(&bcm47xx_bus.ssb, mask, value); ++#endif ++#ifdef CONFIG_BCM47XX_BCMA ++ case BCM47XX_BUS_TYPE_BCMA: ++ return bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, ++ mask, value); ++#endif ++ } ++ return -EINVAL; ++} ++EXPORT_SYMBOL(bcm47xx_gpio_outen); ++ ++u32 bcm47xx_gpio_control(u32 mask, u32 value) ++{ ++ switch (bcm47xx_bus_type) { ++#ifdef CONFIG_BCM47XX_SSB ++ case BCM47XX_BUS_TYPE_SSB: ++ return ssb_gpio_control(&bcm47xx_bus.ssb, mask, value); ++#endif ++#ifdef CONFIG_BCM47XX_BCMA ++ case BCM47XX_BUS_TYPE_BCMA: ++ return bcma_chipco_gpio_control(&bcm47xx_bus.bcma.bus.drv_cc, ++ mask, value); ++#endif ++ } ++ return -EINVAL; ++} ++EXPORT_SYMBOL(bcm47xx_gpio_control); ++ ++u32 bcm47xx_gpio_intmask(u32 mask, u32 value) ++{ ++ switch (bcm47xx_bus_type) { ++#ifdef CONFIG_BCM47XX_SSB ++ case BCM47XX_BUS_TYPE_SSB: ++ return ssb_gpio_intmask(&bcm47xx_bus.ssb, mask, value); ++#endif ++#ifdef CONFIG_BCM47XX_BCMA ++ case BCM47XX_BUS_TYPE_BCMA: ++ return bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc, ++ mask, value); ++#endif ++ } ++ return -EINVAL; ++} ++EXPORT_SYMBOL(bcm47xx_gpio_intmask); ++ ++u32 bcm47xx_gpio_polarity(u32 mask, u32 value) ++{ ++ switch (bcm47xx_bus_type) { ++#ifdef CONFIG_BCM47XX_SSB ++ case BCM47XX_BUS_TYPE_SSB: ++ return ssb_gpio_polarity(&bcm47xx_bus.ssb, mask, value); ++#endif ++#ifdef CONFIG_BCM47XX_BCMA ++ case BCM47XX_BUS_TYPE_BCMA: ++ return bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc, ++ mask, value); ++#endif ++ } ++ return -EINVAL; ++} ++EXPORT_SYMBOL(bcm47xx_gpio_polarity); +--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h ++++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h +@@ -14,4 +14,11 @@ static inline int irq_to_gpio(unsigned i + return -EINVAL; + } + ++u32 bcm47xx_gpio_in(u32 mask); ++u32 bcm47xx_gpio_out(u32 mask, u32 value); ++u32 bcm47xx_gpio_outen(u32 mask, u32 value); ++u32 bcm47xx_gpio_control(u32 mask, u32 value); ++u32 bcm47xx_gpio_intmask(u32 mask, u32 value); ++u32 bcm47xx_gpio_polarity(u32 mask, u32 value); ++ + #endif diff --git a/target/linux/brcm47xx/patches-3.6/500-ssb-add-function-to-return-number-of-gpio-lines.patch b/target/linux/brcm47xx/patches-3.6/500-ssb-add-function-to-return-number-of-gpio-lines.patch deleted file mode 100644 index 8c4634c..0000000 --- a/target/linux/brcm47xx/patches-3.6/500-ssb-add-function-to-return-number-of-gpio-lines.patch +++ /dev/null @@ -1,40 +0,0 @@ ---- a/drivers/ssb/embedded.c -+++ b/drivers/ssb/embedded.c -@@ -171,6 +171,18 @@ u32 ssb_gpio_polarity(struct ssb_bus *bu - } - EXPORT_SYMBOL(ssb_gpio_polarity); - -+int ssb_gpio_count(struct ssb_bus *bus) -+{ -+ if (ssb_chipco_available(&bus->chipco)) -+ return SSB_GPIO_CHIPCO_LINES; -+ else if (ssb_extif_available(&bus->extif)) -+ return SSB_GPIO_EXTIF_LINES; -+ else -+ SSB_WARN_ON(1); -+ return 0; -+} -+EXPORT_SYMBOL(ssb_gpio_count); -+ - #ifdef CONFIG_SSB_DRIVER_GIGE - static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data) - { ---- a/include/linux/ssb/ssb_embedded.h -+++ b/include/linux/ssb/ssb_embedded.h -@@ -7,6 +7,9 @@ - - extern int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks); - -+#define SSB_GPIO_EXTIF_LINES 5 -+#define SSB_GPIO_CHIPCO_LINES 16 -+ - /* Generic GPIO API */ - u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask); - u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value); -@@ -14,5 +17,6 @@ u32 ssb_gpio_outen(struct ssb_bus *bus, - u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value); - u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value); - u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value); -+int ssb_gpio_count(struct ssb_bus *bus); - - #endif /* LINUX_SSB_EMBEDDED_H_ */ diff --git a/target/linux/brcm47xx/patches-3.6/501-bcma-add-gpio-driver.patch b/target/linux/brcm47xx/patches-3.6/501-bcma-add-gpio-driver.patch deleted file mode 100644 index d00a164..0000000 --- a/target/linux/brcm47xx/patches-3.6/501-bcma-add-gpio-driver.patch +++ /dev/null @@ -1,140 +0,0 @@ ---- a/drivers/bcma/driver_chipcommon.c -+++ b/drivers/bcma/driver_chipcommon.c -@@ -158,6 +158,8 @@ void bcma_core_chipcommon_init(struct bc - } - cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc); - -+ spin_lock_init(&cc->gpio_lock); -+ - cc->setup_done = true; - } - -@@ -197,34 +199,81 @@ u32 bcma_chipco_irq_status(struct bcma_d - - u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask) - { -- return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; -+ unsigned long flags; -+ u32 res; -+ -+ spin_lock_irqsave(&cc->gpio_lock, flags); -+ res = bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; -+ spin_unlock_irqrestore(&cc->gpio_lock, flags); -+ -+ return res; - } -+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_in); - - u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) - { -- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); -+ unsigned long flags; -+ u32 res; -+ -+ spin_lock_irqsave(&cc->gpio_lock, flags); -+ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); -+ spin_unlock_irqrestore(&cc->gpio_lock, flags); -+ -+ return res; - } -+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); - - u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) - { -- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); -+ unsigned long flags; -+ u32 res; -+ -+ spin_lock_irqsave(&cc->gpio_lock, flags); -+ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); -+ spin_unlock_irqrestore(&cc->gpio_lock, flags); -+ -+ return res; - } -+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); - - u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) - { -- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); -+ unsigned long flags; -+ u32 res; -+ -+ spin_lock_irqsave(&cc->gpio_lock, flags); -+ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); -+ spin_unlock_irqrestore(&cc->gpio_lock, flags); -+ -+ return res; - } - EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); - - u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) - { -- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); -+ unsigned long flags; -+ u32 res; -+ -+ spin_lock_irqsave(&cc->gpio_lock, flags); -+ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); -+ spin_unlock_irqrestore(&cc->gpio_lock, flags); -+ -+ return res; - } -+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_intmask); - - u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) - { -- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); -+ unsigned long flags; -+ u32 res; -+ -+ spin_lock_irqsave(&cc->gpio_lock, flags); -+ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); -+ spin_unlock_irqrestore(&cc->gpio_lock, flags); -+ -+ return res; - } -+EXPORT_SYMBOL_GPL(bcma_chipco_gpio_polarity); - - #ifdef CONFIG_BCMA_DRIVER_MIPS - void bcma_chipco_serial_init(struct bcma_drv_cc *cc) ---- a/include/linux/bcma/bcma_driver_chipcommon.h -+++ b/include/linux/bcma/bcma_driver_chipcommon.h -@@ -555,6 +555,9 @@ struct bcma_drv_cc { - #endif /* CONFIG_BCMA_DRIVER_MIPS */ - u32 ticks_per_ms; - struct platform_device *watchdog; -+ -+ /* Lock for GPIO register access. */ -+ spinlock_t gpio_lock; - }; - - /* Register access */ -@@ -584,13 +587,22 @@ void bcma_chipco_irq_mask(struct bcma_dr - - u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); - -+#define BCMA_CC_GPIO_LINES 16 -+ - /* Chipcommon GPIO pin access. */ --u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask); --u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value); --u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value); --u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); --u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); --u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); -+extern u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask); -+extern u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value); -+extern u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value); -+extern u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, -+ u32 value); -+extern u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, -+ u32 value); -+extern u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, -+ u32 value); -+static inline int bcma_chipco_gpio_count(void) -+{ -+ return BCMA_CC_GPIO_LINES; -+} - - /* PMU support */ - extern void bcma_pmu_init(struct bcma_drv_cc *cc); diff --git a/target/linux/brcm47xx/patches-3.6/502-bcm47xx-rewrite-gpio-handling.patch b/target/linux/brcm47xx/patches-3.6/502-bcm47xx-rewrite-gpio-handling.patch deleted file mode 100644 index cff3184..0000000 --- a/target/linux/brcm47xx/patches-3.6/502-bcm47xx-rewrite-gpio-handling.patch +++ /dev/null @@ -1,493 +0,0 @@ ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -101,6 +101,7 @@ config ATH79 - - config BCM47XX - bool "Broadcom BCM47XX based boards" -+ select ARCH_REQUIRE_GPIOLIB - select BOOT_RAW - select CEVT_R4K - select CSRC_R4K -@@ -110,7 +111,6 @@ config BCM47XX - select NO_EXCEPT_FILL - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN -- select GENERIC_GPIO - select CFE - help - Support for BCM47XX based boards ---- a/arch/mips/bcm47xx/gpio.c -+++ b/arch/mips/bcm47xx/gpio.c -@@ -4,83 +4,154 @@ - * for more details. - * - * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net> -+ * Copyright (C) 2012 Hauke Mehrtens <hauke@hauke-m.de> -+ * -+ * Parts of this file are based on Atheros AR71XX/AR724X/AR913X GPIO - */ - - #include <linux/export.h> -+#include <linux/gpio.h> - #include <linux/ssb/ssb.h> --#include <linux/ssb/ssb_driver_chipcommon.h> --#include <linux/ssb/ssb_driver_extif.h> --#include <asm/mach-bcm47xx/bcm47xx.h> --#include <asm/mach-bcm47xx/gpio.h> -+#include <linux/ssb/ssb_embedded.h> -+#include <linux/bcma/bcma.h> -+ -+#include <bcm47xx.h> - --#if (BCM47XX_CHIPCO_GPIO_LINES > BCM47XX_EXTIF_GPIO_LINES) --static DECLARE_BITMAP(gpio_in_use, BCM47XX_CHIPCO_GPIO_LINES); --#else --static DECLARE_BITMAP(gpio_in_use, BCM47XX_EXTIF_GPIO_LINES); --#endif - --int gpio_request(unsigned gpio, const char *tag) -+static unsigned long bcm47xx_gpio_count; -+ -+/* low level BCM47xx gpio api */ -+u32 bcm47xx_gpio_in(u32 mask) - { - switch (bcm47xx_bus_type) { - #ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: -- if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && -- ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) -- return -EINVAL; -- -- if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && -- ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) -- return -EINVAL; -- -- if (test_and_set_bit(gpio, gpio_in_use)) -- return -EBUSY; -- -- return 0; -+ return ssb_gpio_in(&bcm47xx_bus.ssb, mask); - #endif - #ifdef CONFIG_BCM47XX_BCMA - case BCM47XX_BUS_TYPE_BCMA: -- if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) -- return -EINVAL; -- -- if (test_and_set_bit(gpio, gpio_in_use)) -- return -EBUSY; -+ return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, mask); -+#endif -+ } -+ return -EINVAL; -+} -+EXPORT_SYMBOL(bcm47xx_gpio_in); - -- return 0; -+u32 bcm47xx_gpio_out(u32 mask, u32 value) -+{ -+ switch (bcm47xx_bus_type) { -+#ifdef CONFIG_BCM47XX_SSB -+ case BCM47XX_BUS_TYPE_SSB: -+ return ssb_gpio_out(&bcm47xx_bus.ssb, mask, value); -+#endif -+#ifdef CONFIG_BCM47XX_BCMA -+ case BCM47XX_BUS_TYPE_BCMA: -+ return bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, mask, -+ value); - #endif - } - return -EINVAL; - } --EXPORT_SYMBOL(gpio_request); -+EXPORT_SYMBOL(bcm47xx_gpio_out); - --void gpio_free(unsigned gpio) -+u32 bcm47xx_gpio_outen(u32 mask, u32 value) - { - switch (bcm47xx_bus_type) { - #ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: -- if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && -- ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) -- return; -+ return ssb_gpio_outen(&bcm47xx_bus.ssb, mask, value); -+#endif -+#ifdef CONFIG_BCM47XX_BCMA -+ case BCM47XX_BUS_TYPE_BCMA: -+ return bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, -+ mask, value); -+#endif -+ } -+ return -EINVAL; -+} -+EXPORT_SYMBOL(bcm47xx_gpio_outen); - -- if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && -- ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) -- return; -+u32 bcm47xx_gpio_control(u32 mask, u32 value) -+{ -+ switch (bcm47xx_bus_type) { -+#ifdef CONFIG_BCM47XX_SSB -+ case BCM47XX_BUS_TYPE_SSB: -+ return ssb_gpio_control(&bcm47xx_bus.ssb, mask, value); -+#endif -+#ifdef CONFIG_BCM47XX_BCMA -+ case BCM47XX_BUS_TYPE_BCMA: -+ return bcma_chipco_gpio_control(&bcm47xx_bus.bcma.bus.drv_cc, -+ mask, value); -+#endif -+ } -+ return -EINVAL; -+} -+EXPORT_SYMBOL(bcm47xx_gpio_control); - -- clear_bit(gpio, gpio_in_use); -- return; -+u32 bcm47xx_gpio_intmask(u32 mask, u32 value) -+{ -+ switch (bcm47xx_bus_type) { -+#ifdef CONFIG_BCM47XX_SSB -+ case BCM47XX_BUS_TYPE_SSB: -+ return ssb_gpio_intmask(&bcm47xx_bus.ssb, mask, value); - #endif - #ifdef CONFIG_BCM47XX_BCMA - case BCM47XX_BUS_TYPE_BCMA: -- if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) -- return; -+ return bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc, -+ mask, value); -+#endif -+ } -+ return -EINVAL; -+} -+EXPORT_SYMBOL(bcm47xx_gpio_intmask); - -- clear_bit(gpio, gpio_in_use); -- return; -+u32 bcm47xx_gpio_polarity(u32 mask, u32 value) -+{ -+ switch (bcm47xx_bus_type) { -+#ifdef CONFIG_BCM47XX_SSB -+ case BCM47XX_BUS_TYPE_SSB: -+ return ssb_gpio_polarity(&bcm47xx_bus.ssb, mask, value); -+#endif -+#ifdef CONFIG_BCM47XX_BCMA -+ case BCM47XX_BUS_TYPE_BCMA: -+ return bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc, -+ mask, value); - #endif - } -+ return -EINVAL; -+} -+EXPORT_SYMBOL(bcm47xx_gpio_polarity); -+ -+ -+static int bcm47xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio) -+{ -+ return bcm47xx_gpio_in(1 << gpio); -+} -+ -+static void bcm47xx_gpio_set_value(struct gpio_chip *chip, -+ unsigned gpio, int value) -+{ -+ bcm47xx_gpio_out(1 << gpio, value ? 1 << gpio : 0); -+} -+ -+static int bcm47xx_gpio_direction_input(struct gpio_chip *chip, -+ unsigned gpio) -+{ -+ bcm47xx_gpio_outen(1 << gpio, 0); -+ return 0; -+} -+ -+static int bcm47xx_gpio_direction_output(struct gpio_chip *chip, -+ unsigned gpio, int value) -+{ -+ /* first set the gpio out value */ -+ bcm47xx_gpio_out(1 << gpio, value ? 1 << gpio : 0); -+ /* then set the gpio mode */ -+ bcm47xx_gpio_outen(1 << gpio, 1 << gpio); -+ return 0; - } --EXPORT_SYMBOL(gpio_free); - --int gpio_to_irq(unsigned gpio) -+static int bcm47xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) - { - switch (bcm47xx_bus_type) { - #ifdef CONFIG_BCM47XX_SSB -@@ -99,4 +170,55 @@ int gpio_to_irq(unsigned gpio) - } - return -EINVAL; - } --EXPORT_SYMBOL_GPL(gpio_to_irq); -+ -+static struct gpio_chip bcm47xx_gpio_chip = { -+ .label = "bcm47xx", -+ .get = bcm47xx_gpio_get_value, -+ .set = bcm47xx_gpio_set_value, -+ .direction_input = bcm47xx_gpio_direction_input, -+ .direction_output = bcm47xx_gpio_direction_output, -+ .to_irq = bcm47xx_gpio_to_irq, -+ .base = 0, -+}; -+ -+void __init bcm47xx_gpio_init(void) -+{ -+ int err; -+ -+ switch (bcm47xx_bus_type) { -+#ifdef CONFIG_BCM47XX_SSB -+ case BCM47XX_BUS_TYPE_SSB: -+ bcm47xx_gpio_count = ssb_gpio_count(&bcm47xx_bus.ssb); -+ break; -+#endif -+#ifdef CONFIG_BCM47XX_BCMA -+ case BCM47XX_BUS_TYPE_BCMA: -+ bcm47xx_gpio_count = bcma_chipco_gpio_count(); -+ break; -+#endif -+ } -+ -+ bcm47xx_gpio_chip.ngpio = bcm47xx_gpio_count; -+ -+ err = gpiochip_add(&bcm47xx_gpio_chip); -+ if (err) -+ panic("cannot add BCM47xx GPIO chip, error=%d", err); -+} -+ -+int gpio_get_value(unsigned gpio) -+{ -+ if (gpio < bcm47xx_gpio_count) -+ return bcm47xx_gpio_in(1 << gpio); -+ -+ return __gpio_get_value(gpio); -+} -+EXPORT_SYMBOL(gpio_get_value); -+ -+void gpio_set_value(unsigned gpio, int value) -+{ -+ if (gpio < bcm47xx_gpio_count) -+ bcm47xx_gpio_out(1 << gpio, value ? 1 << gpio : 0); -+ else -+ __gpio_set_value(gpio, value); -+} -+EXPORT_SYMBOL(gpio_set_value); ---- a/arch/mips/bcm47xx/setup.c -+++ b/arch/mips/bcm47xx/setup.c -@@ -252,6 +252,8 @@ void __init plat_mem_setup(void) - _machine_restart = bcm47xx_machine_restart; - _machine_halt = bcm47xx_machine_halt; - pm_power_off = bcm47xx_machine_halt; -+ -+ bcm47xx_gpio_init(); - } - - static int __init bcm47xx_register_bus_complete(void) ---- a/arch/mips/bcm47xx/wgt634u.c -+++ b/arch/mips/bcm47xx/wgt634u.c -@@ -133,6 +133,7 @@ static int __init wgt634u_init(void) - * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx. - */ - u8 *et0mac; -+ int err; - - if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB) - return -ENODEV; -@@ -146,6 +147,12 @@ static int __init wgt634u_init(void) - - printk(KERN_INFO "WGT634U machine detected.\n"); - -+ err = gpio_request(WGT634U_GPIO_RESET, "reset-buton"); -+ if (err) { -+ printk(KERN_INFO "Can not register gpio for reset button\n"); -+ return 0; -+ } -+ - if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET), - gpio_interrupt, IRQF_SHARED, - "WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) { ---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h -+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h -@@ -56,4 +56,6 @@ void bcm47xx_fill_bcma_boardinfo(struct - const char *prefix); - #endif - -+void bcm47xx_gpio_init(void); -+ - #endif /* __ASM_BCM47XX_H */ ---- a/arch/mips/include/asm/mach-bcm47xx/gpio.h -+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h -@@ -4,152 +4,42 @@ - * for more details. - * - * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net> -+ * Copyright (C) 2012 Hauke Mehrtens <hauke@hauke-m.de> - */ - - #ifndef __BCM47XX_GPIO_H - #define __BCM47XX_GPIO_H - --#include <linux/ssb/ssb_embedded.h> --#include <linux/bcma/bcma.h> --#include <asm/mach-bcm47xx/bcm47xx.h> -- --#define BCM47XX_EXTIF_GPIO_LINES 5 --#define BCM47XX_CHIPCO_GPIO_LINES 16 -- --extern int gpio_request(unsigned gpio, const char *label); --extern void gpio_free(unsigned gpio); --extern int gpio_to_irq(unsigned gpio); -- --static inline int gpio_get_value(unsigned gpio) --{ -- switch (bcm47xx_bus_type) { --#ifdef CONFIG_BCM47XX_SSB -- case BCM47XX_BUS_TYPE_SSB: -- return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio); --#endif --#ifdef CONFIG_BCM47XX_BCMA -- case BCM47XX_BUS_TYPE_BCMA: -- return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, -- 1 << gpio); --#endif -- } -- return -EINVAL; --} -- --#define gpio_get_value_cansleep gpio_get_value -- --static inline void gpio_set_value(unsigned gpio, int value) --{ -- switch (bcm47xx_bus_type) { --#ifdef CONFIG_BCM47XX_SSB -- case BCM47XX_BUS_TYPE_SSB: -- ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio, -- value ? 1 << gpio : 0); -- return; --#endif --#ifdef CONFIG_BCM47XX_BCMA -- case BCM47XX_BUS_TYPE_BCMA: -- bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, -- value ? 1 << gpio : 0); -- return; --#endif -- } --} -- --#define gpio_set_value_cansleep gpio_set_value -- --static inline int gpio_cansleep(unsigned gpio) --{ -- return 0; --} -- --static inline int gpio_is_valid(unsigned gpio) --{ -- return gpio < (BCM47XX_EXTIF_GPIO_LINES + BCM47XX_CHIPCO_GPIO_LINES); --} -+#define ARCH_NR_GPIOS 64 -+#include <asm-generic/gpio.h> - -+/* low level BCM47xx gpio api */ -+u32 bcm47xx_gpio_in(u32 mask); -+u32 bcm47xx_gpio_out(u32 mask, u32 value); -+u32 bcm47xx_gpio_outen(u32 mask, u32 value); -+u32 bcm47xx_gpio_control(u32 mask, u32 value); -+u32 bcm47xx_gpio_intmask(u32 mask, u32 value); -+u32 bcm47xx_gpio_polarity(u32 mask, u32 value); - --static inline int gpio_direction_input(unsigned gpio) --{ -- switch (bcm47xx_bus_type) { --#ifdef CONFIG_BCM47XX_SSB -- case BCM47XX_BUS_TYPE_SSB: -- ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0); -- return 0; --#endif --#ifdef CONFIG_BCM47XX_BCMA -- case BCM47XX_BUS_TYPE_BCMA: -- bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, -- 0); -- return 0; --#endif -- } -- return -EINVAL; --} -+int gpio_get_value(unsigned gpio); -+void gpio_set_value(unsigned gpio, int value); - --static inline int gpio_direction_output(unsigned gpio, int value) -+static inline void gpio_intmask(unsigned gpio, int value) - { -- switch (bcm47xx_bus_type) { --#ifdef CONFIG_BCM47XX_SSB -- case BCM47XX_BUS_TYPE_SSB: -- /* first set the gpio out value */ -- ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio, -- value ? 1 << gpio : 0); -- /* then set the gpio mode */ -- ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio); -- return 0; --#endif --#ifdef CONFIG_BCM47XX_BCMA -- case BCM47XX_BUS_TYPE_BCMA: -- /* first set the gpio out value */ -- bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, -- value ? 1 << gpio : 0); -- /* then set the gpio mode */ -- bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, -- 1 << gpio); -- return 0; --#endif -- } -- return -EINVAL; -+ bcm47xx_gpio_intmask(1 << gpio, value ? 1 << gpio : 0); - } - --static inline int gpio_intmask(unsigned gpio, int value) -+static inline void gpio_polarity(unsigned gpio, int value) - { -- switch (bcm47xx_bus_type) { --#ifdef CONFIG_BCM47XX_SSB -- case BCM47XX_BUS_TYPE_SSB: -- ssb_gpio_intmask(&bcm47xx_bus.ssb, 1 << gpio, -- value ? 1 << gpio : 0); -- return 0; --#endif --#ifdef CONFIG_BCM47XX_BCMA -- case BCM47XX_BUS_TYPE_BCMA: -- bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc, -- 1 << gpio, value ? 1 << gpio : 0); -- return 0; --#endif -- } -- return -EINVAL; -+ bcm47xx_gpio_polarity(1 << gpio, value ? 1 << gpio : 0); - } - --static inline int gpio_polarity(unsigned gpio, int value) -+static inline int irq_to_gpio(int gpio) - { -- switch (bcm47xx_bus_type) { --#ifdef CONFIG_BCM47XX_SSB -- case BCM47XX_BUS_TYPE_SSB: -- ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << gpio, -- value ? 1 << gpio : 0); -- return 0; --#endif --#ifdef CONFIG_BCM47XX_BCMA -- case BCM47XX_BUS_TYPE_BCMA: -- bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc, -- 1 << gpio, value ? 1 << gpio : 0); -- return 0; --#endif -- } - return -EINVAL; - } - -+#define gpio_cansleep __gpio_cansleep -+#define gpio_to_irq __gpio_to_irq - - #endif /* __BCM47XX_GPIO_H */ diff --git a/target/linux/brcm47xx/patches-3.6/812-disable_wgt634u_crap.patch b/target/linux/brcm47xx/patches-3.6/812-disable_wgt634u_crap.patch index 2819ca1..0dc1564 100644 --- a/target/linux/brcm47xx/patches-3.6/812-disable_wgt634u_crap.patch +++ b/target/linux/brcm47xx/patches-3.6/812-disable_wgt634u_crap.patch @@ -1,13 +1,13 @@ --- a/arch/mips/bcm47xx/Makefile +++ b/arch/mips/bcm47xx/Makefile -@@ -4,4 +4,3 @@ - # +@@ -5,4 +5,3 @@ - obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o sprom.o + obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o + obj-y += gpio.o -obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o --- a/arch/mips/bcm47xx/wgt634u.c +++ /dev/null -@@ -1,177 +0,0 @@ +@@ -1,174 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive @@ -21,6 +21,7 @@ -#include <linux/leds.h> -#include <linux/mtd/physmap.h> -#include <linux/ssb/ssb.h> +-#include <linux/ssb/ssb_embedded.h> -#include <linux/interrupt.h> -#include <linux/reboot.h> -#include <linux/gpio.h> @@ -126,7 +127,8 @@ - - /* Interrupt are level triggered, revert the interrupt polarity - to clear the interrupt. */ -- gpio_polarity(WGT634U_GPIO_RESET, state); +- ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << WGT634U_GPIO_RESET, +- state ? 1 << WGT634U_GPIO_RESET : 0); - - if (!state) { - printk(KERN_INFO "Reset button pressed"); @@ -143,7 +145,6 @@ - * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx. - */ - u8 *et0mac; -- int err; - - if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB) - return -ENODEV; @@ -157,17 +158,13 @@ - - printk(KERN_INFO "WGT634U machine detected.\n"); - -- err = gpio_request(WGT634U_GPIO_RESET, "reset-buton"); -- if (err) { -- printk(KERN_INFO "Can not register gpio for reset button\n"); -- return 0; -- } -- - if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET), - gpio_interrupt, IRQF_SHARED, - "WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) { - gpio_direction_input(WGT634U_GPIO_RESET); -- gpio_intmask(WGT634U_GPIO_RESET, 1); +- ssb_gpio_intmask(&bcm47xx_bus.ssb, +- 1 << WGT634U_GPIO_RESET, +- 1 << WGT634U_GPIO_RESET); - ssb_chipco_irq_mask(&bcm47xx_bus.ssb.chipco, - SSB_CHIPCO_IRQ_GPIO, - SSB_CHIPCO_IRQ_GPIO); diff --git a/target/linux/brcm47xx/patches-3.6/820-wgt634u-nvram-fix.patch b/target/linux/brcm47xx/patches-3.6/820-wgt634u-nvram-fix.patch index 74b17c7..745ff50 100644 --- a/target/linux/brcm47xx/patches-3.6/820-wgt634u-nvram-fix.patch +++ b/target/linux/brcm47xx/patches-3.6/820-wgt634u-nvram-fix.patch @@ -5,12 +5,11 @@ out the configuration than the in kernel cfe config reader. --- a/arch/mips/bcm47xx/Makefile +++ b/arch/mips/bcm47xx/Makefile -@@ -3,4 +3,4 @@ - # under Linux. - # +@@ -5,3 +5,4 @@ --obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o sprom.o -+obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o sprom.o cfe_env.o + obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o + obj-y += gpio.o ++obj-y += cfe_env.o --- /dev/null +++ b/arch/mips/bcm47xx/cfe_env.c @@ -0,0 +1,229 @@ @@ -281,7 +280,7 @@ out the configuration than the in kernel cfe config reader. /* TODO: when nvram is on nand flash check for bad blocks first. */ off = FLASH_MIN; while (off <= lim) { -@@ -179,6 +201,12 @@ int bcm47xx_nvram_getenv(char *name, cha +@@ -181,6 +203,12 @@ int bcm47xx_nvram_getenv(char *name, cha return err; } @@ -294,7 +293,7 @@ out the configuration than the in kernel cfe config reader. /* Look for name=value and return value */ var = &nvram_buf[sizeof(struct nvram_header)]; end = nvram_buf + sizeof(nvram_buf) - 2; -@@ -207,6 +235,9 @@ char *nvram_get(const char *name) +@@ -209,6 +237,9 @@ char *nvram_get(const char *name) if (!nvram_buf[0]) nvram_init(); diff --git a/target/linux/generic/config-3.3 b/target/linux/generic/config-3.3 index 94cd081..4b33921 100644 --- a/target/linux/generic/config-3.3 +++ b/target/linux/generic/config-3.3 @@ -193,6 +193,7 @@ CONFIG_BASE_SMALL=0 # CONFIG_BCM63XX is not set # CONFIG_BCM63XX_PHY is not set # CONFIG_BCMA is not set +# CONFIG_BCMA_DRIVER_GPIO is not set CONFIG_BCMA_POSSIBLE=y # CONFIG_BCM_WIMAX is not set # CONFIG_BDI_SWITCH is not set @@ -2850,6 +2851,7 @@ CONFIG_SQUASHFS_XZ=y # CONFIG_SQUASHFS_ZLIB is not set # CONFIG_SSB is not set # CONFIG_SSB_DEBUG is not set +# CONFIG_SSB_DRIVER_GPIO is not set # CONFIG_SSB_PCMCIAHOST is not set CONFIG_SSB_POSSIBLE=y # CONFIG_SSB_SDIOHOST is not set diff --git a/target/linux/generic/config-3.6 b/target/linux/generic/config-3.6 index bec1a12..5ca5995 100644 --- a/target/linux/generic/config-3.6 +++ b/target/linux/generic/config-3.6 @@ -198,6 +198,7 @@ CONFIG_BASE_SMALL=0 # CONFIG_BCM63XX_PHY is not set # CONFIG_BCM87XX_PHY is not set # CONFIG_BCMA is not set +# CONFIG_BCMA_DRIVER_GPIO is not set CONFIG_BCMA_POSSIBLE=y # CONFIG_BCM_WIMAX is not set # CONFIG_BDI_SWITCH is not set @@ -2972,6 +2973,7 @@ CONFIG_SQUASHFS_XZ=y # CONFIG_SQUASHFS_ZLIB is not set # CONFIG_SSB is not set # CONFIG_SSB_DEBUG is not set +# CONFIG_SSB_DRIVER_GPIO is not set # CONFIG_SSB_PCMCIAHOST is not set CONFIG_SSB_POSSIBLE=y # CONFIG_SSB_SDIOHOST is not set diff --git a/target/linux/generic/config-3.7 b/target/linux/generic/config-3.7 index 4240e64..13d6de7 100644 --- a/target/linux/generic/config-3.7 +++ b/target/linux/generic/config-3.7 @@ -202,6 +202,7 @@ CONFIG_BASE_SMALL=0 # CONFIG_BCM63XX_PHY is not set # CONFIG_BCM87XX_PHY is not set # CONFIG_BCMA is not set +# CONFIG_BCMA_DRIVER_GPIO is not set CONFIG_BCMA_POSSIBLE=y # CONFIG_BCM_WIMAX is not set # CONFIG_BDI_SWITCH is not set @@ -3025,6 +3026,7 @@ CONFIG_SQUASHFS_XZ=y # CONFIG_SQUASHFS_ZLIB is not set # CONFIG_SSB is not set # CONFIG_SSB_DEBUG is not set +# CONFIG_SSB_DRIVER_GPIO is not set # CONFIG_SSB_PCMCIAHOST is not set CONFIG_SSB_POSSIBLE=y # CONFIG_SSB_SDIOHOST is not set diff --git a/target/linux/generic/patches-3.3/020-ssb_update.patch b/target/linux/generic/patches-3.3/020-ssb_update.patch index bfcb556..3a3afd0 100644 --- a/target/linux/generic/patches-3.3/020-ssb_update.patch +++ b/target/linux/generic/patches-3.3/020-ssb_update.patch @@ -1,3 +1,75 @@ +--- a/arch/mips/bcm47xx/nvram.c ++++ b/arch/mips/bcm47xx/nvram.c +@@ -43,8 +43,8 @@ static void early_nvram_init(void) + #ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + mcore_ssb = &bcm47xx_bus.ssb.mipscore; +- base = mcore_ssb->flash_window; +- lim = mcore_ssb->flash_window_size; ++ base = mcore_ssb->pflash.window; ++ lim = mcore_ssb->pflash.window_size; + break; + #endif + #ifdef CONFIG_BCM47XX_BCMA +--- a/arch/mips/bcm47xx/wgt634u.c ++++ b/arch/mips/bcm47xx/wgt634u.c +@@ -156,10 +156,10 @@ static int __init wgt634u_init(void) + SSB_CHIPCO_IRQ_GPIO); + } + +- wgt634u_flash_data.width = mcore->flash_buswidth; +- wgt634u_flash_resource.start = mcore->flash_window; +- wgt634u_flash_resource.end = mcore->flash_window +- + mcore->flash_window_size ++ wgt634u_flash_data.width = mcore->pflash.buswidth; ++ wgt634u_flash_resource.start = mcore->pflash.window; ++ wgt634u_flash_resource.end = mcore->pflash.window ++ + mcore->pflash.window_size + - 1; + return platform_add_devices(wgt634u_devices, + ARRAY_SIZE(wgt634u_devices)); +--- a/drivers/ssb/Kconfig ++++ b/drivers/ssb/Kconfig +@@ -136,6 +136,11 @@ config SSB_DRIVER_MIPS + + If unsure, say N + ++config SSB_SFLASH ++ bool "SSB serial flash support" ++ depends on SSB_DRIVER_MIPS && BROKEN ++ default y ++ + # Assumption: We are on embedded, if we compile the MIPS core. + config SSB_EMBEDDED + bool +@@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE + + If unsure, say N + ++config SSB_DRIVER_GPIO ++ bool "SSB GPIO driver" ++ depends on SSB && GPIOLIB ++ help ++ Driver to provide access to the GPIO pins on the bus. ++ ++ If unsure, say N ++ + endmenu +--- a/drivers/ssb/Makefile ++++ b/drivers/ssb/Makefile +@@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o + # built-in drivers + ssb-y += driver_chipcommon.o + ssb-y += driver_chipcommon_pmu.o ++ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o + ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o + ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o + ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o + ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o ++ssb-$(CONFIG_SSB_DRIVER_GPIO) += driver_gpio.o + + # b43 pci-ssb-bridge driver + # Not strictly a part of SSB, but kept here for convenience --- a/drivers/ssb/b43_pci_bridge.c +++ b/drivers/ssb/b43_pci_bridge.c @@ -29,11 +29,15 @@ static const struct pci_device_id b43_pc @@ -34,7 +106,7 @@ #include "ssb_private.h" -@@ -280,6 +282,69 @@ static void calc_fast_powerup_delay(stru +@@ -280,10 +282,76 @@ static void calc_fast_powerup_delay(stru cc->fast_pwrup_delay = tmp; } @@ -104,7 +176,14 @@ void ssb_chipcommon_init(struct ssb_chipcommon *cc) { if (!cc->dev) -@@ -297,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip + return; /* We don't have a ChipCommon */ ++ ++ spin_lock_init(&cc->gpio_lock); ++ + if (cc->dev->id.revision >= 11) + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); + ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status); +@@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip chipco_powercontrol_init(cc); ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); calc_fast_powerup_delay(cc); @@ -116,7 +195,7 @@ } void ssb_chipco_suspend(struct ssb_chipcommon *cc) -@@ -395,10 +465,27 @@ void ssb_chipco_timing_init(struct ssb_c +@@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c } /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ @@ -147,7 +226,106 @@ } void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) -@@ -473,12 +560,7 @@ int ssb_chipco_serial_init(struct ssb_ch +@@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco + + u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + EXPORT_SYMBOL(ssb_chipco_gpio_control); + + u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res = 0; ++ ++ if (cc->dev->id.revision < 20) ++ return 0xffffffff; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res = 0; ++ ++ if (cc->dev->id.revision < 20) ++ return 0xffffffff; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + #ifdef CONFIG_SSB_SERIAL +@@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch chipco_read32(cc, SSB_CHIPCO_CORECTL) | SSB_CHIPCO_CORECTL_UARTCLK0); } else if ((ccrev >= 11) && (ccrev != 15)) { @@ -288,9 +466,30 @@ + return 0; + } +} +--- /dev/null ++++ b/drivers/ssb/driver_chipcommon_sflash.c +@@ -0,0 +1,18 @@ ++/* ++ * Sonics Silicon Backplane ++ * ChipCommon serial flash interface ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/ssb/ssb.h> ++ ++#include "ssb_private.h" ++ ++/* Initialize serial flash access */ ++int ssb_sflash_init(struct ssb_chipcommon *cc) ++{ ++ pr_err("Serial flash support is not implemented yet!\n"); ++ ++ return -ENOTSUPP; ++} --- a/drivers/ssb/driver_extif.c +++ b/drivers/ssb/driver_extif.c -@@ -112,10 +112,30 @@ void ssb_extif_get_clockcontrol(struct s +@@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB); } @@ -320,9 +519,250 @@ extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks); + + return ticks; ++} ++ ++void ssb_extif_init(struct ssb_extif *extif) ++{ ++ if (!extif->dev) ++ return; /* We don't have a Extif core */ ++ spin_lock_init(&extif->gpio_lock); } u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask) +@@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif * + + u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value) + { +- return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0), ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&extif->gpio_lock, flags); ++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0), + mask, value); ++ spin_unlock_irqrestore(&extif->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value) + { +- return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0), ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&extif->gpio_lock, flags); ++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0), + mask, value); ++ spin_unlock_irqrestore(&extif->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value) + { +- return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&extif->gpio_lock, flags); ++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value); ++ spin_unlock_irqrestore(&extif->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value) + { +- return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&extif->gpio_lock, flags); ++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value); ++ spin_unlock_irqrestore(&extif->gpio_lock, flags); ++ ++ return res; + } +--- /dev/null ++++ b/drivers/ssb/driver_gpio.c +@@ -0,0 +1,176 @@ ++/* ++ * Sonics Silicon Backplane ++ * GPIO driver ++ * ++ * Copyright 2011, Broadcom Corporation ++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/gpio.h> ++#include <linux/export.h> ++#include <linux/ssb/ssb.h> ++ ++#include "ssb_private.h" ++ ++static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip) ++{ ++ return container_of(chip, struct ssb_bus, gpio); ++} ++ ++static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio); ++} ++ ++static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0); ++} ++ ++static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip, ++ unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0); ++ return 0; ++} ++ ++static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip, ++ unsigned gpio, int value) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio); ++ ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0); ++ return 0; ++} ++ ++static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0); ++ /* clear pulldown */ ++ ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0); ++ /* Set pullup */ ++ ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio); ++ ++ return 0; ++} ++ ++static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ /* clear pullup */ ++ ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0); ++} ++ ++static int ssb_gpio_chipco_init(struct ssb_bus *bus) ++{ ++ struct gpio_chip *chip = &bus->gpio; ++ ++ chip->label = "ssb_chipco_gpio"; ++ chip->owner = THIS_MODULE; ++ chip->request = ssb_gpio_chipco_request; ++ chip->free = ssb_gpio_chipco_free; ++ chip->get = ssb_gpio_chipco_get_value; ++ chip->set = ssb_gpio_chipco_set_value; ++ chip->direction_input = ssb_gpio_chipco_direction_input; ++ chip->direction_output = ssb_gpio_chipco_direction_output; ++ chip->ngpio = 16; ++ /* There is just one SoC in one device and its GPIO addresses should be ++ * deterministic to address them more easily. The other buses could get ++ * a random base number. */ ++ if (bus->bustype == SSB_BUSTYPE_SSB) ++ chip->base = 0; ++ else ++ chip->base = -1; ++ ++ return gpiochip_add(chip); ++} ++ ++#ifdef CONFIG_SSB_DRIVER_EXTIF ++ ++static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio); ++} ++ ++static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0); ++} ++ ++static int ssb_gpio_extif_direction_input(struct gpio_chip *chip, ++ unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0); ++ return 0; ++} ++ ++static int ssb_gpio_extif_direction_output(struct gpio_chip *chip, ++ unsigned gpio, int value) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio); ++ ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0); ++ return 0; ++} ++ ++static int ssb_gpio_extif_init(struct ssb_bus *bus) ++{ ++ struct gpio_chip *chip = &bus->gpio; ++ ++ chip->label = "ssb_extif_gpio"; ++ chip->owner = THIS_MODULE; ++ chip->get = ssb_gpio_extif_get_value; ++ chip->set = ssb_gpio_extif_set_value; ++ chip->direction_input = ssb_gpio_extif_direction_input; ++ chip->direction_output = ssb_gpio_extif_direction_output; ++ chip->ngpio = 5; ++ /* There is just one SoC in one device and its GPIO addresses should be ++ * deterministic to address them more easily. The other buses could get ++ * a random base number. */ ++ if (bus->bustype == SSB_BUSTYPE_SSB) ++ chip->base = 0; ++ else ++ chip->base = -1; ++ ++ return gpiochip_add(chip); ++} ++ ++#else ++static int ssb_gpio_extif_init(struct ssb_bus *bus) ++{ ++ return -ENOTSUPP; ++} ++#endif ++ ++int ssb_gpio_init(struct ssb_bus *bus) ++{ ++ if (ssb_chipco_available(&bus->chipco)) ++ return ssb_gpio_chipco_init(bus); ++ else if (ssb_extif_available(&bus->extif)) ++ return ssb_gpio_extif_init(bus); ++ else ++ SSB_WARN_ON(1); ++ ++ return -1; ++} --- a/drivers/ssb/driver_mipscore.c +++ b/drivers/ssb/driver_mipscore.c @@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct @@ -337,7 +777,7 @@ mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports); else mcore->nr_serial_ports = 0; -@@ -190,16 +190,32 @@ static void ssb_mips_flash_detect(struct +@@ -190,16 +190,33 @@ static void ssb_mips_flash_detect(struct { struct ssb_bus *bus = mcore->dev->bus; @@ -358,7 +798,8 @@ + switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) { + case SSB_CHIPCO_FLASHT_STSER: + case SSB_CHIPCO_FLASHT_ATSER: -+ pr_err("Serial flash not supported\n"); ++ pr_debug("Found serial flash\n"); ++ ssb_sflash_init(&bus->chipco); + break; + case SSB_CHIPCO_FLASHT_PARA: + pr_debug("Found parallel flash\n"); @@ -378,7 +819,7 @@ } } -@@ -208,9 +224,12 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m +@@ -208,9 +225,12 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m struct ssb_bus *bus = mcore->dev->bus; u32 pll_type, n, m, rate = 0; @@ -393,7 +834,7 @@ ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m); } else return 0; -@@ -246,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipsco +@@ -246,9 +266,9 @@ void ssb_mipscore_init(struct ssb_mipsco hz = 100000000; ns = 1000000000 / hz; @@ -534,7 +975,22 @@ ssb_bus_may_powerdown(bus); err = ssb_devices_register(bus); -@@ -1094,6 +1086,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus) +@@ -812,7 +804,14 @@ static int __devinit ssb_bus_register(st + if (err) + goto err_pcmcia_exit; + ssb_chipcommon_init(&bus->chipco); ++ ssb_extif_init(&bus->extif); + ssb_mipscore_init(&bus->mipscore); ++ err = ssb_gpio_init(bus); ++ if (err == -ENOTSUPP) ++ ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n"); ++ else if (err) ++ ssb_dprintk(KERN_ERR PFX ++ "Error registering GPIO driver: %i\n", err); + err = ssb_fetch_invariants(bus, get_invariants); + if (err) { + ssb_bus_may_powerdown(bus); +@@ -1094,6 +1093,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus) u32 plltype; u32 clkctl_n, clkctl_m; @@ -544,7 +1000,7 @@ if (ssb_extif_available(&bus->extif)) ssb_extif_get_clockcontrol(&bus->extif, &plltype, &clkctl_n, &clkctl_m); -@@ -1131,8 +1126,7 @@ static u32 ssb_tmslow_reject_bitmask(str +@@ -1131,8 +1133,7 @@ static u32 ssb_tmslow_reject_bitmask(str case SSB_IDLOW_SSBREV_27: /* same here */ return SSB_TMSLOW_REJECT; /* this is a guess */ default: @@ -890,7 +1346,7 @@ #define PFX "ssb: " -@@ -207,4 +208,38 @@ static inline void b43_pci_ssb_bridge_ex +@@ -207,4 +208,66 @@ static inline void b43_pci_ssb_bridge_ex } #endif /* CONFIG_SSB_B43_PCI_BRIDGE */ @@ -903,6 +1359,17 @@ + u32 ticks); +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); + ++/* driver_chipcommon_sflash.c */ ++#ifdef CONFIG_SSB_SFLASH ++int ssb_sflash_init(struct ssb_chipcommon *cc); ++#else ++static inline int ssb_sflash_init(struct ssb_chipcommon *cc) ++{ ++ pr_err("Serial flash not supported\n"); ++ return 0; ++} ++#endif /* CONFIG_SSB_SFLASH */ ++ +#ifdef CONFIG_SSB_DRIVER_EXTIF +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks); +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); @@ -928,18 +1395,38 @@ +} +#endif /* CONFIG_SSB_EMBEDDED */ + ++#ifdef CONFIG_SSB_DRIVER_EXTIF ++extern void ssb_extif_init(struct ssb_extif *extif); ++#else ++static inline void ssb_extif_init(struct ssb_extif *extif) ++{ ++} ++#endif ++ ++#ifdef CONFIG_SSB_DRIVER_GPIO ++extern int ssb_gpio_init(struct ssb_bus *bus); ++#else /* CONFIG_SSB_DRIVER_GPIO */ ++static inline int ssb_gpio_init(struct ssb_bus *bus) ++{ ++ return -ENOTSUPP; ++} ++#endif /* CONFIG_SSB_DRIVER_GPIO */ ++ #endif /* LINUX_SSB_PRIVATE_H_ */ --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h -@@ -8,6 +8,7 @@ +@@ -6,8 +6,10 @@ + #include <linux/types.h> + #include <linux/spinlock.h> #include <linux/pci.h> ++#include <linux/gpio.h> #include <linux/mod_devicetable.h> #include <linux/dma-mapping.h> +#include <linux/platform_device.h> #include <linux/ssb/ssb_regs.h> -@@ -16,6 +17,12 @@ struct pcmcia_device; +@@ -16,6 +18,12 @@ struct pcmcia_device; struct ssb_bus; struct ssb_driver; @@ -952,7 +1439,7 @@ struct ssb_sprom { u8 revision; u8 il0mac[6]; /* MAC address for 802.11b/g */ -@@ -26,9 +33,12 @@ struct ssb_sprom { +@@ -26,9 +34,12 @@ struct ssb_sprom { u8 et0mdcport; /* MDIO for enet0 */ u8 et1mdcport; /* MDIO for enet1 */ u16 board_rev; /* Board revision number from SPROM. */ @@ -967,7 +1454,7 @@ u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */ u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */ u16 pa0b0; -@@ -47,10 +57,10 @@ struct ssb_sprom { +@@ -47,10 +58,10 @@ struct ssb_sprom { u8 gpio1; /* GPIO pin 1 */ u8 gpio2; /* GPIO pin 2 */ u8 gpio3; /* GPIO pin 3 */ @@ -982,7 +1469,7 @@ u8 itssi_a; /* Idle TSSI Target for A-PHY */ u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */ u8 tri2g; /* 2.4GHz TX isolation */ -@@ -61,8 +71,8 @@ struct ssb_sprom { +@@ -61,8 +72,8 @@ struct ssb_sprom { u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */ u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */ u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */ @@ -993,7 +1480,7 @@ u8 rssisav2g; /* 2GHz RSSI params */ u8 rssismc2g; u8 rssismf2g; -@@ -82,16 +92,13 @@ struct ssb_sprom { +@@ -82,16 +93,13 @@ struct ssb_sprom { u16 boardflags2_hi; /* Board flags (bits 48-63) */ /* TODO store board flags in a single u64 */ @@ -1013,7 +1500,7 @@ } antenna_gain; struct { -@@ -103,14 +110,85 @@ struct ssb_sprom { +@@ -103,14 +111,85 @@ struct ssb_sprom { } ghz5; } fem; @@ -1101,7 +1588,7 @@ }; -@@ -166,6 +244,7 @@ struct ssb_bus_ops { +@@ -166,6 +245,7 @@ struct ssb_bus_ops { #define SSB_DEV_MINI_MACPHY 0x823 #define SSB_DEV_ARM_1176 0x824 #define SSB_DEV_ARM_7TDMI 0x825 @@ -1109,14 +1596,18 @@ /* Vendor-ID values */ #define SSB_VENDOR_BROADCOM 0x4243 -@@ -354,6 +433,7 @@ struct ssb_bus { +@@ -354,7 +434,11 @@ struct ssb_bus { #ifdef CONFIG_SSB_EMBEDDED /* Lock for GPIO register access. */ spinlock_t gpio_lock; + struct platform_device *watchdog; #endif /* EMBEDDED */ ++#ifdef CONFIG_SSB_DRIVER_GPIO ++ struct gpio_chip gpio; ++#endif /* DRIVER_GPIO */ /* Internal-only stuff follows. Do not touch. */ + struct list_head list; --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h @@ -504,7 +504,9 @@ @@ -1130,16 +1621,18 @@ /* Status register bits for ST flashes */ #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */ -@@ -589,6 +591,8 @@ struct ssb_chipcommon { +@@ -588,7 +590,10 @@ struct ssb_chipcommon { + u32 status; /* Fast Powerup Delay constant */ u16 fast_pwrup_delay; ++ spinlock_t gpio_lock; struct ssb_chipcommon_pmu pmu; + u32 ticks_per_ms; + u32 max_timer_ms; }; static inline bool ssb_chipco_available(struct ssb_chipcommon *cc) -@@ -628,8 +632,7 @@ enum ssb_clkmode { +@@ -628,8 +633,7 @@ enum ssb_clkmode { extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, enum ssb_clkmode mode); @@ -1149,9 +1642,18 @@ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value); +@@ -642,6 +646,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi + u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value); + u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value); + u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value); ++u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value); ++u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value); + + #ifdef CONFIG_SSB_SERIAL + extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc, --- a/include/linux/ssb/ssb_driver_extif.h +++ b/include/linux/ssb/ssb_driver_extif.h -@@ -152,6 +152,9 @@ +@@ -152,12 +152,16 @@ /* watchdog */ #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */ @@ -1161,7 +1663,14 @@ #ifdef CONFIG_SSB_DRIVER_EXTIF -@@ -171,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s + + struct ssb_extif { + struct ssb_device *dev; ++ spinlock_t gpio_lock; + }; + + static inline bool ssb_extif_available(struct ssb_extif *extif) +@@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s extern void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns); @@ -1171,7 +1680,7 @@ /* Extif GPIO pin access */ u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask); -@@ -205,10 +207,52 @@ void ssb_extif_get_clockcontrol(struct s +@@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s } static inline @@ -1414,3 +1923,25 @@ /* Values for boardflags_lo read from SPROM */ #define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ #define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ +--- /dev/null ++++ b/include/linux/bcm47xx_wdt.h +@@ -0,0 +1,19 @@ ++#ifndef LINUX_BCM47XX_WDT_H_ ++#define LINUX_BCM47XX_WDT_H_ ++ ++#include <linux/types.h> ++ ++ ++struct bcm47xx_wdt { ++ u32 (*timer_set)(struct bcm47xx_wdt *, u32); ++ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32); ++ u32 max_timer_ms; ++ ++ void *driver_data; ++}; ++ ++static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt) ++{ ++ return wdt->driver_data; ++} ++#endif /* LINUX_BCM47XX_WDT_H_ */ diff --git a/target/linux/generic/patches-3.3/021-ssb_bcma_watchdog_header.patch b/target/linux/generic/patches-3.3/021-ssb_bcma_watchdog_header.patch deleted file mode 100644 index 18feeab..0000000 --- a/target/linux/generic/patches-3.3/021-ssb_bcma_watchdog_header.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- /dev/null -+++ b/include/linux/bcm47xx_wdt.h -@@ -0,0 +1,19 @@ -+#ifndef LINUX_BCM47XX_WDT_H_ -+#define LINUX_BCM47XX_WDT_H_ -+ -+#include <linux/types.h> -+ -+ -+struct bcm47xx_wdt { -+ u32 (*timer_set)(struct bcm47xx_wdt *, u32); -+ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32); -+ u32 max_timer_ms; -+ -+ void *driver_data; -+}; -+ -+static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt) -+{ -+ return wdt->driver_data; -+} -+#endif /* LINUX_BCM47XX_WDT_H_ */ diff --git a/target/linux/generic/patches-3.3/025-bcma_backport.patch b/target/linux/generic/patches-3.3/025-bcma_backport.patch index 282da42..a00bec3 100644 --- a/target/linux/generic/patches-3.3/025-bcma_backport.patch +++ b/target/linux/generic/patches-3.3/025-bcma_backport.patch @@ -1,33 +1,3 @@ ---- a/arch/mips/bcm47xx/nvram.c -+++ b/arch/mips/bcm47xx/nvram.c -@@ -43,8 +43,8 @@ static void early_nvram_init(void) - #ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: - mcore_ssb = &bcm47xx_bus.ssb.mipscore; -- base = mcore_ssb->flash_window; -- lim = mcore_ssb->flash_window_size; -+ base = mcore_ssb->pflash.window; -+ lim = mcore_ssb->pflash.window_size; - break; - #endif - #ifdef CONFIG_BCM47XX_BCMA ---- a/arch/mips/bcm47xx/wgt634u.c -+++ b/arch/mips/bcm47xx/wgt634u.c -@@ -156,10 +156,10 @@ static int __init wgt634u_init(void) - SSB_CHIPCO_IRQ_GPIO); - } - -- wgt634u_flash_data.width = mcore->flash_buswidth; -- wgt634u_flash_resource.start = mcore->flash_window; -- wgt634u_flash_resource.end = mcore->flash_window -- + mcore->flash_window_size -+ wgt634u_flash_data.width = mcore->pflash.buswidth; -+ wgt634u_flash_resource.start = mcore->pflash.window; -+ wgt634u_flash_resource.end = mcore->pflash.window -+ + mcore->pflash.window_size - - 1; - return platform_add_devices(wgt634u_devices, - ARRAY_SIZE(wgt634u_devices)); --- a/drivers/bcma/Kconfig +++ b/drivers/bcma/Kconfig @@ -29,7 +29,7 @@ config BCMA_HOST_PCI @@ -39,7 +9,7 @@ help PCI core hostmode operation (external PCI bus). -@@ -46,6 +46,25 @@ config BCMA_DRIVER_MIPS +@@ -46,6 +46,33 @@ config BCMA_DRIVER_MIPS If unsure, say N @@ -62,12 +32,20 @@ + + If unsure, say N + ++config BCMA_DRIVER_GPIO ++ bool "BCMA GPIO driver" ++ depends on BCMA && GPIOLIB ++ help ++ Driver to provide access to the GPIO pins of the bcma bus. ++ ++ If unsure, say N ++ config BCMA_DEBUG bool "BCMA debugging" depends on BCMA --- a/drivers/bcma/Makefile +++ b/drivers/bcma/Makefile -@@ -1,8 +1,11 @@ +@@ -1,8 +1,12 @@ bcma-y += main.o scan.o core.o sprom.o bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o +bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o @@ -76,6 +54,7 @@ bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o +bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o ++bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o obj-$(CONFIG_BCMA) += bcma.o @@ -102,7 +81,16 @@ void bcma_bus_unregister(struct bcma_bus *bus); int __init bcma_bus_early_register(struct bcma_bus *bus, struct bcma_device *core_cc, -@@ -39,8 +48,32 @@ void bcma_chipco_serial_init(struct bcma +@@ -22,6 +31,8 @@ int __init bcma_bus_early_register(struc + int bcma_bus_suspend(struct bcma_bus *bus); + int bcma_bus_resume(struct bcma_bus *bus); + #endif ++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, ++ u8 unit); + + /* scan.c */ + int bcma_bus_scan(struct bcma_bus *bus); +@@ -39,8 +50,32 @@ void bcma_chipco_serial_init(struct bcma #endif /* CONFIG_BCMA_DRIVER_MIPS */ /* driver_chipcommon_pmu.c */ @@ -137,7 +125,7 @@ #ifdef CONFIG_BCMA_HOST_PCI /* host_pci.c */ -@@ -48,8 +81,14 @@ extern int __init bcma_host_pci_init(voi +@@ -48,8 +83,24 @@ extern int __init bcma_host_pci_init(voi extern void __exit bcma_host_pci_exit(void); #endif /* CONFIG_BCMA_HOST_PCI */ @@ -152,6 +140,16 @@ +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ ++#ifdef CONFIG_BCMA_DRIVER_GPIO ++/* driver_gpio.c */ ++int bcma_gpio_init(struct bcma_drv_cc *cc); ++#else ++static inline int bcma_gpio_init(struct bcma_drv_cc *cc) ++{ ++ return -ENOTSUPP; ++} ++#endif /* CONFIG_BCMA_DRIVER_GPIO */ ++ #endif --- a/drivers/bcma/core.c +++ b/drivers/bcma/core.c @@ -226,7 +224,7 @@ #include <linux/bcma/bcma.h> static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, -@@ -22,12 +25,93 @@ static inline u32 bcma_cc_write32_masked +@@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked return value; } @@ -323,8 +321,11 @@ + if (cc->early_setup_done) return; ++ spin_lock_init(&cc->gpio_lock); ++ if (cc->core->id.rev >= 11) -@@ -36,6 +120,22 @@ void bcma_core_chipcommon_init(struct bc + cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); + cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); if (cc->core->id.rev >= 35) cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); @@ -347,7 +348,7 @@ if (cc->core->id.rev >= 20) { bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); -@@ -44,7 +144,7 @@ void bcma_core_chipcommon_init(struct bc +@@ -44,7 +146,7 @@ void bcma_core_chipcommon_init(struct bc if (cc->capabilities & BCMA_CC_CAP_PMU) bcma_pmu_init(cc); if (cc->capabilities & BCMA_CC_CAP_PCTL) @@ -356,7 +357,7 @@ if (cc->core->id.rev >= 16) { if (cc->core->bus->sprom.leddc_on_time && -@@ -56,15 +156,33 @@ void bcma_core_chipcommon_init(struct bc +@@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); } @@ -393,7 +394,110 @@ } void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) -@@ -118,8 +236,7 @@ void bcma_chipco_serial_init(struct bcma +@@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_ + + u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + ++/* ++ * If the bit is set to 0, chipcommon controlls this GPIO, ++ * if the bit is set to 1, it is used by some part of the chip and not our code. ++ */ + u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); + + u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res; ++ ++ if (cc->core->id.rev < 20) ++ return 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res; ++ ++ if (cc->core->id.rev < 20) ++ return 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + #ifdef CONFIG_BCMA_DRIVER_MIPS +@@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma struct bcma_serial_port *ports = cc->serial_ports; if (ccrev >= 11 && ccrev != 15) { @@ -403,7 +507,7 @@ if (ccrev >= 21) { /* Turn off UART clock before switching clocksource. */ bcma_cc_write32(cc, BCMA_CC_CORECTL, -@@ -137,8 +254,7 @@ void bcma_chipco_serial_init(struct bcma +@@ -137,8 +325,7 @@ void bcma_chipco_serial_init(struct bcma | BCMA_CC_CORECTL_UARTCLKEN); } } else { @@ -472,7 +576,22 @@ * * Licensed under the GNU/GPL. See COPYING for details. */ -@@ -54,38 +55,19 @@ void bcma_chipco_regctl_maskset(struct b +@@ -12,12 +13,13 @@ + #include <linux/export.h> + #include <linux/bcma/bcma.h> + +-static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) ++u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) + { + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); + bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); + return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); + } ++EXPORT_SYMBOL_GPL(bcma_chipco_pll_read); + + void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value) + { +@@ -54,38 +56,19 @@ void bcma_chipco_regctl_maskset(struct b } EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset); @@ -514,7 +633,7 @@ } /* Set the resource masks. */ -@@ -93,22 +75,12 @@ static void bcma_pmu_resources_init(stru +@@ -93,22 +76,12 @@ static void bcma_pmu_resources_init(stru bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk); if (max_msk) bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk); @@ -542,7 +661,7 @@ } /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */ -@@ -122,51 +94,69 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct +@@ -122,51 +95,69 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct val |= BCMA_CHIPCTL_4331_EXTPA_EN; if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11) val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; @@ -629,7 +748,7 @@ if (cc->pmu.rev == 1) bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, ~BCMA_CC_PMU_CTL_NOILPONW); -@@ -174,37 +164,31 @@ void bcma_pmu_init(struct bcma_drv_cc *c +@@ -174,37 +165,31 @@ void bcma_pmu_init(struct bcma_drv_cc *c bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_NOILPONW); @@ -679,7 +798,7 @@ } return BCMA_CC_PMU_ALP_CLOCK; } -@@ -212,7 +196,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c +@@ -212,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c /* Find the output of the "m" pll divider given pll controls that start with * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. */ @@ -688,7 +807,7 @@ { u32 tmp, div, ndiv, p1, p2, fc; struct bcma_bus *bus = cc->core->bus; -@@ -221,7 +205,8 @@ static u32 bcma_pmu_clock(struct bcma_dr +@@ -221,7 +206,8 @@ static u32 bcma_pmu_clock(struct bcma_dr BUG_ON(!m || m > 4); @@ -698,7 +817,7 @@ /* Detect failure in clock setting */ tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); if (tmp & 0x40000) -@@ -240,60 +225,95 @@ static u32 bcma_pmu_clock(struct bcma_dr +@@ -240,60 +226,95 @@ static u32 bcma_pmu_clock(struct bcma_dr ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; /* Do calculation in Mhz */ @@ -820,7 +939,7 @@ pll = BCMA_CC_PMU5357_MAINPLL_PLL0; break; default: -@@ -301,10 +321,189 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr +@@ -301,10 +322,189 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr break; } @@ -1054,7 +1173,7 @@ + { "M25P40", 0x12, 0x10000, 8, }, + + { "M25P16", 0x14, 0x10000, 32, }, -+ { "M25P32", 0x14, 0x10000, 64, }, ++ { "M25P32", 0x15, 0x10000, 64, }, + { "M25P64", 0x16, 0x10000, 128, }, + { "M25FL128", 0x17, 0x10000, 256, }, + { 0 }, @@ -1199,6 +1318,107 @@ +{ + mutex_init(&gc->phy_mutex); +} +--- /dev/null ++++ b/drivers/bcma/driver_gpio.c +@@ -0,0 +1,98 @@ ++/* ++ * Broadcom specific AMBA ++ * GPIO driver ++ * ++ * Copyright 2011, Broadcom Corporation ++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/gpio.h> ++#include <linux/export.h> ++#include <linux/bcma/bcma.h> ++ ++#include "bcma_private.h" ++ ++static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip) ++{ ++ return container_of(chip, struct bcma_drv_cc, gpio); ++} ++ ++static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ return !!bcma_chipco_gpio_in(cc, 1 << gpio); ++} ++ ++static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0); ++} ++ ++static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_outen(cc, 1 << gpio, 0); ++ return 0; ++} ++ ++static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio); ++ bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0); ++ return 0; ++} ++ ++static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_control(cc, 1 << gpio, 0); ++ /* clear pulldown */ ++ bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0); ++ /* Set pullup */ ++ bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio); ++ ++ return 0; ++} ++ ++static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ /* clear pullup */ ++ bcma_chipco_gpio_pullup(cc, 1 << gpio, 0); ++} ++ ++int bcma_gpio_init(struct bcma_drv_cc *cc) ++{ ++ struct gpio_chip *chip = &cc->gpio; ++ ++ chip->label = "bcma_gpio"; ++ chip->owner = THIS_MODULE; ++ chip->request = bcma_gpio_request; ++ chip->free = bcma_gpio_free; ++ chip->get = bcma_gpio_get_value; ++ chip->set = bcma_gpio_set_value; ++ chip->direction_input = bcma_gpio_direction_input; ++ chip->direction_output = bcma_gpio_direction_output; ++ chip->ngpio = 16; ++ /* There is just one SoC in one device and its GPIO addresses should be ++ * deterministic to address them more easily. The other buses could get ++ * a random base number. */ ++ if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) ++ chip->base = 0; ++ else ++ chip->base = -1; ++ ++ return gpiochip_add(chip); ++} --- a/drivers/bcma/driver_mips.c +++ b/drivers/bcma/driver_mips.c @@ -22,15 +22,15 @@ @@ -1221,36 +1441,112 @@ dev->bus->chipinfo.pkg == 11 && dev->id.id == BCMA_CORE_USB20_HOST; } -@@ -115,7 +115,7 @@ static void bcma_core_mips_set_irq(struc +@@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct + return dev->core_index; + flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30); + +- return flag & 0x1F; ++ if (flag) ++ return flag & 0x1F; ++ else ++ return 0x3f; + } + + /* Get the MIPS IRQ assignment for a specified device. + * If unassigned, 0 is returned. ++ * If disabled, 5 is returned. ++ * If not supported, 6 is returned. + */ + unsigned int bcma_core_mips_irq(struct bcma_device *dev) + { +@@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b + unsigned int irq; + + irqflag = bcma_core_mips_irqflag(dev); ++ if (irqflag == 0x3f) ++ return 6; + +- for (irq = 1; irq <= 4; irq++) ++ for (irq = 0; irq <= 4; irq++) + if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) & + (1 << irqflag)) + return irq; + +- return 0; ++ return 5; + } + EXPORT_SYMBOL(bcma_core_mips_irq); + +@@ -114,8 +121,8 @@ static void bcma_core_mips_set_irq(struc + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0), bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) & ~(1 << irqflag)); - else +- else - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0); ++ else if (oldirq != 5) + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0); /* assign the new one */ if (irq == 0) { -@@ -131,7 +131,7 @@ static void bcma_core_mips_set_irq(struc +@@ -123,17 +130,17 @@ static void bcma_core_mips_set_irq(struc + bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) | + (1 << irqflag)); + } else { +- u32 oldirqflag = bcma_read32(mdev, +- BCMA_MIPS_MIPS74K_INTMASK(irq)); +- if (oldirqflag) { ++ u32 irqinitmask = bcma_read32(mdev, ++ BCMA_MIPS_MIPS74K_INTMASK(irq)); ++ if (irqinitmask) { + struct bcma_device *core; + /* backplane irq line is in use, find out who uses * it and set user to irq 0 */ - list_for_each_entry_reverse(core, &bus->cores, list) { + list_for_each_entry(core, &bus->cores, list) { if ((1 << bcma_core_mips_irqflag(core)) == - oldirqflag) { +- oldirqflag) { ++ irqinitmask) { bcma_core_mips_set_irq(core, 0); -@@ -143,8 +143,8 @@ static void bcma_core_mips_set_irq(struc + break; + } +@@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc 1 << irqflag); } - pr_info("set_irq: core 0x%04x, irq %d => %d\n", - dev->id.id, oldirq + 2, irq + 2); -+ bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n", -+ dev->id.id, oldirq + 2, irq + 2); ++ bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n", ++ dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2); ++} ++ ++static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq, ++ u16 coreid, u8 unit) ++{ ++ struct bcma_device *core; ++ ++ core = bcma_find_core_unit(bus, coreid, unit); ++ if (!core) { ++ bcma_warn(bus, ++ "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n", ++ coreid, unit); ++ return; ++ } ++ ++ bcma_core_mips_set_irq(core, irq); } static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq) -@@ -161,7 +161,7 @@ static void bcma_core_mips_dump_irq(stru + { + int i; + static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; +- printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); ++ printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); + for (i = 0; i <= 6; i++) + printk(" %s%s", irq_name[i], i == irq ? "*" : " "); + printk("\n"); +@@ -161,7 +184,7 @@ static void bcma_core_mips_dump_irq(stru { struct bcma_device *core; @@ -1259,7 +1555,7 @@ bcma_core_mips_print_irq(core, bcma_core_mips_irq(core)); } } -@@ -171,9 +171,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips +@@ -171,9 +194,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips struct bcma_bus *bus = mcore->core->bus; if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) @@ -1271,7 +1567,7 @@ return 0; } EXPORT_SYMBOL(bcma_cpu_clock); -@@ -181,26 +181,50 @@ EXPORT_SYMBOL(bcma_cpu_clock); +@@ -181,76 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock); static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore) { struct bcma_bus *bus = mcore->core->bus; @@ -1306,7 +1602,7 @@ default: - pr_err("flash not supported.\n"); + bcma_err(bus, "Flash type not supported\n"); - } ++ } + + if (cc->core->id.rev == 38 || + bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { @@ -1314,9 +1610,9 @@ + bcma_debug(bus, "Found NAND flash\n"); + bcma_nflash_init(cc); + } -+ } -+} -+ + } + } + +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) +{ + struct bcma_bus *bus = mcore->core->bus; @@ -1328,10 +1624,11 @@ + bcma_core_mips_flash_detect(mcore); + + mcore->early_setup_done = true; - } - ++} ++ void bcma_core_mips_init(struct bcma_drv_mips *mcore) -@@ -209,13 +233,17 @@ void bcma_core_mips_init(struct bcma_drv + { + struct bcma_bus *bus; struct bcma_device *core; bus = mcore->core->bus; @@ -1339,26 +1636,84 @@ + if (mcore->setup_done) + return; + -+ bcma_info(bus, "Initializing MIPS core...\n"); -+ -+ bcma_core_mips_early_init(mcore); ++ bcma_debug(bus, "Initializing MIPS core...\n"); - if (!mcore->setup_done) - mcore->assigned_irqs = 1; -+ mcore->assigned_irqs = 1; ++ bcma_core_mips_early_init(mcore); - /* Assign IRQs to all cores on the bus */ +- /* Assign IRQs to all cores on the bus */ - list_for_each_entry_reverse(core, &bus->cores, list) { -+ list_for_each_entry(core, &bus->cores, list) { - int mips_irq; - if (core->irq) - continue; -@@ -244,13 +272,8 @@ void bcma_core_mips_init(struct bcma_drv - break; +- int mips_irq; +- if (core->irq) +- continue; +- +- mips_irq = bcma_core_mips_irq(core); +- if (mips_irq > 4) +- core->irq = 0; +- else +- core->irq = mips_irq + 2; +- if (core->irq > 5) +- continue; +- switch (core->id.id) { +- case BCMA_CORE_PCI: +- case BCMA_CORE_PCIE: +- case BCMA_CORE_ETHERNET: +- case BCMA_CORE_ETHERNET_GBIT: +- case BCMA_CORE_MAC_GBIT: +- case BCMA_CORE_80211: +- case BCMA_CORE_USB20_HOST: +- /* These devices get their own IRQ line if available, +- * the rest goes on IRQ0 +- */ +- if (mcore->assigned_irqs <= 4) +- bcma_core_mips_set_irq(core, +- mcore->assigned_irqs++); +- break; ++ switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4716: ++ case BCMA_CHIP_ID_BCM4748: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); ++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); ++ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); ++ break; ++ case BCMA_CHIP_ID_BCM5356: ++ case BCMA_CHIP_ID_BCM47162: ++ case BCMA_CHIP_ID_BCM53572: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); ++ break; ++ case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4749: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); ++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); ++ break; ++ case BCMA_CHIP_ID_BCM4706: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT, ++ 0); ++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1); ++ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON, ++ 0); ++ break; ++ default: ++ list_for_each_entry(core, &bus->cores, list) { ++ core->irq = bcma_core_mips_irq(core) + 2; } ++ bcma_err(bus, ++ "Unknown device (0x%x) found, can not configure IRQs\n", ++ bus->chipinfo.id); } - pr_info("IRQ reconfiguration done\n"); -+ bcma_info(bus, "IRQ reconfiguration done\n"); ++ bcma_debug(bus, "IRQ reconfiguration done\n"); bcma_core_mips_dump_irq(bus); - if (mcore->setup_done) @@ -2512,8 +2867,8 @@ } +EXPORT_SYMBOL_GPL(bcma_find_core); + -+static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, -+ u8 unit) ++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, ++ u8 unit) +{ + struct bcma_device *core; + @@ -2546,7 +2901,7 @@ switch (bus->hosttype) { case BCMA_HOSTTYPE_PCI: -@@ -111,41 +140,85 @@ static int bcma_register_cores(struct bc +@@ -111,41 +140,90 @@ static int bcma_register_cores(struct bc err = device_register(&core->dev); if (err) { @@ -2576,6 +2931,11 @@ + bcma_err(bus, "Error registering NAND flash\n"); + } +#endif ++ err = bcma_gpio_init(&bus->drv_cc); ++ if (err == -ENOTSUPP) ++ bcma_debug(bus, "GPIO driver not activated\n"); ++ else if (err) ++ bcma_err(bus, "Error registering GPIO driver: %i\n", err); + + if (bus->hosttype == BCMA_HOSTTYPE_SOC) { + err = bcma_chipco_watchdog_register(&bus->drv_cc); @@ -2639,7 +2999,7 @@ if (core) { bus->drv_cc.core = core; bcma_core_chipcommon_init(&bus->drv_cc); -@@ -159,30 +232,47 @@ int bcma_bus_register(struct bcma_bus *b +@@ -159,30 +237,47 @@ int bcma_bus_register(struct bcma_bus *b } /* Init PCIE core */ @@ -2697,7 +3057,7 @@ } int __init bcma_bus_early_register(struct bcma_bus *bus, -@@ -196,14 +286,14 @@ int __init bcma_bus_early_register(struc +@@ -196,14 +291,14 @@ int __init bcma_bus_early_register(struc bcma_init_bus(bus); match.manuf = BCMA_MANUF_BCM; @@ -2714,7 +3074,7 @@ return -1; } -@@ -215,25 +305,25 @@ int __init bcma_bus_early_register(struc +@@ -215,25 +310,25 @@ int __init bcma_bus_early_register(struc /* Scan for mips core */ err = bcma_bus_scan_early(bus, &match, core_mips); if (err) { @@ -2747,7 +3107,7 @@ return 0; } -@@ -259,8 +349,7 @@ int bcma_bus_resume(struct bcma_bus *bus +@@ -259,8 +354,7 @@ int bcma_bus_resume(struct bcma_bus *bus struct bcma_device *core; /* Init CC core */ @@ -3760,18 +4120,27 @@ extern bool bcma_core_is_enabled(struct bcma_device *core); extern void bcma_core_disable(struct bcma_device *core, u32 flags); extern int bcma_core_enable(struct bcma_device *core, u32 flags); +@@ -289,6 +350,7 @@ extern void bcma_core_set_clockmode(stru + enum bcma_clkmode clkmode); + extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, + bool on); ++extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset); + #define BCMA_DMA_TRANSLATION_MASK 0xC0000000 + #define BCMA_DMA_TRANSLATION_NONE 0x00000000 + #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */ --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h -@@ -1,6 +1,8 @@ +@@ -1,6 +1,9 @@ #ifndef LINUX_BCMA_DRIVER_CC_H_ #define LINUX_BCMA_DRIVER_CC_H_ +#include <linux/platform_device.h> ++#include <linux/gpio.h> + /** ChipCommon core registers. **/ #define BCMA_CC_ID 0x0000 #define BCMA_CC_ID_ID 0x0000FFFF -@@ -24,7 +26,7 @@ +@@ -24,7 +27,7 @@ #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */ #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */ #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ @@ -3780,7 +4149,7 @@ #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */ #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */ #define BCMA_PLLTYPE_NONE 0x00000000 -@@ -45,6 +47,7 @@ +@@ -45,6 +48,7 @@ #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */ @@ -3788,7 +4157,7 @@ #define BCMA_CC_CORECTL 0x0008 #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ -@@ -56,6 +59,9 @@ +@@ -56,6 +60,9 @@ #define BCMA_CC_OTPS_HW_PROTECT 0x00000001 #define BCMA_CC_OTPS_SW_PROTECT 0x00000002 #define BCMA_CC_OTPS_CID_PROTECT 0x00000004 @@ -3798,7 +4167,7 @@ #define BCMA_CC_OTPC 0x0014 /* OTP control */ #define BCMA_CC_OTPC_RECWAIT 0xFF000000 #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00 -@@ -72,6 +78,8 @@ +@@ -72,6 +79,8 @@ #define BCMA_CC_OTPP_READ 0x40000000 #define BCMA_CC_OTPP_START 0x80000000 #define BCMA_CC_OTPP_BUSY 0x80000000 @@ -3807,7 +4176,7 @@ #define BCMA_CC_IRQSTAT 0x0020 #define BCMA_CC_IRQMASK 0x0024 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */ -@@ -79,6 +87,22 @@ +@@ -79,6 +88,22 @@ #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */ #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */ #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */ @@ -3830,7 +4199,7 @@ #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ #define BCMA_CC_JCMD_START 0x80000000 #define BCMA_CC_JCMD_BUSY 0x80000000 -@@ -108,10 +132,58 @@ +@@ -108,10 +133,58 @@ #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */ #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */ #define BCMA_CC_FLASHCTL 0x0040 @@ -3889,7 +4258,7 @@ #define BCMA_CC_BCAST_ADDR 0x0050 #define BCMA_CC_BCAST_DATA 0x0054 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */ -@@ -181,6 +253,45 @@ +@@ -181,6 +254,45 @@ #define BCMA_CC_FLASH_CFG 0x0128 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ #define BCMA_CC_FLASH_WAITCNT 0x012C @@ -3935,7 +4304,7 @@ /* 0x1E0 is defined as shared BCMA_CLKCTLST */ #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ #define BCMA_CC_UART0_DATA 0x0300 -@@ -240,7 +351,60 @@ +@@ -240,7 +352,60 @@ #define BCMA_CC_PLLCTL_ADDR 0x0660 #define BCMA_CC_PLLCTL_DATA 0x0664 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */ @@ -3997,7 +4366,7 @@ /* Divider allocation in 4716/47162/5356 */ #define BCMA_CC_PMU5_MAINPLL_CPU 1 -@@ -256,6 +420,15 @@ +@@ -256,6 +421,15 @@ /* 4706 PMU */ #define BCMA_CC_PMU4706_MAINPLL_PLL0 0 @@ -4013,7 +4382,7 @@ /* ALP clock on pre-PMU chips */ #define BCMA_CC_PMU_ALP_CLOCK 20000000 -@@ -284,6 +457,19 @@ +@@ -284,6 +458,19 @@ #define BCMA_CC_PPL_PCHI_OFF 5 #define BCMA_CC_PPL_PCHI_MASK 0x0000003f @@ -4033,7 +4402,7 @@ /* BCM4331 ChipControl numbers. */ #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ -@@ -297,9 +483,25 @@ +@@ -297,9 +484,25 @@ #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */ #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */ #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */ @@ -4059,7 +4428,7 @@ /* Data for the PMU, if available. * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) */ -@@ -310,11 +512,35 @@ struct bcma_chipcommon_pmu { +@@ -310,11 +513,35 @@ struct bcma_chipcommon_pmu { #ifdef CONFIG_BCMA_DRIVER_MIPS struct bcma_pflash { @@ -4095,7 +4464,7 @@ struct bcma_serial_port { void *regs; unsigned long clockspeed; -@@ -330,15 +556,24 @@ struct bcma_drv_cc { +@@ -330,15 +557,30 @@ struct bcma_drv_cc { u32 capabilities; u32 capabilities_ext; u8 setup_done:1; @@ -4117,10 +4486,16 @@ #endif /* CONFIG_BCMA_DRIVER_MIPS */ + u32 ticks_per_ms; + struct platform_device *watchdog; ++ ++ /* Lock for GPIO register access. */ ++ spinlock_t gpio_lock; ++#ifdef CONFIG_BCMA_DRIVER_GPIO ++ struct gpio_chip gpio; ++#endif }; /* Register access */ -@@ -355,14 +590,14 @@ struct bcma_drv_cc { +@@ -355,14 +597,14 @@ struct bcma_drv_cc { bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); @@ -4137,7 +4512,12 @@ void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); -@@ -378,6 +613,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm +@@ -375,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d + u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); + u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); + u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); ++u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value); ++u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value); /* PMU support */ extern void bcma_pmu_init(struct bcma_drv_cc *cc); @@ -4145,7 +4525,7 @@ extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value); -@@ -387,5 +623,6 @@ extern void bcma_chipco_chipctl_maskset( +@@ -387,5 +632,6 @@ extern void bcma_chipco_chipctl_maskset( u32 offset, u32 mask, u32 set); extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, u32 set); @@ -4257,12 +4637,12 @@ +#endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */ --- a/include/linux/bcma/bcma_driver_mips.h +++ b/include/linux/bcma/bcma_driver_mips.h -@@ -35,13 +35,16 @@ struct bcma_device; +@@ -35,13 +35,15 @@ struct bcma_device; struct bcma_drv_mips { struct bcma_device *core; u8 setup_done:1; +- unsigned int assigned_irqs; + u8 early_setup_done:1; - unsigned int assigned_irqs; }; #ifdef CONFIG_BCMA_DRIVER_MIPS diff --git a/target/linux/generic/patches-3.6/020-ssb_update.patch b/target/linux/generic/patches-3.6/020-ssb_update.patch index 288024d..4113c17 100644 --- a/target/linux/generic/patches-3.6/020-ssb_update.patch +++ b/target/linux/generic/patches-3.6/020-ssb_update.patch @@ -1,3 +1,75 @@ +--- a/arch/mips/bcm47xx/nvram.c ++++ b/arch/mips/bcm47xx/nvram.c +@@ -43,8 +43,8 @@ static void early_nvram_init(void) + #ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + mcore_ssb = &bcm47xx_bus.ssb.mipscore; +- base = mcore_ssb->flash_window; +- lim = mcore_ssb->flash_window_size; ++ base = mcore_ssb->pflash.window; ++ lim = mcore_ssb->pflash.window_size; + break; + #endif + #ifdef CONFIG_BCM47XX_BCMA +--- a/arch/mips/bcm47xx/wgt634u.c ++++ b/arch/mips/bcm47xx/wgt634u.c +@@ -156,10 +156,10 @@ static int __init wgt634u_init(void) + SSB_CHIPCO_IRQ_GPIO); + } + +- wgt634u_flash_data.width = mcore->flash_buswidth; +- wgt634u_flash_resource.start = mcore->flash_window; +- wgt634u_flash_resource.end = mcore->flash_window +- + mcore->flash_window_size ++ wgt634u_flash_data.width = mcore->pflash.buswidth; ++ wgt634u_flash_resource.start = mcore->pflash.window; ++ wgt634u_flash_resource.end = mcore->pflash.window ++ + mcore->pflash.window_size + - 1; + return platform_add_devices(wgt634u_devices, + ARRAY_SIZE(wgt634u_devices)); +--- a/drivers/ssb/Kconfig ++++ b/drivers/ssb/Kconfig +@@ -136,6 +136,11 @@ config SSB_DRIVER_MIPS + + If unsure, say N + ++config SSB_SFLASH ++ bool "SSB serial flash support" ++ depends on SSB_DRIVER_MIPS && BROKEN ++ default y ++ + # Assumption: We are on embedded, if we compile the MIPS core. + config SSB_EMBEDDED + bool +@@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE + + If unsure, say N + ++config SSB_DRIVER_GPIO ++ bool "SSB GPIO driver" ++ depends on SSB && GPIOLIB ++ help ++ Driver to provide access to the GPIO pins on the bus. ++ ++ If unsure, say N ++ + endmenu +--- a/drivers/ssb/Makefile ++++ b/drivers/ssb/Makefile +@@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o + # built-in drivers + ssb-y += driver_chipcommon.o + ssb-y += driver_chipcommon_pmu.o ++ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o + ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o + ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o + ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o + ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o ++ssb-$(CONFIG_SSB_DRIVER_GPIO) += driver_gpio.o + + # b43 pci-ssb-bridge driver + # Not strictly a part of SSB, but kept here for convenience --- a/drivers/ssb/b43_pci_bridge.c +++ b/drivers/ssb/b43_pci_bridge.c @@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc @@ -26,7 +98,7 @@ #include "ssb_private.h" -@@ -280,6 +282,69 @@ static void calc_fast_powerup_delay(stru +@@ -280,10 +282,76 @@ static void calc_fast_powerup_delay(stru cc->fast_pwrup_delay = tmp; } @@ -96,7 +168,14 @@ void ssb_chipcommon_init(struct ssb_chipcommon *cc) { if (!cc->dev) -@@ -297,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip + return; /* We don't have a ChipCommon */ ++ ++ spin_lock_init(&cc->gpio_lock); ++ + if (cc->dev->id.revision >= 11) + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); + ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status); +@@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip chipco_powercontrol_init(cc); ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); calc_fast_powerup_delay(cc); @@ -108,7 +187,7 @@ } void ssb_chipco_suspend(struct ssb_chipcommon *cc) -@@ -395,10 +465,27 @@ void ssb_chipco_timing_init(struct ssb_c +@@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c } /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ @@ -139,7 +218,106 @@ } void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) -@@ -473,12 +560,7 @@ int ssb_chipco_serial_init(struct ssb_ch +@@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco + + u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + EXPORT_SYMBOL(ssb_chipco_gpio_control); + + u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res = 0; ++ ++ if (cc->dev->id.revision < 20) ++ return 0xffffffff; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res = 0; ++ ++ if (cc->dev->id.revision < 20) ++ return 0xffffffff; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + #ifdef CONFIG_SSB_SERIAL +@@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch chipco_read32(cc, SSB_CHIPCO_CORECTL) | SSB_CHIPCO_CORECTL_UARTCLK0); } else if ((ccrev >= 11) && (ccrev != 15)) { @@ -206,9 +384,30 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc) { struct ssb_bus *bus = cc->dev->bus; +--- /dev/null ++++ b/drivers/ssb/driver_chipcommon_sflash.c +@@ -0,0 +1,18 @@ ++/* ++ * Sonics Silicon Backplane ++ * ChipCommon serial flash interface ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/ssb/ssb.h> ++ ++#include "ssb_private.h" ++ ++/* Initialize serial flash access */ ++int ssb_sflash_init(struct ssb_chipcommon *cc) ++{ ++ pr_err("Serial flash support is not implemented yet!\n"); ++ ++ return -ENOTSUPP; ++} --- a/drivers/ssb/driver_extif.c +++ b/drivers/ssb/driver_extif.c -@@ -112,10 +112,30 @@ void ssb_extif_get_clockcontrol(struct s +@@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB); } @@ -238,9 +437,250 @@ extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks); + + return ticks; ++} ++ ++void ssb_extif_init(struct ssb_extif *extif) ++{ ++ if (!extif->dev) ++ return; /* We don't have a Extif core */ ++ spin_lock_init(&extif->gpio_lock); } u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask) +@@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif * + + u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value) + { +- return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0), ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&extif->gpio_lock, flags); ++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0), + mask, value); ++ spin_unlock_irqrestore(&extif->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value) + { +- return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0), ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&extif->gpio_lock, flags); ++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0), + mask, value); ++ spin_unlock_irqrestore(&extif->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value) + { +- return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&extif->gpio_lock, flags); ++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value); ++ spin_unlock_irqrestore(&extif->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value) + { +- return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&extif->gpio_lock, flags); ++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value); ++ spin_unlock_irqrestore(&extif->gpio_lock, flags); ++ ++ return res; + } +--- /dev/null ++++ b/drivers/ssb/driver_gpio.c +@@ -0,0 +1,176 @@ ++/* ++ * Sonics Silicon Backplane ++ * GPIO driver ++ * ++ * Copyright 2011, Broadcom Corporation ++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/gpio.h> ++#include <linux/export.h> ++#include <linux/ssb/ssb.h> ++ ++#include "ssb_private.h" ++ ++static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip) ++{ ++ return container_of(chip, struct ssb_bus, gpio); ++} ++ ++static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio); ++} ++ ++static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0); ++} ++ ++static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip, ++ unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0); ++ return 0; ++} ++ ++static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip, ++ unsigned gpio, int value) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio); ++ ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0); ++ return 0; ++} ++ ++static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0); ++ /* clear pulldown */ ++ ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0); ++ /* Set pullup */ ++ ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio); ++ ++ return 0; ++} ++ ++static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ /* clear pullup */ ++ ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0); ++} ++ ++static int ssb_gpio_chipco_init(struct ssb_bus *bus) ++{ ++ struct gpio_chip *chip = &bus->gpio; ++ ++ chip->label = "ssb_chipco_gpio"; ++ chip->owner = THIS_MODULE; ++ chip->request = ssb_gpio_chipco_request; ++ chip->free = ssb_gpio_chipco_free; ++ chip->get = ssb_gpio_chipco_get_value; ++ chip->set = ssb_gpio_chipco_set_value; ++ chip->direction_input = ssb_gpio_chipco_direction_input; ++ chip->direction_output = ssb_gpio_chipco_direction_output; ++ chip->ngpio = 16; ++ /* There is just one SoC in one device and its GPIO addresses should be ++ * deterministic to address them more easily. The other buses could get ++ * a random base number. */ ++ if (bus->bustype == SSB_BUSTYPE_SSB) ++ chip->base = 0; ++ else ++ chip->base = -1; ++ ++ return gpiochip_add(chip); ++} ++ ++#ifdef CONFIG_SSB_DRIVER_EXTIF ++ ++static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio); ++} ++ ++static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0); ++} ++ ++static int ssb_gpio_extif_direction_input(struct gpio_chip *chip, ++ unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0); ++ return 0; ++} ++ ++static int ssb_gpio_extif_direction_output(struct gpio_chip *chip, ++ unsigned gpio, int value) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio); ++ ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0); ++ return 0; ++} ++ ++static int ssb_gpio_extif_init(struct ssb_bus *bus) ++{ ++ struct gpio_chip *chip = &bus->gpio; ++ ++ chip->label = "ssb_extif_gpio"; ++ chip->owner = THIS_MODULE; ++ chip->get = ssb_gpio_extif_get_value; ++ chip->set = ssb_gpio_extif_set_value; ++ chip->direction_input = ssb_gpio_extif_direction_input; ++ chip->direction_output = ssb_gpio_extif_direction_output; ++ chip->ngpio = 5; ++ /* There is just one SoC in one device and its GPIO addresses should be ++ * deterministic to address them more easily. The other buses could get ++ * a random base number. */ ++ if (bus->bustype == SSB_BUSTYPE_SSB) ++ chip->base = 0; ++ else ++ chip->base = -1; ++ ++ return gpiochip_add(chip); ++} ++ ++#else ++static int ssb_gpio_extif_init(struct ssb_bus *bus) ++{ ++ return -ENOTSUPP; ++} ++#endif ++ ++int ssb_gpio_init(struct ssb_bus *bus) ++{ ++ if (ssb_chipco_available(&bus->chipco)) ++ return ssb_gpio_chipco_init(bus); ++ else if (ssb_extif_available(&bus->extif)) ++ return ssb_gpio_extif_init(bus); ++ else ++ SSB_WARN_ON(1); ++ ++ return -1; ++} --- a/drivers/ssb/driver_mipscore.c +++ b/drivers/ssb/driver_mipscore.c @@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct @@ -255,7 +695,7 @@ mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports); else mcore->nr_serial_ports = 0; -@@ -190,16 +190,32 @@ static void ssb_mips_flash_detect(struct +@@ -190,16 +190,33 @@ static void ssb_mips_flash_detect(struct { struct ssb_bus *bus = mcore->dev->bus; @@ -276,7 +716,8 @@ + switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) { + case SSB_CHIPCO_FLASHT_STSER: + case SSB_CHIPCO_FLASHT_ATSER: -+ pr_err("Serial flash not supported\n"); ++ pr_debug("Found serial flash\n"); ++ ssb_sflash_init(&bus->chipco); + break; + case SSB_CHIPCO_FLASHT_PARA: + pr_debug("Found parallel flash\n"); @@ -296,7 +737,7 @@ } } -@@ -211,9 +227,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m +@@ -211,9 +228,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU) return ssb_pmu_get_cpu_clock(&bus->chipco); @@ -308,7 +749,7 @@ ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m); } else return 0; -@@ -249,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipsco +@@ -249,9 +266,9 @@ void ssb_mipscore_init(struct ssb_mipsco hz = 100000000; ns = 1000000000 / hz; @@ -407,7 +848,22 @@ ssb_bus_may_powerdown(bus); err = ssb_devices_register(bus); -@@ -1118,8 +1126,7 @@ static u32 ssb_tmslow_reject_bitmask(str +@@ -796,7 +804,14 @@ static int __devinit ssb_bus_register(st + if (err) + goto err_pcmcia_exit; + ssb_chipcommon_init(&bus->chipco); ++ ssb_extif_init(&bus->extif); + ssb_mipscore_init(&bus->mipscore); ++ err = ssb_gpio_init(bus); ++ if (err == -ENOTSUPP) ++ ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n"); ++ else if (err) ++ ssb_dprintk(KERN_ERR PFX ++ "Error registering GPIO driver: %i\n", err); + err = ssb_fetch_invariants(bus, get_invariants); + if (err) { + ssb_bus_may_powerdown(bus); +@@ -1118,8 +1133,7 @@ static u32 ssb_tmslow_reject_bitmask(str case SSB_IDLOW_SSBREV_27: /* same here */ return SSB_TMSLOW_REJECT; /* this is a guess */ default: @@ -427,7 +883,7 @@ #define PFX "ssb: " -@@ -210,5 +211,35 @@ static inline void b43_pci_ssb_bridge_ex +@@ -210,5 +211,63 @@ static inline void b43_pci_ssb_bridge_ex /* driver_chipcommon_pmu.c */ extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc); extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc); @@ -437,6 +893,17 @@ + u32 ticks); +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); + ++/* driver_chipcommon_sflash.c */ ++#ifdef CONFIG_SSB_SFLASH ++int ssb_sflash_init(struct ssb_chipcommon *cc); ++#else ++static inline int ssb_sflash_init(struct ssb_chipcommon *cc) ++{ ++ pr_err("Serial flash not supported\n"); ++ return 0; ++} ++#endif /* CONFIG_SSB_SFLASH */ ++ +#ifdef CONFIG_SSB_DRIVER_EXTIF +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks); +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); @@ -461,26 +928,50 @@ + return 0; +} +#endif /* CONFIG_SSB_EMBEDDED */ ++ ++#ifdef CONFIG_SSB_DRIVER_EXTIF ++extern void ssb_extif_init(struct ssb_extif *extif); ++#else ++static inline void ssb_extif_init(struct ssb_extif *extif) ++{ ++} ++#endif ++ ++#ifdef CONFIG_SSB_DRIVER_GPIO ++extern int ssb_gpio_init(struct ssb_bus *bus); ++#else /* CONFIG_SSB_DRIVER_GPIO */ ++static inline int ssb_gpio_init(struct ssb_bus *bus) ++{ ++ return -ENOTSUPP; ++} ++#endif /* CONFIG_SSB_DRIVER_GPIO */ #endif /* LINUX_SSB_PRIVATE_H_ */ --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h -@@ -8,6 +8,7 @@ +@@ -6,8 +6,10 @@ + #include <linux/types.h> + #include <linux/spinlock.h> #include <linux/pci.h> ++#include <linux/gpio.h> #include <linux/mod_devicetable.h> #include <linux/dma-mapping.h> +#include <linux/platform_device.h> #include <linux/ssb/ssb_regs.h> -@@ -432,6 +433,7 @@ struct ssb_bus { +@@ -432,7 +434,11 @@ struct ssb_bus { #ifdef CONFIG_SSB_EMBEDDED /* Lock for GPIO register access. */ spinlock_t gpio_lock; + struct platform_device *watchdog; #endif /* EMBEDDED */ ++#ifdef CONFIG_SSB_DRIVER_GPIO ++ struct gpio_chip gpio; ++#endif /* DRIVER_GPIO */ /* Internal-only stuff follows. Do not touch. */ + struct list_head list; --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h @@ -504,7 +504,9 @@ @@ -494,16 +985,18 @@ /* Status register bits for ST flashes */ #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */ -@@ -589,6 +591,8 @@ struct ssb_chipcommon { +@@ -588,7 +590,10 @@ struct ssb_chipcommon { + u32 status; /* Fast Powerup Delay constant */ u16 fast_pwrup_delay; ++ spinlock_t gpio_lock; struct ssb_chipcommon_pmu pmu; + u32 ticks_per_ms; + u32 max_timer_ms; }; static inline bool ssb_chipco_available(struct ssb_chipcommon *cc) -@@ -628,8 +632,7 @@ enum ssb_clkmode { +@@ -628,8 +633,7 @@ enum ssb_clkmode { extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, enum ssb_clkmode mode); @@ -513,9 +1006,18 @@ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value); +@@ -642,6 +646,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi + u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value); + u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value); + u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value); ++u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value); ++u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value); + + #ifdef CONFIG_SSB_SERIAL + extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc, --- a/include/linux/ssb/ssb_driver_extif.h +++ b/include/linux/ssb/ssb_driver_extif.h -@@ -152,6 +152,9 @@ +@@ -152,12 +152,16 @@ /* watchdog */ #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */ @@ -525,7 +1027,14 @@ #ifdef CONFIG_SSB_DRIVER_EXTIF -@@ -171,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s + + struct ssb_extif { + struct ssb_device *dev; ++ spinlock_t gpio_lock; + }; + + static inline bool ssb_extif_available(struct ssb_extif *extif) +@@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s extern void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns); @@ -535,7 +1044,7 @@ /* Extif GPIO pin access */ u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask); -@@ -205,10 +207,52 @@ void ssb_extif_get_clockcontrol(struct s +@@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s } static inline @@ -627,3 +1136,25 @@ #define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff #define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0 #define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00 +--- /dev/null ++++ b/include/linux/bcm47xx_wdt.h +@@ -0,0 +1,19 @@ ++#ifndef LINUX_BCM47XX_WDT_H_ ++#define LINUX_BCM47XX_WDT_H_ ++ ++#include <linux/types.h> ++ ++ ++struct bcm47xx_wdt { ++ u32 (*timer_set)(struct bcm47xx_wdt *, u32); ++ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32); ++ u32 max_timer_ms; ++ ++ void *driver_data; ++}; ++ ++static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt) ++{ ++ return wdt->driver_data; ++} ++#endif /* LINUX_BCM47XX_WDT_H_ */ diff --git a/target/linux/generic/patches-3.6/021-ssb_bcma_watchdog_header.patch b/target/linux/generic/patches-3.6/021-ssb_bcma_watchdog_header.patch deleted file mode 100644 index 18feeab..0000000 --- a/target/linux/generic/patches-3.6/021-ssb_bcma_watchdog_header.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- /dev/null -+++ b/include/linux/bcm47xx_wdt.h -@@ -0,0 +1,19 @@ -+#ifndef LINUX_BCM47XX_WDT_H_ -+#define LINUX_BCM47XX_WDT_H_ -+ -+#include <linux/types.h> -+ -+ -+struct bcm47xx_wdt { -+ u32 (*timer_set)(struct bcm47xx_wdt *, u32); -+ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32); -+ u32 max_timer_ms; -+ -+ void *driver_data; -+}; -+ -+static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt) -+{ -+ return wdt->driver_data; -+} -+#endif /* LINUX_BCM47XX_WDT_H_ */ diff --git a/target/linux/generic/patches-3.6/025-bcma_backport.patch b/target/linux/generic/patches-3.6/025-bcma_backport.patch index 2e4a70a..15b5c6f 100644 --- a/target/linux/generic/patches-3.6/025-bcma_backport.patch +++ b/target/linux/generic/patches-3.6/025-bcma_backport.patch @@ -1,33 +1,3 @@ ---- a/arch/mips/bcm47xx/nvram.c -+++ b/arch/mips/bcm47xx/nvram.c -@@ -43,8 +43,8 @@ static void early_nvram_init(void) - #ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: - mcore_ssb = &bcm47xx_bus.ssb.mipscore; -- base = mcore_ssb->flash_window; -- lim = mcore_ssb->flash_window_size; -+ base = mcore_ssb->pflash.window; -+ lim = mcore_ssb->pflash.window_size; - break; - #endif - #ifdef CONFIG_BCM47XX_BCMA ---- a/arch/mips/bcm47xx/wgt634u.c -+++ b/arch/mips/bcm47xx/wgt634u.c -@@ -156,10 +156,10 @@ static int __init wgt634u_init(void) - SSB_CHIPCO_IRQ_GPIO); - } - -- wgt634u_flash_data.width = mcore->flash_buswidth; -- wgt634u_flash_resource.start = mcore->flash_window; -- wgt634u_flash_resource.end = mcore->flash_window -- + mcore->flash_window_size -+ wgt634u_flash_data.width = mcore->pflash.buswidth; -+ wgt634u_flash_resource.start = mcore->pflash.window; -+ wgt634u_flash_resource.end = mcore->pflash.window -+ + mcore->pflash.window_size - - 1; - return platform_add_devices(wgt634u_devices, - ARRAY_SIZE(wgt634u_devices)); --- a/drivers/bcma/Kconfig +++ b/drivers/bcma/Kconfig @@ -48,12 +48,12 @@ config BCMA_DRIVER_MIPS @@ -45,9 +15,43 @@ default y config BCMA_DRIVER_GMAC_CMN +@@ -65,6 +65,14 @@ config BCMA_DRIVER_GMAC_CMN + + If unsure, say N + ++config BCMA_DRIVER_GPIO ++ bool "BCMA GPIO driver" ++ depends on BCMA && GPIOLIB ++ help ++ Driver to provide access to the GPIO pins of the bcma bus. ++ ++ If unsure, say N ++ + config BCMA_DEBUG + bool "BCMA debugging" + depends on BCMA +--- a/drivers/bcma/Makefile ++++ b/drivers/bcma/Makefile +@@ -6,6 +6,7 @@ bcma-y += driver_pci.o + bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o + bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o + bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o ++bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o + bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o + bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o + obj-$(CONFIG_BCMA) += bcma.o --- a/drivers/bcma/bcma_private.h +++ b/drivers/bcma/bcma_private.h -@@ -48,12 +48,13 @@ void bcma_chipco_serial_init(struct bcma +@@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc + int bcma_bus_suspend(struct bcma_bus *bus); + int bcma_bus_resume(struct bcma_bus *bus); + #endif ++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, ++ u8 unit); + + /* scan.c */ + int bcma_bus_scan(struct bcma_bus *bus); +@@ -48,12 +50,13 @@ void bcma_chipco_serial_init(struct bcma #endif /* CONFIG_BCMA_DRIVER_MIPS */ /* driver_chipcommon_pmu.c */ @@ -63,7 +67,7 @@ #else static inline int bcma_sflash_init(struct bcma_drv_cc *cc) { -@@ -65,6 +66,7 @@ static inline int bcma_sflash_init(struc +@@ -65,6 +68,7 @@ static inline int bcma_sflash_init(struc #ifdef CONFIG_BCMA_NFLASH /* driver_chipcommon_nflash.c */ int bcma_nflash_init(struct bcma_drv_cc *cc); @@ -71,7 +75,7 @@ #else static inline int bcma_nflash_init(struct bcma_drv_cc *cc) { -@@ -82,6 +84,8 @@ extern void __exit bcma_host_pci_exit(vo +@@ -82,9 +86,21 @@ extern void __exit bcma_host_pci_exit(vo /* driver_pci.c */ u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); @@ -80,6 +84,19 @@ #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc); void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); + #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ + ++#ifdef CONFIG_BCMA_DRIVER_GPIO ++/* driver_gpio.c */ ++int bcma_gpio_init(struct bcma_drv_cc *cc); ++#else ++static inline int bcma_gpio_init(struct bcma_drv_cc *cc) ++{ ++ return -ENOTSUPP; ++} ++#endif /* CONFIG_BCMA_DRIVER_GPIO */ ++ + #endif --- a/drivers/bcma/core.c +++ b/drivers/bcma/core.c @@ -65,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma @@ -109,7 +126,7 @@ #include <linux/bcma/bcma.h> static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, -@@ -22,12 +25,93 @@ static inline u32 bcma_cc_write32_masked +@@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked return value; } @@ -206,8 +223,11 @@ + if (cc->early_setup_done) return; ++ spin_lock_init(&cc->gpio_lock); ++ if (cc->core->id.rev >= 11) -@@ -36,6 +120,22 @@ void bcma_core_chipcommon_init(struct bc + cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); + cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); if (cc->core->id.rev >= 35) cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); @@ -230,7 +250,7 @@ if (cc->core->id.rev >= 20) { bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); -@@ -56,15 +156,33 @@ void bcma_core_chipcommon_init(struct bc +@@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); } @@ -267,7 +287,110 @@ } void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) -@@ -118,8 +236,7 @@ void bcma_chipco_serial_init(struct bcma +@@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_ + + u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + ++/* ++ * If the bit is set to 0, chipcommon controlls this GPIO, ++ * if the bit is set to 1, it is used by some part of the chip and not our code. ++ */ + u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); + + u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res; ++ ++ if (cc->core->id.rev < 20) ++ return 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res; ++ ++ if (cc->core->id.rev < 20) ++ return 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + #ifdef CONFIG_BCMA_DRIVER_MIPS +@@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma struct bcma_serial_port *ports = cc->serial_ports; if (ccrev >= 11 && ccrev != 15) { @@ -325,7 +448,22 @@ } --- a/drivers/bcma/driver_chipcommon_pmu.c +++ b/drivers/bcma/driver_chipcommon_pmu.c -@@ -76,7 +76,10 @@ static void bcma_pmu_resources_init(stru +@@ -13,12 +13,13 @@ + #include <linux/export.h> + #include <linux/bcma/bcma.h> + +-static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) ++u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) + { + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); + bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); + return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); + } ++EXPORT_SYMBOL_GPL(bcma_chipco_pll_read); + + void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value) + { +@@ -76,7 +77,10 @@ static void bcma_pmu_resources_init(stru if (max_msk) bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk); @@ -337,7 +475,7 @@ mdelay(2); } -@@ -101,7 +104,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct +@@ -101,7 +105,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val); } @@ -346,7 +484,7 @@ { struct bcma_bus *bus = cc->core->bus; -@@ -141,7 +144,7 @@ void bcma_pmu_workarounds(struct bcma_dr +@@ -141,7 +145,7 @@ void bcma_pmu_workarounds(struct bcma_dr } } @@ -355,7 +493,7 @@ { u32 pmucap; -@@ -150,7 +153,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c +@@ -150,7 +154,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev, pmucap); @@ -366,7 +504,7 @@ if (cc->pmu.rev == 1) bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, ~BCMA_CC_PMU_CTL_NOILPONW); -@@ -162,7 +168,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c +@@ -162,7 +169,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c bcma_pmu_workarounds(cc); } @@ -375,7 +513,7 @@ { struct bcma_bus *bus = cc->core->bus; -@@ -190,7 +196,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c +@@ -190,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c /* Find the output of the "m" pll divider given pll controls that start with * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. */ @@ -384,7 +522,7 @@ { u32 tmp, div, ndiv, p1, p2, fc; struct bcma_bus *bus = cc->core->bus; -@@ -219,14 +225,14 @@ static u32 bcma_pmu_clock(struct bcma_dr +@@ -219,14 +226,14 @@ static u32 bcma_pmu_clock(struct bcma_dr ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; /* Do calculation in Mhz */ @@ -401,7 +539,7 @@ { u32 tmp, ndiv, p1div, p2div; u32 clock; -@@ -257,7 +263,7 @@ static u32 bcma_pmu_clock_bcm4706(struct +@@ -257,7 +264,7 @@ static u32 bcma_pmu_clock_bcm4706(struct } /* query bus clock frequency for PMU-enabled chipcommon */ @@ -410,7 +548,7 @@ { struct bcma_bus *bus = cc->core->bus; -@@ -265,40 +271,42 @@ u32 bcma_pmu_get_clockcontrol(struct bcm +@@ -265,40 +272,42 @@ u32 bcma_pmu_get_clockcontrol(struct bcm case BCMA_CHIP_ID_BCM4716: case BCMA_CHIP_ID_BCM4748: case BCMA_CHIP_ID_BCM47162: @@ -464,7 +602,7 @@ BCMA_CC_PMU4706_MAINPLL_PLL0, BCMA_CC_PMU5_MAINPLL_CPU); case BCMA_CHIP_ID_BCM5356: -@@ -313,10 +321,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr +@@ -313,10 +322,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr break; } @@ -516,7 +654,7 @@ + { "M25P40", 0x12, 0x10000, 8, }, + + { "M25P16", 0x14, 0x10000, 32, }, -+ { "M25P32", 0x14, 0x10000, 64, }, ++ { "M25P32", 0x15, 0x10000, 64, }, + { "M25P64", 0x16, 0x10000, 128, }, + { "M25FL128", 0x17, 0x10000, 256, }, + { 0 }, @@ -645,18 +783,214 @@ + return 0; } +--- /dev/null ++++ b/drivers/bcma/driver_gpio.c +@@ -0,0 +1,98 @@ ++/* ++ * Broadcom specific AMBA ++ * GPIO driver ++ * ++ * Copyright 2011, Broadcom Corporation ++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/gpio.h> ++#include <linux/export.h> ++#include <linux/bcma/bcma.h> ++ ++#include "bcma_private.h" ++ ++static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip) ++{ ++ return container_of(chip, struct bcma_drv_cc, gpio); ++} ++ ++static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ return !!bcma_chipco_gpio_in(cc, 1 << gpio); ++} ++ ++static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0); ++} ++ ++static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_outen(cc, 1 << gpio, 0); ++ return 0; ++} ++ ++static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio); ++ bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0); ++ return 0; ++} ++ ++static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_control(cc, 1 << gpio, 0); ++ /* clear pulldown */ ++ bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0); ++ /* Set pullup */ ++ bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio); ++ ++ return 0; ++} ++ ++static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ /* clear pullup */ ++ bcma_chipco_gpio_pullup(cc, 1 << gpio, 0); ++} ++ ++int bcma_gpio_init(struct bcma_drv_cc *cc) ++{ ++ struct gpio_chip *chip = &cc->gpio; ++ ++ chip->label = "bcma_gpio"; ++ chip->owner = THIS_MODULE; ++ chip->request = bcma_gpio_request; ++ chip->free = bcma_gpio_free; ++ chip->get = bcma_gpio_get_value; ++ chip->set = bcma_gpio_set_value; ++ chip->direction_input = bcma_gpio_direction_input; ++ chip->direction_output = bcma_gpio_direction_output; ++ chip->ngpio = 16; ++ /* There is just one SoC in one device and its GPIO addresses should be ++ * deterministic to address them more easily. The other buses could get ++ * a random base number. */ ++ if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) ++ chip->base = 0; ++ else ++ chip->base = -1; ++ ++ return gpiochip_add(chip); ++} --- a/drivers/bcma/driver_mips.c +++ b/drivers/bcma/driver_mips.c -@@ -115,7 +115,7 @@ static void bcma_core_mips_set_irq(struc +@@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct + return dev->core_index; + flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30); + +- return flag & 0x1F; ++ if (flag) ++ return flag & 0x1F; ++ else ++ return 0x3f; + } + + /* Get the MIPS IRQ assignment for a specified device. + * If unassigned, 0 is returned. ++ * If disabled, 5 is returned. ++ * If not supported, 6 is returned. + */ + unsigned int bcma_core_mips_irq(struct bcma_device *dev) + { +@@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b + unsigned int irq; + + irqflag = bcma_core_mips_irqflag(dev); ++ if (irqflag == 0x3f) ++ return 6; + +- for (irq = 1; irq <= 4; irq++) ++ for (irq = 0; irq <= 4; irq++) + if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) & + (1 << irqflag)) + return irq; + +- return 0; ++ return 5; + } + EXPORT_SYMBOL(bcma_core_mips_irq); + +@@ -114,8 +121,8 @@ static void bcma_core_mips_set_irq(struc + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0), bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) & ~(1 << irqflag)); - else +- else - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0); ++ else if (oldirq != 5) + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0); /* assign the new one */ if (irq == 0) { -@@ -171,7 +171,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips +@@ -123,9 +130,9 @@ static void bcma_core_mips_set_irq(struc + bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) | + (1 << irqflag)); + } else { +- u32 oldirqflag = bcma_read32(mdev, +- BCMA_MIPS_MIPS74K_INTMASK(irq)); +- if (oldirqflag) { ++ u32 irqinitmask = bcma_read32(mdev, ++ BCMA_MIPS_MIPS74K_INTMASK(irq)); ++ if (irqinitmask) { + struct bcma_device *core; + + /* backplane irq line is in use, find out who uses +@@ -133,7 +140,7 @@ static void bcma_core_mips_set_irq(struc + */ + list_for_each_entry(core, &bus->cores, list) { + if ((1 << bcma_core_mips_irqflag(core)) == +- oldirqflag) { ++ irqinitmask) { + bcma_core_mips_set_irq(core, 0); + break; + } +@@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc + 1 << irqflag); + } + +- bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n", +- dev->id.id, oldirq + 2, irq + 2); ++ bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n", ++ dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2); ++} ++ ++static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq, ++ u16 coreid, u8 unit) ++{ ++ struct bcma_device *core; ++ ++ core = bcma_find_core_unit(bus, coreid, unit); ++ if (!core) { ++ bcma_warn(bus, ++ "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n", ++ coreid, unit); ++ return; ++ } ++ ++ bcma_core_mips_set_irq(core, irq); + } + + static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq) + { + int i; + static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; +- printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); ++ printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); + for (i = 0; i <= 6; i++) + printk(" %s%s", irq_name[i], i == irq ? "*" : " "); + printk("\n"); +@@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips struct bcma_bus *bus = mcore->core->bus; if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) @@ -665,7 +999,7 @@ bcma_err(bus, "No PMU available, need this to get the cpu clock\n"); return 0; -@@ -181,47 +181,66 @@ EXPORT_SYMBOL(bcma_cpu_clock); +@@ -181,85 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock); static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore) { struct bcma_bus *bus = mcore->core->bus; @@ -731,21 +1065,88 @@ struct bcma_device *core; bus = mcore->core->bus; +- bcma_info(bus, "Initializing MIPS core...\n"); + if (mcore->setup_done) + return; -+ - bcma_info(bus, "Initializing MIPS core...\n"); - if (!mcore->setup_done) - mcore->assigned_irqs = 1; ++ bcma_debug(bus, "Initializing MIPS core...\n"); + +- /* Assign IRQs to all cores on the bus */ +- list_for_each_entry(core, &bus->cores, list) { +- int mips_irq; +- if (core->irq) +- continue; +- +- mips_irq = bcma_core_mips_irq(core); +- if (mips_irq > 4) +- core->irq = 0; +- else +- core->irq = mips_irq + 2; +- if (core->irq > 5) +- continue; +- switch (core->id.id) { +- case BCMA_CORE_PCI: +- case BCMA_CORE_PCIE: +- case BCMA_CORE_ETHERNET: +- case BCMA_CORE_ETHERNET_GBIT: +- case BCMA_CORE_MAC_GBIT: +- case BCMA_CORE_80211: +- case BCMA_CORE_USB20_HOST: +- /* These devices get their own IRQ line if available, +- * the rest goes on IRQ0 +- */ +- if (mcore->assigned_irqs <= 4) +- bcma_core_mips_set_irq(core, +- mcore->assigned_irqs++); +- break; + bcma_core_mips_early_init(mcore); + -+ mcore->assigned_irqs = 1; - - /* Assign IRQs to all cores on the bus */ - list_for_each_entry(core, &bus->cores, list) { -@@ -256,10 +275,5 @@ void bcma_core_mips_init(struct bcma_drv - bcma_info(bus, "IRQ reconfiguration done\n"); ++ switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4716: ++ case BCMA_CHIP_ID_BCM4748: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); ++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); ++ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); ++ break; ++ case BCMA_CHIP_ID_BCM5356: ++ case BCMA_CHIP_ID_BCM47162: ++ case BCMA_CHIP_ID_BCM53572: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); ++ break; ++ case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4749: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); ++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); ++ break; ++ case BCMA_CHIP_ID_BCM4706: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT, ++ 0); ++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1); ++ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON, ++ 0); ++ break; ++ default: ++ list_for_each_entry(core, &bus->cores, list) { ++ core->irq = bcma_core_mips_irq(core) + 2; + } ++ bcma_err(bus, ++ "Unknown device (0x%x) found, can not configure IRQs\n", ++ bus->chipinfo.id); + } +- bcma_info(bus, "IRQ reconfiguration done\n"); ++ bcma_debug(bus, "IRQ reconfiguration done\n"); bcma_core_mips_dump_irq(bus); - if (mcore->setup_done) @@ -972,8 +1373,8 @@ } EXPORT_SYMBOL_GPL(bcma_find_core); -+static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, -+ u8 unit) ++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, ++ u8 unit) +{ + struct bcma_device *core; + @@ -987,7 +1388,7 @@ static void bcma_release_core_dev(struct device *dev) { struct bcma_device *core = container_of(dev, struct bcma_device, dev); -@@ -136,6 +149,28 @@ static int bcma_register_cores(struct bc +@@ -136,6 +149,33 @@ static int bcma_register_cores(struct bc dev_id++; } @@ -1006,6 +1407,11 @@ + bcma_err(bus, "Error registering NAND flash\n"); + } +#endif ++ err = bcma_gpio_init(&bus->drv_cc); ++ if (err == -ENOTSUPP) ++ bcma_debug(bus, "GPIO driver not activated\n"); ++ else if (err) ++ bcma_err(bus, "Error registering GPIO driver: %i\n", err); + + if (bus->hosttype == BCMA_HOSTTYPE_SOC) { + err = bcma_chipco_watchdog_register(&bus->drv_cc); @@ -1016,7 +1422,7 @@ return 0; } -@@ -148,6 +183,8 @@ static void bcma_unregister_cores(struct +@@ -148,6 +188,8 @@ static void bcma_unregister_cores(struct if (core->dev_registered) device_unregister(&core->dev); } @@ -1025,7 +1431,7 @@ } int __devinit bcma_bus_register(struct bcma_bus *bus) -@@ -166,6 +203,20 @@ int __devinit bcma_bus_register(struct b +@@ -166,6 +208,20 @@ int __devinit bcma_bus_register(struct b return -1; } @@ -1046,7 +1452,7 @@ /* Init CC core */ core = bcma_find_core(bus, bcma_cc_core_id(bus)); if (core) { -@@ -181,10 +232,17 @@ int __devinit bcma_bus_register(struct b +@@ -181,10 +237,17 @@ int __devinit bcma_bus_register(struct b } /* Init PCIE core */ @@ -1067,7 +1473,7 @@ } /* Init GBIT MAC COMMON core */ -@@ -194,13 +252,6 @@ int __devinit bcma_bus_register(struct b +@@ -194,13 +257,6 @@ int __devinit bcma_bus_register(struct b bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn); } @@ -1081,7 +1487,7 @@ /* Register found cores */ bcma_register_cores(bus); -@@ -211,7 +262,17 @@ int __devinit bcma_bus_register(struct b +@@ -211,7 +267,17 @@ int __devinit bcma_bus_register(struct b void bcma_bus_unregister(struct bcma_bus *bus) { @@ -1099,7 +1505,7 @@ } int __init bcma_bus_early_register(struct bcma_bus *bus, -@@ -248,18 +309,18 @@ int __init bcma_bus_early_register(struc +@@ -248,18 +314,18 @@ int __init bcma_bus_early_register(struc return -1; } @@ -1187,18 +1593,27 @@ struct bcma_drv_mips drv_mips; struct bcma_drv_gmac_cmn drv_gmac_cmn; +@@ -345,6 +350,7 @@ extern void bcma_core_set_clockmode(stru + enum bcma_clkmode clkmode); + extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, + bool on); ++extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset); + #define BCMA_DMA_TRANSLATION_MASK 0xC0000000 + #define BCMA_DMA_TRANSLATION_NONE 0x00000000 + #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */ --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h -@@ -1,6 +1,8 @@ +@@ -1,6 +1,9 @@ #ifndef LINUX_BCMA_DRIVER_CC_H_ #define LINUX_BCMA_DRIVER_CC_H_ +#include <linux/platform_device.h> ++#include <linux/gpio.h> + /** ChipCommon core registers. **/ #define BCMA_CC_ID 0x0000 #define BCMA_CC_ID_ID 0x0000FFFF -@@ -100,6 +102,7 @@ +@@ -100,6 +103,7 @@ #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ @@ -1206,7 +1621,7 @@ #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ #define BCMA_CC_JCMD_START 0x80000000 #define BCMA_CC_JCMD_BUSY 0x80000000 -@@ -266,6 +269,29 @@ +@@ -266,6 +270,29 @@ #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004 #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1 #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001 @@ -1236,7 +1651,7 @@ /* 0x1E0 is defined as shared BCMA_CLKCTLST */ #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ #define BCMA_CC_UART0_DATA 0x0300 -@@ -325,6 +351,60 @@ +@@ -325,6 +352,60 @@ #define BCMA_CC_PLLCTL_ADDR 0x0660 #define BCMA_CC_PLLCTL_DATA 0x0664 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */ @@ -1297,7 +1712,7 @@ /* Divider allocation in 4716/47162/5356 */ #define BCMA_CC_PMU5_MAINPLL_CPU 1 -@@ -415,6 +495,13 @@ +@@ -415,6 +496,13 @@ /* 4313 Chip specific ChipControl register bits */ #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ @@ -1311,7 +1726,7 @@ /* Data for the PMU, if available. * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) */ -@@ -425,11 +512,35 @@ struct bcma_chipcommon_pmu { +@@ -425,11 +513,35 @@ struct bcma_chipcommon_pmu { #ifdef CONFIG_BCMA_DRIVER_MIPS struct bcma_pflash { @@ -1347,7 +1762,7 @@ struct bcma_serial_port { void *regs; unsigned long clockspeed; -@@ -445,15 +556,24 @@ struct bcma_drv_cc { +@@ -445,15 +557,30 @@ struct bcma_drv_cc { u32 capabilities; u32 capabilities_ext; u8 setup_done:1; @@ -1369,10 +1784,16 @@ #endif /* CONFIG_BCMA_DRIVER_MIPS */ + u32 ticks_per_ms; + struct platform_device *watchdog; ++ ++ /* Lock for GPIO register access. */ ++ spinlock_t gpio_lock; ++#ifdef CONFIG_BCMA_DRIVER_GPIO ++ struct gpio_chip gpio; ++#endif }; /* Register access */ -@@ -470,14 +590,14 @@ struct bcma_drv_cc { +@@ -470,14 +597,14 @@ struct bcma_drv_cc { bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); @@ -1389,7 +1810,12 @@ void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); -@@ -493,6 +613,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm +@@ -490,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d + u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); + u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); + u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); ++u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value); ++u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value); /* PMU support */ extern void bcma_pmu_init(struct bcma_drv_cc *cc); @@ -1399,12 +1825,12 @@ u32 value); --- a/include/linux/bcma/bcma_driver_mips.h +++ b/include/linux/bcma/bcma_driver_mips.h -@@ -35,13 +35,16 @@ struct bcma_device; +@@ -35,13 +35,15 @@ struct bcma_device; struct bcma_drv_mips { struct bcma_device *core; u8 setup_done:1; +- unsigned int assigned_irqs; + u8 early_setup_done:1; - unsigned int assigned_irqs; }; #ifdef CONFIG_BCMA_DRIVER_MIPS diff --git a/target/linux/generic/patches-3.7/020-ssb_update.patch b/target/linux/generic/patches-3.7/020-ssb_update.patch index 1e898c7..dec6842 100644 --- a/target/linux/generic/patches-3.7/020-ssb_update.patch +++ b/target/linux/generic/patches-3.7/020-ssb_update.patch @@ -1,3 +1,75 @@ +--- a/arch/mips/bcm47xx/nvram.c ++++ b/arch/mips/bcm47xx/nvram.c +@@ -43,8 +43,8 @@ static void early_nvram_init(void) + #ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + mcore_ssb = &bcm47xx_bus.ssb.mipscore; +- base = mcore_ssb->flash_window; +- lim = mcore_ssb->flash_window_size; ++ base = mcore_ssb->pflash.window; ++ lim = mcore_ssb->pflash.window_size; + break; + #endif + #ifdef CONFIG_BCM47XX_BCMA +--- a/arch/mips/bcm47xx/wgt634u.c ++++ b/arch/mips/bcm47xx/wgt634u.c +@@ -156,10 +156,10 @@ static int __init wgt634u_init(void) + SSB_CHIPCO_IRQ_GPIO); + } + +- wgt634u_flash_data.width = mcore->flash_buswidth; +- wgt634u_flash_resource.start = mcore->flash_window; +- wgt634u_flash_resource.end = mcore->flash_window +- + mcore->flash_window_size ++ wgt634u_flash_data.width = mcore->pflash.buswidth; ++ wgt634u_flash_resource.start = mcore->pflash.window; ++ wgt634u_flash_resource.end = mcore->pflash.window ++ + mcore->pflash.window_size + - 1; + return platform_add_devices(wgt634u_devices, + ARRAY_SIZE(wgt634u_devices)); +--- a/drivers/ssb/Kconfig ++++ b/drivers/ssb/Kconfig +@@ -136,6 +136,11 @@ config SSB_DRIVER_MIPS + + If unsure, say N + ++config SSB_SFLASH ++ bool "SSB serial flash support" ++ depends on SSB_DRIVER_MIPS && BROKEN ++ default y ++ + # Assumption: We are on embedded, if we compile the MIPS core. + config SSB_EMBEDDED + bool +@@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE + + If unsure, say N + ++config SSB_DRIVER_GPIO ++ bool "SSB GPIO driver" ++ depends on SSB && GPIOLIB ++ help ++ Driver to provide access to the GPIO pins on the bus. ++ ++ If unsure, say N ++ + endmenu +--- a/drivers/ssb/Makefile ++++ b/drivers/ssb/Makefile +@@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o + # built-in drivers + ssb-y += driver_chipcommon.o + ssb-y += driver_chipcommon_pmu.o ++ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o + ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o + ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o + ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o + ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o ++ssb-$(CONFIG_SSB_DRIVER_GPIO) += driver_gpio.o + + # b43 pci-ssb-bridge driver + # Not strictly a part of SSB, but kept here for convenience --- a/drivers/ssb/b43_pci_bridge.c +++ b/drivers/ssb/b43_pci_bridge.c @@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc @@ -26,7 +98,7 @@ #include "ssb_private.h" -@@ -280,6 +282,69 @@ static void calc_fast_powerup_delay(stru +@@ -280,10 +282,76 @@ static void calc_fast_powerup_delay(stru cc->fast_pwrup_delay = tmp; } @@ -96,7 +168,14 @@ void ssb_chipcommon_init(struct ssb_chipcommon *cc) { if (!cc->dev) -@@ -297,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip + return; /* We don't have a ChipCommon */ ++ ++ spin_lock_init(&cc->gpio_lock); ++ + if (cc->dev->id.revision >= 11) + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); + ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status); +@@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip chipco_powercontrol_init(cc); ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); calc_fast_powerup_delay(cc); @@ -108,7 +187,7 @@ } void ssb_chipco_suspend(struct ssb_chipcommon *cc) -@@ -395,10 +465,27 @@ void ssb_chipco_timing_init(struct ssb_c +@@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c } /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ @@ -139,7 +218,106 @@ } void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) -@@ -473,12 +560,7 @@ int ssb_chipco_serial_init(struct ssb_ch +@@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco + + u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + EXPORT_SYMBOL(ssb_chipco_gpio_control); + + u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res = 0; ++ ++ if (cc->dev->id.revision < 20) ++ return 0xffffffff; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res = 0; ++ ++ if (cc->dev->id.revision < 20) ++ return 0xffffffff; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + #ifdef CONFIG_SSB_SERIAL +@@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch chipco_read32(cc, SSB_CHIPCO_CORECTL) | SSB_CHIPCO_CORECTL_UARTCLK0); } else if ((ccrev >= 11) && (ccrev != 15)) { @@ -206,9 +384,30 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc) { struct ssb_bus *bus = cc->dev->bus; +--- /dev/null ++++ b/drivers/ssb/driver_chipcommon_sflash.c +@@ -0,0 +1,18 @@ ++/* ++ * Sonics Silicon Backplane ++ * ChipCommon serial flash interface ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/ssb/ssb.h> ++ ++#include "ssb_private.h" ++ ++/* Initialize serial flash access */ ++int ssb_sflash_init(struct ssb_chipcommon *cc) ++{ ++ pr_err("Serial flash support is not implemented yet!\n"); ++ ++ return -ENOTSUPP; ++} --- a/drivers/ssb/driver_extif.c +++ b/drivers/ssb/driver_extif.c -@@ -112,10 +112,30 @@ void ssb_extif_get_clockcontrol(struct s +@@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB); } @@ -238,9 +437,250 @@ extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks); + + return ticks; ++} ++ ++void ssb_extif_init(struct ssb_extif *extif) ++{ ++ if (!extif->dev) ++ return; /* We don't have a Extif core */ ++ spin_lock_init(&extif->gpio_lock); } u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask) +@@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif * + + u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value) + { +- return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0), ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&extif->gpio_lock, flags); ++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0), + mask, value); ++ spin_unlock_irqrestore(&extif->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value) + { +- return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0), ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&extif->gpio_lock, flags); ++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0), + mask, value); ++ spin_unlock_irqrestore(&extif->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value) + { +- return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&extif->gpio_lock, flags); ++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value); ++ spin_unlock_irqrestore(&extif->gpio_lock, flags); ++ ++ return res; + } + + u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value) + { +- return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value); ++ unsigned long flags; ++ u32 res = 0; ++ ++ spin_lock_irqsave(&extif->gpio_lock, flags); ++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value); ++ spin_unlock_irqrestore(&extif->gpio_lock, flags); ++ ++ return res; + } +--- /dev/null ++++ b/drivers/ssb/driver_gpio.c +@@ -0,0 +1,176 @@ ++/* ++ * Sonics Silicon Backplane ++ * GPIO driver ++ * ++ * Copyright 2011, Broadcom Corporation ++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/gpio.h> ++#include <linux/export.h> ++#include <linux/ssb/ssb.h> ++ ++#include "ssb_private.h" ++ ++static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip) ++{ ++ return container_of(chip, struct ssb_bus, gpio); ++} ++ ++static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio); ++} ++ ++static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0); ++} ++ ++static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip, ++ unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0); ++ return 0; ++} ++ ++static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip, ++ unsigned gpio, int value) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio); ++ ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0); ++ return 0; ++} ++ ++static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0); ++ /* clear pulldown */ ++ ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0); ++ /* Set pullup */ ++ ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio); ++ ++ return 0; ++} ++ ++static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ /* clear pullup */ ++ ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0); ++} ++ ++static int ssb_gpio_chipco_init(struct ssb_bus *bus) ++{ ++ struct gpio_chip *chip = &bus->gpio; ++ ++ chip->label = "ssb_chipco_gpio"; ++ chip->owner = THIS_MODULE; ++ chip->request = ssb_gpio_chipco_request; ++ chip->free = ssb_gpio_chipco_free; ++ chip->get = ssb_gpio_chipco_get_value; ++ chip->set = ssb_gpio_chipco_set_value; ++ chip->direction_input = ssb_gpio_chipco_direction_input; ++ chip->direction_output = ssb_gpio_chipco_direction_output; ++ chip->ngpio = 16; ++ /* There is just one SoC in one device and its GPIO addresses should be ++ * deterministic to address them more easily. The other buses could get ++ * a random base number. */ ++ if (bus->bustype == SSB_BUSTYPE_SSB) ++ chip->base = 0; ++ else ++ chip->base = -1; ++ ++ return gpiochip_add(chip); ++} ++ ++#ifdef CONFIG_SSB_DRIVER_EXTIF ++ ++static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio); ++} ++ ++static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0); ++} ++ ++static int ssb_gpio_extif_direction_input(struct gpio_chip *chip, ++ unsigned gpio) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0); ++ return 0; ++} ++ ++static int ssb_gpio_extif_direction_output(struct gpio_chip *chip, ++ unsigned gpio, int value) ++{ ++ struct ssb_bus *bus = ssb_gpio_get_bus(chip); ++ ++ ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio); ++ ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0); ++ return 0; ++} ++ ++static int ssb_gpio_extif_init(struct ssb_bus *bus) ++{ ++ struct gpio_chip *chip = &bus->gpio; ++ ++ chip->label = "ssb_extif_gpio"; ++ chip->owner = THIS_MODULE; ++ chip->get = ssb_gpio_extif_get_value; ++ chip->set = ssb_gpio_extif_set_value; ++ chip->direction_input = ssb_gpio_extif_direction_input; ++ chip->direction_output = ssb_gpio_extif_direction_output; ++ chip->ngpio = 5; ++ /* There is just one SoC in one device and its GPIO addresses should be ++ * deterministic to address them more easily. The other buses could get ++ * a random base number. */ ++ if (bus->bustype == SSB_BUSTYPE_SSB) ++ chip->base = 0; ++ else ++ chip->base = -1; ++ ++ return gpiochip_add(chip); ++} ++ ++#else ++static int ssb_gpio_extif_init(struct ssb_bus *bus) ++{ ++ return -ENOTSUPP; ++} ++#endif ++ ++int ssb_gpio_init(struct ssb_bus *bus) ++{ ++ if (ssb_chipco_available(&bus->chipco)) ++ return ssb_gpio_chipco_init(bus); ++ else if (ssb_extif_available(&bus->extif)) ++ return ssb_gpio_extif_init(bus); ++ else ++ SSB_WARN_ON(1); ++ ++ return -1; ++} --- a/drivers/ssb/driver_mipscore.c +++ b/drivers/ssb/driver_mipscore.c @@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct @@ -271,7 +711,13 @@ return; } -@@ -206,13 +207,14 @@ static void ssb_mips_flash_detect(struct +@@ -202,17 +203,19 @@ static void ssb_mips_flash_detect(struct + switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) { + case SSB_CHIPCO_FLASHT_STSER: + case SSB_CHIPCO_FLASHT_ATSER: +- pr_err("Serial flash not supported\n"); ++ pr_debug("Found serial flash\n"); ++ ssb_sflash_init(&bus->chipco); break; case SSB_CHIPCO_FLASHT_PARA: pr_debug("Found parallel flash\n"); @@ -290,7 +736,7 @@ break; } } -@@ -225,9 +227,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m +@@ -225,9 +228,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU) return ssb_pmu_get_cpu_clock(&bus->chipco); @@ -302,7 +748,7 @@ ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m); } else return 0; -@@ -263,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipsco +@@ -263,9 +266,9 @@ void ssb_mipscore_init(struct ssb_mipsco hz = 100000000; ns = 1000000000 / hz; @@ -401,7 +847,22 @@ ssb_bus_may_powerdown(bus); err = ssb_devices_register(bus); -@@ -1118,8 +1126,7 @@ static u32 ssb_tmslow_reject_bitmask(str +@@ -796,7 +804,14 @@ static int __devinit ssb_bus_register(st + if (err) + goto err_pcmcia_exit; + ssb_chipcommon_init(&bus->chipco); ++ ssb_extif_init(&bus->extif); + ssb_mipscore_init(&bus->mipscore); ++ err = ssb_gpio_init(bus); ++ if (err == -ENOTSUPP) ++ ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n"); ++ else if (err) ++ ssb_dprintk(KERN_ERR PFX ++ "Error registering GPIO driver: %i\n", err); + err = ssb_fetch_invariants(bus, get_invariants); + if (err) { + ssb_bus_may_powerdown(bus); +@@ -1118,8 +1133,7 @@ static u32 ssb_tmslow_reject_bitmask(str case SSB_IDLOW_SSBREV_27: /* same here */ return SSB_TMSLOW_REJECT; /* this is a guess */ default: @@ -421,7 +882,7 @@ #define PFX "ssb: " -@@ -210,5 +211,35 @@ static inline void b43_pci_ssb_bridge_ex +@@ -210,5 +211,63 @@ static inline void b43_pci_ssb_bridge_ex /* driver_chipcommon_pmu.c */ extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc); extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc); @@ -431,6 +892,17 @@ + u32 ticks); +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); + ++/* driver_chipcommon_sflash.c */ ++#ifdef CONFIG_SSB_SFLASH ++int ssb_sflash_init(struct ssb_chipcommon *cc); ++#else ++static inline int ssb_sflash_init(struct ssb_chipcommon *cc) ++{ ++ pr_err("Serial flash not supported\n"); ++ return 0; ++} ++#endif /* CONFIG_SSB_SFLASH */ ++ +#ifdef CONFIG_SSB_DRIVER_EXTIF +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks); +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms); @@ -455,38 +927,64 @@ + return 0; +} +#endif /* CONFIG_SSB_EMBEDDED */ ++ ++#ifdef CONFIG_SSB_DRIVER_EXTIF ++extern void ssb_extif_init(struct ssb_extif *extif); ++#else ++static inline void ssb_extif_init(struct ssb_extif *extif) ++{ ++} ++#endif ++ ++#ifdef CONFIG_SSB_DRIVER_GPIO ++extern int ssb_gpio_init(struct ssb_bus *bus); ++#else /* CONFIG_SSB_DRIVER_GPIO */ ++static inline int ssb_gpio_init(struct ssb_bus *bus) ++{ ++ return -ENOTSUPP; ++} ++#endif /* CONFIG_SSB_DRIVER_GPIO */ #endif /* LINUX_SSB_PRIVATE_H_ */ --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h -@@ -8,6 +8,7 @@ +@@ -6,8 +6,10 @@ + #include <linux/types.h> + #include <linux/spinlock.h> #include <linux/pci.h> ++#include <linux/gpio.h> #include <linux/mod_devicetable.h> #include <linux/dma-mapping.h> +#include <linux/platform_device.h> #include <linux/ssb/ssb_regs.h> -@@ -432,6 +433,7 @@ struct ssb_bus { +@@ -432,7 +434,11 @@ struct ssb_bus { #ifdef CONFIG_SSB_EMBEDDED /* Lock for GPIO register access. */ spinlock_t gpio_lock; + struct platform_device *watchdog; #endif /* EMBEDDED */ ++#ifdef CONFIG_SSB_DRIVER_GPIO ++ struct gpio_chip gpio; ++#endif /* DRIVER_GPIO */ /* Internal-only stuff follows. Do not touch. */ + struct list_head list; --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h -@@ -591,6 +591,8 @@ struct ssb_chipcommon { +@@ -590,7 +590,10 @@ struct ssb_chipcommon { + u32 status; /* Fast Powerup Delay constant */ u16 fast_pwrup_delay; ++ spinlock_t gpio_lock; struct ssb_chipcommon_pmu pmu; + u32 ticks_per_ms; + u32 max_timer_ms; }; static inline bool ssb_chipco_available(struct ssb_chipcommon *cc) -@@ -630,8 +632,7 @@ enum ssb_clkmode { +@@ -630,8 +633,7 @@ enum ssb_clkmode { extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, enum ssb_clkmode mode); @@ -496,9 +994,18 @@ void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value); +@@ -644,6 +646,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi + u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value); + u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value); + u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value); ++u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value); ++u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value); + + #ifdef CONFIG_SSB_SERIAL + extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc, --- a/include/linux/ssb/ssb_driver_extif.h +++ b/include/linux/ssb/ssb_driver_extif.h -@@ -152,6 +152,9 @@ +@@ -152,12 +152,16 @@ /* watchdog */ #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */ @@ -508,7 +1015,14 @@ #ifdef CONFIG_SSB_DRIVER_EXTIF -@@ -171,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s + + struct ssb_extif { + struct ssb_device *dev; ++ spinlock_t gpio_lock; + }; + + static inline bool ssb_extif_available(struct ssb_extif *extif) +@@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s extern void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns); @@ -518,7 +1032,7 @@ /* Extif GPIO pin access */ u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask); -@@ -205,10 +207,52 @@ void ssb_extif_get_clockcontrol(struct s +@@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s } static inline @@ -610,3 +1124,25 @@ #define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff #define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0 #define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00 +--- /dev/null ++++ b/include/linux/bcm47xx_wdt.h +@@ -0,0 +1,19 @@ ++#ifndef LINUX_BCM47XX_WDT_H_ ++#define LINUX_BCM47XX_WDT_H_ ++ ++#include <linux/types.h> ++ ++ ++struct bcm47xx_wdt { ++ u32 (*timer_set)(struct bcm47xx_wdt *, u32); ++ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32); ++ u32 max_timer_ms; ++ ++ void *driver_data; ++}; ++ ++static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt) ++{ ++ return wdt->driver_data; ++} ++#endif /* LINUX_BCM47XX_WDT_H_ */ diff --git a/target/linux/generic/patches-3.7/021-ssb_bcma_watchdog_header.patch b/target/linux/generic/patches-3.7/021-ssb_bcma_watchdog_header.patch deleted file mode 100644 index 18feeab..0000000 --- a/target/linux/generic/patches-3.7/021-ssb_bcma_watchdog_header.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- /dev/null -+++ b/include/linux/bcm47xx_wdt.h -@@ -0,0 +1,19 @@ -+#ifndef LINUX_BCM47XX_WDT_H_ -+#define LINUX_BCM47XX_WDT_H_ -+ -+#include <linux/types.h> -+ -+ -+struct bcm47xx_wdt { -+ u32 (*timer_set)(struct bcm47xx_wdt *, u32); -+ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32); -+ u32 max_timer_ms; -+ -+ void *driver_data; -+}; -+ -+static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt) -+{ -+ return wdt->driver_data; -+} -+#endif /* LINUX_BCM47XX_WDT_H_ */ diff --git a/target/linux/generic/patches-3.7/025-bcma_backport.patch b/target/linux/generic/patches-3.7/025-bcma_backport.patch index 3228ff1..c4f27d1 100644 --- a/target/linux/generic/patches-3.7/025-bcma_backport.patch +++ b/target/linux/generic/patches-3.7/025-bcma_backport.patch @@ -1,36 +1,42 @@ ---- a/arch/mips/bcm47xx/nvram.c -+++ b/arch/mips/bcm47xx/nvram.c -@@ -43,8 +43,8 @@ static void early_nvram_init(void) - #ifdef CONFIG_BCM47XX_SSB - case BCM47XX_BUS_TYPE_SSB: - mcore_ssb = &bcm47xx_bus.ssb.mipscore; -- base = mcore_ssb->flash_window; -- lim = mcore_ssb->flash_window_size; -+ base = mcore_ssb->pflash.window; -+ lim = mcore_ssb->pflash.window_size; - break; - #endif - #ifdef CONFIG_BCM47XX_BCMA ---- a/arch/mips/bcm47xx/wgt634u.c -+++ b/arch/mips/bcm47xx/wgt634u.c -@@ -156,10 +156,10 @@ static int __init wgt634u_init(void) - SSB_CHIPCO_IRQ_GPIO); - } +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -65,6 +65,14 @@ config BCMA_DRIVER_GMAC_CMN -- wgt634u_flash_data.width = mcore->flash_buswidth; -- wgt634u_flash_resource.start = mcore->flash_window; -- wgt634u_flash_resource.end = mcore->flash_window -- + mcore->flash_window_size -+ wgt634u_flash_data.width = mcore->pflash.buswidth; -+ wgt634u_flash_resource.start = mcore->pflash.window; -+ wgt634u_flash_resource.end = mcore->pflash.window -+ + mcore->pflash.window_size - - 1; - return platform_add_devices(wgt634u_devices, - ARRAY_SIZE(wgt634u_devices)); + If unsure, say N + ++config BCMA_DRIVER_GPIO ++ bool "BCMA GPIO driver" ++ depends on BCMA && GPIOLIB ++ help ++ Driver to provide access to the GPIO pins of the bcma bus. ++ ++ If unsure, say N ++ + config BCMA_DEBUG + bool "BCMA debugging" + depends on BCMA +--- a/drivers/bcma/Makefile ++++ b/drivers/bcma/Makefile +@@ -6,6 +6,7 @@ bcma-y += driver_pci.o + bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o + bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o + bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o ++bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o + bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o + bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o + obj-$(CONFIG_BCMA) += bcma.o --- a/drivers/bcma/bcma_private.h +++ b/drivers/bcma/bcma_private.h -@@ -48,8 +48,8 @@ void bcma_chipco_serial_init(struct bcma +@@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc + int bcma_bus_suspend(struct bcma_bus *bus); + int bcma_bus_resume(struct bcma_bus *bus); + #endif ++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, ++ u8 unit); + + /* scan.c */ + int bcma_bus_scan(struct bcma_bus *bus); +@@ -48,8 +50,8 @@ void bcma_chipco_serial_init(struct bcma #endif /* CONFIG_BCMA_DRIVER_MIPS */ /* driver_chipcommon_pmu.c */ @@ -41,7 +47,7 @@ #ifdef CONFIG_BCMA_SFLASH /* driver_chipcommon_sflash.c */ -@@ -84,6 +84,8 @@ extern void __exit bcma_host_pci_exit(vo +@@ -84,9 +86,21 @@ extern void __exit bcma_host_pci_exit(vo /* driver_pci.c */ u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); @@ -50,6 +56,19 @@ #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc); void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); + #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ + ++#ifdef CONFIG_BCMA_DRIVER_GPIO ++/* driver_gpio.c */ ++int bcma_gpio_init(struct bcma_drv_cc *cc); ++#else ++static inline int bcma_gpio_init(struct bcma_drv_cc *cc) ++{ ++ return -ENOTSUPP; ++} ++#endif /* CONFIG_BCMA_DRIVER_GPIO */ ++ + #endif --- a/drivers/bcma/driver_chipcommon.c +++ b/drivers/bcma/driver_chipcommon.c @@ -4,12 +4,15 @@ @@ -68,7 +87,7 @@ #include <linux/bcma/bcma.h> static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, -@@ -22,12 +25,93 @@ static inline u32 bcma_cc_write32_masked +@@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked return value; } @@ -165,8 +184,11 @@ + if (cc->early_setup_done) return; ++ spin_lock_init(&cc->gpio_lock); ++ if (cc->core->id.rev >= 11) -@@ -36,6 +120,22 @@ void bcma_core_chipcommon_init(struct bc + cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); + cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); if (cc->core->id.rev >= 35) cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); @@ -189,7 +211,7 @@ if (cc->core->id.rev >= 20) { bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); -@@ -56,15 +156,33 @@ void bcma_core_chipcommon_init(struct bc +@@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); } @@ -226,7 +248,110 @@ } void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) -@@ -118,8 +236,7 @@ void bcma_chipco_serial_init(struct bcma +@@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_ + + u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + ++/* ++ * If the bit is set to 0, chipcommon controlls this GPIO, ++ * if the bit is set to 1, it is used by some part of the chip and not our code. ++ */ + u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); + + u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) + { +- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); ++ unsigned long flags; ++ u32 res; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res; ++ ++ if (cc->core->id.rev < 20) ++ return 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; ++} ++ ++u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) ++{ ++ unsigned long flags; ++ u32 res; ++ ++ if (cc->core->id.rev < 20) ++ return 0; ++ ++ spin_lock_irqsave(&cc->gpio_lock, flags); ++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value); ++ spin_unlock_irqrestore(&cc->gpio_lock, flags); ++ ++ return res; + } + + #ifdef CONFIG_BCMA_DRIVER_MIPS +@@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma struct bcma_serial_port *ports = cc->serial_ports; if (ccrev >= 11 && ccrev != 15) { @@ -250,7 +375,22 @@ * malloc (required by device_private_init) is not available yet. */ --- a/drivers/bcma/driver_chipcommon_pmu.c +++ b/drivers/bcma/driver_chipcommon_pmu.c -@@ -144,7 +144,7 @@ static void bcma_pmu_workarounds(struct +@@ -13,12 +13,13 @@ + #include <linux/export.h> + #include <linux/bcma/bcma.h> + +-static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) ++u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) + { + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); + bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); + return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); + } ++EXPORT_SYMBOL_GPL(bcma_chipco_pll_read); + + void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value) + { +@@ -144,7 +145,7 @@ static void bcma_pmu_workarounds(struct } } @@ -259,7 +399,7 @@ { u32 pmucap; -@@ -153,7 +153,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c +@@ -153,7 +154,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev, pmucap); @@ -270,7 +410,7 @@ if (cc->pmu.rev == 1) bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, ~BCMA_CC_PMU_CTL_NOILPONW); -@@ -165,7 +168,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c +@@ -165,7 +169,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c bcma_pmu_workarounds(cc); } @@ -279,7 +419,7 @@ { struct bcma_bus *bus = cc->core->bus; -@@ -193,7 +196,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c +@@ -193,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c /* Find the output of the "m" pll divider given pll controls that start with * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. */ @@ -288,7 +428,7 @@ { u32 tmp, div, ndiv, p1, p2, fc; struct bcma_bus *bus = cc->core->bus; -@@ -222,14 +225,14 @@ static u32 bcma_pmu_clock(struct bcma_dr +@@ -222,14 +226,14 @@ static u32 bcma_pmu_clock(struct bcma_dr ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; /* Do calculation in Mhz */ @@ -305,7 +445,7 @@ { u32 tmp, ndiv, p1div, p2div; u32 clock; -@@ -260,7 +263,7 @@ static u32 bcma_pmu_clock_bcm4706(struct +@@ -260,7 +264,7 @@ static u32 bcma_pmu_clock_bcm4706(struct } /* query bus clock frequency for PMU-enabled chipcommon */ @@ -314,7 +454,7 @@ { struct bcma_bus *bus = cc->core->bus; -@@ -268,40 +271,42 @@ static u32 bcma_pmu_get_clockcontrol(str +@@ -268,40 +272,42 @@ static u32 bcma_pmu_get_clockcontrol(str case BCMA_CHIP_ID_BCM4716: case BCMA_CHIP_ID_BCM4748: case BCMA_CHIP_ID_BCM47162: @@ -368,7 +508,7 @@ BCMA_CC_PMU4706_MAINPLL_PLL0, BCMA_CC_PMU5_MAINPLL_CPU); case BCMA_CHIP_ID_BCM5356: -@@ -316,10 +321,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr +@@ -316,10 +322,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr break; } @@ -402,7 +542,7 @@ + { "M25P40", 0x12, 0x10000, 8, }, + + { "M25P16", 0x14, 0x10000, 32, }, -+ { "M25P32", 0x14, 0x10000, 64, }, ++ { "M25P32", 0x15, 0x10000, 64, }, + { "M25P64", 0x16, 0x10000, 128, }, + { "M25FL128", 0x17, 0x10000, 256, }, { 0 }, @@ -455,18 +595,214 @@ sflash->blocksize = e->blocksize; sflash->numblocks = e->numblocks; sflash->size = sflash->blocksize * sflash->numblocks; +--- /dev/null ++++ b/drivers/bcma/driver_gpio.c +@@ -0,0 +1,98 @@ ++/* ++ * Broadcom specific AMBA ++ * GPIO driver ++ * ++ * Copyright 2011, Broadcom Corporation ++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include <linux/gpio.h> ++#include <linux/export.h> ++#include <linux/bcma/bcma.h> ++ ++#include "bcma_private.h" ++ ++static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip) ++{ ++ return container_of(chip, struct bcma_drv_cc, gpio); ++} ++ ++static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ return !!bcma_chipco_gpio_in(cc, 1 << gpio); ++} ++ ++static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0); ++} ++ ++static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_outen(cc, 1 << gpio, 0); ++ return 0; ++} ++ ++static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, ++ int value) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio); ++ bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0); ++ return 0; ++} ++ ++static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ bcma_chipco_gpio_control(cc, 1 << gpio, 0); ++ /* clear pulldown */ ++ bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0); ++ /* Set pullup */ ++ bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio); ++ ++ return 0; ++} ++ ++static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio) ++{ ++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); ++ ++ /* clear pullup */ ++ bcma_chipco_gpio_pullup(cc, 1 << gpio, 0); ++} ++ ++int bcma_gpio_init(struct bcma_drv_cc *cc) ++{ ++ struct gpio_chip *chip = &cc->gpio; ++ ++ chip->label = "bcma_gpio"; ++ chip->owner = THIS_MODULE; ++ chip->request = bcma_gpio_request; ++ chip->free = bcma_gpio_free; ++ chip->get = bcma_gpio_get_value; ++ chip->set = bcma_gpio_set_value; ++ chip->direction_input = bcma_gpio_direction_input; ++ chip->direction_output = bcma_gpio_direction_output; ++ chip->ngpio = 16; ++ /* There is just one SoC in one device and its GPIO addresses should be ++ * deterministic to address them more easily. The other buses could get ++ * a random base number. */ ++ if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) ++ chip->base = 0; ++ else ++ chip->base = -1; ++ ++ return gpiochip_add(chip); ++} --- a/drivers/bcma/driver_mips.c +++ b/drivers/bcma/driver_mips.c -@@ -115,7 +115,7 @@ static void bcma_core_mips_set_irq(struc +@@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct + return dev->core_index; + flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30); + +- return flag & 0x1F; ++ if (flag) ++ return flag & 0x1F; ++ else ++ return 0x3f; + } + + /* Get the MIPS IRQ assignment for a specified device. + * If unassigned, 0 is returned. ++ * If disabled, 5 is returned. ++ * If not supported, 6 is returned. + */ + unsigned int bcma_core_mips_irq(struct bcma_device *dev) + { +@@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b + unsigned int irq; + + irqflag = bcma_core_mips_irqflag(dev); ++ if (irqflag == 0x3f) ++ return 6; + +- for (irq = 1; irq <= 4; irq++) ++ for (irq = 0; irq <= 4; irq++) + if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) & + (1 << irqflag)) + return irq; + +- return 0; ++ return 5; + } + EXPORT_SYMBOL(bcma_core_mips_irq); + +@@ -114,8 +121,8 @@ static void bcma_core_mips_set_irq(struc + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0), bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) & ~(1 << irqflag)); - else +- else - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0); ++ else if (oldirq != 5) + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0); /* assign the new one */ if (irq == 0) { -@@ -171,7 +171,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips +@@ -123,9 +130,9 @@ static void bcma_core_mips_set_irq(struc + bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) | + (1 << irqflag)); + } else { +- u32 oldirqflag = bcma_read32(mdev, +- BCMA_MIPS_MIPS74K_INTMASK(irq)); +- if (oldirqflag) { ++ u32 irqinitmask = bcma_read32(mdev, ++ BCMA_MIPS_MIPS74K_INTMASK(irq)); ++ if (irqinitmask) { + struct bcma_device *core; + + /* backplane irq line is in use, find out who uses +@@ -133,7 +140,7 @@ static void bcma_core_mips_set_irq(struc + */ + list_for_each_entry(core, &bus->cores, list) { + if ((1 << bcma_core_mips_irqflag(core)) == +- oldirqflag) { ++ irqinitmask) { + bcma_core_mips_set_irq(core, 0); + break; + } +@@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc + 1 << irqflag); + } + +- bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n", +- dev->id.id, oldirq + 2, irq + 2); ++ bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n", ++ dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2); ++} ++ ++static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq, ++ u16 coreid, u8 unit) ++{ ++ struct bcma_device *core; ++ ++ core = bcma_find_core_unit(bus, coreid, unit); ++ if (!core) { ++ bcma_warn(bus, ++ "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n", ++ coreid, unit); ++ return; ++ } ++ ++ bcma_core_mips_set_irq(core, irq); + } + + static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq) + { + int i; + static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; +- printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); ++ printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); + for (i = 0; i <= 6; i++) + printk(" %s%s", irq_name[i], i == irq ? "*" : " "); + printk("\n"); +@@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips struct bcma_bus *bus = mcore->core->bus; if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) @@ -475,7 +811,7 @@ bcma_err(bus, "No PMU available, need this to get the cpu clock\n"); return 0; -@@ -181,47 +181,66 @@ EXPORT_SYMBOL(bcma_cpu_clock); +@@ -181,85 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock); static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore) { struct bcma_bus *bus = mcore->core->bus; @@ -541,21 +877,88 @@ struct bcma_device *core; bus = mcore->core->bus; +- bcma_info(bus, "Initializing MIPS core...\n"); + if (mcore->setup_done) + return; -+ - bcma_info(bus, "Initializing MIPS core...\n"); - if (!mcore->setup_done) - mcore->assigned_irqs = 1; ++ bcma_debug(bus, "Initializing MIPS core...\n"); + +- /* Assign IRQs to all cores on the bus */ +- list_for_each_entry(core, &bus->cores, list) { +- int mips_irq; +- if (core->irq) +- continue; +- +- mips_irq = bcma_core_mips_irq(core); +- if (mips_irq > 4) +- core->irq = 0; +- else +- core->irq = mips_irq + 2; +- if (core->irq > 5) +- continue; +- switch (core->id.id) { +- case BCMA_CORE_PCI: +- case BCMA_CORE_PCIE: +- case BCMA_CORE_ETHERNET: +- case BCMA_CORE_ETHERNET_GBIT: +- case BCMA_CORE_MAC_GBIT: +- case BCMA_CORE_80211: +- case BCMA_CORE_USB20_HOST: +- /* These devices get their own IRQ line if available, +- * the rest goes on IRQ0 +- */ +- if (mcore->assigned_irqs <= 4) +- bcma_core_mips_set_irq(core, +- mcore->assigned_irqs++); +- break; + bcma_core_mips_early_init(mcore); + -+ mcore->assigned_irqs = 1; - - /* Assign IRQs to all cores on the bus */ - list_for_each_entry(core, &bus->cores, list) { -@@ -256,10 +275,5 @@ void bcma_core_mips_init(struct bcma_drv - bcma_info(bus, "IRQ reconfiguration done\n"); ++ switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4716: ++ case BCMA_CHIP_ID_BCM4748: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); ++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); ++ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); ++ break; ++ case BCMA_CHIP_ID_BCM5356: ++ case BCMA_CHIP_ID_BCM47162: ++ case BCMA_CHIP_ID_BCM53572: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); ++ break; ++ case BCMA_CHIP_ID_BCM5357: ++ case BCMA_CHIP_ID_BCM4749: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); ++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); ++ break; ++ case BCMA_CHIP_ID_BCM4706: ++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0); ++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT, ++ 0); ++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1); ++ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0); ++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON, ++ 0); ++ break; ++ default: ++ list_for_each_entry(core, &bus->cores, list) { ++ core->irq = bcma_core_mips_irq(core) + 2; + } ++ bcma_err(bus, ++ "Unknown device (0x%x) found, can not configure IRQs\n", ++ bus->chipinfo.id); + } +- bcma_info(bus, "IRQ reconfiguration done\n"); ++ bcma_debug(bus, "IRQ reconfiguration done\n"); bcma_core_mips_dump_irq(bus); - if (mcore->setup_done) @@ -664,8 +1067,8 @@ } EXPORT_SYMBOL_GPL(bcma_find_core); -+static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, -+ u8 unit) ++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, ++ u8 unit) +{ + struct bcma_device *core; + @@ -679,20 +1082,25 @@ static void bcma_release_core_dev(struct device *dev) { struct bcma_device *core = container_of(dev, struct bcma_device, dev); -@@ -153,6 +165,12 @@ static int bcma_register_cores(struct bc +@@ -152,6 +164,17 @@ static int bcma_register_cores(struct bc + bcma_err(bus, "Error registering NAND flash\n"); } #endif - ++ err = bcma_gpio_init(&bus->drv_cc); ++ if (err == -ENOTSUPP) ++ bcma_debug(bus, "GPIO driver not activated\n"); ++ else if (err) ++ bcma_err(bus, "Error registering GPIO driver: %i\n", err); ++ + if (bus->hosttype == BCMA_HOSTTYPE_SOC) { + err = bcma_chipco_watchdog_register(&bus->drv_cc); + if (err) + bcma_err(bus, "Error registering watchdog driver\n"); + } -+ + return 0; } - -@@ -165,6 +183,8 @@ static void bcma_unregister_cores(struct +@@ -165,6 +188,8 @@ static void bcma_unregister_cores(struct if (core->dev_registered) device_unregister(&core->dev); } @@ -701,7 +1109,7 @@ } int __devinit bcma_bus_register(struct bcma_bus *bus) -@@ -183,6 +203,20 @@ int __devinit bcma_bus_register(struct b +@@ -183,6 +208,20 @@ int __devinit bcma_bus_register(struct b return -1; } @@ -722,7 +1130,7 @@ /* Init CC core */ core = bcma_find_core(bus, bcma_cc_core_id(bus)); if (core) { -@@ -198,10 +232,17 @@ int __devinit bcma_bus_register(struct b +@@ -198,10 +237,17 @@ int __devinit bcma_bus_register(struct b } /* Init PCIE core */ @@ -743,7 +1151,7 @@ } /* Init GBIT MAC COMMON core */ -@@ -211,13 +252,6 @@ int __devinit bcma_bus_register(struct b +@@ -211,13 +257,6 @@ int __devinit bcma_bus_register(struct b bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn); } @@ -757,7 +1165,7 @@ /* Register found cores */ bcma_register_cores(bus); -@@ -275,18 +309,18 @@ int __init bcma_bus_early_register(struc +@@ -275,18 +314,18 @@ int __init bcma_bus_early_register(struc return -1; } @@ -826,18 +1234,27 @@ struct bcma_drv_mips drv_mips; struct bcma_drv_gmac_cmn drv_gmac_cmn; +@@ -345,6 +350,7 @@ extern void bcma_core_set_clockmode(stru + enum bcma_clkmode clkmode); + extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, + bool on); ++extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset); + #define BCMA_DMA_TRANSLATION_MASK 0xC0000000 + #define BCMA_DMA_TRANSLATION_NONE 0x00000000 + #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */ --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h -@@ -1,6 +1,8 @@ +@@ -1,6 +1,9 @@ #ifndef LINUX_BCMA_DRIVER_CC_H_ #define LINUX_BCMA_DRIVER_CC_H_ +#include <linux/platform_device.h> ++#include <linux/gpio.h> + /** ChipCommon core registers. **/ #define BCMA_CC_ID 0x0000 #define BCMA_CC_ID_ID 0x0000FFFF -@@ -510,6 +512,7 @@ struct bcma_chipcommon_pmu { +@@ -510,6 +513,7 @@ struct bcma_chipcommon_pmu { #ifdef CONFIG_BCMA_DRIVER_MIPS struct bcma_pflash { @@ -845,7 +1262,7 @@ u8 buswidth; u32 window; u32 window_size; -@@ -532,6 +535,7 @@ struct mtd_info; +@@ -532,6 +536,7 @@ struct mtd_info; struct bcma_nflash { bool present; @@ -853,7 +1270,7 @@ struct mtd_info *mtd; }; -@@ -552,6 +556,7 @@ struct bcma_drv_cc { +@@ -552,6 +557,7 @@ struct bcma_drv_cc { u32 capabilities; u32 capabilities_ext; u8 setup_done:1; @@ -861,16 +1278,22 @@ /* Fast Powerup Delay constant */ u16 fast_pwrup_delay; struct bcma_chipcommon_pmu pmu; -@@ -567,6 +572,8 @@ struct bcma_drv_cc { +@@ -567,6 +573,14 @@ struct bcma_drv_cc { int nr_serial_ports; struct bcma_serial_port serial_ports[4]; #endif /* CONFIG_BCMA_DRIVER_MIPS */ + u32 ticks_per_ms; + struct platform_device *watchdog; ++ ++ /* Lock for GPIO register access. */ ++ spinlock_t gpio_lock; ++#ifdef CONFIG_BCMA_DRIVER_GPIO ++ struct gpio_chip gpio; ++#endif }; /* Register access */ -@@ -583,14 +590,14 @@ struct bcma_drv_cc { +@@ -583,14 +597,14 @@ struct bcma_drv_cc { bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); @@ -887,7 +1310,12 @@ void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); -@@ -606,6 +613,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm +@@ -603,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d + u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); + u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); + u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); ++u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value); ++u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value); /* PMU support */ extern void bcma_pmu_init(struct bcma_drv_cc *cc); @@ -897,12 +1325,12 @@ u32 value); --- a/include/linux/bcma/bcma_driver_mips.h +++ b/include/linux/bcma/bcma_driver_mips.h -@@ -35,13 +35,16 @@ struct bcma_device; +@@ -35,13 +35,15 @@ struct bcma_device; struct bcma_drv_mips { struct bcma_device *core; u8 setup_done:1; +- unsigned int assigned_irqs; + u8 early_setup_done:1; - unsigned int assigned_irqs; }; #ifdef CONFIG_BCMA_DRIVER_MIPS |