| Commit message (Collapse) | Author | Age | Files | Lines |
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Also remove the old UART driver for ar933x.
SVN-Revision: 27314
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SVN-Revision: 27310
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SVN-Revision: 27222
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SVN-Revision: 27166
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Signed-off-by: Jonas Gorski <jonas.gorski+openwrt@gmail.com>
SVN-Revision: 27102
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It messes up the DMA state when the link goes down
SVN-Revision: 27088
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SVN-Revision: 27065
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SVN-Revision: 27060
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Newer WRT160NLs have a flash chip with 4K erase blocks instead of 64K,
resulting in miscalculated partition sizes.
Since the actual sizes did not change, hardcode them to their current
sizes, and make sure they are at least one erase block big (in case Cisco
decides to start to use chips with 128K erase blocks).
Signed-off-by: Jonas Gorski <jonas.gorski+openwrt@gmail.com>
SVN-Revision: 27049
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SVN-Revision: 27041
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SVN-Revision: 27040
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Reported-by: Dave Täht <dave.taht@gmail.com>
SVN-Revision: 27039
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condition that got rx stuck when the interface is brought up during lots of inbound traffic (thx, matteo)
SVN-Revision: 27035
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continously sending MAC pause frames
SVN-Revision: 27034
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SVN-Revision: 26922
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SVN-Revision: 26890
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Reading of the PHY registers occasionally returns with bogus values
under heavy load. This misleads the PHY driver and thus causes false
link/speed change notifications which leads to performance loss.
This is easily noticable during an iperf session:
...
[ 3] 52.0-53.0 sec 11.3 MBytes 94.4 Mbits/sec
[ 3] 53.0-54.0 sec 11.4 MBytes 95.4 Mbits/sec
eth1: link down
br-lan: port 2(eth1) entering forwarding state
eth1: link up (100Mbps/Full duplex)
br-lan: port 2(eth1) entering forwarding state
br-lan: port 2(eth1) entering forwarding state
[ 3] 54.0-55.0 sec 6.75 MBytes 56.6 Mbits/sec
[ 3] 55.0-56.0 sec 0.00 Bytes 0.00 bits/sec
[ 3] 56.0-57.0 sec 10.5 MBytes 88.1 Mbits/sec
...
[ 3] 169.0-170.0 sec 11.4 MBytes 95.4 Mbits/sec
[ 3] 170.0-171.0 sec 11.4 MBytes 95.4 Mbits/sec
eth1: link up (10Mbps/Half duplex)
[ 3] 171.0-172.0 sec 7.63 MBytes 64.0 Mbits/sec
[ 3] 172.0-173.0 sec 9.38 MBytes 78.6 Mbits/sec
eth1: link up (100Mbps/Full duplex)
[ 3] 173.0-174.0 sec 11.3 MBytes 94.4 Mbits/sec
[ 3] 174.0-175.0 sec 11.4 MBytes 95.4 Mbits/sec
SVN-Revision: 26856
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The function __devinit ag71xx_probe() references
a function __devexit ag71xx_phy_disconnect().
This is often seen when error handling in the init function
uses functionality in the exit path.
The fix is often to remove the __devexit annotation of
ag71xx_phy_disconnect() so it may be used outside an exit section.
The function ag71xx_phy_disconnect() references a function in an exit
section.
Often the function ag71xx_ar7240_cleanup() has valid usage outside the
exit section
and the fix is to remove the __devexit annotation of
ag71xx_ar7240_cleanup.
SVN-Revision: 26855
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SVN-Revision: 26854
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SVN-Revision: 26845
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SVN-Revision: 26844
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SVN-Revision: 26843
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SVN-Revision: 26842
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Also initialize that for each SoC and print its value along with the
other frequencies.
SVN-Revision: 26561
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Signed-off-by: Jaiganesh Narayanan <jnarayanan@atheros.com>
SVN-Revision: 26516
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behind the switch instead
SVN-Revision: 26393
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run them on every device open, only on tx timeouts
SVN-Revision: 26392
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SVN-Revision: 24944
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Signed-off-by: Arnaud Lacombe <lacombar@gmail.com>
SVN-Revision: 23983
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Signed-off-by: Arnaud Lacombe <lacombar@gmail.com>
SVN-Revision: 23982
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Signed-off-by: Arnaud Lacombe <lacombar@gmail.com>
SVN-Revision: 23981
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Signed-off-by: Arnaud Lacombe <lacombar@gmail.com>
SVN-Revision: 23980
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Signed-off-by: Arnaud Lacombe <lacombar@gmail.com>
SVN-Revision: 23979
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Signed-off-by: Arnaud Lacombe <lacombar@gmail.com>
SVN-Revision: 23978
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(build errors has been fixed - juhosg)
Signed-off-by: Arnaud Lacombe <lacombar@gmail.com>
SVN-Revision: 23977
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(build error has been fixed - juhosg)
Signed-off-by: Arnaud Lacombe <lacombar@gmail.com>
SVN-Revision: 23975
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SVN-Revision: 23575
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patch to the 2.6.36 patches, add a backport patch to 2.6.32
SVN-Revision: 23574
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SVN-Revision: 23293
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* add a new SPI controller driver
* add SPI driver for the CPLD chip
* convert the NAND driver
* enable the mikroSD slot
* enable more LEDs
SVN-Revision: 22863
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directly into the ethernet driver, as MAC resets also require switch reinitializations and the switch is part of the cpu core anyway switch only tl-wr741nd (and other devices using this board file, such as tl-wr841nd) over to using this by default, as other devices are still untested fixes #7563
SVN-Revision: 22675
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we've figured out what part of it causes the issue described in #7563
SVN-Revision: 22075
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timeouts on ar724x considerably
SVN-Revision: 22055
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with packets while it's being brought down fixes boot time crashes under load reported by matteo
SVN-Revision: 22054
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SVN-Revision: 22016
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SVN-Revision: 21736
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SVN-Revision: 21698
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for some reason (fixes #7236)
SVN-Revision: 21166
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- on ar724x, rx buffers can be aligned with an offset of 2, which keeps the ip header aligned
- alignment offset is only added if the ar8216 workaround is not active and the phy driver does not advertise its own packet alignment
- ar71xx and ar91xx can not handle rx alignment offsets, however taking a hit on unaligned exceptions seems to have less overhead than re-aligning the data for large packets
- use memmove to re-align small packets, if necessary
tested on ar9132, ar7240 and ar7242 based devices without ar8216 headers
SVN-Revision: 20892
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functions
Cc: backfire@openwrt.org
SVN-Revision: 20751
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