| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ar71xx: nuke 3.3 support | Gabor Juhos | 2012-12-17 | 1 | -302/+0 |
| | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 34743 | ||||
| * | ar71xx: reorder some patches | Gabor Juhos | 2012-12-14 | 1 | -10/+10 |
| | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 34674 | ||||
| * | ar71xx: fix GPIO function selection for AR934x | Gabor Juhos | 2012-11-20 | 1 | -6/+4 |
| | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 34275 | ||||
| * | ar71xx: define NAND controller base address and register size for AR934X/QCA955x | Gabor Juhos | 2012-09-12 | 1 | -10/+20 |
| | | | | | SVN-Revision: 33382 | ||||
| * | ar71xx: fix QCA955X_EHCI_SIZE | Gabor Juhos | 2012-09-10 | 1 | -1/+1 |
| | | | | | SVN-Revision: 33360 | ||||
| * | ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934x | Gabor Juhos | 2012-09-09 | 1 | -4/+14 |
| | | | | | SVN-Revision: 33343 | ||||
| * | ar71xx: fix CPU/DDR frequency calculation for SRIF PLLs on AR934x | Gabor Juhos | 2012-09-08 | 1 | -10/+10 |
| | | | | | SVN-Revision: 33335 | ||||
| * | ar71xx: add initial support for the QCA955X SoCs | Gabor Juhos | 2012-07-05 | 1 | -7/+26 |
| | | | | | SVN-Revision: 32606 | ||||
| * | ar71xx: refactor PCI code to allow registering multiple PCI controllers | Gabor Juhos | 2012-07-05 | 1 | -14/+11 |
| | | | | | SVN-Revision: 32605 | ||||
| * | ar71xx: update 3.3 patches | Gabor Juhos | 2012-05-05 | 1 | -8/+37 |
| | | | | | SVN-Revision: 31602 | ||||
| * | ar71xx: add AR934x specific interface speed setup for ge0 | Gabor Juhos | 2012-03-19 | 1 | -4/+12 |
| | | | | | SVN-Revision: 31017 | ||||
| * | ar71xx: add preliminary support for 3.3 | Gabor Juhos | 2012-02-10 | 1 | -0/+231 |
| SVN-Revision: 30410 | |||||
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index : mtk-20170518 | |
| MTK 20170518 : Mediatek SDK based on OpenWRT Barrier Breaker |
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