| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
| |
SVN-Revision: 34161
|
|
|
|
|
|
|
|
|
| |
Combine two pcie patches (2nd patch undid the 1st patch) together
and refresh the other affected patches
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 34132
|
|
|
|
| |
SVN-Revision: 34120
|
|
|
|
|
|
|
|
|
|
| |
Many Laguna products have on-board GPS with Pulse-per-second (PPS)
support. This patch adds kernel support (statically) and adds
the platform data in laguna board support.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 34115
|
|
|
|
|
|
|
| |
SMP already selects HAVE_ARM_TWD and HAVE_ARM_SCU,
ARCH_CNS3XXX already selects MIGHT_HAVE_PCI
SVN-Revision: 34114
|
|
|
|
| |
SVN-Revision: 34113
|
|
|
|
| |
SVN-Revision: 34102
|
|
|
|
| |
SVN-Revision: 34101
|
|
|
|
| |
SVN-Revision: 34095
|
|
|
|
| |
SVN-Revision: 34094
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
ARM Linux PCI/PCIe hardware intialization needs to occur before device_init
as it does not support hotplug. I have modeled the cns3xxx PCIe init after
other ARM platforms. Registering it early resolves resource issues occuring
during bus enumeration that occur when a device driver is linked static in
the kernel.
Instead of passing in a bitmask to enable the 2 available ports, link detect
is used to enable ports that have a valid link.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 34044
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Update header file appropriately and disable read for ownership
Note that the FIQ support implements a workaround that provides a performance
boost over the traditional upstream workaround which ensures cache lines
are exclusive on driver CPU using 'read for ownership'.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/config-3.3 | 2 +-
target/linux/cns3xxx/patches-3.3/460-cns3xxx_fiq_support.patch | 9 ++++-----
2 files changed, 5 insertions(+), 6 deletions(-)
SVN-Revision: 33827
|
|
|
|
| |
SVN-Revision: 33825
|
|
|
|
|
|
|
|
| |
Properly terminate the correct platform resource for laguna UARTs
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33721
|
|
|
|
|
|
|
|
| |
level monitoring and control of Gateworks boards. It is used on several product families spanning several different target architectures (ixp4xx, cns3xxx, davinci).
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33720
|
|
|
|
|
|
|
|
| |
Resolves crashes when probing multiple serial devices
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33719
|
|
|
|
|
|
|
|
|
| |
The Laguna boards do not use all the same pins for SDHCI as the Cavium
reference board.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33684
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The ARM11MPCore Timer/Watchdog registers start at offset 0x600 which is where
all mpcore-wdt boards point the driver base too. I believe this is wrong
because 0x600 is aliased to the timer/watchdog of the 'current CPU' where
0x700 is CPU0's timer/watchdog, and 0x800 is CPU1's timer/watchdog. Thus
if your timer/watchdog application is switching between CPU's it can end up
writing to the wrong CPU's registers which results in random board resets
from watchdog timeouts etc.
This patch forces the timer/watchdog driver to use CPU0's registers always.
Its my opinion that other mpcore-wdt boards should be doing the same thing.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33683
|
|
|
|
|
|
|
|
|
|
|
| |
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/base-files/lib/cns3xxx.sh | 22 ++
target/linux/cns3xxx/base-files/lib/upgrade/platform.sh | 122 ++++++++++++++++
target/linux/cns3xxx/image/Makefile | 19 +-
3 files changed, 159 insertions(+), 4 deletions(-)
SVN-Revision: 33650
|
|
|
|
|
|
|
|
|
|
|
| |
Add GPIO/LED support for Gateworks GW2383
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/patches-3.3/300-laguna_support.patch | 18 +++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
SVN-Revision: 33649
|
|
|
|
|
|
|
|
|
| |
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/patches-3.3/470-gpio_irq.patch | 536 ++++++++++++++++++++
1 file changed, 536 insertions(+)
SVN-Revision: 33648
|
|
|
|
| |
SVN-Revision: 33603
|
|
|
|
|
|
| |
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33581
|
|
|
|
|
|
| |
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33580
|
|
|
|
|
|
|
|
|
| |
Resolves an issue where isochronouse USB would cause the driver to hang as
well as scheduling issues.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33579
|
|
|
|
|
|
|
|
|
| |
For cns3xxx SCU_CONFIGURATION always shows multipe cores but SCU_CPU_STATUS
shows which ones are active.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33566
|
|
|
|
|
|
| |
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33565
|
|
|
|
|
|
| |
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33564
|
|
|
|
| |
SVN-Revision: 33504
|
|
|
|
|
|
| |
performance with jumbo frames
SVN-Revision: 33503
|
|
|
|
| |
SVN-Revision: 33502
|
|
|
|
| |
SVN-Revision: 33500
|
|
|
|
| |
SVN-Revision: 33499
|
|
|
|
|
|
| |
requirement of 64), fix skb fragment chaining
SVN-Revision: 33498
|
|
|
|
| |
SVN-Revision: 33493
|
|
|
|
| |
SVN-Revision: 33492
|
|
|
|
|
|
| |
skb fragment lists
SVN-Revision: 33491
|
|
|
|
| |
SVN-Revision: 33490
|
|
|
|
| |
SVN-Revision: 33489
|
|
|
|
|
|
| |
the new one)
SVN-Revision: 33488
|
|
|
|
| |
SVN-Revision: 33487
|
|
|
|
| |
SVN-Revision: 33486
|
|
|
|
| |
SVN-Revision: 33485
|
|
|
|
| |
SVN-Revision: 33484
|
|
|
|
|
|
|
|
| |
Increase the size of the buffer used for eeprom reads during the platform configuration of the Gateworks laguna. The model name read in is 16 bytes but the original buffer was only 8 bytes.
Signed-off-by: David Acker <dacker@rajant.com>
SVN-Revision: 32833
|
|
|
|
| |
SVN-Revision: 32055
|
|
|
|
| |
SVN-Revision: 31888
|
|
|
|
| |
SVN-Revision: 31887
|
|
|
|
|
|
| |
Compile tested only.
SVN-Revision: 31809
|
|
|
|
| |
SVN-Revision: 31807
|