From 78a9b1a2ade2329658302da89ac052f1d5d8e4b4 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Tue, 19 Jul 2011 18:06:42 +0000 Subject: fixes pci on lantiq AR9 SoC SVN-Revision: 27695 --- target/linux/lantiq/patches-2.6.39/999-fix_pci.patch | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 target/linux/lantiq/patches-2.6.39/999-fix_pci.patch diff --git a/target/linux/lantiq/patches-2.6.39/999-fix_pci.patch b/target/linux/lantiq/patches-2.6.39/999-fix_pci.patch new file mode 100644 index 0000000..94a3bc7 --- /dev/null +++ b/target/linux/lantiq/patches-2.6.39/999-fix_pci.patch @@ -0,0 +1,18 @@ +--- a/arch/mips/pci/pci-lantiq.c ++++ b/arch/mips/pci/pci-lantiq.c +@@ -171,8 +171,13 @@ + u32 temp_buffer; + + /* set clock to 33Mhz */ +- ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR); +- ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR); ++ if (ltq_is_ar9()) { ++ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0x1f00000, LTQ_CGU_IFCCR); ++ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0xe00000, LTQ_CGU_IFCCR); ++ } else { ++ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR); ++ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR); ++ } + + /* external or internal clock ? */ + if (conf->clock) { -- cgit v1.1