From c05048b0bb686bfa927d3a4848127b9052549fb1 Mon Sep 17 00:00:00 2001
From: John Crispin <john@openwrt.org>
Date: Wed, 26 Nov 2014 09:00:17 +0000
Subject: add uboot-oxnas

This adds support for the oxnas target in U-Boot 2014.04
History can be found at https://github.com/kref/u-boot-oxnas up to 2013.10
changes from 2013.10 to 2014.04 can be followed at
https://gitorious.org/openwrt-oxnas

Signed-off-by: Daniel Golle <daniel@makrotopia.org>

SVN-Revision: 43389
---
 .../files/arch/arm/cpu/arm1136/nas782x/Makefile    |  13 +++
 .../files/arch/arm/cpu/arm1136/nas782x/clock.c     |  97 ++++++++++++++++
 .../files/arch/arm/cpu/arm1136/nas782x/pinmux.c    |  43 +++++++
 .../files/arch/arm/cpu/arm1136/nas782x/reset.c     |  91 +++++++++++++++
 .../files/arch/arm/cpu/arm1136/nas782x/timer.c     | 129 +++++++++++++++++++++
 .../arch/arm/include/asm/arch-nas782x/clock.h      |  84 ++++++++++++++
 .../files/arch/arm/include/asm/arch-nas782x/cpu.h  |  26 +++++
 .../arch/arm/include/asm/arch-nas782x/hardware.h   |  30 +++++
 .../arch/arm/include/asm/arch-nas782x/pinmux.h     |  46 ++++++++
 .../files/arch/arm/include/asm/arch-nas782x/spl.h  |   6 +
 .../arch/arm/include/asm/arch-nas782x/sysctl.h     | 125 ++++++++++++++++++++
 .../arch/arm/include/asm/arch-nas782x/timer.h      |  23 ++++
 12 files changed, 713 insertions(+)
 create mode 100644 package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/Makefile
 create mode 100644 package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/clock.c
 create mode 100644 package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/pinmux.c
 create mode 100644 package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/reset.c
 create mode 100644 package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/timer.c
 create mode 100644 package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/clock.h
 create mode 100644 package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/cpu.h
 create mode 100644 package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/hardware.h
 create mode 100644 package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/pinmux.h
 create mode 100644 package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/spl.h
 create mode 100644 package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/sysctl.h
 create mode 100644 package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/timer.h

(limited to 'package/boot/uboot-oxnas/files/arch')

diff --git a/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/Makefile b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/Makefile
new file mode 100644
index 0000000..4c32f5c
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= reset.o
+obj-y	+= timer.o
+obj-y	+= clock.o
+obj-y	+= pinmux.o
diff --git a/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/clock.c b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/clock.c
new file mode 100644
index 0000000..8974ca0
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/clock.c
@@ -0,0 +1,97 @@
+#include <common.h>
+#include <asm/arch/sysctl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+
+typedef struct {
+	unsigned short mhz;
+	unsigned char refdiv;
+	unsigned char outdiv;
+	unsigned int fbdiv;
+	unsigned short bwadj;
+	unsigned short sfreq;
+	unsigned int sslope;
+} PLL_CONFIG;
+
+const PLL_CONFIG C_PLL_CONFIG[] = {
+	{ 500, 1, 2, 3932160, 119, 208, 189 }, //  500 MHz
+	{ 525, 2, 1, 4128768, 125, 139, 297 }, //  525 MHz
+	{ 550, 2, 1, 4325376, 131, 139, 311 }, //  550 MHz
+	{ 575, 2, 1, 4521984, 137, 139, 326 }, //  575 MHz
+	{ 600, 2, 1, 4718592, 143, 138, 339 }, //  600 MHz
+	{ 625, 1, 1, 3276800, 99, 208, 157 }, //  625 MHz
+	{ 650, 1, 1, 3407872, 103, 208, 164 }, //  650 MHz
+	{ 675, 1, 1, 3538944, 107, 208, 170 }, //  675 MHz
+	{ 700, 0, 0, 917504, 27, 416, 22 }, //  700 MHz
+	{ 725, 1, 1, 3801088, 115, 208, 182 }, //  725 MHz
+	{ 750, 0, 0, 983040, 29, 416, 23 }, //  750 MHz
+	{ 775, 3, 0, 4063232, 123, 104, 390 }, //  775 MHz
+	{ 800, 3, 0, 4194304, 127, 104, 403 }, //  800 MHz
+	{ 825, 3, 0, 4325376, 131, 104, 415 }, //  825 MHz
+	{ 850, 2, 0, 3342336, 101, 139, 241 }, //  850 MHz
+	{ 875, 2, 0, 3440640, 104, 139, 248 }, //  875 MHz
+	{ 900, 2, 0, 3538944, 107, 139, 255 }, //  900 MHz
+	{ 925, 2, 0, 3637248, 110, 139, 262 }, //  925 MHz
+	{ 950, 2, 0, 3735552, 113, 139, 269 }, //  950 MHz
+	{ 975, 2, 0, 3833856, 116, 139, 276 }, //  975 MHz
+	{ 1000, 2, 0, 3932160, 119, 139, 283 }, // 1000 MHz
+};
+
+#define PLL_BYPASS (1<<1)
+#define SAT_ENABLE (1<<3)
+
+#define PLL_OUTDIV_SHIFT	4
+#define PLL_REFDIV_SHIFT	8
+#define PLL_BWADJ_SHIFT		16
+
+#define PLL_LOW_FREQ	500
+#define PLL_FREQ_STEP	25
+static void plla_configure(int outdiv, int refdiv, int fbdiv, int bwadj,
+                           int sfreq, int sslope)
+{
+	setbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS);
+	udelay(10);
+	reset_block(SYS_CTRL_RST_PLLA, 1);
+	udelay(10);
+
+	writel((refdiv << PLL_REFDIV_SHIFT) | (outdiv << PLL_OUTDIV_SHIFT) |
+	       SAT_ENABLE | PLL_BYPASS,
+	       SYS_CTRL_PLLA_CTRL0);
+
+	writel(fbdiv, SYS_CTRL_PLLA_CTRL1);
+	writel((bwadj << PLL_BWADJ_SHIFT) | sfreq, SYS_CTRL_PLLA_CTRL2);
+	writel(sslope, SYS_CTRL_PLLA_CTRL3);
+
+	udelay(10); // 5us delay required (from TCI datasheet), use 10us
+
+	reset_block(SYS_CTRL_RST_PLLA, 0);
+
+	udelay(100); // Delay for PLL to lock
+
+	printf("  plla_ctrl0 : %08x\n", readl(SYS_CTRL_PLLA_CTRL0));
+	printf("  plla_ctrl1 : %08x\n", readl(SYS_CTRL_PLLA_CTRL1));
+	printf("  plla_ctrl2 : %08x\n", readl(SYS_CTRL_PLLA_CTRL2));
+	printf("  plla_ctrl3 : %08x\n", readl(SYS_CTRL_PLLA_CTRL3));
+
+	clrbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS); // Take PLL out of bypass
+	puts("\nPLLA Set\n");
+}
+
+int plla_set_config(int mhz)
+{
+	int index = (mhz - PLL_LOW_FREQ) / PLL_FREQ_STEP;
+	const PLL_CONFIG *cfg;
+
+	if (index < 0 || index > ARRAY_SIZE(C_PLL_CONFIG)) {
+		debug("Freq %d MHz out of range, default to lowest\n", mhz);
+		index = 0;
+	}
+	cfg = &C_PLL_CONFIG[index];
+
+	printf("Attempting to set PLLA to %d MHz ...\n", (unsigned) cfg->mhz);
+	plla_configure(cfg->outdiv, cfg->refdiv, cfg->fbdiv, cfg->bwadj,
+	               cfg->sfreq, cfg->sslope);
+
+	return cfg->mhz;
+}
+
diff --git a/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/pinmux.c b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/pinmux.c
new file mode 100644
index 0000000..a6f5e9a
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/pinmux.c
@@ -0,0 +1,43 @@
+#include <common.h>
+#include <asm/arch/pinmux.h>
+
+void pinmux_set(int bank, int pin, int func)
+{
+	u32 reg;
+	u32 base;
+	/* TODO: check parameters */
+
+	if (bank == PINMUX_BANK_MFA)
+		base = SYS_CONTROL_BASE;
+	else
+		base = SEC_CONTROL_BASE;
+
+	clrbits_le32(base + PINMUX_SECONDARY_SEL, BIT(pin));
+	clrbits_le32(base + PINMUX_TERTIARY_SEL, BIT(pin));
+	clrbits_le32(base + PINMUX_QUATERNARY_SEL, BIT(pin));
+	clrbits_le32(base + PINMUX_DEBUG_SEL, BIT(pin));
+	clrbits_le32(base + PINMUX_ALTERNATIVE_SEL, BIT(pin));
+
+	switch (func) {
+	case PINMUX_GPIO:
+	default:
+		return;
+		break;
+	case PINMUX_2:
+		reg = base + PINMUX_SECONDARY_SEL;
+		break;
+	case PINMUX_3:
+		reg = base + PINMUX_TERTIARY_SEL;
+		break;
+	case PINMUX_4:
+		reg = base + PINMUX_QUATERNARY_SEL;
+		break;
+	case PINMUX_DEBUG:
+		reg = base + PINMUX_DEBUG_SEL;
+		break;
+	case PINMUX_ALT:
+		reg = base + PINMUX_ALTERNATIVE_SEL;
+		break;
+	}
+	setbits_le32(reg, BIT(pin));
+}
diff --git a/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/reset.c b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/reset.c
new file mode 100644
index 0000000..276c912
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/reset.c
@@ -0,0 +1,91 @@
+#include <common.h>
+#include <asm/arch/sysctl.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/clock.h>
+
+void reset_cpu(ulong addr)
+{
+	u32 value;
+
+	// Assert reset to cores as per power on defaults
+	// Don't touch the DDR interface as things will come to an impromptu stop
+	// NB Possibly should be asserting reset for PLLB, but there are timing
+	//    concerns here according to the docs
+
+	value =
+		BIT(SYS_CTRL_RST_COPRO     ) |
+		BIT(SYS_CTRL_RST_USBHS     ) |
+		BIT(SYS_CTRL_RST_USBHSPHYA ) |
+		BIT(SYS_CTRL_RST_MACA      ) |
+		BIT(SYS_CTRL_RST_PCIEA     ) |
+		BIT(SYS_CTRL_RST_SGDMA     ) |
+		BIT(SYS_CTRL_RST_CIPHER    ) |
+		BIT(SYS_CTRL_RST_SATA      ) |
+		BIT(SYS_CTRL_RST_SATA_LINK ) |
+		BIT(SYS_CTRL_RST_SATA_PHY  ) |
+		BIT(SYS_CTRL_RST_PCIEPHY   ) |
+		BIT(SYS_CTRL_RST_STATIC    ) |
+		BIT(SYS_CTRL_RST_UART1     ) |
+		BIT(SYS_CTRL_RST_UART2     ) |
+		BIT(SYS_CTRL_RST_MISC      ) |
+		BIT(SYS_CTRL_RST_I2S       ) |
+		BIT(SYS_CTRL_RST_SD        ) |
+		BIT(SYS_CTRL_RST_MACB      ) |
+		BIT(SYS_CTRL_RST_PCIEB     ) |
+		BIT(SYS_CTRL_RST_VIDEO     ) |
+		BIT(SYS_CTRL_RST_USBHSPHYB ) |
+		BIT(SYS_CTRL_RST_USBDEV    );
+
+	writel(value, SYS_CTRL_RST_SET_CTRL);
+
+	// Release reset to cores as per power on defaults
+	writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
+
+	// Disable clocks to cores as per power-on defaults - must leave DDR
+	// related clocks enabled otherwise we'll stop rather abruptly.
+	value =
+		BIT(SYS_CTRL_CLK_COPRO) 	|
+		BIT(SYS_CTRL_CLK_DMA)   	|
+		BIT(SYS_CTRL_CLK_CIPHER)	|
+		BIT(SYS_CTRL_CLK_SD)  		|
+		BIT(SYS_CTRL_CLK_SATA)  	|
+		BIT(SYS_CTRL_CLK_I2S)   	|
+		BIT(SYS_CTRL_CLK_USBHS) 	|
+		BIT(SYS_CTRL_CLK_MAC)   	|
+		BIT(SYS_CTRL_CLK_PCIEA)   	|
+		BIT(SYS_CTRL_CLK_STATIC)	|
+		BIT(SYS_CTRL_CLK_MACB)		|
+		BIT(SYS_CTRL_CLK_PCIEB)		|
+		BIT(SYS_CTRL_CLK_REF600)	|
+		BIT(SYS_CTRL_CLK_USBDEV);
+
+	writel(value, SYS_CTRL_CLK_CLR_CTRL);
+
+	// Enable clocks to cores as per power-on defaults
+
+	// Set sys-control pin mux'ing as per power-on defaults
+
+	writel(0, SYS_CONTROL_BASE + PINMUX_SECONDARY_SEL);
+	writel(0, SYS_CONTROL_BASE + PINMUX_TERTIARY_SEL);
+	writel(0, SYS_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
+	writel(0, SYS_CONTROL_BASE + PINMUX_DEBUG_SEL);
+	writel(0, SYS_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
+	writel(0, SYS_CONTROL_BASE + PINMUX_PULLUP_SEL);
+
+	writel(0, SEC_CONTROL_BASE + PINMUX_SECONDARY_SEL);
+	writel(0, SEC_CONTROL_BASE + PINMUX_TERTIARY_SEL);
+	writel(0, SEC_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
+	writel(0, SEC_CONTROL_BASE + PINMUX_DEBUG_SEL);
+	writel(0, SEC_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
+	writel(0, SEC_CONTROL_BASE + PINMUX_PULLUP_SEL);
+
+	// No need to save any state, as the ROM loader can determine whether reset
+	// is due to power cycling or programatic action, just hit the (self-
+	// clearing) CPU reset bit of the block reset register
+	value =
+		BIT(SYS_CTRL_RST_SCU) |
+		BIT(SYS_CTRL_RST_ARM0) |
+		BIT(SYS_CTRL_RST_ARM1);
+
+	writel(value, SYS_CTRL_RST_SET_CTRL);
+}
diff --git a/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/timer.c b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/timer.c
new file mode 100644
index 0000000..5e87608
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/cpu/arm1136/nas782x/timer.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define TIMER_CLOCK	(CONFIG_SYS_CLK_FREQ / (1 << (CONFIG_TIMER_PRESCALE * 4)))
+#define TIMER_LOAD_VAL 0xFFFFFF
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER	(TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR)) \
+			/ (TIMER_CLOCK / CONFIG_SYS_HZ)
+
+#define READ_TIMER_HW	(TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int timer_init (void)
+{
+	int32_t val;
+
+	/* Start the counter ticking up */
+	writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + TIMER_LOAD);	/* reload value on overflow*/
+
+	val = (CONFIG_TIMER_PRESCALE << TIMER_PRESCALE_SHIFT) |
+			(TIMER_MODE_PERIODIC << TIMER_MODE_SHIFT) |
+			(TIMER_ENABLE << TIMER_ENABLE_SHIFT);		/* mask to enable timer*/
+	writel(val, CONFIG_SYS_TIMERBASE + TIMER_CTRL);	/* start timer */
+
+	/* reset time */
+	gd->arch.lastinc = READ_TIMER;	/* capture current incrementer value */
+	gd->arch.tbl = 0;		/* start "advancing" time stamp */
+
+	return(0);
+}
+/*
+ * timer without interrupts
+ */
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay (unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	if (usec > 100000) {		/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
+		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;		/* finish normalize. */
+
+		tmp = get_timer (0);		/* get current timestamp */
+		while (get_timer (tmp) < tmo)/* loop till event */
+			/*NOP*/;
+	} else {			/* else small number, convert to hw ticks */
+		tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+		/* timeout is no more than 0.1s, and the hw timer will roll over at most once */
+		tmp = READ_TIMER_HW;
+		while (((READ_TIMER_HW -tmp) & TIMER_LOAD_VAL) < tmo)/* loop till event */
+			/*NOP*/;
+	}
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;		/* current tick value */
+
+	if (now >= gd->arch.lastinc) {		/* normal mode (non roll) */
+		/* move stamp fordward with absoulte diff ticks */
+		gd->arch.tbl += (now - gd->arch.lastinc);
+	} else {
+		/* we have rollover of incrementer */
+		gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
+				 - gd->arch.lastinc) + now;
+	}
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
+}
+
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/clock.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/clock.h
new file mode 100644
index 0000000..da7dd1c
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/clock.h
@@ -0,0 +1,84 @@
+#ifndef _NAS782X_CLOCK_H
+#define _NAS782X_CLOCK_H
+
+#include <asm/arch/sysctl.h>
+#include <asm/arch/cpu.h>
+
+/* bit numbers of clock control register */
+#define SYS_CTRL_CLK_COPRO  0
+#define SYS_CTRL_CLK_DMA    1
+#define SYS_CTRL_CLK_CIPHER 2
+#define SYS_CTRL_CLK_SD     3
+#define SYS_CTRL_CLK_SATA   4
+#define SYS_CTRL_CLK_I2S    5
+#define SYS_CTRL_CLK_USBHS  6
+#define SYS_CTRL_CLK_MACA   7
+#define SYS_CTRL_CLK_MAC   SYS_CTRL_CLK_MACA
+#define SYS_CTRL_CLK_PCIEA  8
+#define SYS_CTRL_CLK_STATIC 9
+#define SYS_CTRL_CLK_MACB   10
+#define SYS_CTRL_CLK_PCIEB  11
+#define SYS_CTRL_CLK_REF600 12
+#define SYS_CTRL_CLK_USBDEV 13
+#define SYS_CTRL_CLK_DDR    14
+#define SYS_CTRL_CLK_DDRPHY 15
+#define SYS_CTRL_CLK_DDRCK  16
+
+/* bit numbers of reset control register */
+#define SYS_CTRL_RST_SCU          0
+#define SYS_CTRL_RST_COPRO        1
+#define SYS_CTRL_RST_ARM0         2
+#define SYS_CTRL_RST_ARM1         3
+#define SYS_CTRL_RST_USBHS        4
+#define SYS_CTRL_RST_USBHSPHYA    5
+#define SYS_CTRL_RST_MACA         6
+#define SYS_CTRL_RST_MAC	SYS_CTRL_RST_MACA
+#define SYS_CTRL_RST_PCIEA        7
+#define SYS_CTRL_RST_SGDMA        8
+#define SYS_CTRL_RST_CIPHER       9
+#define SYS_CTRL_RST_DDR          10
+#define SYS_CTRL_RST_SATA         11
+#define SYS_CTRL_RST_SATA_LINK    12
+#define SYS_CTRL_RST_SATA_PHY     13
+#define SYS_CTRL_RST_PCIEPHY      14
+#define SYS_CTRL_RST_STATIC       15
+#define SYS_CTRL_RST_GPIO         16
+#define SYS_CTRL_RST_UART1        17
+#define SYS_CTRL_RST_UART2        18
+#define SYS_CTRL_RST_MISC         19
+#define SYS_CTRL_RST_I2S          20
+#define SYS_CTRL_RST_SD           21
+#define SYS_CTRL_RST_MACB         22
+#define SYS_CTRL_RST_PCIEB        23
+#define SYS_CTRL_RST_VIDEO        24
+#define SYS_CTRL_RST_DDR_PHY      25
+#define SYS_CTRL_RST_USBHSPHYB    26
+#define SYS_CTRL_RST_USBDEV       27
+#define SYS_CTRL_RST_ARMDBG       29
+#define SYS_CTRL_RST_PLLA         30
+#define SYS_CTRL_RST_PLLB         31
+
+static inline void reset_block(int block, int reset)
+{
+	u32 reg;
+	if (reset)
+		reg = SYS_CTRL_RST_SET_CTRL;
+	else
+		reg = SYS_CTRL_RST_CLR_CTRL;
+
+	writel(BIT(block), reg);
+}
+
+static inline void enable_clock(int block)
+{
+	writel(BIT(block), SYS_CTRL_CLK_SET_CTRL);
+}
+
+static inline void disable_clock(int block)
+{
+	writel(BIT(block), SYS_CTRL_CLK_CLR_CTRL);
+}
+
+int plla_set_config(int idx);
+
+#endif /* _NAS782X_CLOCK_H */
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/cpu.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/cpu.h
new file mode 100644
index 0000000..11e803c
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/cpu.h
@@ -0,0 +1,26 @@
+#ifndef _NAS782X_CPU_H
+#define _NAS782X_CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#include <asm/io.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/timer.h>
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+
+#define BIT(x)                  (1 << (x))
+
+/* fix "implicit declaration of function" warnning */
+void *memalign(size_t alignment, size_t bytes);
+void free(void* mem);
+void *malloc(size_t bytes);
+void *calloc(size_t n, size_t elem_size);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#endif /* _NAS782X_CPU_H */
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/hardware.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/hardware.h
new file mode 100644
index 0000000..f26b17f
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/hardware.h
@@ -0,0 +1,30 @@
+#ifndef _NAS782X_HARDWARE_H
+#define _NAS782X_HARDWARE_H
+
+/* Core addresses */
+#define USB_HOST_BASE		0x40200000
+#define MACA_BASE		0x40400000
+#define MACB_BASE		0x40800000
+#define MAC_BASE		MACA_BASE
+#define STATIC_CS0_BASE		0x41000000
+#define STATIC_CS1_BASE		0x41400000
+#define STATIC_CONTROL_BASE	0x41C00000
+#define SATA_DATA_BASE		0x42000000 /* non-functional, DMA just needs an address */
+#define GPIO_1_BASE		0x44000000
+#define GPIO_2_BASE		0x44100000
+#define UART_1_BASE		0x44200000
+#define UART_2_BASE		0x44300000
+#define SYS_CONTROL_BASE	0x44e00000
+#define SEC_CONTROL_BASE	0x44f00000
+#define RPSA_BASE		0x44400000
+#define RPSC_BASE		0x44500000
+#define DDR_BASE		0x44700000
+
+#define SATA_BASE		0x45900000
+#define SATA_0_REGS_BASE	0x45900000
+#define SATA_1_REGS_BASE	0x45910000
+#define SATA_DMA_REGS_BASE	0x459a0000
+#define SATA_SGDMA_REGS_BASE	0x459b0000
+#define SATA_HOST_REGS_BASE	0x459e0000
+
+#endif /* _NAS782X_HARDWARE_H */
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/pinmux.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/pinmux.h
new file mode 100644
index 0000000..810ba5c
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/pinmux.h
@@ -0,0 +1,46 @@
+#ifndef _NAS782X_PINMUX_H
+#define _NAS782X_PINMUX_H
+
+#include <asm/arch/cpu.h>
+
+#define PINMUX_GPIO		0
+#define PINMUX_2		1
+#define PINMUX_3		2
+#define PINMUX_4		3
+#define PINMUX_DEBUG		4
+#define PINMUX_ALT		5
+
+#define PINMUX_BANK_MFA		0
+#define PINMUX_BANK_MFB		1
+
+/* System control multi-function pin function selection */
+#define PINMUX_SECONDARY_SEL		0x14
+#define PINMUX_TERTIARY_SEL		0x8c
+#define PINMUX_QUATERNARY_SEL		0x94
+#define PINMUX_DEBUG_SEL		0x9c
+#define PINMUX_ALTERNATIVE_SEL		0xa4
+#define PINMUX_PULLUP_SEL		0xac
+
+#define PINMUX_UARTA_SIN		PINMUX_ALT
+#define PINMUX_UARTA_SOUT		PINMUX_ALT
+
+#define PINMUX_STATIC_DATA0		PINMUX_2
+#define PINMUX_STATIC_DATA1		PINMUX_2
+#define PINMUX_STATIC_DATA2		PINMUX_2
+#define PINMUX_STATIC_DATA3		PINMUX_2
+#define PINMUX_STATIC_DATA4		PINMUX_2
+#define PINMUX_STATIC_DATA5		PINMUX_2
+#define PINMUX_STATIC_DATA6		PINMUX_2
+#define PINMUX_STATIC_DATA7		PINMUX_2
+#define PINMUX_STATIC_NWE		PINMUX_2
+#define PINMUX_STATIC_NOE		PINMUX_2
+#define PINMUX_STATIC_NCS		PINMUX_2
+#define PINMUX_STATIC_ADDR18		PINMUX_2
+#define PINMUX_STATIC_ADDR19		PINMUX_2
+
+#define PINMUX_MACA_MDC			PINMUX_2
+#define PINMUX_MACA_MDIO		PINMUX_2
+
+extern void pinmux_set(int bank, int pin, int func);
+
+#endif /* _NAS782X_PINMUX_H */
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/spl.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/spl.h
new file mode 100644
index 0000000..f73afda
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/spl.h
@@ -0,0 +1,6 @@
+#ifndef _NAS782X_SPL_H
+#define _NAS782X_SPL_H
+
+#include <asm/arch/cpu.h>
+
+#endif /* _NAS782X_SPL_H */
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/sysctl.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/sysctl.h
new file mode 100644
index 0000000..3867e45
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/sysctl.h
@@ -0,0 +1,125 @@
+#ifndef _NAS782X_SYSCTL_H
+#define _NAS782X_SYSCTL_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#include <asm/arch/hardware.h>
+
+/**
+ * System block reset and clock control
+ */
+#define SYS_CTRL_PCI_STAT		(SYS_CONTROL_BASE + 0x20)
+#define SYS_CTRL_CLK_SET_CTRL		(SYS_CONTROL_BASE + 0x2C)
+#define SYS_CTRL_CLK_CLR_CTRL		(SYS_CONTROL_BASE + 0x30)
+#define SYS_CTRL_RST_SET_CTRL		(SYS_CONTROL_BASE + 0x34)
+#define SYS_CTRL_RST_CLR_CTRL		(SYS_CONTROL_BASE + 0x38)
+#define SYS_CTRL_PLLSYS_CTRL		(SYS_CONTROL_BASE + 0x48)
+#define SYS_CTRL_PLLSYS_KEY_CTRL	(SYS_CONTROL_BASE + 0x6C)
+#define SYS_CTRL_GMAC_CTRL		(SYS_CONTROL_BASE + 0x78)
+
+/* Scratch registers */
+#define SYS_CTRL_SCRATCHWORD0		(SYS_CONTROL_BASE + 0xc4)
+#define SYS_CTRL_SCRATCHWORD1		(SYS_CONTROL_BASE + 0xc8)
+#define SYS_CTRL_SCRATCHWORD2		(SYS_CONTROL_BASE + 0xcc)
+#define SYS_CTRL_SCRATCHWORD3		(SYS_CONTROL_BASE + 0xd0)
+
+#define SYS_CTRL_PLLA_CTRL0		(SYS_CONTROL_BASE + 0x1F0)
+#define SYS_CTRL_PLLA_CTRL1		(SYS_CONTROL_BASE + 0x1F4)
+#define SYS_CTRL_PLLA_CTRL2		(SYS_CONTROL_BASE + 0x1F8)
+#define SYS_CTRL_PLLA_CTRL3		(SYS_CONTROL_BASE + 0x1FC)
+
+#define SYS_CTRL_GMAC_AUTOSPEED		3
+#define SYS_CTRL_GMAC_RGMII		2
+#define SYS_CTRL_GMAC_SIMPLE_MUX	1
+#define SYS_CTRL_GMAC_CKEN_GTX		0
+
+#define SYS_CTRL_CKCTRL_CTRL_ADDR	(SYS_CONTROL_BASE + 0x64)
+
+#define SYS_CTRL_CKCTRL_PCI_DIV_BIT	0
+#define SYS_CTRL_CKCTRL_SLOW_BIT	8
+
+
+#define SYS_CTRL_USBHSMPH_CTRL		(SYS_CONTROL_BASE + 0x40)
+#define SYS_CTRL_USBHSMPH_STAT		(SYS_CONTROL_BASE + 0x44)
+#define SYS_CTRL_REF300_DIV		(SYS_CONTROL_BASE + 0xF8)
+#define SYS_CTRL_USBHSPHY_CTRL		(SYS_CONTROL_BASE + 0x84)
+#define SYS_CTRL_USB_CTRL		(SYS_CONTROL_BASE + 0x90)
+
+/* System control multi-function pin function selection */
+#define SYS_CTRL_SECONDARY_SEL		(SYS_CONTROL_BASE + 0x14)
+#define SYS_CTRL_TERTIARY_SEL		(SYS_CONTROL_BASE + 0x8c)
+#define SYS_CTRL_QUATERNARY_SEL		(SYS_CONTROL_BASE + 0x94)
+#define SYS_CTRL_DEBUG_SEL		(SYS_CONTROL_BASE + 0x9c)
+#define SYS_CTRL_ALTERNATIVE_SEL	(SYS_CONTROL_BASE + 0xa4)
+#define SYS_CTRL_PULLUP_SEL		(SYS_CONTROL_BASE + 0xac)
+
+/* Secure control multi-function pin function selection */
+#define SEC_CTRL_SECONDARY_SEL		(SEC_CONTROL_BASE + 0x14)
+#define SEC_CTRL_TERTIARY_SEL		(SEC_CONTROL_BASE + 0x8c)
+#define SEC_CTRL_QUATERNARY_SEL		(SEC_CONTROL_BASE + 0x94)
+#define SEC_CTRL_DEBUG_SEL		(SEC_CONTROL_BASE + 0x9c)
+#define SEC_CTRL_ALTERNATIVE_SEL	(SEC_CONTROL_BASE + 0xa4)
+#define SEC_CTRL_PULLUP_SEL		(SEC_CONTROL_BASE + 0xac)
+
+#define SEC_CTRL_COPRO_CTRL		(SEC_CONTROL_BASE + 0x68)
+#define SEC_CTRL_SECURE_CTRL		(SEC_CONTROL_BASE + 0x98)
+#define SEC_CTRL_LEON_DEBUG		(SEC_CONTROL_BASE + 0xF0)
+#define SEC_CTRL_PLLB_DIV_CTRL		(SEC_CONTROL_BASE + 0xF8)
+#define SEC_CTRL_PLLB_CTRL0		(SEC_CONTROL_BASE + 0x1F0)
+#define SEC_CTRL_PLLB_CTRL1		(SEC_CONTROL_BASE + 0x1F4)
+#define SEC_CTRL_PLLB_CTRL8		(SEC_CONTROL_BASE + 0x1F4)
+
+#define REF300_DIV_INT_SHIFT		8
+#define REF300_DIV_FRAC_SHIFT		0
+#define REF300_DIV_INT(val)		((val) << REF300_DIV_INT_SHIFT)
+#define REF300_DIV_FRAC(val)		((val) << REF300_DIV_FRAC_SHIFT)
+
+#define USBHSPHY_SUSPENDM_MANUAL_ENABLE		16
+#define USBHSPHY_SUSPENDM_MANUAL_STATE		15
+#define USBHSPHY_ATE_ESET			14
+#define USBHSPHY_TEST_DIN			6
+#define USBHSPHY_TEST_ADD			2
+#define USBHSPHY_TEST_DOUT_SEL			1
+#define USBHSPHY_TEST_CLK			0
+
+#define USB_CTRL_USBAPHY_CKSEL_SHIFT	5
+#define USB_CLK_XTAL0_XTAL1		(0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+#define USB_CLK_XTAL0			(1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+#define USB_CLK_INTERNAL		(2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+
+#define USBAMUX_DEVICE			BIT(4)
+
+#define USBPHY_REFCLKDIV_SHIFT		2
+#define USB_PHY_REF_12MHZ		(0 << USBPHY_REFCLKDIV_SHIFT)
+#define USB_PHY_REF_24MHZ		(1 << USBPHY_REFCLKDIV_SHIFT)
+#define USB_PHY_REF_48MHZ		(2 << USBPHY_REFCLKDIV_SHIFT)
+
+#define USB_CTRL_USB_CKO_SEL_BIT	0
+
+#define USB_INT_CLK_XTAL 		0
+#define USB_INT_CLK_REF300		2
+#define USB_INT_CLK_PLLB		3
+
+#define SYS_CTRL_GMAC_AUTOSPEED		3
+#define SYS_CTRL_GMAC_RGMII		2
+#define SYS_CTRL_GMAC_SIMPLE_MUX	1
+#define SYS_CTRL_GMAC_CKEN_GTX		0
+
+
+#define PLLB_ENSAT			3
+#define PLLB_OUTDIV			4
+#define PLLB_REFDIV			8
+#define PLLB_DIV_INT_SHIFT		8
+#define PLLB_DIV_FRAC_SHIFT		0
+#define PLLB_DIV_INT(val)		((val) << PLLB_DIV_INT_SHIFT)
+#define PLLB_DIV_FRAC(val)		((val) << PLLB_DIV_FRAC_SHIFT)
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#endif /* _NAS782X_SYSCTL_H */
diff --git a/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/timer.h b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/timer.h
new file mode 100644
index 0000000..ea4d71e
--- /dev/null
+++ b/package/boot/uboot-oxnas/files/arch/arm/include/asm/arch-nas782x/timer.h
@@ -0,0 +1,23 @@
+#ifndef _NAS782X_TIMER_H
+#define _NAS782X_TIMER_H
+
+#define TIMER1_BASE		(RPSA_BASE + 0x200)
+#define TIMER2_BASE		(RPSA_BASE + 0x220)
+
+#define TIMER_LOAD		0
+#define TIMER_CURR		4
+#define TIMER_CTRL		8
+#define	TIMER_INTR		0x0C
+
+#define TIMER_PRESCALE_SHIFT		2
+#define TIMER_PRESCALE_1		0
+#define TIMER_PRESCALE_16		1
+#define TIMER_PRESCALE_256		2
+#define TIMER_MODE_SHIFT		6
+#define TIMER_MODE_FREE_RUNNING		0
+#define TIMER_MODE_PERIODIC		1
+#define TIMER_ENABLE_SHIFT		7
+#define TIMER_DISABLE			0
+#define TIMER_ENABLE			1
+
+#endif /* _NAS782X_TIMER_H */
-- 
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