From 9b9b83976c64fd220fde833262f6a0c385677d3b Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 10 Dec 2007 14:05:01 +0000 Subject: add support for GPIO IRQs SVN-Revision: 9700 --- .../adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h') diff --git a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h index a40175b..f96c7d5 100644 --- a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h +++ b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h @@ -247,6 +247,11 @@ #define GPIO_CONF0_OE_MASK (0xFF << GPIO_CONF0_OE_SHIFT) #define GPIO_CONF0_OV_MASK (0xFF << GPIO_CONF0_OV_SHIFT) +/* GPIO_CONF2 register bits */ +#define GPIO_CONF2_CSX0 BIT(4) /* enable CSX0:INTX0 on GPIO 1:2 */ +#define GPIO_CONF2_CSX1 BIT(5) /* enable CSX1:INTX1 on GPIO 3:4 */ +#define GPIO_CONF2_EW BIT(6) /* enable wait state pin for CSX0/1 */ + /* INT_STATUS/INT_MASK register bits */ #define SWITCH_INT_SHD BIT(0) /* Send High Done */ #define SWITCH_INT_SLD BIT(1) /* Send Low Done */ -- cgit v1.1