From af015f956c35717909247a5732f6862d3de1476f Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Sun, 22 Jan 2012 22:38:19 +0000
Subject: ar71xx: add initial support for 3.2
Tested on the following boards:
ALFA AP96
TL-MR3220 v1
TL-WR1043ND v1
TL-WR2543ND v1
TL-WR703N v1
TL-WR741ND v1
TL-WR741ND v4
WNDR3700 v1
WZR-HP-G300NH
SVN-Revision: 29868
---
.../patches-3.2/605-MIPS-ath79-db120-fixes.patch | 220 +++++++++++++++++++++
1 file changed, 220 insertions(+)
create mode 100644 target/linux/ar71xx/patches-3.2/605-MIPS-ath79-db120-fixes.patch
(limited to 'target/linux/ar71xx/patches-3.2/605-MIPS-ath79-db120-fixes.patch')
diff --git a/target/linux/ar71xx/patches-3.2/605-MIPS-ath79-db120-fixes.patch b/target/linux/ar71xx/patches-3.2/605-MIPS-ath79-db120-fixes.patch
new file mode 100644
index 0000000..07b23da
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.2/605-MIPS-ath79-db120-fixes.patch
@@ -0,0 +1,220 @@
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -37,17 +37,26 @@
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
+ #include <linux/pci.h>
++#include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
+
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++#include "common.h"
++#include "dev-ap9x-pci.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
++#include "dev-m25p80.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
+-#include "pci.h"
++#include "machtypes.h"
+
++#define DB120_GPIO_LED_USB 11
+ #define DB120_GPIO_LED_WLAN_5G 12
+ #define DB120_GPIO_LED_WLAN_2G 13
+ #define DB120_GPIO_LED_STATUS 14
+@@ -58,8 +67,50 @@
+ #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
+ #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
+
+-#define DB120_WMAC_CALDATA_OFFSET 0x1000
+-#define DB120_PCIE_CALDATA_OFFSET 0x5000
++#define DB120_MAC0_OFFSET 0
++#define DB120_MAC1_OFFSET 6
++#define DB120_WMAC_CALDATA_OFFSET 0x1000
++#define DB120_PCIE_CALDATA_OFFSET 0x5000
++
++static struct mtd_partition db120_partitions[] = {
++ {
++ .name = "u-boot",
++ .offset = 0,
++ .size = 0x040000,
++ .mask_flags = MTD_WRITEABLE,
++ },
++ {
++ .name = "u-boot-env",
++ .offset = 0x040000,
++ .size = 0x010000,
++ },
++ {
++ .name = "rootfs",
++ .offset = 0x050000,
++ .size = 0x630000,
++ },
++ {
++ .name = "uImage",
++ .offset = 0x680000,
++ .size = 0x160000,
++ },
++ {
++ .name = "NVRAM",
++ .offset = 0x7E0000,
++ .size = 0x010000,
++ },
++ {
++ .name = "ART",
++ .offset = 0x7F0000,
++ .size = 0x010000,
++ .mask_flags = MTD_WRITEABLE,
++ }
++};
++
++static struct flash_platform_data db120_flash_data = {
++ .parts = db120_partitions,
++ .nr_parts = ARRAY_SIZE(db120_partitions),
++};
+
+ static struct gpio_led db120_leds_gpio[] __initdata = {
+ {
+@@ -82,6 +133,11 @@ static struct gpio_led db120_leds_gpio[]
+ .gpio = DB120_GPIO_LED_WLAN_2G,
+ .active_low = 1,
+ },
++ {
++ .name = "db120:green:usb",
++ .gpio = DB120_GPIO_LED_USB,
++ .active_low = 1,
++ }
+ };
+
+ static struct gpio_keys_button db120_gpio_keys[] __initdata = {
+@@ -95,66 +151,65 @@ static struct gpio_keys_button db120_gpi
+ },
+ };
+
+-static struct ath79_spi_controller_data db120_spi0_data = {
+- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+- .cs_line = 0,
+-};
+-
+-static struct spi_board_info db120_spi_info[] = {
+- {
+- .bus_num = 0,
+- .chip_select = 0,
+- .max_speed_hz = 25000000,
+- .modalias = "s25sl064a",
+- .controller_data = &db120_spi0_data,
+- }
+-};
+-
+-static struct ath79_spi_platform_data db120_spi_data = {
+- .bus_num = 0,
+- .num_chipselect = 1,
+-};
+-
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data db120_ath9k_data;
+-
+-static int db120_pci_plat_dev_init(struct pci_dev *dev)
++static void __init db120_gmac_setup(void)
+ {
+- switch (PCI_SLOT(dev->devfn)) {
+- case 0:
+- dev->dev.platform_data = &db120_ath9k_data;
+- break;
+- }
++ void __iomem *base;
++ u32 t;
+
+- return 0;
+-}
++ base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
+
+-static void __init db120_pci_init(u8 *eeprom)
+-{
+- memcpy(db120_ath9k_data.eeprom_data, eeprom,
+- sizeof(db120_ath9k_data.eeprom_data));
++ t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
++ t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
++ AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
++ __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
+
+- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
+- ath79_register_pci();
++ iounmap(base);
+ }
+-#else
+-static inline void db120_pci_init(void) {}
+-#endif /* CONFIG_PCI */
+
+ static void __init db120_setup(void)
+ {
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
++ ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
++ ath79_register_m25p80(&db120_flash_data);
++
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
+ db120_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(db120_gpio_keys),
+ db120_gpio_keys);
+- ath79_register_spi(&db120_spi_data, db120_spi_info,
+- ARRAY_SIZE(db120_spi_info));
+ ath79_register_usb();
+ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
+- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
++ ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
++
++ db120_gmac_setup();
++
++ ath79_register_mdio(0, 0x0);
++ ath79_register_mdio(1, 0x0);
++
++ ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
++#if 0
++ /* GMAC0 is connected to an AR8327 switch */
++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++ ath79_eth0_data.speed = SPEED_1000;
++ ath79_eth0_data.duplex = DUPLEX_FULL;
++#else
++ /* GMAC0 is connected to PHY4 of the internal switch */
++ ath79_switch_data.phy4_mii_en = 1;
++
++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
++ ath79_eth0_data.phy_mask = BIT(4);
++ ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
++#endif
++ ath79_register_eth(0);
++
++ /* GMAC1 is connected to the internal switch */
++ ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
++ ath79_eth1_data.speed = SPEED_1000;
++ ath79_eth1_data.duplex = DUPLEX_FULL;
++
++ ath79_register_eth(1);
+ }
+
+ MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -31,9 +31,11 @@ config ATH79_MACH_AP81
+ config ATH79_MACH_DB120
+ bool "Atheros DB120 reference board"
+ select SOC_AR934X
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
+ select ATH79_DEV_GPIO_BUTTONS
+ select ATH79_DEV_LEDS_GPIO
+- select ATH79_DEV_SPI
++ select ATH79_DEV_M25P80
+ select ATH79_DEV_USB
+ select ATH79_DEV_WMAC
+ help
--
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