From c4664b0f911614a2d19eddcb9b52e2937581ca5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Thu, 19 May 2016 19:32:46 +0200 Subject: kernel: update kernel 4.4 to version 4.4.11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas --- .../ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch') diff --git a/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch index 5d9d802..4d7902e 100644 --- a/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch +++ b/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch @@ -135,8 +135,7 @@ +static void __init ap136_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); - --static int ap136_pci_plat_dev_init(struct pci_dev *dev) ++ + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), @@ -151,7 +150,8 @@ + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); -+ + +-static int ap136_pci_plat_dev_init(struct pci_dev *dev) + ath79_register_mdio(0, 0x0); + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0); + @@ -211,16 +211,16 @@ + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; + ap136_ar8327_pad0_cfg.sgmii_delay_en = true; - -- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); -- ath79_register_pci(); ++ + /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */ + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII; + ap136_ar8327_pad6_cfg.txclk_delay_en = true; + ap136_ar8327_pad6_cfg.rxclk_delay_en = true; + ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; -+ + +- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); +- ath79_register_pci(); + ath79_eth0_pll_data.pll_1000 = 0x56000000; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + -- cgit v1.1