From 4b9680f138264e73517a51f7155d96bf4a96b682 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Mon, 6 Aug 2018 16:21:02 +0200 Subject: ath79: fix QCA9557 eth PLL settings The QCA9557 dtsi is currently missing pll-handle and pll-regs for both eth0 and eth1, therefore PLL settings won't be applied. This commit fixes this behavior. Signed-off-by: David Bauer --- target/linux/ath79/dts/qca9557.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'target/linux/ath79/dts') diff --git a/target/linux/ath79/dts/qca9557.dtsi b/target/linux/ath79/dts/qca9557.dtsi index c3874bc..992ccff 100644 --- a/target/linux/ath79/dts/qca9557.dtsi +++ b/target/linux/ath79/dts/qca9557.dtsi @@ -109,7 +109,7 @@ pll: pll-controller@18050000 { compatible = "qca,ar9557-pll", - "qca,qca9550-pll"; + "qca,qca9550-pll", "syscon"; reg = <0x18050000 0x50>; #clock-cells = <1>; @@ -295,6 +295,9 @@ ð0 { compatible = "qca,qca9550-eth", "syscon", "simple-mfd"; + pll-reg = <0 0x28 0>; + pll-handle = <&pll>; + pll-data = <0x82000101 0x80000101 0x80001313>; phy-mode = "rgmii"; @@ -310,6 +313,9 @@ ð1 { compatible = "qca,qca9550-eth", "syscon", "simple-mfd"; + pll-reg = <0 0x48 0>; + pll-handle = <&pll>; + pll-data = <0x82000101 0x80000101 0x80001313>; phy-mode = "sgmii"; -- cgit v1.1