From 53c474abbdfef8eb3499e2d10c9ad491788b8a72 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sun, 6 May 2018 10:20:11 +0200 Subject: ath79: add new OF only target for QCA MIPS silicon This target aims to replace ar71xx mid-term. The big part that is still missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik subtargets will follow. Signed-off-by: John Crispin --- .../461-spi-ath79-add-fast-flash-read.patch | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 target/linux/ath79/patches-4.14/461-spi-ath79-add-fast-flash-read.patch (limited to 'target/linux/ath79/patches-4.14/461-spi-ath79-add-fast-flash-read.patch') diff --git a/target/linux/ath79/patches-4.14/461-spi-ath79-add-fast-flash-read.patch b/target/linux/ath79/patches-4.14/461-spi-ath79-add-fast-flash-read.patch new file mode 100644 index 0000000..5c3583f --- /dev/null +++ b/target/linux/ath79/patches-4.14/461-spi-ath79-add-fast-flash-read.patch @@ -0,0 +1,60 @@ +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -102,9 +102,6 @@ static void ath79_spi_enable(struct ath7 + /* save CTRL register */ + sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); + sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); +- +- /* TODO: setup speed? */ +- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); + } + + static void ath79_spi_disable(struct ath79_spi *sp) +@@ -205,6 +202,38 @@ static u32 ath79_spi_txrx_mode0(struct s + return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); + } + ++static bool ath79_spi_flash_read_supported(struct spi_device *spi) ++{ ++ if (spi->chip_select || gpio_is_valid(spi->cs_gpio)) ++ return false; ++ ++ return true; ++} ++ ++static int ath79_spi_read_flash_data(struct spi_device *spi, ++ struct spi_flash_read_message *msg) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ ++ if (msg->addr_width > 3) ++ return -EOPNOTSUPP; ++ ++ /* disable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); ++ ++ memcpy_fromio(msg->buf, sp->base + msg->from, msg->len); ++ ++ /* enable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); ++ ++ /* restore IOC register */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); ++ ++ msg->retlen = msg->len; ++ ++ return 0; ++} ++ + static int ath79_spi_probe(struct platform_device *pdev) + { + struct spi_master *master; +@@ -234,6 +263,8 @@ static int ath79_spi_probe(struct platfo + master->num_chipselect = pdata->num_chipselect; + master->cs_gpios = pdata->cs_gpios; + } ++ master->spi_flash_read = ath79_spi_read_flash_data; ++ master->flash_read_supported = ath79_spi_flash_read_supported; + + sp->bitbang.master = master; + sp->bitbang.chipselect = ath79_spi_chipselect; -- cgit v1.1