From d11efa14286ba8b6e6bfa3af0f3c16e1f8492682 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Thu, 2 May 2013 15:28:26 +0000 Subject: bcm63xx: add SMP support for BCM6362 and BCM6368 BCM6358 requires further work due to its shared TLB. Signed-off-by: Jonas Gorski SVN-Revision: 36526 --- ...X-use-a-helper-for-getting-the-right-regi.patch | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 target/linux/brcm63xx/patches-3.8/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch (limited to 'target/linux/brcm63xx/patches-3.8/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch') diff --git a/target/linux/brcm63xx/patches-3.8/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch b/target/linux/brcm63xx/patches-3.8/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch new file mode 100644 index 0000000..3931b21 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.8/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch @@ -0,0 +1,80 @@ +From 7c9d3fe01034adbb890aab7c44534658f89c211b Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 25 Apr 2013 15:35:12 +0200 +Subject: [PATCH 08/13] MIPS: BCM63XX: use a helper for getting the right + register address + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/irq.c | 30 ++++++++++++++++++++++++------ + 1 file changed, 24 insertions(+), 6 deletions(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -251,6 +251,20 @@ static inline u32 get_ext_irq_perf_reg(i + return ext_irq_cfg_reg2; + } + ++static inline u32 get_irq_stat_addr(int cpu) ++{ ++ if (cpu == 0) ++ return irq_stat_addr0; ++ return irq_stat_addr1; ++} ++ ++static inline u32 get_irq_mask_addr(int cpu) ++{ ++ if (cpu == 0) ++ return irq_mask_addr0; ++ return irq_mask_addr1; ++} ++ + static inline void handle_internal(int intbit) + { + if (is_ext_irq_cascaded && +@@ -274,13 +288,15 @@ void __dispatch_internal_##width(void) + unsigned int src, tgt; \ + bool irqs_pending = false; \ + static int i; \ ++ u32 irq_stat_addr = get_irq_stat_addr(0); \ ++ u32 irq_mask_addr = get_irq_mask_addr(0); \ + \ + /* read registers in reverse order */ \ + for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ + u32 val; \ + \ +- val = bcm_readl(irq_stat_addr0 + src * sizeof(u32)); \ +- val &= bcm_readl(irq_mask_addr0 + src * sizeof(u32)); \ ++ val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \ ++ val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \ + pending[--tgt] = val; \ + \ + if (val) \ +@@ -306,10 +322,11 @@ static void __internal_irq_mask_##width( + u32 val; \ + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ ++ u32 irq_mask_addr = get_irq_mask_addr(0); \ + \ +- val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32)); \ ++ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ + val &= ~(1 << bit); \ +- bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32)); \ ++ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ + } \ + \ + static void __internal_irq_unmask_##width(unsigned int irq) \ +@@ -317,10 +334,11 @@ static void __internal_irq_unmask_##widt + u32 val; \ + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ ++ u32 irq_mask_addr = get_irq_mask_addr(0); \ + \ +- val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32)); \ ++ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ + val |= (1 << bit); \ +- bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32)); \ ++ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ + } + + BUILD_IPIC_INTERNAL(32); -- cgit v1.1