From 2bbd43d065dabbd3b8824680a793db8464cf0a2e Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Wed, 11 Dec 2013 10:56:09 +0000 Subject: imx6: add flexcan support backport upstream changes to 3.10: - 0060-flexcan.patch: - add flexcan pinctrl and devicetree config - 0061-can-flexcan-use-correct-clock-as-base-for-bit-rate-c.patch - fix a clock issue - 0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch - fix a clock issue Signed-off-by: Tim Harvey SVN-Revision: 39033 --- ...6q-fix-the-wrong-parent-of-can_root-clock.patch | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch (limited to 'target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch') diff --git a/target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch b/target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch new file mode 100644 index 0000000..8ea02f6 --- /dev/null +++ b/target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch @@ -0,0 +1,25 @@ +From 9b3d423707c3b1f6633be1be7e959623e10c596b Mon Sep 17 00:00:00 2001 +From: Jiada Wang +Date: Wed, 30 Oct 2013 04:25:51 -0700 +Subject: [PATCH] ARM: i.MX6q: fix the wrong parent of can_root clock + +instead of pll3_usb_otg the parent of can_root clock +should be pll3_60m. + +Signed-off-by: Jiada Wang +Signed-off-by: Shawn Guo +--- + arch/arm/mach-imx/clk-imx6q.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/mach-imx/clk-imx6q.c ++++ b/arch/arm/mach-imx/clk-imx6q.c +@@ -442,7 +442,7 @@ int __init mx6q_clocks_init(void) + clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); + clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); + clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); +- clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6); ++ clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); + clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); + clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); + clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); -- cgit v1.1