From c6c731fe311f7da42777ffd31804a4f6aa3f8e19 Mon Sep 17 00:00:00 2001 From: Yutang Jiang Date: Sat, 29 Oct 2016 00:14:32 +0800 Subject: layerscape: add 64b/32b target for ls1043ardb device Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang --- .../3013-dts-ls1043ardb-add-mdio-phy-nodes.patch | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 target/linux/layerscape/patches-4.4/3013-dts-ls1043ardb-add-mdio-phy-nodes.patch (limited to 'target/linux/layerscape/patches-4.4/3013-dts-ls1043ardb-add-mdio-phy-nodes.patch') diff --git a/target/linux/layerscape/patches-4.4/3013-dts-ls1043ardb-add-mdio-phy-nodes.patch b/target/linux/layerscape/patches-4.4/3013-dts-ls1043ardb-add-mdio-phy-nodes.patch new file mode 100644 index 0000000..8347b4f --- /dev/null +++ b/target/linux/layerscape/patches-4.4/3013-dts-ls1043ardb-add-mdio-phy-nodes.patch @@ -0,0 +1,81 @@ +From e2b301610e6201df40deb62942b18c772365eb1c Mon Sep 17 00:00:00 2001 +From: Shaohui Xie +Date: Thu, 21 Jan 2016 11:29:22 +0800 +Subject: [PATCH 13/70] dts: ls1043ardb: add mdio & phy nodes + +Signed-off-by: Shaohui Xie +--- + arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 65 +++++++++++++++++++++ + 1 file changed, 65 insertions(+) + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts +@@ -115,3 +115,68 @@ + &duart1 { + status = "okay"; + }; ++ ++&fman0 { ++ ethernet@e0000 { ++ phy-handle = <&qsgmii_phy1>; ++ phy-connection-type = "qsgmii"; ++ }; ++ ++ ethernet@e2000 { ++ phy-handle = <&qsgmii_phy2>; ++ phy-connection-type = "qsgmii"; ++ }; ++ ++ ethernet@e4000 { ++ phy-handle = <&rgmii_phy1>; ++ phy-connection-type = "rgmii"; ++ }; ++ ++ ethernet@e6000 { ++ phy-handle = <&rgmii_phy2>; ++ phy-connection-type = "rgmii"; ++ }; ++ ++ ethernet@e8000 { ++ phy-handle = <&qsgmii_phy3>; ++ phy-connection-type = "qsgmii"; ++ }; ++ ++ ethernet@ea000 { ++ phy-handle = <&qsgmii_phy4>; ++ phy-connection-type = "qsgmii"; ++ }; ++ ++ ethernet@f0000 { /* 10GEC1 */ ++ phy-handle = <&aqr105_phy>; ++ phy-connection-type = "xgmii"; ++ }; ++ ++ mdio@fc000 { ++ rgmii_phy1: ethernet-phy@1 { ++ reg = <0x1>; ++ }; ++ rgmii_phy2: ethernet-phy@2 { ++ reg = <0x2>; ++ }; ++ qsgmii_phy1: ethernet-phy@3 { ++ reg = <0x4>; ++ }; ++ qsgmii_phy2: ethernet-phy@4 { ++ reg = <0x5>; ++ }; ++ qsgmii_phy3: ethernet-phy@5 { ++ reg = <0x6>; ++ }; ++ qsgmii_phy4: ethernet-phy@6 { ++ reg = <0x7>; ++ }; ++ }; ++ ++ mdio@fd000 { ++ aqr105_phy: ethernet-phy@c { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <0x1>; ++ }; ++ }; ++}; -- cgit v1.1