From 799d0dddf608ff012b49282d5832ddd2ef1b916e Mon Sep 17 00:00:00 2001 From: Yutang Jiang Date: Wed, 28 Dec 2016 01:28:02 +0800 Subject: layerscape: add ls2088ardb device support The QorIQ LS2088A processor is built on the Layerscape architecture combining eight ARM A72 processor cores with advanced, high-performance datapath acceleration and network, peripheral interfaces required for networking, telecom, wireless infrastructure, aerospace applications and general-purpose embedded applications. Features summary: - Eight 64-bit ARM v8 Cortex-A72 CPUs - Two 64-bit DDR4 SDRAM memory controller with ECC - One 32-bit DDR3 SDRAM memory controller with ECC - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces - IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc Signed-off-by: Yutang Jiang --- .../8230-layerscape-pci-fix-linkup-issue.patch | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 target/linux/layerscape/patches-4.4/8230-layerscape-pci-fix-linkup-issue.patch (limited to 'target/linux/layerscape/patches-4.4/8230-layerscape-pci-fix-linkup-issue.patch') diff --git a/target/linux/layerscape/patches-4.4/8230-layerscape-pci-fix-linkup-issue.patch b/target/linux/layerscape/patches-4.4/8230-layerscape-pci-fix-linkup-issue.patch new file mode 100644 index 0000000..0feb800 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/8230-layerscape-pci-fix-linkup-issue.patch @@ -0,0 +1,42 @@ +From 1b23a4e0f03063f823ea38065c1106f62a56b408 Mon Sep 17 00:00:00 2001 +From: Mingkai Hu +Date: Mon, 7 Nov 2016 15:03:51 +0800 +Subject: [PATCH 230/238] layerscape/pci: fix linkup issue + +commit e6612d785198abbb39142e2acb63f9bff26ab718 +[context adjustment] + +Signed-off-by: Mingkai Hu +Integrated-by: Zhao Qiang +--- + drivers/pci/host/pci-layerscape.c | 13 +++++++++---- + 1 file changed, 9 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c +index 00feabf..f85ebcf 100644 +--- a/drivers/pci/host/pci-layerscape.c ++++ b/drivers/pci/host/pci-layerscape.c +@@ -158,11 +158,16 @@ static void ls1021_pcie_host_init(struct pcie_port *pp) + static int ls_pcie_link_up(struct pcie_port *pp) + { + struct ls_pcie *pcie = to_ls_pcie(pp); +- u32 state; ++ u32 state, offset; ++ ++ if (of_get_property(pp->dev->of_node, "fsl,lut_diff", NULL)) ++ offset = 0x407fc; ++ else ++ offset = PCIE_LUT_DBG; + +- state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> +- pcie->drvdata->ltssm_shift) & +- LTSSM_STATE_MASK; ++ state = (ioread32(pcie->lut + offset) >> ++ pcie->drvdata->ltssm_shift) & ++ LTSSM_STATE_MASK; + + if (state < LTSSM_PCIE_L0) + return 0; +-- +1.7.9.5 + -- cgit v1.1