From 7950e1b9f47417bcd4b80e4361dfc6dccb000ba7 Mon Sep 17 00:00:00 2001
From: Chuanhong Guo <gch981213@gmail.com>
Date: Thu, 21 Jun 2018 00:56:38 +0800
Subject: ramips: Add support for Phicomm K2G

Specification:
- SoC: MediaTek MT7620A
- Flash: 8 MB
- RAM: 64 MB
- Ethernet: 4 FE ports and 1 GE port (RTL8211F on port 5)
- Wireless radio: MT7620 for 2.4G and MT7612E for 5G, both equipped with external PA.
- UART: 1 x UART on PCB - 57600 8N1

Flash instruction:
The U-boot is based on Ralink SDK so we can flash the firmware using UART:
1. Configure PC with a static IP address and setup an TFTP server.
2. Put the firmware into the tftp directory.
3. Connect the UART line as described on the PCB.
4. Power up the device and press 2, follow the instruction to
   set device and tftp server IP address and input the firmware
   file name. U-boot will then load the firmware and write it into
   the flash.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---
 target/linux/ramips/dts/K2G.dts | 139 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 139 insertions(+)
 create mode 100644 target/linux/ramips/dts/K2G.dts

(limited to 'target/linux/ramips/dts')

diff --git a/target/linux/ramips/dts/K2G.dts b/target/linux/ramips/dts/K2G.dts
new file mode 100644
index 0000000..7aed533
--- /dev/null
+++ b/target/linux/ramips/dts/K2G.dts
@@ -0,0 +1,139 @@
+/dts-v1/;
+
+#include "mt7620a.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	compatible = "phicomm,k2g", "ralink,mt7620a-soc";
+	model = "Phicomm K2G";
+
+	aliases {
+		serial0 = &uartlite;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		led_blue: blue {
+			label = "k2g:blue:status";
+			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+		};
+
+		yellow {
+			label = "k2g:yellow:status";
+			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+		};
+
+		red {
+			label = "k2g:red:status";
+			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <20>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			u-boot@0 {
+				reg = <0x0 0x30000>;
+				read-only;
+			};
+
+			u-boot-env@30000 {
+				reg = <0x30000 0x10000>;
+				read-only;
+			};
+
+			factory: factory@40000 {
+				reg = <0x40000 0x10000>;
+				read-only;
+			};
+
+			permanent_config@50000 {
+				reg = <0x50000 0x50000>;
+				read-only;
+			};
+
+			firmware@a0000 {
+				reg = <0xa0000 0x760000>;
+			};
+		};
+	};
+};
+
+&pinctrl {
+	state_default: pinctrl0 {
+		gpio {
+			ralink,group = "i2c", "uartf";
+			ralink,function = "gpio";
+		};
+	};
+};
+
+&ethernet {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii2_pins &mdio_pins>;
+	mtd-mac-address = <&factory 0x28>;
+	mediatek,portmap = "llllw";
+
+	port@5 {
+		status = "okay";
+		phy-handle = <&phy5>;
+		phy-mode = "rgmii";
+	};
+
+	mdio-bus {
+		status = "okay";
+
+		phy5: ethernet-phy@5 {
+			reg = <5>;
+			phy-mode = "rgmii";
+		};
+	};
+};
+
+&pcie {
+	status = "okay";
+
+	pcie-bridge {
+		mt76@0,0 {
+			reg = <0x0000 0 0 0 0>;
+			device_type = "pci";
+			mediatek,mtd-eeprom = <&factory 0x8000>;
+			ieee80211-freq-limit = <5000000 6000000>;
+		};
+	};
+};
+
+&wmac {
+	ralink,mtd-eeprom = <&factory 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pa_pins>;
+};
-- 
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