From c957af0a0f6a2c45b9b3c84f45f4a3aa44d293c6 Mon Sep 17 00:00:00 2001 From: Zoltan Herpai Date: Wed, 5 Feb 2014 08:42:28 +0000 Subject: sunxi: initial 3.13 support Signed-off-by: Zoltan HERPAI SVN-Revision: 39471 --- ...-sun5i-timer-add-support-for-reset-ctrler.patch | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 target/linux/sunxi/patches-3.13/200-sun5i-timer-add-support-for-reset-ctrler.patch (limited to 'target/linux/sunxi/patches-3.13/200-sun5i-timer-add-support-for-reset-ctrler.patch') diff --git a/target/linux/sunxi/patches-3.13/200-sun5i-timer-add-support-for-reset-ctrler.patch b/target/linux/sunxi/patches-3.13/200-sun5i-timer-add-support-for-reset-ctrler.patch new file mode 100644 index 0000000..c13d991 --- /dev/null +++ b/target/linux/sunxi/patches-3.13/200-sun5i-timer-add-support-for-reset-ctrler.patch @@ -0,0 +1,69 @@ +From 99489f45debd07f6e1cfa36f5c9890409714518d Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Fri, 20 Dec 2013 22:41:08 +0100 +Subject: [PATCH] clocksource: sun5i: Add support for reset controller + +The Allwinner A31 that uses this timer has the timer IP asserted in reset. +Add an optional reset property to the DT, and deassert the timer from reset if +it's there. + +Signed-off-by: Maxime Ripard +--- + .../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt | 4 ++++ + drivers/clocksource/timer-sun5i.c | 6 ++++++ + 2 files changed, 10 insertions(+) + +diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt +index 7c26154..27cfc7d 100644 +--- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt ++++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt +@@ -9,6 +9,9 @@ Required properties: + one) + - clocks: phandle to the source clock (usually the AHB clock) + ++Optionnal properties: ++- resets: phandle to a reset controller asserting the timer ++ + Example: + + timer@01c60000 { +@@ -19,4 +22,5 @@ timer@01c60000 { + <0 53 1>, + <0 54 1>; + clocks = <&ahb1_gates 19>; ++ resets = <&ahb1rst 19>; + }; +diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c +index bddc522..f74d75e 100644 +--- a/drivers/clocksource/timer-sun5i.c ++++ b/drivers/clocksource/timer-sun5i.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -143,6 +144,7 @@ static u32 sun5i_timer_sched_read(void) + + static void __init sun5i_timer_init(struct device_node *node) + { ++ struct reset_control *rstc; + unsigned long rate; + struct clk *clk; + int ret, irq; +@@ -162,6 +164,10 @@ static void __init sun5i_timer_init(struct device_node *node) + clk_prepare_enable(clk); + rate = clk_get_rate(clk); + ++ rstc = of_reset_control_get(node, NULL); ++ if (!IS_ERR(rstc)) ++ reset_control_deassert(rstc); ++ + writel(~0, timer_base + TIMER_INTVAL_LO_REG(1)); + writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, + timer_base + TIMER_CTL_REG(1)); +-- +1.8.5.1 + -- cgit v1.1