From 05e32e9dc84ee96728596c0b8b86de7eae8de229 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sun, 21 Apr 2013 15:38:56 +0200 Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses --- arch/mips/bcm63xx/irq.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,9 @@ static void __internal_irq_mask_64(unsig static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused; static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; +static DEFINE_SPINLOCK(ipic_lock); +static DEFINE_SPINLOCK(epic_lock); + #ifndef BCMCPU_RUNTIME_DETECT #ifdef CONFIG_BCM63XX_CPU_3368 #define irq_stat_reg0 PERF_IRQSTAT_3368_REG @@ -324,8 +328,10 @@ void __dispatch_internal_##width(int cpu u32 irq_stat_addr = get_irq_stat_addr(cpu); \ u32 irq_mask_addr = get_irq_mask_addr(cpu); \ int *next = &i[cpu]; \ + unsigned long flags; \ \ /* read registers in reverse order */ \ + spin_lock_irqsave(&ipic_lock, flags); \ for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ u32 val; \ \ @@ -336,6 +342,7 @@ void __dispatch_internal_##width(int cpu if (val) \ irqs_pending = true; \ } \ + spin_unlock_irqrestore(&ipic_lock, flags); \ \ if (!irqs_pending) \ return; \ @@ -357,10 +364,13 @@ static void __internal_irq_mask_##width( unsigned reg = (irq / 32) ^ (width/32 - 1); \ unsigned bit = irq & 0x1f; \ u32 irq_mask_addr = get_irq_mask_addr(0); \ + unsigned long flags; \ \ + spin_lock_irqsave(&ipic_lock, flags); \ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ val &= ~(1 << bit); \ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ + spin_unlock_irqrestore(&ipic_lock, flags); \ } \ \ static void __internal_irq_unmask_##width(unsigned int irq) \ @@ -369,10 +379,13 @@ static void __internal_irq_unmask_##widt unsigned reg = (irq / 32) ^ (width/32 - 1); \ unsigned bit = irq & 0x1f; \ u32 irq_mask_addr = get_irq_mask_addr(0); \ + unsigned long flags; \ \ + spin_lock_irqsave(&ipic_lock, flags); \ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ val |= (1 << bit); \ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ + spin_unlock_irqrestore(&ipic_lock, flags); \ } BUILD_IPIC_INTERNAL(32); @@ -431,8 +444,10 @@ static void bcm63xx_external_irq_mask(st { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; + unsigned long flags; regaddr = get_ext_irq_perf_reg(irq); + spin_lock_irqsave(&epic_lock, flags); reg = bcm_perf_readl(regaddr); if (BCMCPU_IS_6348()) @@ -441,6 +456,8 @@ static void bcm63xx_external_irq_mask(st reg &= ~EXTIRQ_CFG_MASK(irq % 4); bcm_perf_writel(reg, regaddr); + spin_unlock_irqrestore(&epic_lock, flags); + if (is_ext_irq_cascaded) internal_irq_mask(irq + ext_irq_start); } @@ -449,8 +466,10 @@ static void bcm63xx_external_irq_unmask( { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; + unsigned long flags; regaddr = get_ext_irq_perf_reg(irq); + spin_lock_irqsave(&epic_lock, flags); reg = bcm_perf_readl(regaddr); if (BCMCPU_IS_6348()) @@ -459,6 +478,7 @@ static void bcm63xx_external_irq_unmask( reg |= EXTIRQ_CFG_MASK(irq % 4); bcm_perf_writel(reg, regaddr); + spin_unlock_irqrestore(&epic_lock, flags); if (is_ext_irq_cascaded) internal_irq_unmask(irq + ext_irq_start); @@ -468,8 +488,10 @@ static void bcm63xx_external_irq_clear(s { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; + unsigned long flags; regaddr = get_ext_irq_perf_reg(irq); + spin_lock_irqsave(&epic_lock, flags); reg = bcm_perf_readl(regaddr); if (BCMCPU_IS_6348()) @@ -478,6 +500,7 @@ static void bcm63xx_external_irq_clear(s reg |= EXTIRQ_CFG_CLEAR(irq % 4); bcm_perf_writel(reg, regaddr); + spin_unlock_irqrestore(&epic_lock, flags); } static int bcm63xx_external_irq_set_type(struct irq_data *d, @@ -486,6 +509,7 @@ static int bcm63xx_external_irq_set_type unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; int levelsense, sense, bothedge; + unsigned long flags; flow_type &= IRQ_TYPE_SENSE_MASK; @@ -520,6 +544,7 @@ static int bcm63xx_external_irq_set_type } regaddr = get_ext_irq_perf_reg(irq); + spin_lock_irqsave(&epic_lock, flags); reg = bcm_perf_readl(regaddr); irq %= 4; @@ -564,6 +589,7 @@ static int bcm63xx_external_irq_set_type } bcm_perf_writel(reg, regaddr); + spin_unlock_irqrestore(&epic_lock, flags); irqd_set_trigger_type(d, flow_type); if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))