path: root/package/boot/uboot-layerscape/patches/0049-DNCPE-296-PFE-reset-woraround-fix.patch

From 1b9cf577511123dd05e1d3b1fe7fd5db43b6097f Mon Sep 17 00:00:00 2001
From: Anji J <anji.jagarlmudi@freescale.com>
Date: Wed, 25 May 2016 13:40:13 +0530
Subject: [PATCH 49/93] DNCPE-296 PFE reset woraround fix

- Linux driver depends on U-boot TMU initialization,
  but U-boot tmu initialization is not as expected by Linux driver.
- Align U-boot TMU initialization with Linux driver
- LLM base address in DDR changed to match with Linux driver expectation.
- Remove unwanted pfe_mod.h
- Start PFE/network at bootup time.
---
 common/cmd_pfe_commands.c              |    9 +-
 drivers/net/pfe_eth/pfe.c              |   16 ++--
 drivers/net/pfe_eth/pfe/cbus/tmu_csr.h |    7 ++
 drivers/net/pfe_eth/pfe_eth.h          |    9 +-
 drivers/net/pfe_eth/pfe_mod.h          |  140 --------------------------------
 include/configs/ls1012a_common.h       |    1 -
 6 files changed, 24 insertions(+), 158 deletions(-)
 delete mode 100644 drivers/net/pfe_eth/pfe_mod.h

diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
index 0e22097..ca479d7 100644
--- a/common/cmd_pfe_commands.c
+++ b/common/cmd_pfe_commands.c
@@ -932,7 +932,7 @@ static void send_dummy_pkt_to_hif(void)
 	/*Allocate BMU2 buffer */
 	buf = readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL);
 
-	printf("Sending a dummy pkt to HIF %x\n", buf);
+	debug("Sending a dummy pkt to HIF %x\n", buf);
 	buf += 0x80;
 	memcpy((void *)DDR_PFE_TO_VIRT(buf), dummy_pkt, sizeof(dummy_pkt));
 	/*Write length and pkt to TMU*/
@@ -945,14 +945,13 @@ static void pfe_command_stop(int argc, char * const argv[])
 {
 	int id;
 	u32 rx_status;
-	printf("Stopping PFE \n");
+	printf("Stopping PFE... \n");
 
 	/*Mark all descriptors as LAST_BD */
 	hif_rx_desc_disable();
 
 	/*If HIF Rx BDP is busy send a dummy packet */
 	rx_status = readl(HIF_RX_STATUS);
-	printf("rx_status %x %x\n",rx_status, BDP_CSR_RX_DMA_ACTV);
 	if(rx_status & BDP_CSR_RX_DMA_ACTV)
 		send_dummy_pkt_to_hif();
 	udelay(10);
@@ -964,12 +963,10 @@ static void pfe_command_stop(int argc, char * const argv[])
 
 	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
 	{
-		printf("Stop %d\n", id);
 		/*Inform PE to stop */
 		pe_dmem_write(id, cpu_to_be32(1), PEMBOX_ADDR_CLASS, 4);
 		udelay(10);
 
-		printf("Reading %d\n", id);
 		/*Read status */
 		if(!pe_dmem_read(id, PEMBOX_ADDR_CLASS+4, 4))
 			printf("Failed to stop PE%d\n", id);
@@ -979,12 +976,10 @@ static void pfe_command_stop(int argc, char * const argv[])
 	{
 		if(id == TMU2_ID) continue;
 
-		printf("Stop %d\n", id);
 		/*Inform PE to stop */
 		pe_dmem_write(id, 1, PEMBOX_ADDR_TMU, 4);
 		udelay(10);
 
-		printf("Reading %d\n", id);
 		/*Read status */
 		if(!pe_dmem_read(id, PEMBOX_ADDR_TMU+4, 4))
 			printf("Failed to stop PE%d\n", id);
diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
index 3b5570a..2c31cad 100644
--- a/drivers/net/pfe_eth/pfe.c
+++ b/drivers/net/pfe_eth/pfe.c
@@ -1489,17 +1489,16 @@ void tmu_init(TMU_CFG *cfg)
 	writel(0x3FF,	TMU_TDQ2_SCH_CTRL);
 #endif
 	writel(0x3FF,	TMU_TDQ3_SCH_CTRL);
-	
-	
+
 	if (PLL_CLK_EN == 0)
 		writel(0x0,	TMU_PE_SYS_CLK_RATIO);	// Clock ratio: for 1:1 the value is 0
 	else
 		writel(0x1,	TMU_PE_SYS_CLK_RATIO);	// Clock ratio: for 1:2 the value is 1
 
-	//printf("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
+	debug("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
 	writel(cfg->llm_base_addr,	TMU_LLM_BASE_ADDR);	// Extra packet pointers will be stored from this address onwards
-	
-	//printf("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
+
+	debug("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
 	writel(cfg->llm_queue_len,	TMU_LLM_QUE_LEN);
 	writel(5,			TMU_TDQ_IIFG_CFG);
 	writel(DDR_BUF_SIZE,		TMU_BMU_BUF_SIZE);
@@ -1531,7 +1530,12 @@ void tmu_init(TMU_CFG *cfg)
 			u32 qmax;
 			writel((phyno << 8) | q, TMU_TEQ_CTRL);
 			writel(1 << 22, TMU_TEQ_QCFG);
-			qmax = ((phyno == 3) || (q < 8)) ? 255 : 127;
+
+			if (phyno == 3)
+				qmax = DEFAULT_TMU3_QDEPTH;
+			else
+				qmax = (q == 0) ? DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH;
+
 			writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
 			writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
 		}
diff --git a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
index cbcbb1f..64fad04 100644
--- a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
+++ b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
@@ -93,10 +93,17 @@
 #define MEM_INIT_DONE	(1 << 7)
 #define LLM_INIT	(1 << 8)
 #define LLM_INIT_DONE	(1 << 9)
+#define ECC_MEM_INIT_DONE	(1<<10)
 
 typedef struct {
 	u32 llm_base_addr;
 	u32 llm_queue_len;
 } TMU_CFG;
 
+/* Not HW related for pfe_ctrl / pfe common defines */
+#define DEFAULT_MAX_QDEPTH	80
+#define DEFAULT_Q0_QDEPTH	511 //We keep one large queue for host tx qos
+#define DEFAULT_TMU3_QDEPTH	127
+
+
 #endif /* _TMU_CSR_H_ */
diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
index dfcc00e..c16b8c0 100644
--- a/drivers/net/pfe_eth/pfe_eth.h
+++ b/drivers/net/pfe_eth/pfe_eth.h
@@ -39,11 +39,8 @@
 #define BMU2_BUF_COUNT		(3 * SZ_1K)
 #define BMU2_DDR_SIZE		(DDR_BUF_SIZE * BMU2_BUF_COUNT)
 
-#define TMU_LLM_BASEADDR	(BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
-#define TMU_LLM_QUEUE_LEN	(16 * 256)			/**< Must be power of two and at least 16 * 8 = 128 bytes */
-#define TMU_LLM_SIZE		(4 * 16 * TMU_LLM_QUEUE_LEN)	/**< (4 TMU's x 16 queues x queue_len) */
 
-#define HIF_RX_PKT_DDR_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
+#define HIF_RX_PKT_DDR_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
 #define HIF_RX_PKT_DDR_SIZE     (HIF_RX_DESC_NT * DDR_BUF_SIZE)
 #define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
 #define HIF_TX_PKT_DDR_SIZE     (HIF_TX_DESC_NT * DDR_BUF_SIZE)
@@ -72,6 +69,10 @@
 #define TMU_DDR_DATA_BASEADDR	(CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
 #define TMU_DDR_DATA_SIZE	(32 * SZ_1K)
 
+#define TMU_LLM_BASEADDR	(TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
+#define TMU_LLM_QUEUE_LEN	(16 * 256)			/**< Must be power of two and at least 16 * 8 = 128 bytes */
+#define TMU_LLM_SIZE		(4 * 16 * TMU_LLM_QUEUE_LEN)	/**< (4 TMU's x 16 queues x queue_len) */
+
 //#define ROUTE_TABLE_BASEADDR	(TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
 #define ROUTE_TABLE_BASEADDR	0x800000
 #define ROUTE_TABLE_HASH_BITS_MAX	15	/**< 32K entries */
diff --git a/drivers/net/pfe_eth/pfe_mod.h b/drivers/net/pfe_eth/pfe_mod.h
deleted file mode 100644
index 9436b72..0000000
--- a/drivers/net/pfe_eth/pfe_mod.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- *  (C) Copyright 2011
- *  Author : Mindspeed Technologes
- *  
- *  See file CREDITS for list of people who contributed to this
- *  project.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License as
- *  published by the Free Software Foundation; either version 2 of
- *  the License, or (at your option) any later version.
- *  
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *  
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- *  MA 02111-1307 USA
- * */
-
-
-#ifndef _PFE_MOD_H_
-#define _PFE_MOD_H_
-
-#include <linux/device.h>
-
-#include "pfe/pfe.h"
-#include "pfe/cbus.h"
-#include "pfe/cbus/bmu.h"
-
-#include "pfe_driver.h"
-
-struct pfe;
-
-
-struct pfe {
-	unsigned long ddr_phys_baseaddr;
-	void *ddr_baseaddr;
-	void *cbus_baseaddr;
-	void *apb_baseaddr;
-	void *iram_baseaddr;
-	int hif_irq;
-	struct device *dev;
-	struct pci_dev *pdev;
-
-#if 0
-	struct pfe_ctrl ctrl;
-	struct pfe_hif hif;
-	struct pfe_eth eth;
-#endif
-};
-
-extern struct pfe *pfe;
-
-int pfe_probe(struct pfe *pfe);
-int pfe_remove(struct pfe *pfe);
-
-#ifndef SZ_1K
-#define SZ_1K 1024
-#endif
-
-#ifndef SZ_1M
-#define SZ_1M (1024 * 1024)
-#endif
-
-/* DDR Mapping */
-#if !defined(CONFIG_PLATFORM_PCI)
-#define UTIL_CODE_BASEADDR	0
-#define UTIL_CODE_SIZE		(128 * SZ_1K)
-#define UTIL_DDR_DATA_BASEADDR	(UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
-#define UTIL_DDR_DATA_SIZE	(64 * SZ_1K)
-#define CLASS_DDR_DATA_BASEADDR	(UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
-#define CLASS_DDR_DATA_SIZE	(32 * SZ_1K)
-#define TMU_DDR_DATA_BASEADDR	(CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
-#define TMU_DDR_DATA_SIZE	(32 * SZ_1K)
-#define ROUTE_TABLE_BASEADDR	(TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
-#define ROUTE_TABLE_HASH_BITS	15	/**< 32K entries */
-#define ROUTE_TABLE_SIZE	((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
-#define BMU2_DDR_BASEADDR	(ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
-#define BMU2_BUF_COUNT		(4096 - 256)			/**< This is to get a total DDR size of 12MiB */
-#define BMU2_DDR_SIZE		(DDR_BUF_SIZE * BMU2_BUF_COUNT)
-#define TMU_LLM_BASEADDR	(BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
-#define TMU_LLM_QUEUE_LEN	(16 * 256)			/**< Must be power of two and at least 16 * 8 = 128 bytes */
-#define TMU_LLM_SIZE		(4 * 16 * TMU_LLM_QUEUE_LEN)	/**< (4 TMU's x 16 queues x queue_len) */
-
-#if (TMU_LLM_BASEADDR + TMU_LLM_SIZE) > 0xC00000
-#error DDR mapping above 12MiB
-#endif
-
-#else
-
-#define UTIL_CODE_BASEADDR	0
-#if defined(CONFIG_UTIL_PE_DISABLED)
-#define UTIL_CODE_SIZE		(0 * SZ_1K)
-#else
-#define UTIL_CODE_SIZE		(8 * SZ_1K)
-#endif
-#define UTIL_DDR_DATA_BASEADDR	(UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
-#define UTIL_DDR_DATA_SIZE	(0 * SZ_1K)
-#define CLASS_DDR_DATA_BASEADDR	(UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
-#define CLASS_DDR_DATA_SIZE	(0 * SZ_1K)
-#define TMU_DDR_DATA_BASEADDR	(CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
-#define TMU_DDR_DATA_SIZE	(0 * SZ_1K)
-#define ROUTE_TABLE_BASEADDR	(TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
-#define ROUTE_TABLE_HASH_BITS	5	/**< 32 entries */
-#define ROUTE_TABLE_SIZE	((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
-#define BMU2_DDR_BASEADDR	(ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
-#define BMU2_BUF_COUNT		8
-#define BMU2_DDR_SIZE		(DDR_BUF_SIZE * BMU2_BUF_COUNT)
-#define TMU_LLM_BASEADDR	(BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
-#define TMU_LLM_QUEUE_LEN	(16 * 8)			/**< Must be power of two and at least 16 * 8 = 128 bytes */
-#define TMU_LLM_SIZE		(4 * 16 * TMU_LLM_QUEUE_LEN)	/**< (4 TMU's x 16 queues x queue_len) */
-#define HIF_DESC_BASEADDR	(TMU_LLM_BASEADDR + TMU_LLM_SIZE)
-#define HIF_RX_DESC_SIZE	(16*HIF_RX_DESC_NT)
-#define HIF_TX_DESC_SIZE	(16*HIF_TX_DESC_NT)
-#define HIF_DESC_SIZE		(HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
-#define HIF_RX_PKT_DDR_BASEADDR	(HIF_DESC_BASEADDR + HIF_DESC_SIZE)
-#define HIF_RX_PKT_DDR_SIZE	(HIF_RX_DESC_NT * DDR_BUF_SIZE)
-#define HIF_TX_PKT_DDR_BASEADDR	(HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
-#define HIF_TX_PKT_DDR_SIZE	(HIF_TX_DESC_NT * DDR_BUF_SIZE)
-#define ROUTE_BASEADDR		(HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
-#define ROUTE_SIZE		(2 * CLASS_ROUTE_SIZE)
-
-#if (ROUTE_BASEADDR + ROUTE_SIZE) > 0x10000
-#error DDR mapping above 64KiB
-#endif
-
-#define PFE_HOST_TO_PCI(addr)	(((u32)addr)- ((u32)DDR_BASE_ADDR))
-#define PFE_PCI_TO_HOST(addr)	(((u32)addr)+ ((u32)DDR_BASE_ADDR))
-#endif
-
-/* LMEM Mapping */
-#define BMU1_LMEM_BASEADDR	0
-#define BMU1_BUF_COUNT		256
-#define BMU1_LMEM_SIZE		(LMEM_BUF_SIZE * BMU1_BUF_COUNT)
-
-#endif /* _PFE_MOD_H */
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 3c4ab6c..57fc057 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -113,7 +113,6 @@
 #define CONFIG_FSL_PPFE
 
 #ifdef CONFIG_FSL_PPFE
-#define CONFIG_CMD_PFE_START 
 #define CONFIG_CMD_PFE_COMMANDS
 #define CONFIG_UTIL_PE_DISABLED
 
-- 
1.7.9.5