summaryrefslogtreecommitdiff
path: root/package/ltq-dsl/src/lantiq_mei.c
blob: 062b0286f92514ec45e069c36b4c5b775ad8d358 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
/******************************************************************************

                               Copyright (c) 2009
                            Infineon Technologies AG
                     Am Campeon 1-12; 81726 Munich, Germany

  For licensing information, see the file 'LICENSE' in the root folder of
  this software module.

******************************************************************************/

/*!
  \defgroup AMAZON_S_MEI Amazon-S MEI Driver Module
  \brief Amazon-S MEI driver module
 */

/*!
  \defgroup Internal Compile Parametere
  \ingroup AMAZON_S_MEI
  \brief exported functions for other driver use
 */

/*!
  \file amazon_s_mei_bsp.c
  \ingroup AMAZON_S_MEI
  \brief Amazon-S MEI driver file
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/version.h>
#include <generated/utsrelease.h>
#include <linux/types.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/proc_fs.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/sched.h>
#include <asm/uaccess.h>
#include <asm/hardirq.h>

#include <lantiq.h>
#include <lantiq_regs.h>
#include "ifxmips_atm.h"
#define IFX_MEI_BSP
#include "ifxmips_mei_interface.h"

/*#define LQ_RCU_RST                   IFX_RCU_RST_REQ
#define LQ_RCU_RST_REQ_ARC_JTAG      IFX_RCU_RST_REQ_ARC_JTAG
#define LQ_RCU_RST_REQ_DFE		  IFX_RCU_RST_REQ_DFE
#define LQ_RCU_RST_REQ_AFE		  IFX_RCU_RST_REQ_AFE
#define IFXMIPS_FUSE_BASE_ADDR            IFX_FUSE_BASE_ADDR
#define IFXMIPS_ICU_IM0_IER               IFX_ICU_IM0_IER
#define IFXMIPS_ICU_IM2_IER               IFX_ICU_IM2_IER
#define LQ_MEI_INT                   IFX_MEI_INT
#define LQ_MEI_DYING_GASP_INT        IFX_MEI_DYING_GASP_INT
#define LQ_MEI_BASE_ADDR  		  IFX_MEI_SPACE_ACCESS
#define IFXMIPS_PMU_PWDCR		  IFX_PMU_PWDCR
#define IFXMIPS_MPS_CHIPID                IFX_MPS_CHIPID

#define ifxmips_port_reserve_pin 	  ifx_gpio_pin_reserve
#define ifxmips_port_set_dir_in		  ifx_gpio_dir_in_set
#define ifxmips_port_clear_altsel0        ifx_gpio_altsel0_set
#define ifxmips_port_clear_altsel1 	  ifx_gpio_altsel1_clear
#define ifxmips_port_set_open_drain       ifx_gpio_open_drain_clear
#define ifxmips_port_free_pin		  ifx_gpio_pin_free
#define ifxmips_mask_and_ack_irq	  bsp_mask_and_ack_irq
#define IFXMIPS_MPS_CHIPID_VERSION_GET    IFX_MCD_CHIPID_VERSION_GET
#define lq_r32(reg)                        __raw_readl(reg)
#define lq_w32(val, reg)                   __raw_writel(val, reg)
#define lq_w32_mask(clear, set, reg)       lq_w32((lq_r32(reg) & ~clear) | set, reg)
*/

#define LQ_RCU_RST_REQ_DFE		(1 << 7)
#define LQ_RCU_RST_REQ_AFE		(1 << 11)
#define LQ_PMU_PWDCR        ((u32 *)(LQ_PMU_BASE_ADDR + 0x001C))
#define LQ_PMU_PWDSR        ((u32 *)(LQ_PMU_BASE_ADDR + 0x0020))
#define LQ_RCU_RST          ((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
#define LQ_RCU_RST_ALL      0x40000000
#define LQ_ICU_BASE_ADDR    (KSEG1 | 0x1F880200)

#define LQ_ICU_IM0_ISR      ((u32 *)(LQ_ICU_BASE_ADDR + 0x0000))
#define LQ_ICU_IM0_IER      ((u32 *)(LQ_ICU_BASE_ADDR + 0x0008))
#define LQ_ICU_IM0_IOSR     ((u32 *)(LQ_ICU_BASE_ADDR + 0x0010))
#define LQ_ICU_IM0_IRSR     ((u32 *)(LQ_ICU_BASE_ADDR + 0x0018))
#define LQ_ICU_IM0_IMR      ((u32 *)(LQ_ICU_BASE_ADDR + 0x0020))


#define LQ_ICU_IM1_ISR      ((u32 *)(LQ_ICU_BASE_ADDR + 0x0028))
#define LQ_ICU_IM2_ISR      ((u32 *)(LQ_ICU_BASE_ADDR + 0x0050))
#define LQ_ICU_IM3_ISR      ((u32 *)(LQ_ICU_BASE_ADDR + 0x0078))
#define LQ_ICU_IM4_ISR      ((u32 *)(LQ_ICU_BASE_ADDR + 0x00A0))

#define LQ_ICU_OFFSET       (LQ_ICU_IM1_ISR - LQ_ICU_IM0_ISR)
#define LQ_ICU_IM2_IER		(LQ_ICU_IM0_IER + LQ_ICU_OFFSET)

#define IFX_MEI_EMSG(fmt, args...) pr_err("[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)
#define IFX_MEI_DMSG(fmt, args...) pr_debug("[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args)

#define LQ_FUSE_BASE          (KSEG1 + 0x1F107354)

#ifdef CONFIG_LQ_MEI_FW_LOOPBACK
//#define DFE_MEM_TEST
//#define DFE_PING_TEST
#define DFE_ATM_LOOPBACK


#ifdef DFE_ATM_LOOPBACK
#include <asm/ifxmips/ifxmips_mei_fw_loopback.h>
#endif

void dfe_loopback_irq_handler (DSL_DEV_Device_t *pDev);

#endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK

DSL_DEV_Version_t bsp_mei_version = {
	major:	5,
	minor:	0,
	revision:0
};
DSL_DEV_HwVersion_t bsp_chip_info;

#define IFX_MEI_DEVNAME "ifx_mei"
#define BSP_MAX_DEVICES 1

DSL_DEV_MeiError_t DSL_BSP_FWDownload (DSL_DEV_Device_t *, const char *, unsigned long, long *, long *);
DSL_DEV_MeiError_t DSL_BSP_Showtime (DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
DSL_DEV_MeiError_t DSL_BSP_AdslLedInit (DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);
//DSL_DEV_MeiError_t DSL_BSP_AdslLedSet (DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedMode_t);
DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess (DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t*, DSL_uint32_t);
DSL_DEV_MeiError_t DSL_BSP_SendCMV (DSL_DEV_Device_t *, u16 *, int, u16 *);

int DSL_BSP_KernelIoctls (DSL_DEV_Device_t *, unsigned int, unsigned long);

static DSL_DEV_MeiError_t IFX_MEI_RunAdslModem (DSL_DEV_Device_t *);
static DSL_DEV_MeiError_t IFX_MEI_CpuModeSet (DSL_DEV_Device_t *, DSL_DEV_CpuMode_t);
static DSL_DEV_MeiError_t IFX_MEI_DownloadBootCode (DSL_DEV_Device_t *);
static DSL_DEV_MeiError_t IFX_MEI_ArcJtagEnable (DSL_DEV_Device_t *, int);
static DSL_DEV_MeiError_t IFX_MEI_AdslMailboxIRQEnable (DSL_DEV_Device_t *, int);

static int IFX_MEI_GetPage (DSL_DEV_Device_t *, u32, u32, u32, u32 *, u32 *);
static int IFX_MEI_BarUpdate (DSL_DEV_Device_t *, int);

static ssize_t IFX_MEI_Write (DSL_DRV_file_t *, const char *, size_t, loff_t *);
static int IFX_MEI_UserIoctls (DSL_DRV_inode_t *, DSL_DRV_file_t *, unsigned int, unsigned long);
static int IFX_MEI_Open (DSL_DRV_inode_t *, DSL_DRV_file_t *);
static int IFX_MEI_Release (DSL_DRV_inode_t *, DSL_DRV_file_t *);

void AMAZON_SE_MEI_ARC_MUX_Test(void);

#ifdef CONFIG_PROC_FS
static int IFX_MEI_ProcRead (struct file *, char *, size_t, loff_t *);
static ssize_t IFX_MEI_ProcWrite (struct file *, const char *, size_t, loff_t *);

#define PROC_ITEMS 11
#define MEI_DIRNAME "ifxmips_mei"

static struct proc_dir_entry *meidir;
static struct file_operations IFX_MEI_ProcOperations = {
      read:IFX_MEI_ProcRead,
      write:IFX_MEI_ProcWrite,
};
static reg_entry_t regs[BSP_MAX_DEVICES][PROC_ITEMS];   //total items to be monitored by /proc/mei
#define NUM_OF_REG_ENTRY        (sizeof(regs[0])/sizeof(reg_entry_t))
#endif //CONFIG_PROC_FS

void IFX_MEI_ARC_MUX_Test(void);

static int adsl_dummy_ledcallback(void);

int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);

int (*ifx_mei_atm_showtime_exit)(void) = NULL;
EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);

static int (*g_adsl_ledcallback)(void) = adsl_dummy_ledcallback;

static unsigned int g_tx_link_rate[2] = {0};

static void *g_xdata_addr = NULL;

static u32 *mei_arc_swap_buff = NULL;	//  holding swap pages

extern void lq_mask_and_ack_irq(unsigned int irq_nr);
#define MEI_MASK_AND_ACK_IRQ lq_mask_and_ack_irq

#define MEI_MAJOR	105
static int dev_major = MEI_MAJOR;

static struct file_operations bsp_mei_operations = {
      owner:THIS_MODULE,
      open:IFX_MEI_Open,
      release:IFX_MEI_Release,
      write:IFX_MEI_Write,
      unlocked_ioctl:IFX_MEI_UserIoctls,
};

static DSL_DEV_Device_t dsl_devices[BSP_MAX_DEVICES];

static ifx_mei_device_private_t
	sDanube_Mei_Private[BSP_MAX_DEVICES];

static DSL_BSP_EventCallBack_t dsl_bsp_event_callback[DSL_BSP_CB_LAST + 1];

/**
 * Write a value to register
 * This function writes a value to danube register
 *
 * \param  	ul_address	The address to write
 * \param  	ul_data		The value to write
 * \ingroup	Internal
 */
static void
IFX_MEI_LongWordWrite (u32 ul_address, u32 ul_data)
{
	IFX_MEI_WRITE_REGISTER_L (ul_data, ul_address);
	wmb();
	return;
}

/**
 * Write a value to register
 * This function writes a value to danube register
 *
 * \param 	pDev		the device pointer
 * \param  	ul_address	The address to write
 * \param  	ul_data		The value to write
 * \ingroup	Internal
 */
static void
IFX_MEI_LongWordWriteOffset (DSL_DEV_Device_t * pDev, u32 ul_address,
				   u32 ul_data)
{
	IFX_MEI_WRITE_REGISTER_L (ul_data, pDev->base_address + ul_address);
	wmb();
	return;
}

/**
 * Read the danube register
 * This function read the value from danube register
 *
 * \param  	ul_address	The address to write
 * \param  	pul_data	Pointer to the data
 * \ingroup	Internal
 */
static void
IFX_MEI_LongWordRead (u32 ul_address, u32 * pul_data)
{
	*pul_data = IFX_MEI_READ_REGISTER_L (ul_address);
	rmb();
	return;
}

/**
 * Read the danube register
 * This function read the value from danube register
 *
 * \param 	pDev		the device pointer
 * \param  	ul_address	The address to write
 * \param  	pul_data	Pointer to the data
 * \ingroup	Internal
 */
static void
IFX_MEI_LongWordReadOffset (DSL_DEV_Device_t * pDev, u32 ul_address,
				  u32 * pul_data)
{
	*pul_data = IFX_MEI_READ_REGISTER_L (pDev->base_address + ul_address);
	rmb();
	return;
}

/**
 * Write several DWORD datas to ARC memory via ARC DMA interface
 * This function writes several DWORD datas to ARC memory via DMA interface.
 *
 * \param 	pDev		the device pointer
 * \param  	destaddr	The address to write
 * \param  	databuff	Pointer to the data buffer
 * \param  	databuffsize	Number of DWORDs to write
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_DMAWrite (DSL_DEV_Device_t * pDev, u32 destaddr,
			u32 * databuff, u32 databuffsize)
{
	u32 *p = databuff;
	u32 temp;

	if (destaddr & 3)
		return DSL_DEV_MEI_ERR_FAILURE;

	//      Set the write transfer address
	IFX_MEI_LongWordWriteOffset (pDev, ME_DX_AD, destaddr);

	//      Write the data pushed across DMA
	while (databuffsize--) {
		temp = *p;
		if (destaddr == MEI_TO_ARC_MAILBOX)
			MEI_HALF_WORD_SWAP (temp);
		IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DX_DATA, temp);
		p++;
	}

	return DSL_DEV_MEI_ERR_SUCCESS;

}

/**
 * Read several DWORD datas from ARC memory via ARC DMA interface
 * This function reads several DWORD datas from ARC memory via DMA interface.
 *
 * \param 	pDev		the device pointer
 * \param  	srcaddr		The address to read
 * \param  	databuff	Pointer to the data buffer
 * \param  	databuffsize	Number of DWORDs to read
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_DMARead (DSL_DEV_Device_t * pDev, u32 srcaddr, u32 * databuff,
		       u32 databuffsize)
{
	u32 *p = databuff;
	u32 temp;

	if (srcaddr & 3)
		return DSL_DEV_MEI_ERR_FAILURE;

	//      Set the read transfer address
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DX_AD, srcaddr);

	//      Read the data popped across DMA
	while (databuffsize--) {
		IFX_MEI_LongWordReadOffset (pDev, (u32) ME_DX_DATA, &temp);
		if (databuff == (u32 *) DSL_DEV_PRIVATE(pDev)->CMV_RxMsg)	// swap half word
			MEI_HALF_WORD_SWAP (temp);
		*p = temp;
		p++;
	}

	return DSL_DEV_MEI_ERR_SUCCESS;

}

/**
 * Switch the ARC control mode
 * This function switchs the ARC control mode to JTAG mode or MEI mode
 *
 * \param 	pDev		the device pointer
 * \param  	mode		The mode want to switch: JTAG_MASTER_MODE or MEI_MASTER_MODE.
 * \ingroup	Internal
 */
static void
IFX_MEI_ControlModeSet (DSL_DEV_Device_t * pDev, int mode)
{
	u32 temp = 0x0;

	IFX_MEI_LongWordReadOffset (pDev, (u32) ME_DBG_MASTER, &temp);
	switch (mode) {
	case JTAG_MASTER_MODE:
		temp &= ~(HOST_MSTR);
		break;
	case MEI_MASTER_MODE:
		temp |= (HOST_MSTR);
		break;
	default:
		IFX_MEI_EMSG ("IFX_MEI_ControlModeSet: unkonwn mode [%d]\n", mode);
		return;
	}
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_MASTER, temp);
}

/**
 * Disable ARC to MEI interrupt
 *
 * \param 	pDev		the device pointer
 * \ingroup	Internal
 */
static void
IFX_MEI_IRQDisable (DSL_DEV_Device_t * pDev)
{
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_MASK,  0x0);
}

/**
 * Eable ARC to MEI interrupt
 *
 * \param 	pDev		the device pointer
 * \ingroup	Internal
 */
static void
IFX_MEI_IRQEnable (DSL_DEV_Device_t * pDev)
{
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_MASK, MSGAV_EN);
}

/**
 * Poll for transaction complete signal
 * This function polls and waits for transaction complete signal.
 *
 * \param 	pDev		the device pointer
 * \ingroup	Internal
 */
static void
meiPollForDbgDone (DSL_DEV_Device_t * pDev)
{
	u32 query = 0;
	int i = 0;

	while (i < WHILE_DELAY) {
		IFX_MEI_LongWordReadOffset (pDev, (u32) ME_ARC2ME_STAT,  &query);
		query &= (ARC_TO_MEI_DBG_DONE);
		if (query)
			break;
		i++;
		if (i == WHILE_DELAY) {
			IFX_MEI_EMSG ("PollforDbg fail!\n");
		}
	}
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_DBG_DONE);	// to clear this interrupt
}

/**
 * ARC Debug Memory Access for a single DWORD reading.
 * This function used for direct, address-based access to ARC memory.
 *
 * \param 	pDev		the device pointer
 * \param  	DEC_mode	ARC memory space to used
 * \param  	address	  	Address to read
 * \param  	data	  	Pointer to data
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
_IFX_MEI_DBGLongWordRead (DSL_DEV_Device_t * pDev, u32 DEC_mode,
				u32 address, u32 * data)
{
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DECODE, DEC_mode);
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_RD_AD, address);
	meiPollForDbgDone (pDev);
	IFX_MEI_LongWordReadOffset (pDev, (u32) ME_DBG_DATA, data);
	return DSL_DEV_MEI_ERR_SUCCESS;
}

/**
 * ARC Debug Memory Access for a single DWORD writing.
 * This function used for direct, address-based access to ARC memory.
 *
 * \param 	pDev		the device pointer
 * \param  	DEC_mode	ARC memory space to used
 * \param  	address	  	The address to write
 * \param  	data	  	The data to write
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
_IFX_MEI_DBGLongWordWrite (DSL_DEV_Device_t * pDev, u32 DEC_mode,
				 u32 address, u32 data)
{
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DECODE, DEC_mode);
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_WR_AD, address);
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DATA, data);
	meiPollForDbgDone (pDev);
	return DSL_DEV_MEI_ERR_SUCCESS;
}

/**
 * ARC Debug Memory Access for writing.
 * This function used for direct, address-based access to ARC memory.
 *
 * \param 	pDev		the device pointer
 * \param  	destaddr	The address to read
 * \param  	databuffer  	Pointer to data
 * \param	databuffsize	The number of DWORDs to read
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */

static DSL_DEV_MeiError_t
IFX_MEI_DebugWrite (DSL_DEV_Device_t * pDev, u32 destaddr,
			  u32 * databuff, u32 databuffsize)
{
	u32 i;
	u32 temp = 0x0;
	u32 address = 0x0;
	u32 *buffer = 0x0;

	//      Open the debug port before DMP memory write
	IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);

	//      For the requested length, write the address and write the data
	address = destaddr;
	buffer = databuff;
	for (i = 0; i < databuffsize; i++) {
		temp = *buffer;
		_IFX_MEI_DBGLongWordWrite (pDev, ME_DBG_DECODE_DMP1_MASK, address, temp);
		address += 4;
		buffer++;
	}

	//      Close the debug port after DMP memory write
	IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);

	return DSL_DEV_MEI_ERR_SUCCESS;
}

/**
 * ARC Debug Memory Access for reading.
 * This function used for direct, address-based access to ARC memory.
 *
 * \param 	pDev		the device pointer
 * \param  	srcaddr	  	The address to read
 * \param  	databuffer  	Pointer to data
 * \param	databuffsize	The number of DWORDs to read
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_DebugRead (DSL_DEV_Device_t * pDev, u32 srcaddr, u32 * databuff, u32 databuffsize)
{
	u32 i;
	u32 temp = 0x0;
	u32 address = 0x0;
	u32 *buffer = 0x0;

	//      Open the debug port before DMP memory read
	IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);

	//      For the requested length, write the address and read the data
	address = srcaddr;
	buffer = databuff;
	for (i = 0; i < databuffsize; i++) {
		_IFX_MEI_DBGLongWordRead (pDev, ME_DBG_DECODE_DMP1_MASK, address, &temp);
		*buffer = temp;
		address += 4;
		buffer++;
	}

	//      Close the debug port after DMP memory read
	IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);

	return DSL_DEV_MEI_ERR_SUCCESS;
}

/**
 * Send a message to ARC MailBox.
 * This function sends a message to ARC Mailbox via ARC DMA interface.
 *
 * \param 	pDev		the device pointer
 * \param  	msgsrcbuffer  	Pointer to message.
 * \param	msgsize		The number of words to write.
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_MailboxWrite (DSL_DEV_Device_t * pDev, u16 * msgsrcbuffer,
			    u16 msgsize)
{
	int i;
	u32 arc_mailbox_status = 0x0;
	u32 temp = 0;
	DSL_DEV_MeiError_t meiMailboxError = DSL_DEV_MEI_ERR_SUCCESS;

	//      Write to mailbox
	meiMailboxError =
		IFX_MEI_DMAWrite (pDev, MEI_TO_ARC_MAILBOX, (u32 *) msgsrcbuffer, msgsize / 2);
	meiMailboxError =
		IFX_MEI_DMAWrite (pDev, MEI_TO_ARC_MAILBOXR, (u32 *) (&temp), 1);

	//      Notify arc that mailbox write completed
	DSL_DEV_PRIVATE(pDev)->cmv_waiting = 1;
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ME2ARC_INT, MEI_TO_ARC_MSGAV);

	i = 0;
	while (i < WHILE_DELAY) {	// wait for ARC to clear the bit
		IFX_MEI_LongWordReadOffset (pDev, (u32) ME_ME2ARC_INT, &arc_mailbox_status);
		if ((arc_mailbox_status & MEI_TO_ARC_MSGAV) != MEI_TO_ARC_MSGAV)
			break;
		i++;
		if (i == WHILE_DELAY) {
			IFX_MEI_EMSG (">>> Timeout waiting for ARC to clear MEI_TO_ARC_MSGAV!!!"
			      " MEI_TO_ARC message size = %d DWORDs <<<\n", msgsize/2);
			meiMailboxError = DSL_DEV_MEI_ERR_FAILURE;
		}
	}

	return meiMailboxError;
}

/**
 * Read a message from ARC MailBox.
 * This function reads a message from ARC Mailbox via ARC DMA interface.
 *
 * \param 	pDev		the device pointer
 * \param  	msgsrcbuffer  	Pointer to message.
 * \param	msgsize		The number of words to read
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_MailboxRead (DSL_DEV_Device_t * pDev, u16 * msgdestbuffer,
			   u16 msgsize)
{
	DSL_DEV_MeiError_t meiMailboxError = DSL_DEV_MEI_ERR_SUCCESS;
	//      Read from mailbox
	meiMailboxError =
		IFX_MEI_DMARead (pDev, ARC_TO_MEI_MAILBOX, (u32 *) msgdestbuffer, msgsize / 2);

	//      Notify arc that mailbox read completed
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV);

	return meiMailboxError;
}

/**
 * Download boot pages to ARC.
 * This function downloads boot pages to ARC.
 *
 * \param 	pDev		the device pointer
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_DownloadBootPages (DSL_DEV_Device_t * pDev)
{
	int boot_loop;
	int page_size;
	u32 dest_addr;

	/*
	 **     DMA the boot code page(s)
	 */

	for (boot_loop = 1;
	     boot_loop <
	     (DSL_DEV_PRIVATE(pDev)->img_hdr-> count); boot_loop++) {
		if ((DSL_DEV_PRIVATE(pDev)-> img_hdr->page[boot_loop].p_size) & BOOT_FLAG) {
			page_size = IFX_MEI_GetPage (pDev, boot_loop,
						       GET_PROG, MAXSWAPSIZE,
						       mei_arc_swap_buff,
						       &dest_addr);
			if (page_size > 0) {
				IFX_MEI_DMAWrite (pDev, dest_addr,
							mei_arc_swap_buff,
							page_size);
			}
		}
		if ((DSL_DEV_PRIVATE(pDev)-> img_hdr->page[boot_loop].d_size) & BOOT_FLAG) {
			page_size = IFX_MEI_GetPage (pDev, boot_loop,
						       GET_DATA, MAXSWAPSIZE,
						       mei_arc_swap_buff,
						       &dest_addr);
			if (page_size > 0) {
				IFX_MEI_DMAWrite (pDev, dest_addr,
							mei_arc_swap_buff,
							page_size);
			}
		}
	}
	return DSL_DEV_MEI_ERR_SUCCESS;
}

/**
 * Initial efuse rar.
 **/
static void
IFX_MEI_FuseInit (DSL_DEV_Device_t * pDev)
{
	u32 data = 0;
	IFX_MEI_DMAWrite (pDev, IRAM0_BASE, &data, 1);
	IFX_MEI_DMAWrite (pDev, IRAM0_BASE + 4, &data, 1);
	IFX_MEI_DMAWrite (pDev, IRAM1_BASE, &data, 1);
	IFX_MEI_DMAWrite (pDev, IRAM1_BASE + 4, &data, 1);
	IFX_MEI_DMAWrite (pDev, BRAM_BASE, &data, 1);
	IFX_MEI_DMAWrite (pDev, BRAM_BASE + 4, &data, 1);
	IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE, &data, 1);
	IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE + 4, &data, 1);
}

/**
 * efuse rar program
 **/
static void
IFX_MEI_FuseProg (DSL_DEV_Device_t * pDev)
{
	u32 reg_data, fuse_value;
	int i = 0;

	IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, &reg_data);
	while ((reg_data & 0x10000000) == 0) {
		IFX_MEI_LongWordRead ((u32) LQ_RCU_RST,  &reg_data);
		i++;
		/* 0x4000 translate to  about 16 ms@111M, so should be enough */
		if (i == 0x4000)
			return;
	}
	// STEP a: Prepare memory for external accesses
	// Write fuse_en bit24
	IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, &reg_data);
	IFX_MEI_LongWordWrite ((u32) LQ_RCU_RST, reg_data | (1 << 24));

	IFX_MEI_FuseInit (pDev);
	for (i = 0; i < 4; i++) {
		IFX_MEI_LongWordRead ((u32) (LQ_FUSE_BASE) + i * 4, &fuse_value);
		switch (fuse_value & 0xF0000) {
		case 0x80000:
			reg_data = ((fuse_value & RX_DILV_ADDR_BIT_MASK) |
				 (RX_DILV_ADDR_BIT_MASK + 0x1));
			IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE, &reg_data, 1);
			break;
		case 0x90000:
			reg_data = ((fuse_value & RX_DILV_ADDR_BIT_MASK) |
				 (RX_DILV_ADDR_BIT_MASK + 0x1));
			IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE + 4, &reg_data, 1);
			break;
		case 0xA0000:
			reg_data = ((fuse_value & IRAM0_ADDR_BIT_MASK) |
				 (IRAM0_ADDR_BIT_MASK + 0x1));
			IFX_MEI_DMAWrite (pDev, IRAM0_BASE, &reg_data, 1);
			break;
		case 0xB0000:
			reg_data = ((fuse_value & IRAM0_ADDR_BIT_MASK) |
				 (IRAM0_ADDR_BIT_MASK + 0x1));
			IFX_MEI_DMAWrite (pDev, IRAM0_BASE + 4, &reg_data, 1);
			break;
		case 0xC0000:
			reg_data = ((fuse_value & IRAM1_ADDR_BIT_MASK) |
				 (IRAM1_ADDR_BIT_MASK + 0x1));
			IFX_MEI_DMAWrite (pDev, IRAM1_BASE, &reg_data, 1);
			break;
		case 0xD0000:
			reg_data = ((fuse_value & IRAM1_ADDR_BIT_MASK) |
				 (IRAM1_ADDR_BIT_MASK + 0x1));
			IFX_MEI_DMAWrite (pDev, IRAM1_BASE + 4, &reg_data, 1);
			break;
		case 0xE0000:
			reg_data = ((fuse_value & BRAM_ADDR_BIT_MASK) |
				 (BRAM_ADDR_BIT_MASK + 0x1));
			IFX_MEI_DMAWrite (pDev, BRAM_BASE, &reg_data, 1);
			break;
		case 0xF0000:
			reg_data = ((fuse_value & BRAM_ADDR_BIT_MASK) |
				 (BRAM_ADDR_BIT_MASK + 0x1));
			IFX_MEI_DMAWrite (pDev, BRAM_BASE + 4, &reg_data, 1);
			break;
		default:	// PPE efuse
			break;
		}
	}
	IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, &reg_data);
	IFX_MEI_LongWordWrite ((u32) LQ_RCU_RST, reg_data & ~(1 << 24));
	IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, &reg_data);
}

/**
 * Enable DFE Clock
 * This function enables DFE Clock
 *
 * \param 	pDev		the device pointer
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_EnableCLK (DSL_DEV_Device_t * pDev)
{
	u32 arc_debug_data = 0;
	IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
	//enable ac_clk signal
	_IFX_MEI_DBGLongWordRead (pDev, ME_DBG_DECODE_DMP1_MASK,
					CRI_CCR0, &arc_debug_data);
	arc_debug_data |= ACL_CLK_MODE_ENABLE;
	_IFX_MEI_DBGLongWordWrite (pDev, ME_DBG_DECODE_DMP1_MASK,
					 CRI_CCR0, arc_debug_data);
	IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
	return DSL_DEV_MEI_ERR_SUCCESS;
}

/**
 * Halt the ARC.
 * This function halts the ARC.
 *
 * \param 	pDev		the device pointer
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_HaltArc (DSL_DEV_Device_t * pDev)
{
	u32 arc_debug_data = 0x0;

	//      Switch arc control from JTAG mode to MEI mode
	IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
	_IFX_MEI_DBGLongWordRead (pDev, MEI_DEBUG_DEC_AUX_MASK,
					ARC_DEBUG, &arc_debug_data);
	arc_debug_data |= ARC_DEBUG_HALT;
	_IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
					 ARC_DEBUG, arc_debug_data);
	//      Switch arc control from MEI mode to JTAG mode
	IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);

	MEI_WAIT (10);

	return DSL_DEV_MEI_ERR_SUCCESS;
}

/**
 * Run the ARC.
 * This function runs the ARC.
 *
 * \param 	pDev		the device pointer
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_RunArc (DSL_DEV_Device_t * pDev)
{
	u32 arc_debug_data = 0x0;

	//      Switch arc control from JTAG mode to MEI mode- write '1' to bit0
	IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
	_IFX_MEI_DBGLongWordRead (pDev, MEI_DEBUG_DEC_AUX_MASK,
					AUX_STATUS, &arc_debug_data);

	//      Write debug data reg with content ANDd with 0xFDFFFFFF (halt bit cleared)
	arc_debug_data &= ~ARC_AUX_HALT;
	_IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
					 AUX_STATUS, arc_debug_data);

	//      Switch arc control from MEI mode to JTAG mode- write '0' to bit0
	IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);
	//      Enable mask for arc codeswap interrupts
	IFX_MEI_IRQEnable (pDev);

	return DSL_DEV_MEI_ERR_SUCCESS;

}

/**
 * Reset the ARC.
 * This function resets the ARC.
 *
 * \param 	pDev		the device pointer
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_ResetARC (DSL_DEV_Device_t * pDev)
{
	u32 arc_debug_data = 0;

	IFX_MEI_HaltArc (pDev);

	IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, &arc_debug_data);
	IFX_MEI_LongWordWrite ((u32) LQ_RCU_RST,
		arc_debug_data | LQ_RCU_RST_REQ_DFE | LQ_RCU_RST_REQ_AFE);

	// reset ARC
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_RST_CTRL, MEI_SOFT_RESET);
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_RST_CTRL, 0);

	IFX_MEI_IRQDisable (pDev);

	IFX_MEI_EnableCLK (pDev);

#if 0
	// reset part of PPE
	*(unsigned long *) (BSP_PPE32_SRST) = 0xC30;
	*(unsigned long *) (BSP_PPE32_SRST) = 0xFFF;
#endif

	DSL_DEV_PRIVATE(pDev)->modem_ready = 0;

	return DSL_DEV_MEI_ERR_SUCCESS;
}

DSL_DEV_MeiError_t
DSL_BSP_Showtime (DSL_DEV_Device_t * dev, DSL_uint32_t rate_fast, DSL_uint32_t rate_intl)
{
    struct port_cell_info port_cell = {0};

	IFX_MEI_EMSG ("Datarate US intl = %d, fast = %d\n", (int)rate_intl,
			    (int)rate_fast);

    if ( rate_fast )
        g_tx_link_rate[0] = rate_fast / (53 * 8);
    if ( rate_intl )
        g_tx_link_rate[1] = rate_intl / (53 * 8);

    if ( g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 ) {
        IFX_MEI_EMSG ("Got rate fail.\n");
    }

	if ( ifx_mei_atm_showtime_enter )
	{
	    port_cell.port_num = 2;
	    port_cell.tx_link_rate[0] = g_tx_link_rate[0];
	    port_cell.tx_link_rate[1] = g_tx_link_rate[1];
        ifx_mei_atm_showtime_enter(&port_cell, g_xdata_addr);
	}
	else
	{
		IFX_MEI_EMSG("no hookup from ATM driver to set cell rate\n");
	}

	return DSL_DEV_MEI_ERR_SUCCESS;
};

/**
 * Reset/halt/run the DFE.
 * This function provide operations to reset/halt/run the DFE.
 *
 * \param 	pDev		the device pointer
 * \param	mode		which operation want to do
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_CpuModeSet (DSL_DEV_Device_t *pDev,
			  DSL_DEV_CpuMode_t mode)
{
	DSL_DEV_MeiError_t err_ret = DSL_DEV_MEI_ERR_FAILURE;
	switch (mode) {
	case DSL_CPU_HALT:
		err_ret = IFX_MEI_HaltArc (pDev);
		break;
	case DSL_CPU_RUN:
		err_ret = IFX_MEI_RunArc (pDev);
		break;
	case DSL_CPU_RESET:
		err_ret = IFX_MEI_ResetARC (pDev);
		break;
	default:
		break;
	}
	return err_ret;
}

/**
 * Accress DFE memory.
 * This function provide a way to access DFE memory;
 *
 * \param 	pDev		the device pointer
 * \param	type		read or write
 * \param	destaddr	destination address
 * \param	databuff	pointer to hold data
 * \param	databuffsize	size want to read/write
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
DSL_DEV_MeiError_t
DSL_BSP_MemoryDebugAccess (DSL_DEV_Device_t * pDev,
				DSL_BSP_MemoryAccessType_t type,
				DSL_uint32_t destaddr, DSL_uint32_t *databuff,
				DSL_uint32_t databuffsize)
{
	DSL_DEV_MeiError_t meierr = DSL_DEV_MEI_ERR_SUCCESS;
	switch (type) {
	case DSL_BSP_MEMORY_READ:
		meierr = IFX_MEI_DebugRead (pDev, (u32)destaddr, (u32*)databuff, (u32)databuffsize);
		break;
	case DSL_BSP_MEMORY_WRITE:
		meierr = IFX_MEI_DebugWrite (pDev, (u32)destaddr, (u32*)databuff, (u32)databuffsize);
		break;
	}
	return DSL_DEV_MEI_ERR_SUCCESS;
};

/**
 * Download boot code to ARC.
 * This function downloads boot code to ARC.
 *
 * \param 	pDev		the device pointer
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_DownloadBootCode (DSL_DEV_Device_t *pDev)
{
	IFX_MEI_IRQDisable (pDev);

	IFX_MEI_EnableCLK (pDev);

	IFX_MEI_FuseProg (pDev);	//program fuse rar

	IFX_MEI_DownloadBootPages (pDev);

	return DSL_DEV_MEI_ERR_SUCCESS;
};

/**
 * Enable Jtag debugger interface
 * This function setups mips gpio to enable jtag debugger
 *
 * \param 	pDev		the device pointer
 * \param 	enable		enable or disable
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_ArcJtagEnable (DSL_DEV_Device_t *dev, int enable)
{
	/*
	int meierr=0;
	u32 reg_data;
	switch (enable) {
	case 1:
                //reserve gpio 9, 10, 11, 14, 19 for ARC JTAG
		ifxmips_port_reserve_pin (0, 9);
		ifxmips_port_reserve_pin (0, 10);
		ifxmips_port_reserve_pin (0, 11);
		ifxmips_port_reserve_pin (0, 14);
		ifxmips_port_reserve_pin (1, 3);

		ifxmips_port_set_dir_in(0, 11);
		ifxmips_port_clear_altsel0(0, 11);
		ifxmips_port_clear_altsel1(0, 11);
		ifxmips_port_set_open_drain(0, 11);
        //enable ARC JTAG
        IFX_MEI_LongWordRead ((u32) LQ_RCU_RST, &reg_data);
        IFX_MEI_LongWordWrite ((u32) LQ_RCU_RST, reg_data | LQ_RCU_RST_REQ_ARC_JTAG);
		break;
	case 0:
	default:
		break;
	}
jtag_end:
	if (meierr)
		return DSL_DEV_MEI_ERR_FAILURE;
*/
	printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
	printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);

	return DSL_DEV_MEI_ERR_SUCCESS;
};

/**
 * Enable DFE to MIPS interrupt
 * This function enable DFE to MIPS interrupt
 *
 * \param 	pDev		the device pointer
 * \param 	enable		enable or disable
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_AdslMailboxIRQEnable (DSL_DEV_Device_t *pDev, int enable)
{
	DSL_DEV_MeiError_t meierr;
	switch (enable) {
	case 0:
		meierr = DSL_DEV_MEI_ERR_SUCCESS;
		IFX_MEI_IRQDisable (pDev);
		break;
	case 1:
		IFX_MEI_IRQEnable (pDev);
		meierr = DSL_DEV_MEI_ERR_SUCCESS;
		break;
	default:
		meierr = DSL_DEV_MEI_ERR_FAILURE;
		break;

	}
	return meierr;
}

/**
 * Get the modem status
 * This function return the modem status
 *
 * \param 	pDev		the device pointer
 * \return	1: modem ready 0: not ready
 * \ingroup	Internal
 */
static int
IFX_MEI_IsModemReady (DSL_DEV_Device_t * pDev)
{
	return DSL_DEV_PRIVATE(pDev)->modem_ready;
}

DSL_DEV_MeiError_t
DSL_BSP_AdslLedInit (DSL_DEV_Device_t * dev,
			  DSL_DEV_LedId_t led_number,
			  DSL_DEV_LedType_t type,
			  DSL_DEV_LedHandler_t handler)
{
#if 0
        struct led_config_param param;
        if (led_number == DSL_LED_LINK_ID && type == DSL_LED_LINK_TYPE && handler == /*DSL_LED_HD_CPU*/DSL_LED_HD_FW) {
                param.operation_mask = CONFIG_OPERATION_UPDATE_SOURCE;
                param.led = 0x01;
                param.source = 0x01;
//                bsp_led_config (&param);

        } else if (led_number == DSL_LED_DATA_ID && type == DSL_LED_DATA_TYPE && (handler == DSL_LED_HD_FW)) {
                param.operation_mask = CONFIG_OPERATION_UPDATE_SOURCE;
                param.led = 0x02;
                param.source = 0x02;
//                bsp_led_config (&param);
        }
#endif
        return DSL_DEV_MEI_ERR_SUCCESS;
};
#if 0
DSL_DEV_MeiError_t
DSL_BSP_AdslLedSet (DSL_DEV_Device_t * dev, DSL_DEV_LedId_t led_number, DSL_DEV_LedMode_t mode)
{
	printk(KERN_INFO "[%s %d]: mode = %#x, led_number = %d\n", __func__, __LINE__, mode, led_number);
	switch (mode) {
	case DSL_LED_OFF:
		switch (led_number) {
		case DSL_LED_LINK_ID:
#ifdef CONFIG_BSP_LED
			bsp_led_set_blink (1, 0);
			bsp_led_set_data (1, 0);
#endif
			break;
		case DSL_LED_DATA_ID:
#ifdef CONFIG_BSP_LED
			bsp_led_set_blink (0, 0);
			bsp_led_set_data (0, 0);
#endif
			break;
		}
		break;
	case DSL_LED_FLASH:
		switch (led_number) {
		case DSL_LED_LINK_ID:
#ifdef CONFIG_BSP_LED
			bsp_led_set_blink (1, 1);	// data
#endif
			break;
		case DSL_LED_DATA_ID:
#ifdef CONFIG_BSP_LED
			bsp_led_set_blink (0, 1);	// data
#endif
			break;
		}
		break;
	case DSL_LED_ON:
		switch (led_number) {
		case DSL_LED_LINK_ID:
#ifdef CONFIG_BSP_LED
			bsp_led_set_blink (1, 0);
			bsp_led_set_data (1, 1);
#endif
			break;
		case DSL_LED_DATA_ID:
#ifdef CONFIG_BSP_LED
			bsp_led_set_blink (0, 0);
			bsp_led_set_data (0, 1);
#endif
			break;
		}
		break;
	}
	return DSL_DEV_MEI_ERR_SUCCESS;
};

#endif

/**
* Compose a message.
* This function compose a message from opcode, group, address, index, size, and data
*
* \param       opcode          The message opcode
* \param       group           The message group number
* \param       address         The message address.
* \param       index           The message index.
* \param       size            The number of words to read/write.
* \param       data            The pointer to data.
* \param       CMVMSG          The pointer to message buffer.
* \ingroup     Internal
*/
void
makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data, u16 *CMVMSG)
{
        memset (CMVMSG, 0, MSG_LENGTH * 2);
        CMVMSG[0] = (opcode << 4) + (size & 0xf);
        CMVMSG[1] = (((index == 0) ? 0 : 1) << 7) + (group & 0x7f);
        CMVMSG[2] = address;
        CMVMSG[3] = index;
        if (opcode == H2D_CMV_WRITE)
                memcpy (CMVMSG + 4, data, size * 2);
        return;
}

/**
 * Send a message to ARC and read the response
 * This function sends a message to arc, waits the response, and reads the responses.
 *
 * \param 	pDev		the device pointer
 * \param	request		Pointer to the request
 * \param	reply		Wait reply or not.
 * \param	response	Pointer to the response
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
DSL_DEV_MeiError_t
DSL_BSP_SendCMV (DSL_DEV_Device_t * pDev, u16 * request, int reply, u16 * response)	// write cmv to arc, if reply needed, wait for reply
{
	DSL_DEV_MeiError_t meierror;
#if defined(BSP_PORT_RTEMS)
	int delay_counter = 0;
#endif

	if (MEI_MUTEX_LOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema))
		return -ERESTARTSYS;

	DSL_DEV_PRIVATE(pDev)->cmv_reply = reply;
	memset (DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, 0,
		sizeof (DSL_DEV_PRIVATE(pDev)->
			CMV_RxMsg));
	DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;

	meierror = IFX_MEI_MailboxWrite (pDev, request, MSG_LENGTH);

	if (meierror != DSL_DEV_MEI_ERR_SUCCESS) {
		DSL_DEV_PRIVATE(pDev)->cmv_waiting = 0;
		DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
		IFX_MEI_EMSG ("MailboxWrite Fail!\n");
		IFX_MEI_EMSG ("Resetting ARC...\n");
		IFX_MEI_ResetARC(pDev);
		MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
		return meierror;
	}
	else {
		DSL_DEV_PRIVATE(pDev)->cmv_count++;
	}

	if (DSL_DEV_PRIVATE(pDev)->cmv_reply ==
	    NO_REPLY) {
		MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
		return DSL_DEV_MEI_ERR_SUCCESS;
	}

#if !defined(BSP_PORT_RTEMS)
	if (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0)
		MEI_WAIT_EVENT_TIMEOUT (DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav, CMV_TIMEOUT);
#else
	while (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0 && delay_counter < CMV_TIMEOUT / 5) {
		MEI_WAIT (5);
		delay_counter++;
	}
#endif

	DSL_DEV_PRIVATE(pDev)->cmv_waiting = 0;
	if (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0) {	//CMV_timeout
		DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
		IFX_MEI_EMSG ("\%s: DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT\n",
				    __FUNCTION__);
		MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
		return DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT;
	}
	else {
		DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;
		DSL_DEV_PRIVATE(pDev)->
			reply_count++;
		memcpy (response, DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH * 2);
		MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
		return DSL_DEV_MEI_ERR_SUCCESS;
	}
	MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);
	return DSL_DEV_MEI_ERR_SUCCESS;
}

/**
 * Reset the ARC, download boot codes, and run the ARC.
 * This function resets the ARC, downloads boot codes to ARC, and runs the ARC.
 *
 * \param 	pDev		the device pointer
 * \return	DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE
 * \ingroup	Internal
 */
static DSL_DEV_MeiError_t
IFX_MEI_RunAdslModem (DSL_DEV_Device_t *pDev)
{
	int nSize = 0, idx = 0;
	uint32_t im0_register, im2_register;
//	DSL_DEV_WinHost_Message_t m;

	if (mei_arc_swap_buff == NULL) {
		mei_arc_swap_buff =
			(u32 *) kmalloc (MAXSWAPSIZE * 4, GFP_KERNEL);
		if (mei_arc_swap_buff == NULL) {
			IFX_MEI_EMSG (">>> malloc fail for codeswap buff!!! <<<\n");
			return DSL_DEV_MEI_ERR_FAILURE;
		}
                IFX_MEI_DMSG("allocate %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff);
	}

	DSL_DEV_PRIVATE(pDev)->img_hdr =
		(ARC_IMG_HDR *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[0].address;
	if ((DSL_DEV_PRIVATE(pDev)->img_hdr->
	     count) * sizeof (ARC_SWP_PAGE_HDR) > SDRAM_SEGMENT_SIZE) {
		IFX_MEI_EMSG ("firmware header size is bigger than 64K segment size\n");
		return DSL_DEV_MEI_ERR_FAILURE;
	}
	// check image size
	for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) {
		nSize += DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].nCopy;
	}
	if (nSize !=
	    DSL_DEV_PRIVATE(pDev)->image_size) {
		IFX_MEI_EMSG ("Firmware download is not completed. Please download firmware again!\n");
		return DSL_DEV_MEI_ERR_FAILURE;
	}
	// TODO: check crc
	///

	IFX_MEI_ResetARC (pDev);
	IFX_MEI_HaltArc (pDev);
	IFX_MEI_BarUpdate (pDev, DSL_DEV_PRIVATE(pDev)->nBar);

	//IFX_MEI_DMSG("Starting to meiDownloadBootCode\n");

	IFX_MEI_DownloadBootCode (pDev);

	im0_register = (*LQ_ICU_IM0_IER) & (1 << 20);
	im2_register = (*LQ_ICU_IM2_IER) & (1 << 20);
	/* Turn off irq */
	#ifdef CONFIG_LANTIQ_AMAZON_SE
	disable_irq (IFXMIPS_USB_OC_INT0);
	disable_irq (IFXMIPS_USB_OC_INT2);
	#elif defined(CONFIG_LANTIQ_AR9)
	disable_irq (IFXMIPS_USB_OC_INT0);
	disable_irq (IFXMIPS_USB_OC_INT2);
	#elif defined(CONFIG_SOC_LANTIQ_XWAY)
	disable_irq (LQ_USB_OC_INT);
	#else
	#error unkonwn arch
	#endif
	disable_irq (pDev->nIrq[IFX_DYING_GASP]);

	IFX_MEI_RunArc (pDev);

	MEI_WAIT_EVENT_TIMEOUT (DSL_DEV_PRIVATE(pDev)->wait_queue_modemready, 1000);

	#ifdef CONFIG_LANTIQ_AMAZON_SE
	MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT0);
	MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT2);
	#elif defined(CONFIG_LANTIQ_AMAZON_S)
	MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT0);
	MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT2);
	#elif defined(CONFIG_SOC_LANTIQ_XWAY)
	MEI_MASK_AND_ACK_IRQ (LQ_USB_OC_INT);
	#else
	#error unkonwn arch
	#endif
	MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DYING_GASP]);

	/* Re-enable irq */
	enable_irq(pDev->nIrq[IFX_DYING_GASP]);
	*LQ_ICU_IM0_IER |= im0_register;
	*LQ_ICU_IM2_IER |= im2_register;

	if (DSL_DEV_PRIVATE(pDev)->modem_ready != 1) {
		IFX_MEI_EMSG ("Modem failed to be ready!\n");
		return DSL_DEV_MEI_ERR_FAILURE;
	} else {
		IFX_MEI_DMSG("Modem is ready.\n");
		return DSL_DEV_MEI_ERR_SUCCESS;
	}
}

/**
 * Get the page's data pointer
 * This function caculats the data address from the firmware header.
 *
 * \param 	pDev		the device pointer
 * \param	Page		The page number.
 * \param	data		Data page or program page.
 * \param	MaxSize		The maximum size to read.
 * \param	Buffer		Pointer to data.
 * \param	Dest		Pointer to the destination address.
 * \return	The number of bytes to read.
 * \ingroup	Internal
 */
static int
IFX_MEI_GetPage (DSL_DEV_Device_t * pDev, u32 Page, u32 data,
		       u32 MaxSize, u32 * Buffer, u32 * Dest)
{
	u32 size;
	u32 i;
	u32 *p;
	u32 idx, offset, nBar = 0;

	if (Page > DSL_DEV_PRIVATE(pDev)->img_hdr->count)
		return -2;
	/*
	 **     Get program or data size, depending on "data" flag
	 */
	size = (data == GET_DATA) ? (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].d_size) :
			     (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_size);
	size &= BOOT_FLAG_MASK;	//      Clear boot bit!
	if (size > MaxSize)
		return -1;

	if (size == 0)
		return 0;
	/*
	 **     Get program or data offset, depending on "data" flag
	 */
	i = data ? (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].d_offset) :
			(DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_offset);

	/*
	 **     Copy data/program to buffer
	 */

	idx = i / SDRAM_SEGMENT_SIZE;
	offset = i % SDRAM_SEGMENT_SIZE;
	p = (u32 *) ((u8 *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address + offset);

	for (i = 0; i < size; i++) {
		if (offset + i * 4 - (nBar * SDRAM_SEGMENT_SIZE) >= SDRAM_SEGMENT_SIZE) {
			idx++;
			nBar++;
			p = (u32 *) ((u8 *) KSEG1ADDR ((u32)DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address));
		}
		Buffer[i] = *p++;
	}

	/*
	 **     Pass back data/program destination address
	 */
	*Dest = data ? (DSL_DEV_PRIVATE(pDev)-> img_hdr->page[Page].d_dest) :
				(DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_dest);

	return size;
}

/**
 * Free the memory for ARC firmware
 *
 * \param 	pDev		the device pointer
 * \param	type	Free all memory or free the unused memory after showtime
 * \ingroup	Internal
 */
const char *free_str[4] = {"Invalid", "Free_Reload", "Free_Showtime", "Free_All"};
static int
IFX_MEI_DFEMemoryFree (DSL_DEV_Device_t * pDev, int type)
{
        int idx = 0;
        smmu_mem_info_t *adsl_mem_info =
                DSL_DEV_PRIVATE(pDev)->adsl_mem_info;

        for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) {
                if (type == FREE_ALL ||adsl_mem_info[idx].type == type) {
                        if (adsl_mem_info[idx].size > 0) {
                                IFX_MEI_DMSG ("Freeing memory %p (%s)\n", adsl_mem_info[idx].org_address, free_str[adsl_mem_info[idx].type]);
                                if ( idx == XDATA_REGISTER ) {
                                    g_xdata_addr = NULL;
                                    if ( ifx_mei_atm_showtime_exit )
                                        ifx_mei_atm_showtime_exit();
                                }
				kfree (adsl_mem_info[idx].org_address);
                                adsl_mem_info[idx].org_address = 0;
                                adsl_mem_info[idx].address = 0;
                                adsl_mem_info[idx].size = 0;
                                adsl_mem_info[idx].type = 0;
                                adsl_mem_info[idx].nCopy = 0;
                        }
                }
        }

	if(mei_arc_swap_buff != NULL){
                IFX_MEI_DMSG("free %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff);
		kfree(mei_arc_swap_buff);
		mei_arc_swap_buff=NULL;
	}

        return 0;
}
static int
IFX_MEI_DFEMemoryAlloc (DSL_DEV_Device_t * pDev, long size)
{
	unsigned long mem_ptr;
	char *org_mem_ptr = NULL;
	int idx = 0;
	long total_size = 0;
	int err = 0;
	smmu_mem_info_t *adsl_mem_info =
		((ifx_mei_device_private_t *) pDev->pPriv)->adsl_mem_info;
//		DSL_DEV_PRIVATE(pDev)->adsl_mem_info;
	int allocate_size = SDRAM_SEGMENT_SIZE;

	IFX_MEI_DMSG("image_size = %ld\n", size);
	// Alloc Swap Pages
	for (idx = 0; size > 0 && idx < MAX_BAR_REGISTERS; idx++) {
		// skip bar15 for XDATA usage.
		if (idx == XDATA_REGISTER)
			continue;
#if 0
                if (size < SDRAM_SEGMENT_SIZE) {
                        allocate_size = size;
                        if (allocate_size < 1024)
                                allocate_size = 1024;
                }
#endif
                if (idx == (MAX_BAR_REGISTERS - 1))
                        allocate_size = size;
                else
                        allocate_size = SDRAM_SEGMENT_SIZE;
		org_mem_ptr = kmalloc (allocate_size + 1024, GFP_KERNEL);
		if (org_mem_ptr == NULL) {
                        IFX_MEI_EMSG ("%d: kmalloc %d bytes memory fail!\n", idx, allocate_size);
			err = -ENOMEM;
			goto allocate_error;
		}
                mem_ptr = (unsigned long) (org_mem_ptr + 1023) & ~(1024 -1);
                adsl_mem_info[idx].address = (char *) mem_ptr;
                adsl_mem_info[idx].org_address = org_mem_ptr;
                adsl_mem_info[idx].size = allocate_size;
                size -= allocate_size;
                total_size += allocate_size;
	}
	if (size > 0) {
		IFX_MEI_EMSG ("Image size is too large!\n");
		err = -EFBIG;
		goto allocate_error;
	}
	err = idx;
	return err;

      allocate_error:
	IFX_MEI_DFEMemoryFree (pDev, FREE_ALL);
	return err;
}

/**
 * Program the BAR registers
 *
 * \param 	pDev		the device pointer
 * \param	nTotalBar	The number of bar to program.
 * \ingroup	Internal
 */
static int
IFX_MEI_BarUpdate (DSL_DEV_Device_t * pDev, int nTotalBar)
{
	int idx = 0;
	smmu_mem_info_t *adsl_mem_info =
		DSL_DEV_PRIVATE(pDev)->adsl_mem_info;

	for (idx = 0; idx < nTotalBar; idx++) {
		//skip XDATA register
		if (idx == XDATA_REGISTER)
			continue;
		IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XMEM_BAR_BASE + idx * 4,
			(((uint32_t) adsl_mem_info[idx].address) & 0x0FFFFFFF));
	}
	for (idx = nTotalBar; idx < MAX_BAR_REGISTERS; idx++) {
		if (idx == XDATA_REGISTER)
			continue;
		IFX_MEI_LongWordWriteOffset (pDev,  (u32) ME_XMEM_BAR_BASE  + idx * 4,
			 (((uint32_t)adsl_mem_info[nTotalBar - 1].address) & 0x0FFFFFFF));
		/* These are for /proc/danube_mei/meminfo purpose */
		adsl_mem_info[idx].address = adsl_mem_info[nTotalBar - 1].address;
		adsl_mem_info[idx].org_address = adsl_mem_info[nTotalBar - 1].org_address;
		adsl_mem_info[idx].size = 0; /* Prevent it from being freed */
	}

    g_xdata_addr = adsl_mem_info[XDATA_REGISTER].address;
	IFX_MEI_LongWordWriteOffset (pDev,  (u32) ME_XMEM_BAR_BASE  + XDATA_REGISTER * 4,
		(((uint32_t) adsl_mem_info [XDATA_REGISTER].address) & 0x0FFFFFFF));
	// update MEI_XDATA_BASE_SH
	IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XDATA_BASE_SH,
		 ((unsigned long)adsl_mem_info[XDATA_REGISTER].address) & 0x0FFFFFFF);

	return DSL_DEV_MEI_ERR_SUCCESS;
}

/* This copies the firmware from secondary storage to 64k memory segment in SDRAM */
DSL_DEV_MeiError_t
DSL_BSP_FWDownload (DSL_DEV_Device_t * pDev, const char *buf,
			 unsigned long size, long *loff, long *current_offset)
{
	ARC_IMG_HDR img_hdr_tmp;
	smmu_mem_info_t *adsl_mem_info = DSL_DEV_PRIVATE(pDev)->adsl_mem_info;

	size_t nRead = 0, nCopy = 0;
	char *mem_ptr;
	ssize_t retval = -ENOMEM;
	int idx = 0;

        IFX_MEI_DMSG("\n");

	if (*loff == 0) {
		if (size < sizeof (img_hdr_tmp)) {
			IFX_MEI_EMSG ("Firmware size is too small!\n");
			return retval;
		}
		copy_from_user ((char *) &img_hdr_tmp, buf, sizeof (img_hdr_tmp));
		// header of image_size and crc are not included.
		DSL_DEV_PRIVATE(pDev)->image_size = le32_to_cpu (img_hdr_tmp.size) + 8;

		if (DSL_DEV_PRIVATE(pDev)->image_size > 1024 * 1024) {
			IFX_MEI_EMSG ("Firmware size is too large!\n");
			return retval;
		}
		// check if arc is halt
		IFX_MEI_ResetARC (pDev);
		IFX_MEI_HaltArc (pDev);

		IFX_MEI_DFEMemoryFree (pDev, FREE_ALL);	//free all

		retval = IFX_MEI_DFEMemoryAlloc (pDev,  DSL_DEV_PRIVATE(pDev)->image_size);
		if (retval < 0) {
			IFX_MEI_EMSG ("Error: No memory space left.\n");
			goto error;
		}
		for (idx = 0; idx < retval; idx++) {
			//skip XDATA register
			if (idx == XDATA_REGISTER)
				continue;
			if (idx * SDRAM_SEGMENT_SIZE < le32_to_cpu (img_hdr_tmp.page[0].p_offset))
				adsl_mem_info[idx].type = FREE_RELOAD;
			else
				adsl_mem_info[idx].type = FREE_SHOWTIME;
		}
		DSL_DEV_PRIVATE(pDev)->nBar = retval;

		DSL_DEV_PRIVATE(pDev)->img_hdr =
			(ARC_IMG_HDR *) adsl_mem_info[0].address;

		adsl_mem_info[XDATA_REGISTER].org_address = kmalloc (SDRAM_SEGMENT_SIZE + 1024, GFP_KERNEL);
		adsl_mem_info[XDATA_REGISTER].address =
			(char *) ((unsigned long) (adsl_mem_info[XDATA_REGISTER].org_address + 1023) & 0xFFFFFC00);

		adsl_mem_info[XDATA_REGISTER].size = SDRAM_SEGMENT_SIZE;

		if (adsl_mem_info[XDATA_REGISTER].address == NULL) {
			IFX_MEI_EMSG ("kmalloc memory fail!\n");
			retval = -ENOMEM;
			goto error;
		}
		adsl_mem_info[XDATA_REGISTER].type = FREE_RELOAD;
		IFX_MEI_DMSG("-> IFX_MEI_BarUpdate()\n");
		IFX_MEI_BarUpdate (pDev, (DSL_DEV_PRIVATE(pDev)->nBar));
	}
	else if (DSL_DEV_PRIVATE(pDev)-> image_size == 0) {
		IFX_MEI_EMSG ("Error: Firmware size=0! \n");
		goto error;
	}

	nRead = 0;
	while (nRead < size) {
		long offset = ((long) (*loff) + nRead) % SDRAM_SEGMENT_SIZE;
		idx = (((long) (*loff)) + nRead) / SDRAM_SEGMENT_SIZE;
		mem_ptr = (char *) KSEG1ADDR ((unsigned long) (adsl_mem_info[idx].address) + offset);
		if ((size - nRead + offset) > SDRAM_SEGMENT_SIZE)
			nCopy = SDRAM_SEGMENT_SIZE - offset;
		else
			nCopy = size - nRead;
		copy_from_user (mem_ptr, buf + nRead, nCopy);
		for (offset = 0; offset < (nCopy / 4); offset++) {
			((unsigned long *) mem_ptr)[offset] = le32_to_cpu (((unsigned long *) mem_ptr)[offset]);
		}
		nRead += nCopy;
		adsl_mem_info[idx].nCopy += nCopy;
	}

	*loff += size;
	*current_offset = size;
	return DSL_DEV_MEI_ERR_SUCCESS;
error:
	IFX_MEI_DFEMemoryFree (pDev, FREE_ALL);
	return DSL_DEV_MEI_ERR_FAILURE;
}
/*
 * Register a callback event.
 * Return:
 * -1 if the event already has a callback function registered.
 *  0 success
 */
int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *p)
{
	if (!p) {
                IFX_MEI_EMSG("Invalid parameter!\n");
                return -EINVAL;
	}
        if (p->event > DSL_BSP_CB_LAST || p->event < DSL_BSP_CB_FIRST) {
                IFX_MEI_EMSG("Invalid Event %d\n", p->event);
                return -EINVAL;
        }
        if (dsl_bsp_event_callback[p->event].function) {
                IFX_MEI_EMSG("Event %d already has a callback function registered!\n", p->event);
                return -1;
        } else {
                dsl_bsp_event_callback[p->event].function = p->function;
                dsl_bsp_event_callback[p->event].event    = p->event;
                dsl_bsp_event_callback[p->event].pData    = p->pData;
        }
        return 0;
}
int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *p)
{
	if (!p) {
                IFX_MEI_EMSG("Invalid parameter!\n");
                return -EINVAL;
	}
        if (p->event > DSL_BSP_CB_LAST || p->event < DSL_BSP_CB_FIRST) {
                IFX_MEI_EMSG("Invalid Event %d\n", p->event);
                return -EINVAL;
        }
        if (dsl_bsp_event_callback[p->event].function) {
                IFX_MEI_EMSG("Unregistering Event %d...\n", p->event);
                dsl_bsp_event_callback[p->event].function = NULL;
                dsl_bsp_event_callback[p->event].pData    = NULL;
        } else {
                IFX_MEI_EMSG("Event %d is not registered!\n", p->event);
                return -1;
        }
        return 0;
}

/**
 * MEI Dying Gasp interrupt handler
 *
 * \param int1
 * \param void0
 * \param regs	Pointer to the structure of danube mips registers
 * \ingroup	Internal
 */
static irqreturn_t IFX_MEI_Dying_Gasp_IrqHandle (int int1, void *void0)
{
	DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) void0;
        DSL_BSP_CB_Type_t event;

	if (pDev == NULL)
		IFX_MEI_EMSG("Error: Got Interrupt but pDev is NULL!!!!\n");

#ifndef CONFIG_SMP
	disable_irq (pDev->nIrq[IFX_DYING_GASP]);
#else
	disable_irq_nosync(pDev->nIrq[IFX_DYING_GASP]);
#endif
	event = DSL_BSP_CB_DYING_GASP;

	if (dsl_bsp_event_callback[event].function)
		(*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData);

#ifdef CONFIG_USE_EMULATOR
    IFX_MEI_EMSG("Dying Gasp! Shutting Down... (Work around for Amazon-S Venus emulator)\n");
#else
	IFX_MEI_EMSG("Dying Gasp! Shutting Down...\n");
//	kill_proc (1, SIGINT, 1);       /* Ask init to reboot us */
#endif
        return IRQ_HANDLED;
}

extern void ifx_usb_enable_afe_oc(void);

/**
 * MEI interrupt handler
 *
 * \param int1
 * \param void0
 * \param regs	Pointer to the structure of danube mips registers
 * \ingroup	Internal
 */
static irqreturn_t IFX_MEI_IrqHandle (int int1, void *void0)
{
	u32 scratch;
	DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) void0;
#if defined(CONFIG_LQ_MEI_FW_LOOPBACK) && defined(DFE_PING_TEST)
	dfe_loopback_irq_handler (pDev);
	return IRQ_HANDLED;
#endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK
        DSL_BSP_CB_Type_t event;

	if (pDev == NULL)
		IFX_MEI_EMSG("Error: Got Interrupt but pDev is NULL!!!!\n");

	IFX_MEI_DebugRead (pDev, ARC_MEI_MAILBOXR, &scratch, 1);
	if (scratch & OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK) {
		IFX_MEI_EMSG("Receive Code Swap Request interrupt!!!\n");
		return IRQ_HANDLED;
	}
	else if (scratch & OMB_CLEAREOC_INTERRUPT_CODE)	 {
		// clear eoc message interrupt
		IFX_MEI_DMSG("OMB_CLEAREOC_INTERRUPT_CODE\n");
                event = DSL_BSP_CB_CEOC_IRQ;
		IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV);
                if (dsl_bsp_event_callback[event].function)
			(*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData);
        } else if (scratch & OMB_REBOOT_INTERRUPT_CODE) {
                // Reboot
                IFX_MEI_DMSG("OMB_REBOOT_INTERRUPT_CODE\n");
                event = DSL_BSP_CB_FIRMWARE_REBOOT;

		IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV);

                if (dsl_bsp_event_callback[event].function)
                        (*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData);
        } else { // normal message
                IFX_MEI_MailboxRead (pDev, DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH);
                if (DSL_DEV_PRIVATE(pDev)-> cmv_waiting == 1) {
                        DSL_DEV_PRIVATE(pDev)-> arcmsgav = 1;
                        DSL_DEV_PRIVATE(pDev)-> cmv_waiting = 0;
#if !defined(BSP_PORT_RTEMS)
                        MEI_WAKEUP_EVENT (DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav);
#endif
                }
		else {
			DSL_DEV_PRIVATE(pDev)-> modem_ready_cnt++;
			memcpy ((char *) DSL_DEV_PRIVATE(pDev)->Recent_indicator,
				(char *) DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH * 2);
			if (((DSL_DEV_PRIVATE(pDev)->CMV_RxMsg[0] & 0xff0) >> 4) == D2H_AUTONOMOUS_MODEM_READY_MSG) {
				//check ARC ready message
				IFX_MEI_DMSG ("Got MODEM_READY_MSG\n");
				DSL_DEV_PRIVATE(pDev)->modem_ready = 1;
				MEI_WAKEUP_EVENT (DSL_DEV_PRIVATE(pDev)->wait_queue_modemready);
			}
		}
	}

	return IRQ_HANDLED;
}

int
DSL_BSP_ATMLedCBRegister (int (*ifx_adsl_ledcallback) (void))
{
    g_adsl_ledcallback = ifx_adsl_ledcallback;
    return 0;
}

int
DSL_BSP_ATMLedCBUnregister (int (*ifx_adsl_ledcallback) (void))
{
    g_adsl_ledcallback = adsl_dummy_ledcallback;
    return 0;
}

#if 0
int
DSL_BSP_EventCBRegister (int (*ifx_adsl_callback)
			        (DSL_BSP_CB_Event_t * param))
{
	int error = 0;

	if (DSL_EventCB == NULL) {
		DSL_EventCB = ifx_adsl_callback;
	}
	else {
		error = -EIO;
	}
	return error;
}

int
DSL_BSP_EventCBUnregister (int (*ifx_adsl_callback)
				  (DSL_BSP_CB_Event_t * param))
{
	int error = 0;

	if (DSL_EventCB == ifx_adsl_callback) {
		DSL_EventCB = NULL;
	}
	else {
		error = -EIO;
	}
	return error;
}

static int
DSL_BSP_GetEventCB (int (**ifx_adsl_callback)
			   (DSL_BSP_CB_Event_t * param))
{
	*ifx_adsl_callback = DSL_EventCB;
	return 0;
}
#endif

#ifdef CONFIG_LQ_MEI_FW_LOOPBACK
#define mte_reg_base	(0x4800*4+0x20000)

/* Iridia Registers Address Constants */
#define MTE_Reg(r)    	(int)(mte_reg_base + (r*4))

#define IT_AMODE       	MTE_Reg(0x0004)

#define TIMER_DELAY   	(1024)
#define BC0_BYTES     	(32)
#define BC1_BYTES     	(30)
#define NUM_MB        	(12)
#define TIMEOUT_VALUE 	2000

static void
BFMWait (u32 cycle)
{
	u32 i;
	for (i = 0; i < cycle; i++);
}

static void
WriteRegLong (u32 addr, u32 data)
{
	//*((volatile u32 *)(addr)) =  data;
	IFX_MEI_WRITE_REGISTER_L (data, addr);
}

static u32
ReadRegLong (u32 addr)
{
	// u32  rd_val;
	//rd_val = *((volatile u32 *)(addr));
	// return rd_val;
	return IFX_MEI_READ_REGISTER_L (addr);
}

/* This routine writes the mailbox with the data in an input array */
static void
WriteMbox (u32 * mboxarray, u32 size)
{
	IFX_MEI_DebugWrite (&dsl_devices[0], IMBOX_BASE, mboxarray, size);
	IFX_MEI_DMSG("write to %X\n", IMBOX_BASE);
	IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ME2ARC_INT, MEI_TO_ARC_MSGAV);
}

/* This routine reads the output mailbox and places the results into an array */
static void
ReadMbox (u32 * mboxarray, u32 size)
{
	IFX_MEI_DebugRead (&dsl_devices[0], OMBOX_BASE, mboxarray, size);
	IFX_MEI_DMSG("read from %X\n", OMBOX_BASE);
}

static void
MEIWriteARCValue (u32 address, u32 value)
{
	u32 i, check = 0;

	/* Write address register */
	IFX_MEI_WRITE_REGISTER_L (address,  ME_DBG_WR_AD + LQ_MEI_BASE_ADDR);

	/* Write data register */
	IFX_MEI_WRITE_REGISTER_L (value, ME_DBG_DATA + LQ_MEI_BASE_ADDR);

	/* wait until complete - timeout at 40 */
	for (i = 0; i < 40; i++) {
		check = IFX_MEI_READ_REGISTER_L (ME_ARC2ME_STAT + LQ_MEI_BASE_ADDR);

		if ((check & ARC_TO_MEI_DBG_DONE))
			break;
	}
	/* clear the flag */
	IFX_MEI_WRITE_REGISTER_L (ARC_TO_MEI_DBG_DONE, ME_ARC2ME_STAT + LQ_MEI_BASE_ADDR);
}

void
arc_code_page_download (uint32_t arc_code_length, uint32_t * start_address)
{
	int count;

	IFX_MEI_DMSG("try to download pages,size=%d\n", arc_code_length);
	IFX_MEI_ControlModeSet (&dsl_devices[0], MEI_MASTER_MODE);
	IFX_MEI_HaltArc (&dsl_devices[0]);
	IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_DX_AD, 0);
	for (count = 0; count < arc_code_length; count++) {
		IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_DX_DATA,
						   *(start_address + count));
	}
	IFX_MEI_ControlModeSet (&dsl_devices[0], JTAG_MASTER_MODE);
}
static int
load_jump_table (unsigned long addr)
{
	int i;
	uint32_t addr_le, addr_be;
	uint32_t jump_table[32];

	for (i = 0; i < 16; i++) {
		addr_le = i * 8 + addr;
		addr_be = ((addr_le >> 16) & 0xffff);
		addr_be |= ((addr_le & 0xffff) << 16);
		jump_table[i * 2 + 0] = 0x0f802020;
		jump_table[i * 2 + 1] = addr_be;
		//printk("jt %X %08X %08X\n",i,jump_table[i*2+0],jump_table[i*2+1]);
	}
	arc_code_page_download (32, &jump_table[0]);
return 0;
}

int got_int = 0;

void
dfe_loopback_irq_handler (DSL_DEV_Device_t *pDev)
{
	uint32_t rd_mbox[10];

	memset (&rd_mbox[0], 0, 10 * 4);
	ReadMbox (&rd_mbox[0], 6);
	if (rd_mbox[0] == 0x0) {
		FX_MEI_DMSG("Get ARC_ACK\n");
		got_int = 1;
	}
	else if (rd_mbox[0] == 0x5) {
		IFX_MEI_DMSG("Get ARC_BUSY\n");
		got_int = 2;
	}
	else if (rd_mbox[0] == 0x3) {
		IFX_MEI_DMSG("Get ARC_EDONE\n");
		if (rd_mbox[1] == 0x0) {
			got_int = 3;
			IFX_MEI_DMSG("Get E_MEMTEST\n");
			if (rd_mbox[2] != 0x1) {
				got_int = 4;
				IFX_MEI_DMSG("Get Result %X\n", rd_mbox[2]);
			}
		}
	}
	IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ARC2ME_STAT,
		ARC_TO_MEI_DBG_DONE);
	MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DFEIR]);
	disable_irq (pDev->nIrq[IFX_DFEIR]);
	//got_int = 1;
	return;
}

static void
wait_mem_test_result (void)
{
	uint32_t mbox[5];
	mbox[0] = 0;

	IFX_MEI_DMSG("Waiting Starting\n");
	while (mbox[0] == 0) {
		ReadMbox (&mbox[0], 5);
	}
	IFX_MEI_DMSG("Try to get mem test result.\n");
	ReadMbox (&mbox[0], 5);
	if (mbox[0] == 0xA) {
		IFX_MEI_DMSG("Success.\n");
	}
	else if (mbox[0] == 0xA) {
		IFX_MEI_EMSG("Fail,address %X,except data %X,receive data %X\n",
			mbox[1], mbox[2], mbox[3]);
	}
	else {
		IFX_MEI_EMSG("Fail\n");
	}
}

static int
arc_ping_testing (DSL_DEV_Device_t *pDev)
{
#define MEI_PING 0x00000001
	uint32_t wr_mbox[10], rd_mbox[10];
	int i;

	for (i = 0; i < 10; i++) {
		wr_mbox[i] = 0;
		rd_mbox[i] = 0;
	}

	FX_MEI_DMSG("send ping msg\n");
	wr_mbox[0] = MEI_PING;
	WriteMbox (&wr_mbox[0], 10);

	while (got_int == 0) {
		MEI_WAIT (100);
	}

	IFX_MEI_DMSG("send start event\n");
	got_int = 0;

	wr_mbox[0] = 0x4;
	wr_mbox[1] = 0;
	wr_mbox[2] = 0;
	wr_mbox[3] = (uint32_t) 0xf5acc307e;
	wr_mbox[4] = 5;
	wr_mbox[5] = 2;
	wr_mbox[6] = 0x1c000;
	wr_mbox[7] = 64;
	wr_mbox[8] = 0;
	wr_mbox[9] = 0;
	WriteMbox (&wr_mbox[0], 10);
	DSL_ENABLE_IRQ (pDev->nIrq[IFX_DFEIR]);
	//printk("IFX_MEI_MailboxWrite ret=%d\n",i);
	IFX_MEI_LongWordWriteOffset (&dsl_devices[0],
					   (u32) ME_ME2ARC_INT,
					   MEI_TO_ARC_MSGAV);
	IFX_MEI_DMSG("sleeping\n");
	while (1) {
		if (got_int > 0) {

			if (got_int > 3)
				IFX_MEI_DMSG("got_int >>>> 3\n");
			else
				IFX_MEI_DMSG("got int = %d\n", got_int);
			got_int = 0;
			//schedule();
			DSL_ENABLE_IRQ (pDev->nIrq[IFX_DFEIR]);
		}
		//mbox_read(&rd_mbox[0],6);
		MEI_WAIT (100);
	}
	return 0;
}

static DSL_DEV_MeiError_t
DFE_Loopback_Test (void)
{
	int i = 0;
	u32 arc_debug_data = 0, temp;
	DSL_DEV_Device_t *pDev = &dsl_devices[0];
	uint32_t wr_mbox[10];

	IFX_MEI_ResetARC (pDev);
	// start the clock
	arc_debug_data = ACL_CLK_MODE_ENABLE;
	IFX_MEI_DebugWrite (pDev, CRI_CCR0, &arc_debug_data, 1);

#if defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK)
	// WriteARCreg(AUX_XMEM_LTEST,0);
	IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
#define AUX_XMEM_LTEST 0x128
	_IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,  AUX_XMEM_LTEST, 0);
	IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);

	// WriteARCreg(AUX_XDMA_GAP,0);
	IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
#define AUX_XDMA_GAP 0x114
	_IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, AUX_XDMA_GAP, 0);
	IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);

	IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
	temp = 0;
	_IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
		(u32) ME_XDATA_BASE_SH +  LQ_MEI_BASE_ADDR, temp);
	IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);

	i = IFX_MEI_DFEMemoryAlloc (pDev, SDRAM_SEGMENT_SIZE * 16);
	if (i >= 0) {
		int idx;

		for (idx = 0; idx < i; idx++) {
			DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].type = FREE_RELOAD;
			IFX_MEI_WRITE_REGISTER_L ((((uint32_t) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address) & 0x0fffffff),
							LQ_MEI_BASE_ADDR + ME_XMEM_BAR_BASE  + idx * 4);
			IFX_MEI_DMSG("bar%d(%X)=%X\n", idx,
				LQ_MEI_BASE_ADDR + ME_XMEM_BAR_BASE  +
				idx * 4, (((uint32_t)
					   ((ifx_mei_device_private_t *)
					    pDev->pPriv)->adsl_mem_info[idx].
					   address) & 0x0fffffff));
			memset ((u8 *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address, 0, SDRAM_SEGMENT_SIZE);
		}

		IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XDATA_BASE_SH,
					   ((unsigned long) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[XDATA_REGISTER].address) & 0x0FFFFFFF);
	}
	else {
		IFX_MEI_EMSG ("cannot load image: no memory\n");
		return DSL_DEV_MEI_ERR_FAILURE;
	}
	//WriteARCreg(AUX_IC_CTRL,2);
	IFX_MEI_DMSG("Setting MEI_MASTER_MODE..\n");
	IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);
#define AUX_IC_CTRL 0x11
	_IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,
					 AUX_IC_CTRL, 2);
	IFX_MEI_DMSG("Setting JTAG_MASTER_MODE..\n");
	IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);

	IFX_MEI_DMSG("Halting ARC...\n");
	IFX_MEI_HaltArc (&dsl_devices[0]);

#ifdef DFE_PING_TEST

	IFX_MEI_DMSG("ping test image size=%d\n", sizeof (arc_ahb_access_code));
	memcpy ((u8 *) (DSL_DEV_PRIVATE(pDev)->
			adsl_mem_info[0].address + 0x1004),
		&arc_ahb_access_code[0], sizeof (arc_ahb_access_code));
	load_jump_table (0x80000 + 0x1004);

#endif //DFE_PING_TEST

	IFX_MEI_DMSG("ARC ping test code download complete\n");
#endif //defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK)
#ifdef DFE_MEM_TEST
	IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ARC2ME_MASK, MSGAV_EN);

	arc_code_page_download (1537, &code_array[0]);
	IFX_MEI_DMSG("ARC mem test code download complete\n");
#endif //DFE_MEM_TEST
#ifdef DFE_ATM_LOOPBACK
	arc_debug_data = 0xf;
	arc_code_page_download (sizeof(code_array) / sizeof(*code_array), &code_array[0]);
	wr_mbox[0] = 0;	    //TIMER_DELAY   - org: 1024
	wr_mbox[1] = 0;		//TXFB_START0
	wr_mbox[2] = 0x7f;	//TXFB_END0     - org: 49
	wr_mbox[3] = 0x80;	//TXFB_START1   - org: 80
	wr_mbox[4] = 0xff;	//TXFB_END1     - org: 109
	wr_mbox[5] = 0x100;	//RXFB_START0   - org: 0
	wr_mbox[6] = 0x17f;	//RXFB_END0     - org: 49
	wr_mbox[7] = 0x180;	//RXFB_START1   - org: 256
	wr_mbox[8] = 0x1ff;	//RXFB_END1     - org: 315
	WriteMbox (&wr_mbox[0], 9);
	// Start Iridia IT_AMODE (in dmp access) why is it required?
	IFX_MEI_DebugWrite (&dsl_devices[0], 0x32010, &arc_debug_data, 1);
#endif //DFE_ATM_LOOPBACK
	IFX_MEI_IRQEnable (pDev);
	IFX_MEI_DMSG("run ARC...\n");
	IFX_MEI_RunArc (&dsl_devices[0]);

#ifdef DFE_PING_TEST
	arc_ping_testing (pDev);
#endif //DFE_PING_TEST
#ifdef DFE_MEM_TEST
	wait_mem_test_result ();
#endif //DFE_MEM_TEST

	IFX_MEI_DFEMemoryFree (pDev, FREE_ALL);
	return DSL_DEV_MEI_ERR_SUCCESS;
}

#endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK

static int
IFX_MEI_InitDevNode (int num)
{
	if (num == 0) {
		if ((dev_major = register_chrdev (dev_major, IFX_MEI_DEVNAME, &bsp_mei_operations)) < 0) {
			IFX_MEI_EMSG ("register_chrdev(%d %s) failed!\n", dev_major, IFX_MEI_DEVNAME);
			return -ENODEV;
		}
	}
	return 0;
}

static int
IFX_MEI_CleanUpDevNode (int num)
{
	if (num == 0)
		unregister_chrdev (dev_major, MEI_DIRNAME);
	return 0;
}

static int
IFX_MEI_InitDevice (int num)
{
	DSL_DEV_Device_t *pDev;
        u32 temp;
	pDev = &dsl_devices[num];
	if (pDev == NULL)
		return -ENOMEM;
	pDev->pPriv = &sDanube_Mei_Private[num];
	memset (pDev->pPriv, 0, sizeof (ifx_mei_device_private_t));

	memset (&DSL_DEV_PRIVATE(pDev)->
		adsl_mem_info[0], 0,
		sizeof (smmu_mem_info_t) * MAX_BAR_REGISTERS);

	if (num == 0) {
		pDev->nIrq[IFX_DFEIR]      = LQ_MEI_INT;
		pDev->nIrq[IFX_DYING_GASP] = LQ_MEI_DYING_GASP_INT;
		pDev->base_address = LQ_MEI_BASE_ADDR;

                /* Power up MEI */
#ifdef CONFIG_LANTIQ_AMAZON_SE
		*LQ_PMU_PWDCR &= ~(1 << 9);  // enable dsl
                *LQ_PMU_PWDCR &= ~(1 << 15); // enable AHB base
#else
        	temp = lq_r32(LQ_PMU_PWDCR);
        	temp &= 0xffff7dbe;
        	lq_w32(temp, LQ_PMU_PWDCR);
#endif
	}
	pDev->nInUse = 0;
	DSL_DEV_PRIVATE(pDev)->modem_ready = 0;
	DSL_DEV_PRIVATE(pDev)->arcmsgav = 0;

	MEI_INIT_WAKELIST ("arcq", DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav);	// for ARCMSGAV
	MEI_INIT_WAKELIST ("arcr", DSL_DEV_PRIVATE(pDev)->wait_queue_modemready);	// for arc modem ready

	MEI_MUTEX_INIT (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema, 1);	// semaphore initialization, mutex
#if 0
	MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DFEIR]);
	MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DYING_GASP]);
#endif
	if (request_irq (pDev->nIrq[IFX_DFEIR], IFX_MEI_IrqHandle, 0, "DFEIR", pDev) != 0) {
		IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DFEIR]);
		return -1;
	}
	/*if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, "DYING_GASP", pDev) != 0) {
		IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DYING_GASP]);
		return -1;
	}*/
//	IFX_MEI_DMSG("Device %d initialized. IER %#x\n", num, bsp_get_irq_ier(pDev->nIrq[IFX_DYING_GASP]));
	return 0;
}

static int
IFX_MEI_ExitDevice (int num)
{
	DSL_DEV_Device_t *pDev;
	pDev = &dsl_devices[num];

	if (pDev == NULL)
		return -EIO;

	disable_irq (pDev->nIrq[IFX_DFEIR]);
	disable_irq (pDev->nIrq[IFX_DYING_GASP]);

	free_irq(pDev->nIrq[IFX_DFEIR], pDev);
	free_irq(pDev->nIrq[IFX_DYING_GASP], pDev);

	return 0;
}

static DSL_DEV_Device_t *
IFX_BSP_HandleGet (int maj, int num)
{
	if (num > BSP_MAX_DEVICES)
		return NULL;
	return &dsl_devices[num];
}

DSL_DEV_Device_t *
DSL_BSP_DriverHandleGet (int maj, int num)
{
	DSL_DEV_Device_t *pDev;

	if (num > BSP_MAX_DEVICES)
		return NULL;

	pDev = &dsl_devices[num];
	if (!try_module_get(pDev->owner))
		return NULL;

	pDev->nInUse++;
	return pDev;
}

int
DSL_BSP_DriverHandleDelete (DSL_DEV_Device_t * nHandle)
{
	DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) nHandle;
	if (pDev->nInUse)
		pDev->nInUse--;
        module_put(pDev->owner);
	return 0;
}

static int
IFX_MEI_Open (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil)
{
	int maj = MAJOR (ino->i_rdev);
	int num = MINOR (ino->i_rdev);

	DSL_DEV_Device_t *pDev = NULL;
	if ((pDev = DSL_BSP_DriverHandleGet (maj, num)) == NULL) {
		IFX_MEI_EMSG("open(%d:%d) fail!\n", maj, num);
		return -EIO;
	}
	fil->private_data = pDev;
	return 0;
}

static int
IFX_MEI_Release (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil)
{
	//int maj = MAJOR(ino->i_rdev);
	int num = MINOR (ino->i_rdev);
	DSL_DEV_Device_t *pDev;

	pDev = &dsl_devices[num];
	if (pDev == NULL)
		return -EIO;
	DSL_BSP_DriverHandleDelete (pDev);
	return 0;
}

/**
 * Callback function for linux userspace program writing
 */
static ssize_t
IFX_MEI_Write (DSL_DRV_file_t * filp, const char *buf, size_t size, loff_t * loff)
{
	DSL_DEV_MeiError_t mei_error = DSL_DEV_MEI_ERR_FAILURE;
	long offset = 0;
	DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) filp->private_data;

	if (pDev == NULL)
		return -EIO;

	mei_error =
		DSL_BSP_FWDownload (pDev, buf, size, (long *) loff,  &offset);

	if (mei_error == DSL_DEV_MEI_ERR_FAILURE)
		return -EIO;
	return (ssize_t) offset;
}

/**
 * Callback function for linux userspace program ioctling
 */
static int
IFX_MEI_IoctlCopyFrom (int from_kernel, char *dest, char *from, int size)
{
	int ret = 0;

	if (!from_kernel)
		ret = copy_from_user ((char *) dest, (char *) from, size);
	else
		ret = (int)memcpy ((char *) dest, (char *) from, size);
	return ret;
}

static int
IFX_MEI_IoctlCopyTo (int from_kernel, char *dest, char *from, int size)
{
	int ret = 0;

	if (!from_kernel)
		ret = copy_to_user ((char *) dest, (char *) from, size);
	else
		ret = (int)memcpy ((char *) dest, (char *) from, size);
	return ret;
}

static int
IFX_MEI_Ioctls (DSL_DEV_Device_t * pDev, int from_kernel, unsigned int command, unsigned long lon)
{
	int i = 0;
	int meierr = DSL_DEV_MEI_ERR_SUCCESS;
	u32 base_address = LQ_MEI_BASE_ADDR;
	DSL_DEV_WinHost_Message_t winhost_msg, m;
	DSL_DEV_MeiDebug_t debugrdwr;
	DSL_DEV_MeiReg_t regrdwr;

	switch (command) {

	case DSL_FIO_BSP_CMV_WINHOST:
		IFX_MEI_IoctlCopyFrom (from_kernel, (char *) winhost_msg.msg.TxMessage,
					     (char *) lon, MSG_LENGTH * 2);

		if ((meierr = DSL_BSP_SendCMV (pDev, winhost_msg.msg.TxMessage, YES_REPLY,
					   winhost_msg.msg.RxMessage)) != DSL_DEV_MEI_ERR_SUCCESS) {
			IFX_MEI_EMSG ("WINHOST CMV fail :TxMessage:%X %X %X %X, RxMessage:%X %X %X %X %X\n",
				 winhost_msg.msg.TxMessage[0], winhost_msg.msg.TxMessage[1], winhost_msg.msg.TxMessage[2], winhost_msg.msg.TxMessage[3],
				 winhost_msg.msg.RxMessage[0], winhost_msg.msg.RxMessage[1], winhost_msg.msg.RxMessage[2], winhost_msg.msg.RxMessage[3],
				 winhost_msg.msg.RxMessage[4]);
			meierr = DSL_DEV_MEI_ERR_FAILURE;
		}
		else {
			IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,
						   (char *) winhost_msg.msg.RxMessage,
						   MSG_LENGTH * 2);
		}
		break;

	case DSL_FIO_BSP_CMV_READ:
		IFX_MEI_IoctlCopyFrom (from_kernel, (char *) (&regrdwr),
					     (char *) lon, sizeof (DSL_DEV_MeiReg_t));

		IFX_MEI_LongWordRead ((u32) regrdwr.iAddress,
					    (u32 *) & (regrdwr.iData));

		IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,
					   (char *) (&regrdwr),
					   sizeof (DSL_DEV_MeiReg_t));

		break;

	case DSL_FIO_BSP_CMV_WRITE:
		IFX_MEI_IoctlCopyFrom (from_kernel, (char *) (&regrdwr),
					     (char *) lon, sizeof (DSL_DEV_MeiReg_t));

		IFX_MEI_LongWordWrite ((u32) regrdwr.iAddress,
					     regrdwr.iData);
		break;

	case DSL_FIO_BSP_GET_BASE_ADDRESS:
		IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,
					   (char *) (&base_address),
					   sizeof (base_address));
		break;

	case DSL_FIO_BSP_IS_MODEM_READY:
		i = IFX_MEI_IsModemReady (pDev);
		IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,
					   (char *) (&i), sizeof (int));
		meierr = DSL_DEV_MEI_ERR_SUCCESS;
		break;
	case DSL_FIO_BSP_RESET:
	case DSL_FIO_BSP_REBOOT:
		meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_RESET);
		meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_HALT);
		break;

	case DSL_FIO_BSP_HALT:
		meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_HALT);
		break;

	case DSL_FIO_BSP_RUN:
		meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_RUN);
		break;
	case DSL_FIO_BSP_BOOTDOWNLOAD:
		meierr = IFX_MEI_DownloadBootCode (pDev);
		break;
	case DSL_FIO_BSP_JTAG_ENABLE:
		meierr = IFX_MEI_ArcJtagEnable (pDev, 1);
		break;

	case DSL_FIO_BSP_REMOTE:
		IFX_MEI_IoctlCopyFrom (from_kernel, (char *) (&i),
					     (char *) lon, sizeof (int));

		meierr = IFX_MEI_AdslMailboxIRQEnable (pDev, i);
		break;

	case DSL_FIO_BSP_DSL_START:
		IFX_MEI_DMSG("DSL_FIO_BSP_DSL_START\n");
		if ((meierr = IFX_MEI_RunAdslModem (pDev)) != DSL_DEV_MEI_ERR_SUCCESS) {
			IFX_MEI_EMSG ("IFX_MEI_RunAdslModem() error...");
			meierr = DSL_DEV_MEI_ERR_FAILURE;
		}
		break;

	case DSL_FIO_BSP_DEBUG_READ:
	case DSL_FIO_BSP_DEBUG_WRITE:
		IFX_MEI_IoctlCopyFrom (from_kernel,
					     (char *) (&debugrdwr),
					     (char *) lon,
					     sizeof (debugrdwr));

		if (command == DSL_FIO_BSP_DEBUG_READ)
			meierr = DSL_BSP_MemoryDebugAccess (pDev,
								 DSL_BSP_MEMORY_READ,
								 debugrdwr.
								 iAddress,
								 debugrdwr.
								 buffer,
								 debugrdwr.
								 iCount);
		else
			meierr = DSL_BSP_MemoryDebugAccess (pDev,
								 DSL_BSP_MEMORY_WRITE,
								 debugrdwr.
								 iAddress,
								 debugrdwr.
								 buffer,
								 debugrdwr.
								 iCount);

		IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&debugrdwr), sizeof (debugrdwr));
		break;
	case DSL_FIO_BSP_GET_VERSION:
		IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&bsp_mei_version), sizeof (DSL_DEV_Version_t));
		break;

#define LQ_MPS_CHIPID_VERSION_GET(value)  (((value) >> 28) & ((1 << 4) - 1))
	case DSL_FIO_BSP_GET_CHIP_INFO:
                bsp_chip_info.major = 1;
                bsp_chip_info.minor = LQ_MPS_CHIPID_VERSION_GET(*LQ_MPS_CHIPID);
                IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&bsp_chip_info), sizeof (DSL_DEV_HwVersion_t));
                meierr = DSL_DEV_MEI_ERR_SUCCESS;
		break;

        case DSL_FIO_BSP_FREE_RESOURCE:
                makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_STAT, 4, 0, 1, NULL, m.msg.TxMessage);
                if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS) {
                        meierr = DSL_DEV_MEI_ERR_FAILURE;
                        return -EIO;
                }
                IFX_MEI_DMSG("RxMessage[4] = %#x\n", m.msg.RxMessage[4]);
                if (!(m.msg.RxMessage[4] & DSL_DEV_STAT_CODESWAP_COMPLETE)) {
                        meierr = DSL_DEV_MEI_ERR_FAILURE;
                        return -EAGAIN;
                }
                IFX_MEI_DMSG("Freeing all memories marked FREE_SHOWTIME\n");
                IFX_MEI_DFEMemoryFree (pDev, FREE_SHOWTIME);
                meierr = DSL_DEV_MEI_ERR_SUCCESS;
		break;
#ifdef CONFIG_IFXMIPS_AMAZON_SE
	case DSL_FIO_ARC_MUX_TEST:
		AMAZON_SE_MEI_ARC_MUX_Test();
		break;
#endif
	default:
//		IFX_MEI_EMSG("Invalid IOCTL command: %d\n");
		break;
	}
	return meierr;
}

#ifdef CONFIG_IFXMIPS_AMAZON_SE
void AMAZON_SE_MEI_ARC_MUX_Test(void)
{
	u32 *p, i;
	*LQ_RCU_RST |= LQ_RCU_RST_REQ_MUX_ARC;

	p = (u32*)(DFE_LDST_BASE_ADDR + IRAM0_BASE);
	IFX_MEI_EMSG("Writing to IRAM0(%p)...\n", p);
	for (i = 0; i < IRAM0_SIZE/sizeof(u32); i++, p++) {
		*p = 0xdeadbeef;
		if (*p != 0xdeadbeef)
			IFX_MEI_EMSG("%p: %#x\n", p, *p);
	}

	p = (u32*)(DFE_LDST_BASE_ADDR + IRAM1_BASE);
	IFX_MEI_EMSG("Writing to IRAM1(%p)...\n", p);
	for (i = 0; i < IRAM1_SIZE/sizeof(u32); i++, p++) {
		*p = 0xdeadbeef;
		if (*p != 0xdeadbeef)
			IFX_MEI_EMSG("%p: %#x\n", p, *p);
	}

	p = (u32*)(DFE_LDST_BASE_ADDR + BRAM_BASE);
	IFX_MEI_EMSG("Writing to BRAM(%p)...\n", p);
	for (i = 0; i < BRAM_SIZE/sizeof(u32); i++, p++) {
		*p = 0xdeadbeef;
		if (*p != 0xdeadbeef)
			IFX_MEI_EMSG("%p: %#x\n", p, *p);
	}

	p = (u32*)(DFE_LDST_BASE_ADDR + XRAM_BASE);
	IFX_MEI_EMSG("Writing to XRAM(%p)...\n", p);
	for (i = 0; i < XRAM_SIZE/sizeof(u32); i++, p++) {
		*p = 0xdeadbeef;
		if (*p != 0xdeadbeef)
			IFX_MEI_EMSG("%p: %#x\n", p, *p);
	}

	p = (u32*)(DFE_LDST_BASE_ADDR + YRAM_BASE);
	IFX_MEI_EMSG("Writing to YRAM(%p)...\n", p);
	for (i = 0; i < YRAM_SIZE/sizeof(u32); i++, p++) {
		*p = 0xdeadbeef;
		if (*p != 0xdeadbeef)
			IFX_MEI_EMSG("%p: %#x\n", p, *p);
	}

	p = (u32*)(DFE_LDST_BASE_ADDR + EXT_MEM_BASE);
	IFX_MEI_EMSG("Writing to EXT_MEM(%p)...\n", p);
	for (i = 0; i < EXT_MEM_SIZE/sizeof(u32); i++, p++) {
		*p = 0xdeadbeef;
		if (*p != 0xdeadbeef)
			IFX_MEI_EMSG("%p: %#x\n", p, *p);
	}
	*LQ_RCU_RST &= ~LQ_RCU_RST_REQ_MUX_ARC;
}
#endif
int
DSL_BSP_KernelIoctls (DSL_DEV_Device_t * pDev, unsigned int command,
			   unsigned long lon)
{
	int error = 0;

	error = IFX_MEI_Ioctls (pDev, 1, command, lon);
	return error;
}

static int
IFX_MEI_UserIoctls (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil,
			  unsigned int command, unsigned long lon)
{
	int error = 0;
	int maj = MAJOR (ino->i_rdev);
	int num = MINOR (ino->i_rdev);
	DSL_DEV_Device_t *pDev;

	pDev = IFX_BSP_HandleGet (maj, num);
	if (pDev == NULL)
		return -EIO;

	error = IFX_MEI_Ioctls (pDev, 0, command, lon);
	return error;
}

#ifdef CONFIG_PROC_FS
/*
 * Register a callback function for linux proc filesystem
 */
static int
IFX_MEI_InitProcFS (int num)
{
	struct proc_dir_entry *entry;
	int i ;
	DSL_DEV_Device_t *pDev;
	reg_entry_t regs_temp[PROC_ITEMS] = {
		/* flag, name,      description } */
		{NULL, "arcmsgav", "arc to mei message ", 0},
		{NULL, "cmv_reply", "cmv needs reply", 0},
		{NULL, "cmv_waiting", "waiting for cmv reply from arc", 0},
		{NULL, "modem_ready_cnt", "ARC to MEI indicator count", 0},
		{NULL, "cmv_count", "MEI to ARC CMVs", 0},
		{NULL, "reply_count", "ARC to MEI Reply", 0},
		{NULL, "Recent_indicator", "most recent indicator", 0},
		{NULL, "fw_version", "Firmware Version", 0},
		{NULL, "fw_date", "Firmware Date", 0},
		{NULL, "meminfo", "Memory Allocation Information", 0},
		{NULL, "version", "MEI version information", 0},
	};

	pDev = &dsl_devices[num];
	if (pDev == NULL)
		return -ENOMEM;

	regs_temp[0].flag = &(DSL_DEV_PRIVATE(pDev)->arcmsgav);
	regs_temp[1].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_reply);
	regs_temp[2].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_waiting);
	regs_temp[3].flag = &(DSL_DEV_PRIVATE(pDev)->modem_ready_cnt);
	regs_temp[4].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_count);
	regs_temp[5].flag = &(DSL_DEV_PRIVATE(pDev)->reply_count);
	regs_temp[6].flag = (int *) &(DSL_DEV_PRIVATE(pDev)->Recent_indicator);

	memcpy ((char *) regs[num], (char *) regs_temp, sizeof (regs_temp));
	// procfs
	meidir = proc_mkdir (MEI_DIRNAME, NULL);
	if (meidir == NULL) {
		IFX_MEI_EMSG ("Failed to create /proc/%s\n",  MEI_DIRNAME);
		return (-ENOMEM);
	}

	for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
		entry = create_proc_entry (regs[num][i].name,
					   S_IWUSR | S_IRUSR | S_IRGRP |
					   S_IROTH, meidir);
		if (entry) {
			regs[num][i].low_ino = entry->low_ino;
			entry->proc_fops = &IFX_MEI_ProcOperations;
		}
		else {
			IFX_MEI_EMSG ("Failed to create /proc/%s/%s\n", MEI_DIRNAME, regs[num][i].name);
			return (-ENOMEM);
		}
	}
	return 0;
}

/*
 * Reading function for linux proc filesystem
 */
static int
IFX_MEI_ProcRead (struct file *file, char *buf, size_t nbytes, loff_t * ppos)
{
	int i_ino = (file->f_dentry->d_inode)->i_ino;
	char *p = buf;
	int i;
	int num;
	reg_entry_t *entry = NULL;
	DSL_DEV_Device_t *pDev = NULL;
	DSL_DEV_WinHost_Message_t m;

	for (num = 0; num < BSP_MAX_DEVICES; num++) {
		for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
			if (regs[num][i].low_ino == (unsigned short)i_ino) {
				entry = &regs[num][i];
				pDev = &dsl_devices[num];
				break;
			}
		}
	}
	if (entry == NULL)
		return -EINVAL;
	else if (strcmp(entry->name, "meminfo") == 0) {
		if (*ppos > 0)	/* Assume reading completed in previous read */
			return 0;
		p += sprintf (p, "No           Address     Size\n");
		for (i = 0; i < MAX_BAR_REGISTERS; i++) {
			p += sprintf (p, "BAR[%02d] Addr:0x%08X Size:%lu\n",
					  i, (u32) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[i].address,
					  DSL_DEV_PRIVATE(pDev)-> adsl_mem_info[i].size);
			//printk( "BAR[%02d] Addr:0x%08X Size:%d\n",i,adsl_mem_info[i].address,adsl_mem_info[i].size);
		}
		*ppos += (p - buf);
	} else if (strcmp(entry->name, "fw_version") == 0) {
		if (*ppos > 0)	/* Assume reading completed in previous read */
			return 0;
		if (DSL_DEV_PRIVATE(pDev)->modem_ready_cnt < 1)
			return -EAGAIN;
                //major:bits 0-7
                //minor:bits 8-15
                makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 54, 0, 1, NULL, m.msg.TxMessage);
		if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
			return -EIO;
		p += sprintf(p, "FW Version: %d.%d.", m.msg.RxMessage[4] & 0xFF, (m.msg.RxMessage[4] >> 8) & 0xFF);
                //sub_version:bits 4-7
                //int_version:bits 0-3
                //spl_appl:bits 8-13
                //rel_state:bits 14-15
                makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 54, 1, 1, NULL, m.msg.TxMessage);
		if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
			return -EIO;
		p += sprintf(p, "%d.%d.%d.%d\n",
			(m.msg.RxMessage[4] >> 4) & 0xF, m.msg.RxMessage[4] & 0xF,
			(m.msg.RxMessage[4] >> 14) & 3, (m.msg.RxMessage[4] >> 8) & 0x3F);
                *ppos += (p - buf);
	} else if (strcmp(entry->name, "fw_date") == 0) {
		if (*ppos > 0)	/* Assume reading completed in previous read */
			return 0;
		if (DSL_DEV_PRIVATE(pDev)->modem_ready_cnt < 1)
			return -EAGAIN;

                makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 0, 1, NULL, m.msg.TxMessage);
		if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
			return -EIO;
		/* Day/Month */
		p += sprintf(p, "FW Date: %d.%d.", m.msg.RxMessage[4] & 0xFF, (m.msg.RxMessage[4] >> 8) & 0xFF);

                makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 2, 1, NULL, m.msg.TxMessage);
		if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
			return -EIO;
		/* Year */
		p += sprintf(p, "%d ", m.msg.RxMessage[4]);

                makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 1, 1, NULL, m.msg.TxMessage);
		if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS)
			return -EIO;
		/* Hour:Minute */
		p += sprintf(p, "%d:%d\n", (m.msg.RxMessage[4] >> 8) & 0xFF, m.msg.RxMessage[4] & 0xFF);

                *ppos += (p - buf);
	} else if (strcmp(entry->name, "version") == 0) {
		if (*ppos > 0)	/* Assume reading completed in previous read */
			return 0;
		p += sprintf (p, "IFX MEI V%ld.%ld.%ld\n", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);

		*ppos += (p - buf);
	} else if (entry->flag != (int *) DSL_DEV_PRIVATE(pDev)->Recent_indicator) {
		if (*ppos > 0)	/* Assume reading completed in previous read */
			return 0;	// indicates end of file
		p += sprintf (p, "0x%08X\n\n", *(entry->flag));
		*ppos += (p - buf);
		if ((p - buf) > nbytes)	/* Assume output can be read at one time */
			return -EINVAL;
	} else {
		if ((int) (*ppos) / ((int) 7) == 16)
			return 0;	// indicate end of the message
		p += sprintf (p, "0x%04X\n\n", *(((u16 *) (entry->flag)) + (int) (*ppos) / ((int) 7)));
		*ppos += (p - buf);
	}
	return p -  buf;
}

/*
 * Writing function for linux proc filesystem
 */
static ssize_t
IFX_MEI_ProcWrite (struct file *file, const char *buffer, size_t count, loff_t * ppos)
{
	int i_ino = (file->f_dentry->d_inode)->i_ino;
	reg_entry_t *current_reg = NULL;
	int i = 0;
	int num = 0;
	unsigned long newRegValue = 0;
	char *endp = NULL;
	DSL_DEV_Device_t *pDev = NULL;

	for (num = 0; num < BSP_MAX_DEVICES; num++) {
		for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
			if (regs[num][i].low_ino == i_ino) {
				current_reg = &regs[num][i];
				pDev = &dsl_devices[num];
				break;
			}
		}
	}
	if ((current_reg == NULL)
	    || (current_reg->flag ==
		(int *) DSL_DEV_PRIVATE(pDev)->
		Recent_indicator))
		return -EINVAL;

	newRegValue = simple_strtoul (buffer, &endp, 0);
	*(current_reg->flag) = (int) newRegValue;
	return (count + endp - buffer);
}
#endif //CONFIG_PROC_FS

static int adsl_dummy_ledcallback(void)
{
    return 0;
}

int ifx_mei_atm_led_blink(void)
{
    return g_adsl_ledcallback();
}
EXPORT_SYMBOL(ifx_mei_atm_led_blink);

int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
{
    int i;

    if ( is_showtime ) {
        *is_showtime = g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 ? 0 : 1;
    }

    if ( port_cell ) {
        for ( i = 0; i < port_cell->port_num && i < 2; i++ )
            port_cell->tx_link_rate[i] = g_tx_link_rate[i];
    }

    if ( xdata_addr ) {
        if ( g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 )
            *xdata_addr = NULL;
        else
            *xdata_addr = g_xdata_addr;
    }

    return 0;
}
EXPORT_SYMBOL(ifx_mei_atm_showtime_check);

/*
 * Writing function for linux proc filesystem
 */
int __init
IFX_MEI_ModuleInit (void)
{
	int i = 0;
	static struct class *dsl_class;

	pr_info("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);

	for (i = 0; i < BSP_MAX_DEVICES; i++) {
		if (IFX_MEI_InitDevice (i) != 0) {
			IFX_MEI_EMSG("Init device fail!\n");
			return -EIO;
		}
		IFX_MEI_InitDevNode (i);
#ifdef CONFIG_PROC_FS
		IFX_MEI_InitProcFS (i);
#endif
	}
		for (i = 0; i <= DSL_BSP_CB_LAST ; i++)
		dsl_bsp_event_callback[i].function = NULL;

#ifdef CONFIG_LQ_MEI_FW_LOOPBACK
	IFX_MEI_DMSG("Start loopback test...\n");
	DFE_Loopback_Test ();
#endif
	dsl_class = class_create(THIS_MODULE, "ifx_mei");
	device_create(dsl_class, NULL, MKDEV(MEI_MAJOR, 0), NULL, "ifx_mei");
	return 0;
}

void __exit
IFX_MEI_ModuleExit (void)
{
	int i = 0;
	int num;

	for (num = 0; num < BSP_MAX_DEVICES; num++) {
		IFX_MEI_CleanUpDevNode (num);
#ifdef CONFIG_PROC_FS
		for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
			remove_proc_entry (regs[num][i].name, meidir);
		}
#endif
	}

	remove_proc_entry (MEI_DIRNAME, NULL);
	for (i = 0; i < BSP_MAX_DEVICES; i++) {
		for (i = 0; i < BSP_MAX_DEVICES; i++) {
			IFX_MEI_ExitDevice (i);
		}
	}
}

/* export function for DSL Driver */

/* The functions of MEI_DriverHandleGet and MEI_DriverHandleDelete are
something like open/close in kernel space , where the open could be used
to register a callback for autonomous messages and returns a mei driver context pointer (comparable to the file descriptor in user space)
   The context will be required for the multi line chips future! */

EXPORT_SYMBOL (DSL_BSP_DriverHandleGet);
EXPORT_SYMBOL (DSL_BSP_DriverHandleDelete);

EXPORT_SYMBOL (DSL_BSP_ATMLedCBRegister);
EXPORT_SYMBOL (DSL_BSP_ATMLedCBUnregister);
EXPORT_SYMBOL (DSL_BSP_KernelIoctls);
EXPORT_SYMBOL (DSL_BSP_AdslLedInit);
//EXPORT_SYMBOL (DSL_BSP_AdslLedSet);
EXPORT_SYMBOL (DSL_BSP_FWDownload);
EXPORT_SYMBOL (DSL_BSP_Showtime);

EXPORT_SYMBOL (DSL_BSP_MemoryDebugAccess);
EXPORT_SYMBOL (DSL_BSP_SendCMV);

// provide a register/unregister function for DSL driver to register a event callback function
EXPORT_SYMBOL (DSL_BSP_EventCBRegister);
EXPORT_SYMBOL (DSL_BSP_EventCBUnregister);

module_init (IFX_MEI_ModuleInit);
module_exit (IFX_MEI_ModuleExit);

MODULE_LICENSE("Dual BSD/GPL");