summaryrefslogtreecommitdiff
path: root/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch
blob: 6358e478074924dc86ab98b6b0c1fb04cd1c56ff (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
--- a/arch/mips/ath79/mach-ap136.c
+++ b/arch/mips/ath79/mach-ap136.c
@@ -1,5 +1,5 @@
 /*
- * Qualcomm Atheros AP136 reference board support
+ * Atheros AP136 reference board support
  *
  * Copyright (c) 2012 Qualcomm Atheros
  * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
@@ -18,23 +18,28 @@
  *
  */
 
-#include <linux/pci.h>
-#include <linux/ath9k_platform.h>
+#include <linux/platform_device.h>
+#include <linux/ar8216_platform.h>
 
-#include "machtypes.h"
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "common.h"
+#include "dev-ap9x-pci.h"
 #include "dev-gpio-buttons.h"
+#include "dev-eth.h"
 #include "dev-leds-gpio.h"
-#include "dev-spi.h"
+#include "dev-m25p80.h"
+#include "dev-nfc.h"
 #include "dev-usb.h"
 #include "dev-wmac.h"
-#include "pci.h"
+#include "machtypes.h"
 
-#define AP136_GPIO_LED_STATUS_RED	14
-#define AP136_GPIO_LED_STATUS_GREEN	19
 #define AP136_GPIO_LED_USB		4
-#define AP136_GPIO_LED_WLAN_2G		13
 #define AP136_GPIO_LED_WLAN_5G		12
+#define AP136_GPIO_LED_WLAN_2G		13
+#define AP136_GPIO_LED_STATUS_RED	14
 #define AP136_GPIO_LED_WPS_RED		15
+#define AP136_GPIO_LED_STATUS_GREEN	19
 #define AP136_GPIO_LED_WPS_GREEN	20
 
 #define AP136_GPIO_BTN_WPS		16
@@ -43,8 +48,10 @@
 #define AP136_KEYS_POLL_INTERVAL	20	/* msecs */
 #define AP136_KEYS_DEBOUNCE_INTERVAL	(3 * AP136_KEYS_POLL_INTERVAL)
 
-#define AP136_WMAC_CALDATA_OFFSET 0x1000
-#define AP136_PCIE_CALDATA_OFFSET 0x5000
+#define AP136_MAC0_OFFSET		0
+#define AP136_MAC1_OFFSET		6
+#define AP136_WMAC_CALDATA_OFFSET	0x1000
+#define AP136_PCIE_CALDATA_OFFSET	0x5000
 
 static struct gpio_led ap136_leds_gpio[] __initdata = {
 	{
@@ -98,64 +105,158 @@ static struct gpio_keys_button ap136_gpi
 	},
 };
 
-static struct ath79_spi_controller_data ap136_spi0_data = {
-	.cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
-	.cs_line = 0,
+static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
+static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
+
+static struct ar8327_platform_data ap136_ar8327_data = {
+	.pad0_cfg = &ap136_ar8327_pad0_cfg,
+	.pad6_cfg = &ap136_ar8327_pad6_cfg,
+	.port0_cfg = {
+		.force_link = 1,
+		.speed = AR8327_PORT_SPEED_1000,
+		.duplex = 1,
+		.txpause = 1,
+		.rxpause = 1,
+	},
+	.port6_cfg = {
+		.force_link = 1,
+		.speed = AR8327_PORT_SPEED_1000,
+		.duplex = 1,
+		.txpause = 1,
+		.rxpause = 1,
+	},
 };
 
-static struct spi_board_info ap136_spi_info[] = {
+static struct mdio_board_info ap136_mdio0_info[] = {
 	{
-		.bus_num	= 0,
-		.chip_select	= 0,
-		.max_speed_hz	= 25000000,
-		.modalias	= "mx25l6405d",
-		.controller_data = &ap136_spi0_data,
-	}
+		.bus_id = "ag71xx-mdio.0",
+		.phy_addr = 0,
+		.platform_data = &ap136_ar8327_data,
+	},
 };
 
-static struct ath79_spi_platform_data ap136_spi_data = {
-	.bus_num	= 0,
-	.num_chipselect	= 1,
-};
+static void __init ap136_gmac_setup(void)
+{
+	void __iomem *base;
+	u32 t;
 
-#ifdef CONFIG_PCI
-static struct ath9k_platform_data ap136_ath9k_data;
+	base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
 
-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
-{
-	if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
-		dev->dev.platform_data = &ap136_ath9k_data;
+	t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
 
-	return 0;
-}
+	t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
+	t |= QCA955X_ETH_CFG_RGMII_EN;
 
-static void __init ap136_pci_init(u8 *eeprom)
-{
-	memcpy(ap136_ath9k_data.eeprom_data, eeprom,
-	       sizeof(ap136_ath9k_data.eeprom_data));
+	__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
 
-	ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
-	ath79_register_pci();
+	iounmap(base);
 }
-#else
-static inline void ap136_pci_init(void) {}
-#endif /* CONFIG_PCI */
 
-static void __init ap136_setup(void)
+static void __init ap136_common_setup(void)
 {
 	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 
+	ath79_register_m25p80(NULL);
+
 	ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
 				 ap136_leds_gpio);
 	ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
 					ARRAY_SIZE(ap136_gpio_keys),
 					ap136_gpio_keys);
-	ath79_register_spi(&ap136_spi_data, ap136_spi_info,
-			   ARRAY_SIZE(ap136_spi_info));
+
 	ath79_register_usb();
-	ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
-	ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
+	ath79_register_nfc();
+
+	ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
+	ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
+
+	ap136_gmac_setup();
+
+	ath79_register_mdio(0, 0x0);
+
+	ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
+
+	mdiobus_register_board_info(ap136_mdio0_info,
+				    ARRAY_SIZE(ap136_mdio0_info));
+
+	/* GMAC0 is connected to the RMGII interface */
+	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+	ath79_eth0_data.phy_mask = BIT(0);
+	ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
+
+	ath79_register_eth(0);
+
+	/* GMAC1 is connected tot eh SGMII interface */
+	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
+	ath79_eth1_data.speed = SPEED_1000;
+	ath79_eth1_data.duplex = DUPLEX_FULL;
+
+	ath79_register_eth(1);
+}
+
+static void __init ap136_010_setup(void)
+{
+	/* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
+	ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
+	ap136_ar8327_pad0_cfg.txclk_delay_en = true;
+	ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
+	ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
+	ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
+
+	/* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */
+	ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
+	ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
+	ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
+
+	ath79_eth0_pll_data.pll_1000 = 0xa6000000;
+	ath79_eth1_pll_data.pll_1000 = 0x03000101;
+
+	ap136_common_setup();
+}
+
+MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
+	     "Atheros AP136-010 reference board",
+	     ap136_010_setup);
+
+static void __init ap136_020_setup(void)
+{
+	/* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
+	ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
+	ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
+
+	/* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
+	ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
+	ap136_ar8327_pad6_cfg.txclk_delay_en = true;
+	ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
+	ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
+	ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
+
+	ath79_eth0_pll_data.pll_1000 = 0x56000000;
+	ath79_eth1_pll_data.pll_1000 = 0x03000101;
+
+	ap136_common_setup();
+}
+
+MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
+	     "Atheros AP136-020 reference board",
+	     ap136_020_setup);
+
+/*
+ * AP135-020 is similar to AP136-020, any future AP135 specific init
+ * code can be added here.
+ */
+static void __init ap135_020_setup(void)
+{
+	ap136_leds_gpio[0].name = "ap135:green:status";
+	ap136_leds_gpio[1].name = "ap135:red:status";
+	ap136_leds_gpio[2].name = "ap135:green:wps";
+	ap136_leds_gpio[3].name = "ap135:red:wps";
+	ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
+	ap136_leds_gpio[5].name = "ap135:red:usb";
+
+	ap136_020_setup();
 }
 
-MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",
-	     ap136_setup);
+MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",
+	     "Atheros AP135-020 reference board",
+	     ap135_020_setup);
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -18,7 +18,9 @@ enum ath79_mach_type {
 	ATH79_MACH_GENERIC = 0,
 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
 	ATH79_MACH_AP121_MINI,		/* Atheros AP121-MINI reference board */
-	ATH79_MACH_AP136,		/* Atheros AP136 reference board */
+	ATH79_MACH_AP135_020,		/* Atheros AP135-020 reference board */
+	ATH79_MACH_AP136_010,		/* Atheros AP136-010 reference board */
+	ATH79_MACH_AP136_020,		/* Atheros AP136-020 reference board */
 	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
 	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
 	ATH79_MACH_PB44,		/* Atheros PB44 reference board */
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -16,16 +16,17 @@ config ATH79_MACH_AP121
 	  Atheros AP121 reference board.
 
 config ATH79_MACH_AP136
-	bool "Atheros AP136 reference board"
+	bool "Atheros AP136/AP135 reference board"
 	select SOC_QCA955X
 	select ATH79_DEV_GPIO_BUTTONS
 	select ATH79_DEV_LEDS_GPIO
+	select ATH79_DEV_NFC
 	select ATH79_DEV_SPI
 	select ATH79_DEV_USB
 	select ATH79_DEV_WMAC
 	help
 	  Say 'Y' here if you want your kernel to support the
-	  Atheros AP136 reference board.
+	  Atheros AP136 or AP135 reference boards.
 
 config ATH79_MACH_AP81
 	bool "Atheros AP81 reference board"