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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/clock/ath79-clk.h>
#include "ath79.dtsi"
/ {
compatible = "qca,qca9557";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "mips,mips24Kc";
clocks = <&pll ATH79_CLK_CPU>;
reg = <0>;
};
};
ahb {
apb {
ddr_ctrl: memory-controller@18000000 {
compatible = "qca,ar9557-ddr-controller",
"qca,ar7240-ddr-controller";
reg = <0x18000000 0x100>;
#qca,ddr-wb-channel-cells = <1>;
};
uart: uart@18020000 {
compatible = "ns16550a";
reg = <0x18020000 0x20>;
interrupts = <3>;
clocks = <&pll ATH79_CLK_REF>;
clock-names = "uart";
reg-io-width = <4>;
reg-shift = <2>;
no-loopback-test;
status = "disabled";
};
gpio: gpio@18040000 {
compatible = "qca,ar9557-gpio",
"qca,ar9340-gpio";
reg = <0x18040000 0x28>;
interrupts = <2>;
ngpios = <24>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pinmux: pinmux@1804002c {
compatible = "pinctrl-single";
reg = <0x1804002c 0x40>;
#size-cells = <0>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x1>;
#pinctrl-cells = <2>;
jtag_disable_pins: pinmux_jtag_disable_pins {
pinctrl-single,bits = <0x40 0x2 0x2>;
};
};
pll: pll-controller@18050000 {
compatible = "qca,ar9557-pll",
"qca,qca9550-pll";
reg = <0x18050000 0x20>;
#clock-cells = <1>;
clock-output-names = "cpu", "ddr", "ahb";
};
wdt: wdt@18060008 {
compatible = "qca,ar7130-wdt";
reg = <0x18060008 0x8>;
interrupts = <4>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "wdt";
};
rst: reset-controller@1806001c {
compatible = "qca,ar9557-reset",
"qca,ar7100-reset",
"simple-bus";
reg = <0x1806001c 0x4>;
#reset-cells = <1>;
interrupt-parent = <&cpuintc>;
intc2: interrupt-controller@2 {
compatible = "qcom,qca9556-intc";
interrupts = <2>;
interrupt-controller;
#interrupt-cells = <1>;
qcom,pending-bits = <0x1f0>, /* pcie rc1 */
<0xf>; /* wmac */
};
intc3: interrupt-controller@3 {
compatible = "qcom,qca9556-intc";
interrupts = <3>;
interrupt-controller;
#interrupt-cells = <1>;
qcom,pending-bits = <0x1f000>, /* pcie rc2 */
<0x1000000>, /* usb1 */
<0x10000000>; /* usb2 */
};
};
pcie0: pcie-controller@180c0000 {
compatible = "qcom,ar7240-pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0x0>;
reg = <0x180c0000 0x1000>, /* CRP */
<0x180f0000 0x100>, /* CTRL */
<0x14000000 0x1000>; /* CFG */
reg-names = "crp_base", "ctrl_base", "cfg_base";
ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
interrupt-parent = <&intc2>;
interrupts = <0>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 1>;
interrupt-map = <0 0 0 0 &pcie0 0>;
status = "disabled";
};
};
spi: spi@1f000000 {
compatible = "qca,ar9557-spi", "qca,ar7100-spi";
reg = <0x1f000000 0x10>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "ahb";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&mdio0 {
resets = <&rst 22>;
reset-names = "mdio";
};
ð0 {
compatible = "qca,qca9550-eth", "syscon";
pll-data = <0x82000101 0x80000101 0x80001313>;
phy-mode = "rgmii";
resets = <&rst 9>;
reset-names = "mac";
};
&mdio1 {
resets = <&rst 23>;
reset-names = "mdio";
};
ð1 {
compatible = "qca,qca9550-eth", "syscon";
pll-data = <0x82000101 0x80000101 0x80001313>;
phy-mode = "sgmii";
resets = <&rst 13>;
reset-names = "mac";
};
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