summaryrefslogtreecommitdiff
path: root/target/linux/brcm63xx/patches-3.3/520-bcm63xx-add-support-for-96368MVWG-board.patch
blob: d23861ba352f8eb333e7443b8171ec79eec5aee1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
From eeacc2529942051504bc957726aa178671344421 Mon Sep 17 00:00:00 2001
From: Maxime Bizon <mbizon@freebox.fr>
Date: Wed, 20 Jan 2010 16:21:30 +0100
Subject: [PATCH 32/63] bcm63xx: add support for 96368MVWG board.

---
 arch/mips/bcm63xx/boards/board_bcm963xx.c          |   95 ++++++++++++++++++++
 .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h |    2 +
 2 files changed, 97 insertions(+), 0 deletions(-)

--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -2015,6 +2015,80 @@ static struct board_info __initdata boar
 #endif
 
 /*
+ * known 6368 boards
+ */
+#ifdef CONFIG_BCM63XX_CPU_6368
+static struct board_info __initdata board_96368mvwg = {
+	.name				= "96368MVWG",
+	.expected_cpu_id		= 0x6368,
+
+	.has_uart0			= 1,
+	.has_pci			= 1,
+	.has_enetsw			= 1,
+
+	.enetsw = {
+		.used_ports = {
+			[1] = {
+				.used	= 1,
+				.phy_id	= 2,
+				.name	= "port1",
+			},
+
+			[2] = {
+				.used	= 1,
+				.phy_id	= 3,
+				.name	= "port2",
+			},
+
+			[4] = {
+				.used	= 1,
+				.phy_id	= 0x12,
+				.external_phy = 1,
+				.name	= "port0",
+			},
+
+			[5] = {
+				.used	= 1,
+				.phy_id	= 0x11,
+				.external_phy = 1,
+				.name	= "port3",
+			},
+		},
+	},
+
+	.leds = {
+		{
+			.name		= "96368MVWG:green:adsl",
+			.gpio		= 2,
+			.active_low	= 1,
+		},
+		{
+			.name		= "96368MVWG:green:ppp",
+			.gpio		= 5,
+		},
+		{
+			.name		= "96368MVWG:green:power",
+			.gpio		= 22,
+			.active_low	= 1,
+			.default_trigger = "default-on",
+		},
+		{
+			.name		= "96368MVWG:green:wps",
+			.gpio		= 23,
+			.active_low	= 1,
+		},
+		{
+			.name		= "96368MVWG:green:ppp-fail",
+			.gpio		= 31,
+		},
+	},
+
+	.has_ohci0 = 1,
+	.has_ehci0 = 1,
+};
+#endif
+
+/*
  * all boards
  */
 static const struct board_info __initdata *bcm963xx_boards[] = {
@@ -2063,6 +2137,10 @@ static const struct board_info __initdat
 	&board_HW553,
 	&board_spw303v,
 #endif
+
+#ifdef CONFIG_BCM63XX_CPU_6368
+	&board_96368mvwg,
+#endif
 };
 
 static void __init nb4_nvram_fixup(void)
@@ -2244,12 +2322,25 @@ void __init board_prom_init(void)
 		bcm63xx_pci_enabled = 1;
 		if (BCMCPU_IS_6348())
 			val |= GPIO_MODE_6348_G2_PCI;
+
+		if (BCMCPU_IS_6368())
+			val |= GPIO_MODE_6368_PCI_REQ1 |
+				GPIO_MODE_6368_PCI_GNT1 |
+				GPIO_MODE_6368_PCI_INTB |
+				GPIO_MODE_6368_PCI_REQ0 |
+				GPIO_MODE_6368_PCI_GNT0;
 	}
 #endif
 
 	if (board.has_pccard) {
 		if (BCMCPU_IS_6348())
 			val |= GPIO_MODE_6348_G1_MII_PCCARD;
+
+		if (BCMCPU_IS_6368())
+			val |= GPIO_MODE_6368_PCMCIA_CD1 |
+				GPIO_MODE_6368_PCMCIA_CD2 |
+				GPIO_MODE_6368_PCMCIA_VS1 |
+				GPIO_MODE_6368_PCMCIA_VS2;
 	}
 
 	if (board.has_enet0 && !board.enet0.use_internal_phy) {