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authorGabor Juhos <juhosg@openwrt.org>2008-09-17 13:29:47 +0000
committerGabor Juhos <juhosg@openwrt.org>2008-09-17 13:29:47 +0000
commita43e2d5ac682241b9e8583284350f5f434def199 (patch)
treeeacbf508e03212ff206dee9a8b24b0f6601bc447
parent954c24c5ed6d5e0ab96eb9c5de706129dafef887 (diff)
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fix the PCI byte lane enable generation code, based on a patch by Chris Dearman
SVN-Revision: 12617
-rw-r--r--target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
index e3e80a9..f27c171 100644
--- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
+++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
@@ -59,17 +59,18 @@ static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
/* Byte lane enable bits */
static u8 ble_table[4][4] = {
- {0xf, 0xe, 0xd, 0xc},
- {0xc, 0x9, 0x3, 0x1},
- {0x0, 0x0, 0x0, 0x0},
- {0x0, 0x0, 0x0, 0x0},
+ {0x0, 0xf, 0xf, 0xf},
+ {0xe, 0xd, 0xb, 0x7},
+ {0xc, 0xf, 0x3, 0xf},
+ {0xf, 0xf, 0xf, 0xf},
};
static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
{
u32 t;
- t = ble_table[size][where & 3];
+ t = ble_table[size & 3][where & 3];
+ BUG_ON(t == 0xf);
t <<= (local) ? 20 : 4;
return t;
}