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| author | Nicolas Thill <nico@openwrt.org> | 2007-10-01 10:16:14 +0000 |
|---|---|---|
| committer | Nicolas Thill <nico@openwrt.org> | 2007-10-01 10:16:14 +0000 |
| commit | 05f07554267ea9c054c6b2b05628c85330cf894f (patch) | |
| tree | b257323c3f786073b63b8be5259a94e41dd187ba /package/acx/patches/003-endianness-fixes.patch | |
| parent | ffec4f291341a1e158b8c13d51219fa7ecfae244 (diff) | |
| download | mtk-20170518-05f07554267ea9c054c6b2b05628c85330cf894f.zip mtk-20170518-05f07554267ea9c054c6b2b05628c85330cf894f.tar.gz mtk-20170518-05f07554267ea9c054c6b2b05628c85330cf894f.tar.bz2 | |
revert to vlynq bus clock divisor guessing
SVN-Revision: 9086
Diffstat (limited to 'package/acx/patches/003-endianness-fixes.patch')
0 files changed, 0 insertions, 0 deletions