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| author | John Crispin <john@openwrt.org> | 2011-02-01 21:38:07 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2011-02-01 21:38:07 +0000 |
| commit | 39dc61352323c974c8fba6b2af70b7dcbd6176f7 (patch) | |
| tree | 7e26211667b2d3e45e22ed36a727866247f7506c /package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h | |
| parent | 9b9162fa1aa177c6636ec0140555641e1e95689d (diff) | |
| download | mtk-20170518-39dc61352323c974c8fba6b2af70b7dcbd6176f7.zip mtk-20170518-39dc61352323c974c8fba6b2af70b7dcbd6176f7.tar.gz mtk-20170518-39dc61352323c974c8fba6b2af70b7dcbd6176f7.tar.bz2 | |
drop uboot-ifxmips, use uboot-lantiq instead
SVN-Revision: 25294
Diffstat (limited to 'package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h')
| -rw-r--r-- | package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h | 50 |
1 files changed, 0 insertions, 50 deletions
diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h deleted file mode 100644 index 54bb6c9..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xa02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x0 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x4e20 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 |