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authorGabor Juhos <juhosg@openwrt.org>2008-11-26 17:17:13 +0000
committerGabor Juhos <juhosg@openwrt.org>2008-11-26 17:17:13 +0000
commit9f93bd51cfb695111000605877602089622e42f0 (patch)
tree3874ea9eaaaa40932203566bd309f24608fd4f9a /target/linux/ar71xx/files/arch/mips
parent4fc7535fc7a84d75361a028095ebec24fb6535ee (diff)
downloadmtk-20170518-9f93bd51cfb695111000605877602089622e42f0.zip
mtk-20170518-9f93bd51cfb695111000605877602089622e42f0.tar.gz
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rename DDR registers
SVN-Revision: 13363
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/platform.c4
-rw-r--r--target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c16
2 files changed, 10 insertions, 10 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/platform.c b/target/linux/ar71xx/files/arch/mips/ar71xx/platform.c
index 81cd20a..deda410 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/platform.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/platform.c
@@ -198,7 +198,7 @@ static struct resource ar71xx_eth0_resources[] = {
struct ag71xx_platform_data ar71xx_eth0_data = {
.reset_bit = RESET_MODULE_GE0_MAC,
- .flush_reg = DDR_REG_FLUSH_GE0,
+ .flush_reg = AR71XX_DDR_REG_FLUSH_GE0,
};
static struct platform_device ar71xx_eth0_device = {
@@ -237,7 +237,7 @@ static struct resource ar71xx_eth1_resources[] = {
struct ag71xx_platform_data ar71xx_eth1_data = {
.reset_bit = RESET_MODULE_GE1_MAC,
- .flush_reg = DDR_REG_FLUSH_GE1,
+ .flush_reg = AR71XX_DDR_REG_FLUSH_GE1,
};
static struct platform_device ar71xx_eth1_device = {
diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
index f27c171..383a708 100644
--- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
+++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
@@ -316,14 +316,14 @@ static int __init __ar71xx_pci_bios_init(unsigned nr_irqs,
ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
AR71XX_PCI_CFG_SIZE);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
- ar71xx_ddr_wr(DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
+ ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
ar71xx_pci_delay();