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authorGabor Juhos <juhosg@openwrt.org>2012-07-05 08:26:47 +0000
committerGabor Juhos <juhosg@openwrt.org>2012-07-05 08:26:47 +0000
commitd1b237b335776be151889d5339c672d784475c3c (patch)
treebe879011f76a6bdf58b86fdac7f05b69c39e5fcb /target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
parent7284cf73d69ffad645078ac5c7910913bf9757a5 (diff)
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ar71xx: add initial support for the QCA955X SoCs
SVN-Revision: 32606
Diffstat (limited to 'target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch')
-rw-r--r--target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch33
1 files changed, 26 insertions, 7 deletions
diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
index cb18fd2..7166475 100644
--- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
@@ -36,7 +36,16 @@
#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define AR934X_WMAC_SIZE 0x20000
#define AR934X_EHCI_BASE 0x1b000000
-@@ -146,6 +156,9 @@
+@@ -110,6 +120,8 @@
+ #define QCA955X_EHCI0_BASE 0x1b000000
+ #define QCA955X_EHCI1_BASE 0x1b400000
+ #define QCA955X_EHCI_SIZE 0x1000
++#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
++#define QCA955X_GMAC_SIZE 0x40
+
+ /*
+ * DDR_CTRL block
+@@ -165,6 +177,9 @@
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
@@ -46,7 +55,7 @@
#define AR724X_PLL_REG_CPU_CONFIG 0x00
#define AR724X_PLL_REG_PCIE_CONFIG 0x18
-@@ -158,6 +171,8 @@
+@@ -177,6 +192,8 @@
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
@@ -55,7 +64,7 @@
#define AR913X_PLL_REG_CPU_CONFIG 0x00
#define AR913X_PLL_REG_ETH_CONFIG 0x04
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
-@@ -170,6 +185,9 @@
+@@ -189,6 +206,9 @@
#define AR913X_AHB_DIV_SHIFT 19
#define AR913X_AHB_DIV_MASK 0x1
@@ -65,7 +74,7 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
-@@ -191,6 +209,7 @@
+@@ -210,6 +230,7 @@
#define AR934X_PLL_CPU_CONFIG_REG 0x00
#define AR934X_PLL_DDR_CONFIG_REG 0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
@@ -73,7 +82,7 @@
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-@@ -311,16 +330,50 @@
+@@ -368,16 +389,50 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
@@ -124,7 +133,7 @@
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -425,10 +478,138 @@
+@@ -518,6 +573,14 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@@ -139,8 +148,9 @@
#define AR71XX_GPIO_COUNT 16
#define AR724X_GPIO_COUNT 18
#define AR913X_GPIO_COUNT 22
- #define AR933X_GPIO_COUNT 30
+@@ -525,4 +588,133 @@
#define AR934X_GPIO_COUNT 23
+ #define QCA955X_GPIO_COUNT 24
+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
@@ -262,4 +272,13 @@
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
+
++/*
++ * QCA955X GMAC Interface
++ */
++
++#define QCA955X_GMAC_REG_ETH_CFG 0x00
++
++#define QCA955X_ETH_CFG_RGMII_GMAC0 BIT(0)
++#define QCA955X_ETH_CFG_SGMII_GMAC0 BIT(6)
++
#endif /* __ASM_MACH_AR71XX_REGS_H */