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authorGabor Juhos <juhosg@openwrt.org>2012-09-09 14:05:20 +0000
committerGabor Juhos <juhosg@openwrt.org>2012-09-09 14:05:20 +0000
commit94bac7366c2ad13a479c5476659658aeece43ca5 (patch)
tree124e976c2bef866eedff2c6a00fa9ec973aeca28 /target/linux/ar71xx/patches-3.3
parent759205777494fbf0b20eb9e133f4debb9e0d06ff (diff)
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ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934x
SVN-Revision: 33343
Diffstat (limited to 'target/linux/ar71xx/patches-3.3')
-rw-r--r--target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch18
1 files changed, 14 insertions, 4 deletions
diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
index ce1b9c5..84d7166 100644
--- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
@@ -74,15 +74,25 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
-@@ -212,6 +232,7 @@
+@@ -212,6 +232,8 @@
#define AR934X_PLL_CPU_CONFIG_REG 0x00
#define AR934X_PLL_DDR_CONFIG_REG 0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-@@ -370,16 +391,50 @@
+@@ -244,6 +266,8 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
++
+ #define QCA955X_PLL_CPU_CONFIG_REG 0x00
+ #define QCA955X_PLL_DDR_CONFIG_REG 0x04
+ #define QCA955X_PLL_CLK_CTRL_REG 0x08
+@@ -370,16 +394,50 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
@@ -133,7 +143,7 @@
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
-@@ -520,6 +575,14 @@
+@@ -520,6 +578,14 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@@ -148,7 +158,7 @@
#define AR71XX_GPIO_COUNT 16
#define AR724X_GPIO_COUNT 18
#define AR913X_GPIO_COUNT 22
-@@ -548,4 +611,133 @@
+@@ -548,4 +614,133 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7