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authorJohn Crispin <john@openwrt.org>2016-03-23 12:52:31 +0000
committerJohn Crispin <john@openwrt.org>2016-03-23 12:52:31 +0000
commit9213fefb4dafe08b6b3e4f341581d18d520f7228 (patch)
tree1ab6a6dca003beb8d6028fc160a2f22cddcc5664 /target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
parent0afb47718e5dde09231e816e99a382456e064479 (diff)
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ar71xx: Add QCA955X GPIO mux and function definitions
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> SVN-Revision: 49075
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch')
-rw-r--r--target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch13
1 files changed, 7 insertions, 6 deletions
diff --git a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index 272039f..4590a9b 100644
--- a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -600,7 +600,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_REV_ID_REVISION_MASK 0xf
/*
-@@ -634,12 +747,32 @@
+@@ -634,6 +747,25 @@
#define AR934X_GPIO_REG_OUT_FUNC5 0x40
#define AR934X_GPIO_REG_FUNC 0x6c
@@ -623,9 +623,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
+#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
+
- #define AR71XX_GPIO_COUNT 16
- #define AR7240_GPIO_COUNT 18
- #define AR7241_GPIO_COUNT 20
+ #define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
+ #define QCA955X_GPIO_REG_OUT_FUNC1 0x30
+ #define QCA955X_GPIO_REG_OUT_FUNC2 0x34
+@@ -648,6 +780,7 @@
#define AR913X_GPIO_COUNT 22
#define AR933X_GPIO_COUNT 30
#define AR934X_GPIO_COUNT 23
@@ -633,7 +634,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define QCA955X_GPIO_COUNT 24
/*
-@@ -663,6 +796,24 @@
+@@ -671,6 +804,24 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
@@ -658,7 +659,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
-@@ -804,6 +955,16 @@
+@@ -877,6 +1028,16 @@
#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
/*