strip the kernel version suffix from target directories, except for brcm-2.4 (the -2.4 will be included in the board name here). CONFIG_LINUX_<ver>_<board> becomes CONFIG_TARGET_<board>, same for profiles.

SVN-Revision: 8653

29 files changed, 0 insertions, 15408 deletions

diff --git a/target/linux/at91-2.6/image/dfboot/Makefile b/target/linux/at91-2.6/image/dfboot/Makefile
deleted file mode 100644
index 355a4b5..0000000
--- a/target/linux/at91-2.6/image/dfboot/Makefile
+++ /dev/null
@@ -1,35 +0,0 @@
-#
-# Copyright (C) 2006 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-# $Id$
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_NAME:=dfboot
-PKG_VERSION:=0.1
-PKG_RELEASE:=1
-
-PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)
-
-include $(INCLUDE_DIR)/package.mk
-
-define Build/Prepare
-	mkdir -p $(PKG_BUILD_DIR)
-	$(CP) ./src/* $(PKG_BUILD_DIR)/
-endef
-
-define Build/Compile
-	$(MAKE) -C $(PKG_BUILD_DIR) \
-		$(TARGET_CONFIGURE_OPTS) \
-		CFLAGS="$(TARGET_CFLAGS)"
-endef
-
-define Build/InstallDev
-	dd if=$(PKG_BUILD_DIR)/binary/dfboot.bin of=$(PKG_BUILD_DIR)/binary/dfboot.block bs=32k count=1 conv=sync
-endef
-
-$(eval $(call Build/DefaultTargets))
diff --git a/target/linux/at91-2.6/image/dfboot/src/Makefile b/target/linux/at91-2.6/image/dfboot/src/Makefile
deleted file mode 100644
index ff92e0d..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/Makefile
+++ /dev/null
@@ -1,94 +0,0 @@
-# Makefile for DataFlashBoot.bin
-# Must use toolchain with H/W FLoating Point
-
-BASENAME=dfboot
-BINNAME=$(BASENAME).bin
-OUTNAME=$(BASENAME).out
-LSSNAME=$(BASENAME).lss
-MAPNAME=$(BASENAME).map
-
-BASENAME2=dfbptest
-BINNAME2=$(BASENAME2).bin
-OUTNAME2=$(BASENAME2).out
-LSSNAME2=$(BASENAME2).lss
-MAPNAME2=$(BASENAME2).map
-
-INCPATH=include
-
-CFLAGS_LOCAL=-Os -Wall -I$(INCPATH)
-BUILD=$(CC) $(CFLAGS) $(CFLAGS_LOCAL)
-
-LDFLAGS+=-T elf32-littlearm.lds -Ttext 0
-LINK=$(LD) $(LDFLAGS)
-
-OBJS=objs/cstartup_ram.o objs/at45.o objs/com.o objs/dataflash.o\
-	objs/div0.o objs/init.o objs/main.o objs/asm_isr.o objs/asm_mci_isr.o\
-	objs/mci_device.o objs/jump.o objs/_udivsi3.o objs/_umodsi3.o
-
-OBJS2=objs/cstartup_ram.o objs/at45.o objs/com.o objs/dataflash.o\
-	objs/div0.o objs/init.o objs/ptmain.o objs/asm_isr.o objs/asm_mci_isr.o\
-	objs/mci_device.o objs/jump.o objs/_udivsi3.o objs/_umodsi3.o
-
-I=config.h com.h dataflash.h embedded_services.h main.h stdio.h include/AT91RM9200.h include/lib_AT91RM9200.h 
-
-all:clean $(BASENAME) $(BASENAME2)
-
-$(BASENAME): $(OBJS)
-	$(LINK) -n -o $(OUTNAME) $(OBJS)
-	$(OBJCOPY) $(OUTNAME) -O binary $(BINNAME)
-	$(OBJDUMP) -h -s $(OUTNAME) > $(LSSNAME)
-	$(NM) -n $(OUTNAME) | grep -v '\( [aUw] \)\|\(__crc_\)\|\( \$[adt]\)' > $(MAPNAME)
-	cp $(BINNAME) binary
-	
-$(BASENAME2): $(OBJS2)
-	$(LINK) -n -o $(OUTNAME2) $(OBJS2)
-	$(OBJCOPY) $(OUTNAME2) -O binary $(BINNAME2)
-	$(OBJDUMP) -h -s $(OUTNAME2) > $(LSSNAME2)
-	$(NM) -n $(OUTNAME2) | grep -v '\( [aUw] \)\|\(__crc_\)\|\( \$[adt]\)' > $(MAPNAME2)
-	cp $(BINNAME2) binary
-	
-# C objects here
-objs/at45.o: at45.c	$(I)
-	$(BUILD) -c -o objs/at45.o		at45.c
-objs/com.o: com.c	$(I)
-	$(BUILD) -c -o objs/com.o		com.c
-objs/dataflash.o: dataflash.c	$(I)
-	$(BUILD) -c -o objs/dataflash.o		dataflash.c
-objs/mci_device.o: mci_device.c	$(I)
-	$(BUILD) -c -o objs/mci_device.o		mci_device.c
-objs/div0.o: div0.c	$(I)
-	$(BUILD) -c -o objs/div0.o		div0.c
-objs/init.o: init.c	$(I)
-	$(BUILD) -c -o objs/init.o		init.c
-objs/main.o: main.c	$(I)
-	$(BUILD) -c -o objs/main.o		main.c
-objs/ptmain.o: main.c	$(I)
-	$(BUILD) -c -D PRODTEST -o objs/ptmain.o		main.c
-
-# ASM objects here
-objs/asm_isr.o: asm_isr.S
-	$(BUILD) -c -o objs/asm_isr.o		asm_isr.S
-objs/asm_mci_isr.o: asm_mci_isr.S
-	$(BUILD) -c -o objs/asm_mci_isr.o		asm_mci_isr.S
-objs/cstartup_ram.o: cstartup_ram.S
-	$(BUILD) -c -o objs/cstartup_ram.o	cstartup_ram.S
-objs/jump.o: jump.S
-	$(BUILD) -c -o objs/jump.o		jump.S
-objs/_udivsi3.o: _udivsi3.S
-	$(BUILD) -c -o objs/_udivsi3.o		_udivsi3.S
-objs/_umodsi3.o: _umodsi3.S
-	$(BUILD) -c -o objs/_umodsi3.o 		_umodsi3.S
-
-install:	$(BINNAME) $(BINNAME2)
-	cp $(BINNAME) binary
-	cp $(BINNAME2) binary
-
-clean:
-	rm -f *~
-	rm -f objs/*
-	rm -f *.out
-	rm -f *.bin
-	rm -f *.lss
-	rm -f *.map
-	rm -f .unpacked
-	mkdir -p objs
diff --git a/target/linux/at91-2.6/image/dfboot/src/_udivsi3.S b/target/linux/at91-2.6/image/dfboot/src/_udivsi3.S
deleted file mode 100644
index 2cdcd48..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/_udivsi3.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-dividend	.req	r0
-divisor		.req	r1
-result		.req	r2
-curbit		.req	r3
-/* ip		.req	r12	*/
-/* sp		.req	r13	*/
-/* lr		.req	r14	*/
-/* pc		.req	r15	*/
-	.text
-	.globl	 __udivsi3
-	.type  __udivsi3       ,function
-	.align	0
- __udivsi3      :
-	cmp	divisor, #0
-	beq	Ldiv0
-	mov	curbit, #1
-	mov	result, #0
-	cmp	dividend, divisor
-	bcc	Lgot_result
-Loop1:
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-	cmp	divisor, #0x10000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #4
-	movcc	curbit, curbit, lsl #4
-	bcc	Loop1
-Lbignum:
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-	cmp	divisor, #0x80000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #1
-	movcc	curbit, curbit, lsl #1
-	bcc	Lbignum
-Loop3:
-	@ Test for possible subtractions, and note which bits
-	@ are done in the result.  On the final pass, this may subtract
-	@ too much from the dividend, but the result will be ok, since the
-	@ "bit" will have been shifted out at the bottom.
-	cmp	dividend, divisor
-	subcs	dividend, dividend, divisor
-	orrcs	result, result, curbit
-	cmp	dividend, divisor, lsr #1
-	subcs	dividend, dividend, divisor, lsr #1
-	orrcs	result, result, curbit, lsr #1
-	cmp	dividend, divisor, lsr #2
-	subcs	dividend, dividend, divisor, lsr #2
-	orrcs	result, result, curbit, lsr #2
-	cmp	dividend, divisor, lsr #3
-	subcs	dividend, dividend, divisor, lsr #3
-	orrcs	result, result, curbit, lsr #3
-	cmp	dividend, #0			@ Early termination?
-	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
-	movne	divisor, divisor, lsr #4
-	bne	Loop3
-Lgot_result:
-	mov	r0, result
-	mov 	pc, lr
-Ldiv0:
-	str	lr, [sp, #-4]!
-	bl	 __div0       (PLT)
-	mov	r0, #0			@ about as wrong as it could be
-	ldmia	sp!, {pc}
-	.size  __udivsi3       , . -  __udivsi3
-/* # 235 "libgcc1.S" */
-/* # 320 "libgcc1.S" */
-/* # 421 "libgcc1.S" */
-/* # 433 "libgcc1.S" */
-/* # 456 "libgcc1.S" */
-/* # 500 "libgcc1.S" */
-/* # 580 "libgcc1.S" */
diff --git a/target/linux/at91-2.6/image/dfboot/src/_umodsi3.S b/target/linux/at91-2.6/image/dfboot/src/_umodsi3.S
deleted file mode 100644
index e4aebe8..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/_umodsi3.S
+++ /dev/null
@@ -1,88 +0,0 @@
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-/* # 145 "libgcc1.S" */
-dividend	.req	r0
-divisor		.req	r1
-overdone	.req	r2
-curbit		.req	r3
-/* ip		.req	r12	*/
-/* sp		.req	r13	*/
-/* lr		.req	r14	*/
-/* pc		.req	r15	*/
-	.text
-	.globl	 __umodsi3
-	.type  __umodsi3       ,function
-	.align 0
- __umodsi3      :
-	cmp	divisor, #0
-	beq	Ldiv0
-	mov	curbit, #1
-	cmp	dividend, divisor
-	movcc  	pc, lr
-Loop1:
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-	cmp	divisor, #0x10000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #4
-	movcc	curbit, curbit, lsl #4
-	bcc	Loop1
-Lbignum:
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-	cmp	divisor, #0x80000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #1
-	movcc	curbit, curbit, lsl #1
-	bcc	Lbignum
-Loop3:
-	@ Test for possible subtractions.  On the final pass, this may
-	@ subtract too much from the dividend, so keep track of which
-	@ subtractions are done, we can fix them up afterwards...
-	mov	overdone, #0
-	cmp	dividend, divisor
-	subcs	dividend, dividend, divisor
-	cmp	dividend, divisor, lsr #1
-	subcs	dividend, dividend, divisor, lsr #1
-	orrcs	overdone, overdone, curbit, ror #1
-	cmp	dividend, divisor, lsr #2
-	subcs	dividend, dividend, divisor, lsr #2
-	orrcs	overdone, overdone, curbit, ror #2
-	cmp	dividend, divisor, lsr #3
-	subcs	dividend, dividend, divisor, lsr #3
-	orrcs	overdone, overdone, curbit, ror #3
-	mov	ip, curbit
-	cmp	dividend, #0			@ Early termination?
-	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
-	movne	divisor, divisor, lsr #4
-	bne	Loop3
-	@ Any subtractions that we should not have done will be recorded in
-	@ the top three bits of "overdone".  Exactly which were not needed
-	@ are governed by the position of the bit, stored in ip.
-	@ If we terminated early, because dividend became zero,
-	@ then none of the below will match, since the bit in ip will not be
-	@ in the bottom nibble.
-	ands	overdone, overdone, #0xe0000000
-	moveq  	pc, lr				@ No fixups needed
-	tst	overdone, ip, ror #3
-	addne	dividend, dividend, divisor, lsr #3
-	tst	overdone, ip, ror #2
-	addne	dividend, dividend, divisor, lsr #2
-	tst	overdone, ip, ror #1
-	addne	dividend, dividend, divisor, lsr #1
-	mov 	pc, lr
-Ldiv0:
-	str	lr, [sp, #-4]!
-	bl	 __div0       (PLT)
-	mov	r0, #0			@ about as wrong as it could be
-	ldmia	sp!, {pc}
-	.size  __umodsi3       , . -  __umodsi3
-/* # 320 "libgcc1.S" */
-/* # 421 "libgcc1.S" */
-/* # 433 "libgcc1.S" */
-/* # 456 "libgcc1.S" */
-/* # 500 "libgcc1.S" */
-/* # 580 "libgcc1.S" */
diff --git a/target/linux/at91-2.6/image/dfboot/src/asm_isr.S b/target/linux/at91-2.6/image/dfboot/src/asm_isr.S
deleted file mode 100644
index 8d1d52e..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/asm_isr.S
+++ /dev/null
@@ -1,75 +0,0 @@
-#include "AT91RM9200_inc.h"
-
-#define ARM_MODE_USER           0x10
-#define ARM_MODE_FIQ            0x11
-#define ARM_MODE_IRQ            0x12
-#define ARM_MODE_SVC            0x13
-#define ARM_MODE_ABORT          0x17
-#define ARM_MODE_UNDEF          0x1B
-#define ARM_MODE_SYS            0x1F
-
-#define I_BIT                   0x80
-#define F_BIT                   0x40
-#define T_BIT                   0x20
-
-
-/* -----------------------------------------------------------------------------
-   AT91F_ASM_SPI_Handler
-   ---------------------
-      Handler called by the AIC
-        
-      Save context
-        Call C handler
-    Restore context
-   ----------------------------------------------------------------------------- */
-		
-.global AT91F_ST_ASM_HANDLER
-
-AT91F_ST_ASM_HANDLER:
-/*  Adjust and save LR_irq in IRQ stack */
- 	sub         r14, r14, #4
-	stmfd       sp!, {r14}
-
-/*  Write in the IVR to support Protect Mode
-  No effect in Normal Mode
-  De-assert the NIRQ and clear the source in Protect Mode */
-	ldr         r14, =AT91C_BASE_AIC
-	str         r14, [r14, #AIC_IVR]
-
-/*  Save SPSR and r0 in IRQ stack */
-	mrs         r14, SPSR
-	stmfd       sp!, {r0, r14}
-
-/*  Enable Interrupt and Switch in SYS Mode */
-	mrs         r0, CPSR
-	bic         r0, r0, #I_BIT
-	orr         r0, r0, #ARM_MODE_SYS
-	msr         CPSR_c, r0
- 
-/* Save scratch/used registers and LR in User Stack */
-	stmfd       sp!, { r1-r3, r12, r14}
-
-	ldr     r1, =AT91F_ST_HANDLER
-	mov     r14, pc
-	bx      r1
-
-/*  Restore scratch/used registers and LR from User Stack */
-	ldmia       sp!, { r1-r3, r12, r14}
-
-/*  Disable Interrupt and switch back in IRQ mode */
-	mrs         r0, CPSR
-	bic         r0, r0, #ARM_MODE_SYS
-	orr         r0, r0, #I_BIT | ARM_MODE_IRQ
-	msr         CPSR_c, r0
-
-/*  Mark the End of Interrupt on the AIC */
-	ldr         r0, =AT91C_BASE_AIC
-	str         r0, [r0, #AIC_EOICR]
-
-/*  Restore SPSR_irq and r0 from IRQ stack */
-	ldmia       sp!, {r0, r14}
-	msr         SPSR_cxsf, r14
-
-/*  Restore adjusted  LR_irq from IRQ stack directly in the PC */
-	ldmia       sp!, {pc}^
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/asm_mci_isr.S b/target/linux/at91-2.6/image/dfboot/src/asm_mci_isr.S
deleted file mode 100644
index 0f66fc0..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/asm_mci_isr.S
+++ /dev/null
@@ -1,75 +0,0 @@
-#include <AT91RM9200_inc.h>
-
-#define ARM_MODE_USER           0x10
-#define ARM_MODE_FIQ            0x11
-#define ARM_MODE_IRQ            0x12
-#define ARM_MODE_SVC            0x13
-#define ARM_MODE_ABORT          0x17
-#define ARM_MODE_UNDEF          0x1B
-#define ARM_MODE_SYS            0x1F
-
-#define I_BIT                   0x80
-#define F_BIT                   0x40
-#define T_BIT                   0x20
-
-
-/* -----------------------------------------------------------------------------
-   AT91F_ASM_MCI_Handler
-   ---------------------
-      Handler called by the AIC
-        
-      Save context
-        Call C handler
-    Restore context
-   ----------------------------------------------------------------------------- */
-		
-.global AT91F_ASM_MCI_Handler  
-
-AT91F_ASM_MCI_Handler:
-/*  Adjust and save LR_irq in IRQ stack */
- 	sub         r14, r14, #4
-	stmfd       sp!, {r14}
-
-/*  Write in the IVR to support Protect Mode
-  No effect in Normal Mode
-  De-assert the NIRQ and clear the source in Protect Mode */
-	ldr         r14, =AT91C_BASE_AIC
-	str         r14, [r14, #AIC_IVR]
-
-/*  Save SPSR and r0 in IRQ stack */
-	mrs         r14, SPSR
-	stmfd       sp!, {r0, r14}
-
-/*  Enable Interrupt and Switch in SYS Mode */
-	mrs         r0, CPSR
-	bic         r0, r0, #I_BIT
-	orr         r0, r0, #ARM_MODE_SYS
-	msr         CPSR_c, r0
- 
-/* Save scratch/used registers and LR in User Stack */
-	stmfd       sp!, { r1-r3, r12, r14}
-
-	ldr     r1, =AT91F_MCI_Handler
-	mov     r14, pc
-	bx      r1
-
-/*  Restore scratch/used registers and LR from User Stack */
-	ldmia       sp!, { r1-r3, r12, r14}
-
-/*  Disable Interrupt and switch back in IRQ mode */
-	mrs         r0, CPSR
-	bic         r0, r0, #ARM_MODE_SYS
-	orr         r0, r0, #I_BIT | ARM_MODE_IRQ
-	msr         CPSR_c, r0
-
-/*  Mark the End of Interrupt on the AIC */
-	ldr         r0, =AT91C_BASE_AIC
-	str         r0, [r0, #AIC_EOICR]
-
-/*  Restore SPSR_irq and r0 from IRQ stack */
-	ldmia       sp!, {r0, r14}
-	msr         SPSR_cxsf, r14
-
-/*  Restore adjusted  LR_irq from IRQ stack directly in the PC */
-	ldmia       sp!, {pc}^
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/at45.c b/target/linux/at91-2.6/image/dfboot/src/at45.c
deleted file mode 100644
index 8830d7e..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/at45.c
+++ /dev/null
@@ -1,595 +0,0 @@
-/*----------------------------------------------------------------------------
- *      ATMEL Microcontroller Software Support  -  ROUSSET  -
- *----------------------------------------------------------------------------
- * The software is delivered "AS IS" without warranty or condition of any
- * kind, either express, implied or statutory. This includes without
- * limitation any warranty or condition with respect to merchantability or
- * fitness for any particular purpose, or against the infringements of
- * intellectual property rights of others.
- *----------------------------------------------------------------------------
- * File Name           : at45c.h
- * Object              : 
- *
- * 1.0  10/12/03 HIi    : Creation.
- * 1.01 03/05/04 HIi    : Bug Fix in AT91F_DataFlashWaitReady() Function.
- *----------------------------------------------------------------------------
- */
-#include "config.h"
-#include "stdio.h"
-#include "AT91RM9200.h"
-#include "lib_AT91RM9200.h"
-#include "dataflash.h"
-#include "main.h"
-
-
-/*----------------------------------------------------------------------------*/
-/* \fn    AT91F_SpiInit                                                       */
-/* \brief SPI Low level Init                                                  */
-/*----------------------------------------------------------------------------*/
-void AT91F_SpiInit(void) {
-	/* Configure PIOs */
-	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | 
-	                           AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
-	                           AT91C_PA6_NPCS3 | AT91C_PA0_MISO |
-	                           AT91C_PA2_SPCK;
-	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 |
-	                           AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
-	                           AT91C_PA6_NPCS3 | AT91C_PA0_MISO |
-	                           AT91C_PA2_SPCK;
-	/* Enable CLock */
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
-
-	/* Reset the SPI */
-	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
-
-	/* Configure SPI in Master Mode with No CS selected !!! */
-	AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
-
-	/* Configure CS0 and CS3 */
-	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
-	                       (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
-	                       ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
-	                       (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
-	                       ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-}
-
-
-/*----------------------------------------------------------------------------*/
-/* \fn    AT91F_SpiEnable                                                     */
-/* \brief Enable SPI chip select                                              */
-/*----------------------------------------------------------------------------*/
-static void AT91F_SpiEnable(int cs) {
-	switch(cs) {
-	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
-		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
-		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH << 16) & AT91C_SPI_PCS);
-		break;
-	case 3:	/* Configure SPI CS3 for Serial DataFlash Card */
-		/* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
-		AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7;	/* Set in PIO mode */
-		AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7;	/* Configure in output */
-		/* Clear Output */
-		AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
-		/* Configure PCS */
-		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
-		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
-		break;
-	}
-
-	/* SPI_Enable */
-	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-/*----------------------------------------------------------------------------*/
-/* \fn    AT91F_SpiWrite                                                      */
-/* \brief Set the PDC registers for a transfert                               */
-/*----------------------------------------------------------------------------*/
-static unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
-{
-   	unsigned int timeout;
-	
-   	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-
-   	/* Initialize the Transmit and Receive Pointer */
-    	AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
-    	AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
-
-    	/* Intialize the Transmit and Receive Counters */
-    	AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
-    	AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
-
-	if ( pDesc->tx_data_size != 0 ) {
-	   	/* Initialize the Next Transmit and Next Receive Pointer */
-	   	AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
-		AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
-
-		/* Intialize the Next Transmit and Next Receive Counters */
-		AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
-	 	AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
-   	}
-
-	/* ARM simple, non interrupt dependent timer */
-	timeout = 0;
-
-	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
-	while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF));
-
-   	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-
-	if (timeout >= AT91C_DATAFLASH_TIMEOUT){
-		return AT91C_DATAFLASH_ERROR;
-	}
-
-	return AT91C_DATAFLASH_OK;
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn    AT91F_DataFlashSendCommand					*/
-/* \brief Generic function to send a command to the dataflash		*/
-/*----------------------------------------------------------------------*/
-static AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char OpCode,
-	unsigned int CmdSize,
-	unsigned int DataflashAddress)
-{
-	unsigned int adr;
-
-	/* process the address to obtain page address and byte address */
-	adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) 
-	        << pDataFlash->pDevice->page_offset) +
-	        (DataflashAddress % (pDataFlash->pDevice->pages_size));
-
-	/* fill the  command  buffer */
-	pDataFlash->pDataFlashDesc->command[0] = OpCode;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-	{
-		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
-		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
-		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
-		pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
-	}
-	else
-	{	
-		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
-		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
-		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
-		pDataFlash->pDataFlashDesc->command[4] = 0;
-	}
-	pDataFlash->pDataFlashDesc->command[5] = 0;
-	pDataFlash->pDataFlashDesc->command[6] = 0;
-	pDataFlash->pDataFlashDesc->command[7] = 0;
-
-	/* Initialize the SpiData structure for the spi write fuction */
-	pDataFlash->pDataFlashDesc->tx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
-	pDataFlash->pDataFlashDesc->tx_cmd_size =  CmdSize ;
-	pDataFlash->pDataFlashDesc->rx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
-	pDataFlash->pDataFlashDesc->rx_cmd_size =  CmdSize ;
-
-	return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);			
-}
-
-
-/*----------------------------------------------------------------------*/
-/* \fn    AT91F_DataFlashGetStatus					*/
-/* \brief Read the status register of the dataflash			*/
-/*----------------------------------------------------------------------*/
-static AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
-{
-	AT91S_DataFlashStatus status;
-
-	/* first send the read status command (D7H) */
-	pDesc->command[0] = DB_STATUS;
-	pDesc->command[1] = 0;
-
-	pDesc->DataFlash_state = GET_STATUS;
-    	pDesc->tx_data_size    = 0 ; /* Transmit the command and receive response */
-    	pDesc->tx_cmd_pt       = pDesc->command ;
-    	pDesc->rx_cmd_pt       = pDesc->command ;
-    	pDesc->rx_cmd_size     = 2 ;
-    	pDesc->tx_cmd_size     = 2 ;
-    	status = AT91F_SpiWrite (pDesc);
-
-	pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
-	return status;
-}
-
-/*-----------------------------------------------------------------------------
- * Function Name       : AT91F_DataFlashWaitReady
- * Object              : wait for dataflash ready (bit7 of the status register == 1)
- * Input Parameters    : DataFlash Service and timeout
- * Return value        : DataFlash status "ready or not"
- *-----------------------------------------------------------------------------
- */
-static AT91S_DataFlashStatus AT91F_DataFlashWaitReady(
-	AT91PS_DataflashDesc pDataFlashDesc,
-	unsigned int timeout)
-{
-	pDataFlashDesc->DataFlash_state = IDLE;
-        do {
-                AT91F_DataFlashGetStatus(pDataFlashDesc);
-                timeout--;
-        }
-        while(((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0));
-
-        if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
-                return AT91C_DATAFLASH_ERROR;
-
-        return AT91C_DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashContinuousRead                          */
-/* Object              : Continuous stream Read                                 */
-/* Input Parameters    : DataFlash Service                                      */
-/*                     : <src> = dataflash address                              */
-/*                     : <*dataBuffer> = data buffer pointer                    */
-/*                     : <sizeToRead> = data buffer size                        */
-/* Return value        : State of the dataflash                                 */
-/*------------------------------------------------------------------------------*/
-static AT91S_DataFlashStatus AT91F_DataFlashContinuousRead(
- 	AT91PS_DataFlash pDataFlash,
-	int src,
-	unsigned char *dataBuffer,
-	int sizeToRead )
-{
-	AT91S_DataFlashStatus status;
-	/* Test the size to read in the device */
-	if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
-		return AT91C_DATAFLASH_MEMORY_OVERFLOW;
-
-	pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
-	pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
-	pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
-	pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
-	
-	status = AT91F_DataFlashSendCommand(pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
-	/* Send the command to the dataflash */
-	return(status);
-}
-
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_MainMemoryToBufferTransfer                       */
-/* Object              : Read a page in the SRAM Buffer 1 or 2                  */
-/* Input Parameters    : DataFlash Service                                      */
-/*                     : Page concerned                                         */
-/*                     :                                                        */
-/* Return value        : State of the dataflash                                 */
-/*------------------------------------------------------------------------------*/
-static AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfer(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned int page)
-{
-	int cmdsize;
-	/* Test if the buffer command is legal */
-	if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
-		return AT91C_DATAFLASH_BAD_COMMAND;
-
-	/* no data to transmit or receive */
-    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
-	cmdsize = 4;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand(pDataFlash, BufferCommand, cmdsize,
-	                                  page*pDataFlash->pDevice->pages_size));
-}
-
-
-
-/*----------------------------------------------------------------------------- */
-/* Function Name       : AT91F_DataFlashWriteBuffer                             */
-/* Object              : Write data to the internal sram buffer 1 or 2          */
-/* Input Parameters    : DataFlash Service                                      */
-/*                     : <BufferCommand> = command to write buffer1 or buffer2  */
-/*                     : <*dataBuffer> = data buffer to write                   */
-/*                     : <bufferAddress> = address in the internal buffer       */
-/*                     : <SizeToWrite> = data buffer size                       */
-/* Return value        : State of the dataflash                                 */
-/*------------------------------------------------------------------------------*/
-static AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned char *dataBuffer,
-	unsigned int bufferAddress,
-	int SizeToWrite )
-{
-	int cmdsize;
-	/* Test if the buffer command is legal */
-	if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
-		return AT91C_DATAFLASH_BAD_COMMAND;
-
-	/* buffer address must be lower than page size */
-	if (bufferAddress > pDataFlash->pDevice->pages_size)
-		return AT91C_DATAFLASH_BAD_ADDRESS;
-
-    	/* Send first Write Command */
-	pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
-	pDataFlash->pDataFlashDesc->command[1] = 0;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-	{
-	   	pDataFlash->pDataFlashDesc->command[2] = 0;
-	   	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
-	   	pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
-		cmdsize = 5;
-	}
-	else
-	{
-	   	pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
-	   	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
-	   	pDataFlash->pDataFlashDesc->command[4] = 0;
-		cmdsize = 4;
-	}
-		
-	pDataFlash->pDataFlashDesc->tx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
-	pDataFlash->pDataFlashDesc->tx_cmd_size  = cmdsize ;
-	pDataFlash->pDataFlashDesc->rx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
-	pDataFlash->pDataFlashDesc->rx_cmd_size  = cmdsize ;
-
-	pDataFlash->pDataFlashDesc->rx_data_pt 	 = dataBuffer ;
-	pDataFlash->pDataFlashDesc->tx_data_pt 	 = dataBuffer ;
-	pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ;
-	pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
-
-	return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_PageErase                                        */             
-/* Object              : Read a page in the SRAM Buffer 1 or 2                  */
-/* Input Parameters    : DataFlash Service                                      */
-/*                     : Page concerned                                         */
-/*                     :                                                        */
-/* Return value        : State of the dataflash                                 */
-/*------------------------------------------------------------------------------*/
-static AT91S_DataFlashStatus AT91F_PageErase(
-	AT91PS_DataFlash pDataFlash,
-	unsigned int page)
-{
-	int cmdsize;
-	/* Test if the buffer command is legal */	
-	/* no data to transmit or receive */
-    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
-	
-	cmdsize = 4;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	return(AT91F_DataFlashSendCommand(pDataFlash, DB_PAGE_ERASE, cmdsize,
-	                                  page*pDataFlash->pDevice->pages_size));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_WriteBufferToMain                                */
-/* Object              : Write buffer to the main memory                        */
-/* Input Parameters    : DataFlash Service                                      */
-/*                     : <BufferCommand> = command to send to buf1 or buf2      */
-/*                     : <dest> = main memory address                           */
-/* Return value        : State of the dataflash                                 */
-/*------------------------------------------------------------------------------*/
-static AT91S_DataFlashStatus AT91F_WriteBufferToMain (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char BufferCommand,
-	unsigned int dest )
-{
-	int cmdsize;
-	/* Test if the buffer command is correct */
-	if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
-	    (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
-	    (BufferCommand != DB_BUF2_PAGE_PGM) &&
-	    (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
-		return AT91C_DATAFLASH_BAD_COMMAND;
-
-	/* no data to transmit or receive */
-	pDataFlash->pDataFlashDesc->tx_data_size = 0;
-
-	cmdsize = 4;
-	if (pDataFlash->pDevice->pages_number >= 16384)
-		cmdsize = 5;
-	/* Send the command to the dataflash */
-	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_PartialPageWrite                                 */
-/* Object              : Erase partially a page                                 */
-/* Input Parameters    : <page> = page number                                   */
-/*                     : <AdrInpage> = adr to begin the fading                  */
-/*                     : <length> = Number of bytes to erase                    */
-/*------------------------------------------------------------------------------*/
-static AT91S_DataFlashStatus AT91F_PartialPageWrite (
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	unsigned int dest,
-	unsigned int size)
-{
-	unsigned int page;
-	unsigned int AdrInPage;
-
-	page = dest / (pDataFlash->pDevice->pages_size);
-	AdrInPage = dest % (pDataFlash->pDevice->pages_size);
-
-	/* Read the contents of the page in the Sram Buffer */
-	AT91F_MainMemoryToBufferTransfer(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
-	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);
-	
-	/*Update the SRAM buffer */
-	AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
-	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);
-	
-	/* Erase page if a 128 Mbits device */
-	if (pDataFlash->pDevice->pages_number >= 16384)
-	{
-		AT91F_PageErase(pDataFlash, page);
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);
-	}
-
-	/* Rewrite the modified Sram Buffer in the main memory */
-	return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM,
-	                               (page*pDataFlash->pDevice->pages_size)));
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashWrite                                   */
-/* Object              :                                                        */
-/* Input Parameters    : <*src> = Source buffer                                 */
-/*                     : <dest> = dataflash adress                              */
-/*                     : <size> = data buffer size                              */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashWrite(
-	AT91PS_DataFlash pDataFlash,
-	unsigned char *src,
-	int dest,
-	int size )
-{
-	unsigned int length;
-	unsigned int page;
-	unsigned int status;
-
-	AT91F_SpiEnable(pDataFlash->pDevice->cs);
-
-	if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
-		return AT91C_DATAFLASH_MEMORY_OVERFLOW;
-
-    	/* If destination does not fit a page start address */
-	if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size)))  != 0 ) {
-		length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
-
-		if (size < length)
-			length = size;
-
-		if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
-			return AT91C_DATAFLASH_ERROR;
-
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);
-
-		/* Update size, source and destination pointers */
-        	size -= length;
-        	dest += length;
-        	src += length;
-	}
-
-	while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) 
-	{
-		/* program dataflash page */		
-		page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
-
-		status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src,
-		                                    0, pDataFlash->pDevice->pages_size);
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);
-	
-		status = AT91F_PageErase(pDataFlash, page);
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);
-		if (!status)
-			return AT91C_DATAFLASH_ERROR;
-		
-		status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
-		if(!status)
-			return AT91C_DATAFLASH_ERROR;
-
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);
-	
-		/* Update size, source and destination pointers */
-	   	size -= pDataFlash->pDevice->pages_size ;
-	   	dest += pDataFlash->pDevice->pages_size ;
-	   	src  += pDataFlash->pDevice->pages_size ;
-	}
-
-	/* If still some bytes to read */
-	if ( size > 0 ) {
-		/* program dataflash page */
-		if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
-			return AT91C_DATAFLASH_ERROR;
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);
-	}
-	return AT91C_DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashRead                                    */
-/* Object              : Read a block in dataflash                              */
-/* Input Parameters    :                                                        */
-/* Return value        :                                                        */
-/*------------------------------------------------------------------------------*/
-int AT91F_DataFlashRead(
-	AT91PS_DataFlash pDataFlash,
-	unsigned long addr,
-	unsigned long size,
-	char *buffer)
-{
-	unsigned long SizeToRead;
-
-	AT91F_SpiEnable(pDataFlash->pDevice->cs);
-
-	if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT) != AT91C_DATAFLASH_OK)
-		return -1;
-
-	while (size)
-	{
-		SizeToRead = (size < 0x8000)? size:0x8000;
-
-		if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT)
-		    != AT91C_DATAFLASH_OK)
-			return -1;
-
-		if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (unsigned char *)buffer,
-		                                   SizeToRead) != AT91C_DATAFLASH_OK)
-			return -1;
-
-		size -= SizeToRead;
-		addr += SizeToRead;
-		buffer += SizeToRead;
-	}
-
-   	return AT91C_DATAFLASH_OK;
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataflashProbe                                   */
-/* Object              :                                                        */
-/* Input Parameters    :                                                        */
-/* Return value	       : Dataflash status register                              */
-/*------------------------------------------------------------------------------*/
-int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
-{
-	AT91F_SpiEnable(cs);
-   	AT91F_DataFlashGetStatus(pDesc);
-   	return ((pDesc->command[1] == 0xFF)? 0: (pDesc->command[1] & 0x3C));
-}
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataFlashErase                                   */
-/* Object              :                                                        */
-/* Input Parameters    : <*pDataFlash> = Device info                            */
-/*------------------------------------------------------------------------------*/
-AT91S_DataFlashStatus AT91F_DataFlashErase(AT91PS_DataFlash pDataFlash)
-{
-	unsigned int page;
-	unsigned int status;
-
-	AT91F_SpiEnable(pDataFlash->pDevice->cs);
- 
- 	for(page=0; page < pDataFlash->pDevice->pages_number; page++)
-	    {
-		/* Erase dataflash page */
-		if ((page & 0x00FF) == 0)
-			printf("\rERA %d/%d", page, pDataFlash->pDevice->pages_number);
-		status = AT91F_PageErase(pDataFlash, page);
-		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);
-		if (!status)
-			return AT91C_DATAFLASH_ERROR;
-   	}
-
-	return AT91C_DATAFLASH_OK;
-}
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/com.c b/target/linux/at91-2.6/image/dfboot/src/com.c
deleted file mode 100644
index aacfb55..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/com.c
+++ /dev/null
@@ -1,368 +0,0 @@
-/*----------------------------------------------------------------------------
- *         ATMEL Microcontroller Software Support  -  ROUSSET  -
- *----------------------------------------------------------------------------
- * The software is delivered "AS IS" without warranty or condition of any
- * kind, either express, implied or statutory. This includes without
- * limitation any warranty or condition with respect to merchantability or
- * fitness for any particular purpose, or against the infringements of
- * intellectual property rights of others.
- *----------------------------------------------------------------------------
- * File Name           : com.c
- * Object              : 
- * Creation            : HIi   03/27/2003
- *
- *----------------------------------------------------------------------------
- */
-#include "AT91RM9200.h"
-#include "lib_AT91RM9200.h"
-#include "config.h"
-#include "com.h"
-#include "stdio.h"
-
-static char erase_seq[] = "\b \b";		/* erase sequence	*/
-
-#define MAX_UARTS 1
-
-//unsigned int usa[2] = {(unsigned int)AT91C_BASE_DBGU, (unsigned int)AT91C_ALTERNATE_USART};
-unsigned int usa[1] = {(unsigned int)AT91C_BASE_DBGU};
-unsigned int us;
-int port_detected;
-
-void at91_init_uarts(void)
-{
-	int i;
-
-	port_detected = 0;
-	AT91F_DBGU_CfgPIO();
-	AT91F_US0_CfgPIO();
-	AT91F_US0_CfgPMC();
-
-	for(i=0; i<MAX_UARTS; i++) {
-		us = usa[i];
-		AT91F_US_ResetRx((AT91PS_USART)us);
-		AT91F_US_ResetTx((AT91PS_USART)us);
-
-		// Configure DBGU
-		AT91F_US_Configure(
-			(AT91PS_USART)us, // DBGU base address
-			AT91C_MASTER_CLOCK,            // 60 MHz
-			AT91C_US_ASYNC_MODE,           // mode Register to be programmed
-			115200,                        // baudrate to be programmed
-			0                              // timeguard to be programmed
-			);
-
-		// Enable Transmitter
-		AT91F_US_EnableTx((AT91PS_USART)us);
-		// Enable Receiver
-		AT91F_US_EnableRx((AT91PS_USART)us);
-	}
-	us = usa[0];
-}
-
-int at91_serial_putc(int ch)
-{
-	if (ch == '\n')
-		at91_serial_putc('\r');
-	while (!AT91F_US_TxReady((AT91PS_USART)us));
-	AT91F_US_PutChar((AT91PS_USART)us, (char)ch);
-	return ch;
-}
-
-/* This getc is modified to be able work on more than one port. On certain
- * boards (i.e. Figment Designs VersaLink), the debug port is not available
- * once the unit is in it's enclosure, so, if one needs to get into dfboot
- * for any reason it is impossible. With this getc, it scans between the debug
- * port and another port and once it receives a character, it sets that port
- * as the debug port. */
-int at91_serial_getc()
-{
-	while(1) {
-#if 0
-		if (!port_detected) {
-			if (us == usa[0]) {
-				us = usa[1];
-			}
-			else {
-				us = usa[0];
-			}
-		}
-#endif
-		if(AT91F_US_RxReady((AT91PS_USART)us)) {
-#if 0
-			port_detected = 1;
-#endif
-			return((int)AT91F_US_GetChar((AT91PS_USART)us));
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------------
- * Function Name       : AT91F_ReadLine()
- * Object              : 
- * Input Parameters    : 
- * Return value		: 
- *-----------------------------------------------------------------------------
- */
-int AT91F_ReadLine (const char *const prompt, char *console_buffer)
-{
-	char *p = console_buffer;
-	int	n = 0;					/* buffer index		*/
-	int	plen = strlen (prompt);	/* prompt length	*/
-	int	col;					/* output column cnt	*/
-	char	c;
-
-	/* print prompt */
-	if (prompt)
-		printf(prompt);
-	col = plen;
-
-	for (;;) {
-		c = getc();
-
-		switch (c) {
-			case '\r':				/* Enter		*/
-			case '\n':
-				*p = '\0';
-				puts ("\n");
-				return (p - console_buffer);
-
-			case 0x03:				/* ^C - break	*/
-				console_buffer[0] = '\0';	/* discard input */
-				return (-1);
-
-			case 0x08:				/* ^H  - backspace	*/
-			case 0x7F:				/* DEL - backspace	*/
-				if (n) {
-					--p;
-					printf(erase_seq);
-					col--;
-					n--;
-					}
-				continue;
-
-			default:
-			/*
-			 * Must be a normal character then
-			 */
-			if (n < (AT91C_CB_SIZE -2)) 
-			{
-				++col;		/* echo input		*/
-				putc(c);
-				*p++ = c;
-				++n;
-			} 
-			else 
-			{			/* Buffer full		*/
-				putc('\a');
-			}
-		}
-	}
-}
-
-
-/*-----------------------------------------------------------------------------
- * Function Name       : AT91F_WaitKeyPressed()
- * Object              : 
- * Input Parameters    : 
- * Return value		: 
- *-----------------------------------------------------------------------------
- */
-void AT91F_WaitKeyPressed(void)
-{
-	int c;
-    	puts("KEY");
-		c = getc();
-	putc('\n');
-}
-
-int puts(const char *str)
-{
-  while(*str != 0) {
-		at91_serial_putc(*str);
-		str++;
-		}
-	return 1;
-}
-
-int putc(int c)
-{
-  return at91_serial_putc(c);
-}
-
-int putchar(c)
-{
-	return putc(c);
-}
-
-int getc()
-{
-  return at91_serial_getc();
-}
-
-int strlen(const char *str)
-{
-  int len = 0;
-
-  if(str == (char *)0)
-    return 0;
-
-  while(*str++ != 0)
-    len++;
-
-  return len;
-}
-
-#define ZEROPAD 1               /* pad with zero */
-#define SIGN    2               /* unsigned/signed long */
-#define LEFT    4              /* left justified */
-#define LARGE   8              /* use 'ABCDEF' instead of 'abcdef' */
-
-#define do_div(n,base) ({ \
-        int __res; \
-        __res = ((unsigned) n) % (unsigned) base; \
-        n = ((unsigned) n) / (unsigned) base; \
-        __res; \
-})
-
-static int number(int num, int base, int size,
-                  int precision, int type)
-{
-  char c, sign, tmp[66];
-  const char *digits="0123456789ABCDEF";
-  int i;
-
-  if (type & LEFT)
-    type &= ~ZEROPAD;
-  if (base < 2 || base > 16)
-    return 0;
-  c = (type & ZEROPAD) ? '0' : ' ';
-  sign = 0;
-
-  if(type & SIGN && num < 0)
-    {
-      sign = '-';
-      num = -num;
-      size--;
-    }
-  
-  i = 0;
-  if(num == 0)
-    tmp[i++] = digits[0];
-  else while(num != 0)
-    tmp[i++] = digits[do_div(num, base)];
-
-  if(i > precision)
-    precision = i;
-  size -= precision;
-  
-  if(!(type&(ZEROPAD+LEFT)))
-    while(size-->0)
-      putc(' ');
-  
-  if(sign)
-    putc(sign);
-
-  if (!(type & LEFT))
-    while (size-- > 0)
-      putc(c);
-
-  while (i < precision--)
-    putc('0');
-  
-  while (i-- > 0)
-    putc(tmp[i]);
-
-  while (size-- > 0)
-    putc(' ');;
-
-  return 1;
-}
-
-int hvfprintf(const char *fmt, va_list va)
-{
-  char *s;
-
-	do {
-		if(*fmt == '%')	{
-			bool done = false;
-
-			int type = 0;
-			int precision = 0;
-
-			do {
-				fmt++;
-				switch(*fmt) {
-				case '0' :
-					if(!precision)
-						type |= ZEROPAD;
-				case '1' :
-				case '2' :
-				case '3' :
-				case '4' :
-				case '5' :
-				case '6' :
-				case '7' :
-				case '8' :
-				case '9' :
-					precision = precision * 10 + (*fmt - '0');
-					break;
-				case '.' :
-					break;
-				case 's' :
-					s = va_arg(va, char *);
-					if(!s)
-						puts("<NULL>");
-					else
-						puts(s);
-					done = true;
-					break;
-				case 'c' :
-					putc(va_arg(va, int));
-					done = true;
-					break;
-				case 'd' :
-					number(va_arg(va, int), 10, 0, precision, type);
-					done = true;
-					break;
-				case 'x' :
-				case 'X' :
-					number(va_arg(va, int), 16, 0, precision, type);
-					done = true;
-					break;
-				case '%' :
-					putc(*fmt);
-					done = true;
-				default: 
-					putc('%');
-					putc(*fmt);
-					done = true;
-					break;
-				} 
-			} while(!done);
-		} else if(*fmt == '\\') {
-			fmt++;
-			if(*fmt == 'r') {
-				putc('\r');
-			} else if(*fmt == 'n') { 
-				putc('\n');
-			}
-        	} else {
-         		putc(*fmt);
-        	}
-		fmt++;
-	} while(*fmt != 0);
-  
-  return 0;
-}
-
-int printf(const char *fmt, ...)
-{
-  va_list ap;
-  int i;
-
-  va_start(ap, fmt);
-  i = hvfprintf(fmt, ap);
-  va_end(ap);
-
-  return i;
-}
diff --git a/target/linux/at91-2.6/image/dfboot/src/com.h b/target/linux/at91-2.6/image/dfboot/src/com.h
deleted file mode 100644
index 7af09e4..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/com.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*----------------------------------------------------------------------------
- *      ATMEL Microcontroller Software Support  -  ROUSSET  -
- *----------------------------------------------------------------------------
- * The software is delivered "AS IS" without warranty or condition of any
- * kind, either express, implied or statutory. This includes without
- * limitation any warranty or condition with respect to merchantability or
- * fitness for any particular purpose, or against the infringements of
- * intellectual property rights of others.
- *----------------------------------------------------------------------------
- * File Name           : com.h
- * Object              : 
- *
- * 1.0 27/03/03 HIi    : Creation
- *----------------------------------------------------------------------------
- */
-#ifndef com_h
-#define com_h
-
-#define AT91C_CB_SIZE 20 /* size of the console buffer */
-
-/* Escape sequences */
-#define ESC \033
-
-extern int AT91F_ReadLine (const char *const prompt, char *console_buffer);
-extern void AT91F_WaitKeyPressed(void);
-
-#endif
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/config.h b/target/linux/at91-2.6/image/dfboot/src/config.h
deleted file mode 100644
index 3be8d49..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/config.h
+++ /dev/null
@@ -1,17 +0,0 @@
-
-#ifndef _CONFIG_H
-#define _CONFIG_H
-
-//#define	PAGESZ_1056			1
-#undef PAGESZ_1056
-#define	SPI_LOW_SPEED			1
-#define AT91C_DELAY_TO_BOOT 		1500
-
-#define	CRC_RETRIES			0x100
-
-#define AT91C_MASTER_CLOCK              59904000
-#define AT91C_BAUD_RATE                 115200
-
-#define AT91C_ALTERNATE_USART	AT91C_BASE_US0
-
-#endif
diff --git a/target/linux/at91-2.6/image/dfboot/src/cstartup_ram.S b/target/linux/at91-2.6/image/dfboot/src/cstartup_ram.S
deleted file mode 100644
index 2239000..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/cstartup_ram.S
+++ /dev/null
@@ -1,144 +0,0 @@
-#include "AT91RM9200_inc.h"
-		
-/*---------------------------
-ARM Core Mode and Status Bits
----------------------------*/
-.section start
-	.text
-			
-#define ARM_MODE_USER   0x10
-#define ARM_MODE_FIQ    0x11
-#define ARM_MODE_IRQ    0x12
-#define ARM_MODE_SVC    0x13
-#define ARM_MODE_ABORT  0x17
-#define ARM_MODE_UNDEF  0x1B
-#define ARM_MODE_SYS    0x1F
-
-#define I_BIT           0x80
-#define F_BIT           0x40
-#define T_BIT           0x20
-
-/*----------------------------------------------------------------------------
- Area Definition
-----------------
- Must be defined as function to put first in the code as it must be mapped
- at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap.
-_---------------------------------------------------------------------------*/
-
-  .align  4
-	.globl _start
-_start:
-
-/*----------------------------------------------------------------------------
- Exception vectors ( before Remap )
-------------------------------------
- These vectors are read at address 0.
- They absolutely requires to be in relative addresssing mode in order to
- guarantee a valid jump. For the moment, all are just looping (what may be
- dangerous in a final system). If an exception occurs before remap, this
- would result in an infinite loop.
-----------------------------------------------------------------------------*/
-                b           reset			       	/* reset */
-                b           undefvec        	/* Undefined Instruction */
-                b           swivec          	/* Software Interrupt */
-                b           pabtvec         	/* Prefetch Abort */
-                b           dabtvec         	/* Data Abort */
-                b           rsvdvec         	/* reserved */
-                b           aicvec				    /* IRQ : read the AIC */
-                b           fiqvec          	/* FIQ */
-
-undefvec:
-swivec:
-pabtvec:
-dabtvec:
-rsvdvec:
-aicvec:
-fiqvec:
-	b	undefvec
-
-reset:
-
-#define MEMEND 0x00004000
-
-/* ----------------------------
- Setup the stack for each mode
----------------------------- */
-
-#define IRQ_STACK_SIZE  0x10
-#define FIQ_STACK_SIZE  0x04
-#define ABT_STACK_SIZE  0x04
-#define UND_STACK_SIZE  0x04
-#define SVC_STACK_SIZE  0x10
-#define USER_STACK_SIZE 0x400
-	
-                ldr     r0,= MEMEND
-
-/*- Set up Supervisor Mode and set Supervisor Mode Stack*/
-                msr     CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT
-                mov     r13, r0                     /* Init stack Undef*/
-                sub     r0, r0, #SVC_STACK_SIZE
-
-/*- Set up Interrupt Mode and set IRQ Mode Stack*/
-                msr     CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
-                mov     r13, r0                     /* Init stack IRQ*/
-                sub     r0, r0, #IRQ_STACK_SIZE
-
-/*- Set up Fast Interrupt Mode and set FIQ Mode Stack*/
-                msr     CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
-                mov     r13, r0                     /* Init stack FIQ*/
-                sub     r0, r0, #FIQ_STACK_SIZE
-
-/*- Set up Abort Mode and set Abort Mode Stack*/
-                msr     CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT
-                mov     r13, r0                     /* Init stack Abort*/
-                sub     r0, r0, #ABT_STACK_SIZE
-
-/*- Set up Undefined Instruction Mode and set Undef Mode Stack*/
-                msr     CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT
-                mov     r13, r0                     /* Init stack Undef*/
-                sub     r0, r0, #UND_STACK_SIZE
-
-/*- Set up user Mode and set System Mode Stack*/
-                msr     CPSR_c, #ARM_MODE_SYS | I_BIT | F_BIT
-                bic     r0, r0, #3                  /* Insure word alignement */
-               	mov     sp, r0                      /* Init stack System */
-
-
-		ldr       r0, = AT91F_LowLevelInit
-		mov       lr, pc
-		bx        r0
-
-/*----------------------------------------
- Read/modify/write CP15 control register
-----------------------------------------*/
-		mrc     p15, 0, r0, c1, c0,0  /* read cp15 control registre (cp15 r1) in r0 */
-		ldr     r3,= 0xC0000080      /* Reset bit :Little Endian end fast bus mode */
-		ldr     r4,= 0xC0001000      /* Set bit :Asynchronous clock mode, Not Fast Bus, I-Cache enable */
-		bic     r0, r0, r3
-		orr     r0, r0, r4
-		mcr     p15, 0, r0, c1, c0,0 /* write r0 in cp15 control registre (cp15 r1) */
-
-/* Enable interrupts */
-		msr     CPSR_c, #ARM_MODE_SYS | F_BIT
-
-/*------------------------------------------------------------------------------
-- Branch on C code Main function (with interworking)
-----------------------------------------------------
-- Branch must be performed by an interworking call as either an ARM or Thumb
-- _start function must be supported. This makes the code not position-
-- independent. A Branch with link would generate errors
-----------------------------------------------------------------------------*/
-	
-/*- Branch to _start by interworking*/
-		ldr     r4, = main
-	        mov     lr, pc
-	        bx      r4
-	
-/*-----------------------------------------------------------------------------
-- Loop for ever
----------------
-- End of application. Normally, never occur.
-- Could jump on Software Reset ( B 0x0 ).
-------------------------------------------------------------------------------*/
-End:
-	        b       End
diff --git a/target/linux/at91-2.6/image/dfboot/src/dataflash.c b/target/linux/at91-2.6/image/dfboot/src/dataflash.c
deleted file mode 100644
index 5e54460..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/dataflash.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*----------------------------------------------------------------------------
- *         ATMEL Microcontroller Software Support  -  ROUSSET  -
- *----------------------------------------------------------------------------
- * The software is delivered "AS IS" without warranty or condition of any
- * kind, either express, implied or statutory. This includes without
- * limitation any warranty or condition with respect to merchantability or
- * fitness for any particular purpose, or against the infringements of
- * intellectual property rights of others.
- *----------------------------------------------------------------------------
- * File Name           : dataflash.c
- * Object              : High level functions for the dataflash
- * Creation            : HIi   10/10/2003
- *----------------------------------------------------------------------------
- */
-#include "config.h"
-#include "stdio.h"
-#include "dataflash.h"
-
-
-AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
-static AT91S_DataFlash DataFlashInst;
-
-int cs[][CFG_MAX_DATAFLASH_BANKS] = {
-	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
-	{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3}
-};
-
-int AT91F_DataflashInit(void)
-{
-	int i;
-	int dfcode;
-	int Nb_device = 0;
-		
-	AT91F_SpiInit();
-
-	for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) {
-		dataflash_info[i].id = 0;
-		dataflash_info[i].Device.pages_number = 0;
-		dfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc);
-
-		switch (dfcode) {
-		case AT45DB161:
-			dataflash_info[i].Device.pages_number = 4096;
-			dataflash_info[i].Device.pages_size = 528;
-			dataflash_info[i].Device.page_offset = 10;
-			dataflash_info[i].Device.byte_mask = 0x300;
-			dataflash_info[i].Device.cs = cs[i][1];
-			dataflash_info[i].Desc.DataFlash_state = IDLE;
-			dataflash_info[i].logical_address = cs[i][0];
-			dataflash_info[i].id = dfcode;
-			Nb_device++;
-			break;
-
-		case AT45DB321:
-			dataflash_info[i].Device.pages_number = 8192;
-			dataflash_info[i].Device.pages_size = 528;
-			dataflash_info[i].Device.page_offset = 10;
-			dataflash_info[i].Device.byte_mask = 0x300;
-			dataflash_info[i].Device.cs = cs[i][1];
-			dataflash_info[i].Desc.DataFlash_state = IDLE;
-			dataflash_info[i].logical_address = cs[i][0];
-			dataflash_info[i].id = dfcode;
-			Nb_device++;
-			break;
-
-		case AT45DB642:
-			dataflash_info[i].Device.pages_number = 8192;
-			dataflash_info[i].Device.pages_size = 1056;
-			dataflash_info[i].Device.page_offset = 11;
-			dataflash_info[i].Device.byte_mask = 0x700;
-			dataflash_info[i].Device.cs = cs[i][1];
-			dataflash_info[i].Desc.DataFlash_state = IDLE;
-			dataflash_info[i].logical_address = cs[i][0];
-			dataflash_info[i].id = dfcode;
-			Nb_device++;
-			break;
-		case AT45DB128:
-			dataflash_info[i].Device.pages_number = 16384;
-			dataflash_info[i].Device.pages_size = 1056;
-			dataflash_info[i].Device.page_offset = 11;
-			dataflash_info[i].Device.byte_mask = 0x700;
-			dataflash_info[i].Device.cs = cs[i][1];
-			dataflash_info[i].Desc.DataFlash_state = IDLE;
-			dataflash_info[i].logical_address = cs[i][0];
-			dataflash_info[i].id = dfcode;
-			Nb_device++;
-			break;
-		default:
-			break;
-		}
-	}			
-	return (Nb_device);
-}
-
-
-void AT91F_DataflashPrintInfo(void)
-{
-	int i;
-	for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) {
-		if (dataflash_info[i].id != 0) {
-			printf ("DF:AT45DB");
-			switch (dataflash_info[i].id) {
-			case AT45DB161:
-				printf ("161");
-				break;
-
-			case AT45DB321:
-				printf ("321");
-				break;
-
-			case AT45DB642:
-				printf ("642");
-				break;
-			case AT45DB128:				
-				printf ("128");
-				break;
-			}
-
-			printf ("\n# PG: %6d\n"
-				"PG SZ: %6d\n"
-				"SZ=%8d bytes\n"
-				"ADDR: %08X\n",
-				(unsigned int) dataflash_info[i].Device.pages_number,
-				(unsigned int) dataflash_info[i].Device.pages_size,
-				(unsigned int) dataflash_info[i].Device.pages_number *
-				dataflash_info[i].Device.pages_size,
-				(unsigned int) dataflash_info[i].logical_address);
-		}
-	}
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : AT91F_DataflashSelect                                  */
-/* Object              : Select the correct device                              */
-/*------------------------------------------------------------------------------*/
-static AT91PS_DataFlash AT91F_DataflashSelect(AT91PS_DataFlash pFlash,
-                                              unsigned int *addr)
-{
-	char addr_valid = 0;
-	int i;
-
-	for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++)
-		if ((*addr & 0xFF000000) == dataflash_info[i].logical_address) {
-			addr_valid = 1;
-			break;
-		}
-	if (!addr_valid) {
-		pFlash = (AT91PS_DataFlash) 0;
-		return pFlash;
-	}
-	pFlash->pDataFlashDesc = &(dataflash_info[i].Desc);
-	pFlash->pDevice = &(dataflash_info[i].Device);
-	*addr -= dataflash_info[i].logical_address;
-	return (pFlash);
-}
-
-
-/*------------------------------------------------------------------------------*/
-/* Function Name       : read_dataflash                                         */
-/* Object              : dataflash memory read                                  */
-/*------------------------------------------------------------------------------*/
-int read_dataflash(unsigned long addr, unsigned long size, char *result)
-{
-	unsigned int AddrToRead = addr;
-	AT91PS_DataFlash pFlash = &DataFlashInst;
-
-	pFlash = AT91F_DataflashSelect (pFlash, &AddrToRead);
-	if (pFlash == 0)
-		return -1;
-
-	return (AT91F_DataFlashRead(pFlash, AddrToRead, size, result));
-}
-
-
-/*-----------------------------------------------------------------------------*/
-/* Function Name       : write_dataflash                                       */
-/* Object              : write a block in dataflash                            */
-/*-----------------------------------------------------------------------------*/
-int write_dataflash(unsigned long addr_dest, unsigned int addr_src,
-                    unsigned int size)
-{
-	unsigned int AddrToWrite = addr_dest;
-	AT91PS_DataFlash pFlash = &DataFlashInst;
-
-	pFlash = AT91F_DataflashSelect(pFlash, &AddrToWrite);
-	if (AddrToWrite == -1)
-		return -1;
-
-	return AT91F_DataFlashWrite(pFlash, (unsigned char *) addr_src, AddrToWrite, size);
-}
-
-/*-----------------------------------------------------------------------------*/
-/* Function Name       : erase_dataflash                                       */
-/* Object              : Erase entire dataflash                                */
-/*-----------------------------------------------------------------------------*/
-int erase_dataflash(unsigned long addr_dest)
-{
-	unsigned int AddrToWrite = addr_dest;
-	AT91PS_DataFlash pFlash = &DataFlashInst;
-
-	pFlash = AT91F_DataflashSelect (pFlash, &AddrToWrite);
-	if (AddrToWrite == -1)
-		return -1;
-
-	return AT91F_DataFlashErase(pFlash);
-}
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/dataflash.h b/target/linux/at91-2.6/image/dfboot/src/dataflash.h
deleted file mode 100644
index 8fab63f..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/dataflash.h
+++ /dev/null
@@ -1,181 +0,0 @@
-//*---------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*---------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*---------------------------------------------------------------------------
-//* File Name           : AT91_SpiDataFlash.h
-//* Object              : Data Flash Atmel Description File
-//* Translator          :
-//*
-//* 1.0 03/04/01 HI	: Creation
-//*
-//*---------------------------------------------------------------------------
-
-#ifndef _DataFlash_h
-#define _DataFlash_h
-
-/* Max value = 15Mhz to be compliant with the Continuous array read function */
-#ifdef	SPI_LOW_SPEED
-#define AT91C_SPI_CLK 14976000/4
-#else
-#define AT91C_SPI_CLK 14976000 
-#endif
-
-/* AC characteristics */
-/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */
-
-#define DATAFLASH_TCSS (0xf << 16)	/* 250ns 15/60000000 */
-#define DATAFLASH_TCHS (0x1 << 24)	/* 250ns 32*1/60000000 */
-
-
-#define AT91C_SPI_PCS0_SERIAL_DATAFLASH		0xE     /* Chip Select 0 : NPCS0 %1110 */
-#define AT91C_SPI_PCS3_DATAFLASH_CARD		0x7     /* Chip Select 3 : NPCS3 %0111 */
-
-#define CFG_MAX_DATAFLASH_BANKS 	    2
-#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000
-#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000
-
-typedef struct {
-	unsigned long base;		/* logical base address for a bank */
-	unsigned long size;		/* total bank size */
-	unsigned long page_count;
-	unsigned long page_size;
-	unsigned long id;		/* device id */
-} dataflash_info_t;
-
-typedef unsigned int AT91S_DataFlashStatus;
-
-/*----------------------------------------------------------------------*/
-/* DataFlash Structures							*/
-/*----------------------------------------------------------------------*/
-
-/*---------------------------------------------*/
-/* DataFlash Descriptor Structure Definition   */
-/*---------------------------------------------*/
-typedef struct _AT91S_DataflashDesc {
-	unsigned char *tx_cmd_pt;
-	unsigned int tx_cmd_size;
-	unsigned char *rx_cmd_pt;
-	unsigned int rx_cmd_size;
-	unsigned char *tx_data_pt;
-	unsigned int tx_data_size;
-	unsigned char *rx_data_pt;
-	unsigned int rx_data_size;
-	volatile unsigned char DataFlash_state;
-	unsigned char command[8];
-} AT91S_DataflashDesc, *AT91PS_DataflashDesc;
-
-/*---------------------------------------------*/
-/* DataFlash device definition structure       */
-/*---------------------------------------------*/
-typedef struct _AT91S_Dataflash {
-	int pages_number;			/* dataflash page number */
-	int pages_size;				/* dataflash page size */
-	int page_offset;			/* page offset in command */
-	int byte_mask;				/* byte mask in command */
-	int cs;
-} AT91S_DataflashFeatures, *AT91PS_DataflashFeatures;
-
-
-/*---------------------------------------------*/
-/* DataFlash Structure Definition	       */
-/*---------------------------------------------*/
-typedef struct _AT91S_DataFlash {
-	AT91PS_DataflashDesc pDataFlashDesc;	/* dataflash descriptor */
-	AT91PS_DataflashFeatures pDevice;	/* Pointer on a dataflash features array */
-} AT91S_DataFlash, *AT91PS_DataFlash;
-
-
-typedef struct _AT91S_DATAFLASH_INFO {
-
-	AT91S_DataflashDesc 	Desc;
-	AT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */
-	unsigned long 			logical_address;
-	unsigned int 			id;			/* device id */
-} AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO;
-
-
-/*-------------------------------------------------------------------------------------------------*/
-
-#define AT45DB161		0x2c
-#define AT45DB321		0x34
-#define AT45DB642		0x3c
-#define AT45DB128		0x10
-
-#define AT91C_DATAFLASH_TIMEOUT			20000	/* For AT91F_DataFlashWaitReady */
-
-/* DataFlash return value */
-#define AT91C_DATAFLASH_BUSY			0x00
-#define AT91C_DATAFLASH_OK			0x01
-#define AT91C_DATAFLASH_ERROR			0x02
-#define AT91C_DATAFLASH_MEMORY_OVERFLOW		0x03
-#define AT91C_DATAFLASH_BAD_COMMAND		0x04
-#define AT91C_DATAFLASH_BAD_ADDRESS		0x05
-
-
-/* Driver State */
-#define IDLE		0x0
-#define BUSY		0x1
-#define ERROR		0x2
-
-/* DataFlash Driver State */
-#define GET_STATUS	0x0F
-
-/*-------------------------------------------------------------------------------------------------*/
-/* Command Definition										   */
-/*-------------------------------------------------------------------------------------------------*/
-
-/* READ COMMANDS */
-#define DB_CONTINUOUS_ARRAY_READ	0xE8	/* Continuous array read */
-#define DB_BURST_ARRAY_READ		0xE8	/* Burst array read */
-#define DB_PAGE_READ			0xD2	/* Main memory page read */
-#define DB_BUF1_READ			0xD4	/* Buffer 1 read */
-#define DB_BUF2_READ			0xD6	/* Buffer 2 read */
-#define DB_STATUS			0xD7	/* Status Register */
-
-/* PROGRAM and ERASE COMMANDS */
-#define DB_BUF1_WRITE			0x84	/* Buffer 1 write */
-#define DB_BUF2_WRITE			0x87	/* Buffer 2 write */
-#define DB_BUF1_PAGE_ERASE_PGM		0x83	/* Buffer 1 to main memory page program with built-In erase */
-#define DB_BUF1_PAGE_ERASE_FASTPGM	0x93	/* Buffer 1 to main memory page program with built-In erase, Fast program */
-#define DB_BUF2_PAGE_ERASE_PGM		0x86	/* Buffer 2 to main memory page program with built-In erase */
-#define DB_BUF2_PAGE_ERASE_FASTPGM	0x96	/* Buffer 1 to main memory page program with built-In erase, Fast program */
-#define DB_BUF1_PAGE_PGM		0x88	/* Buffer 1 to main memory page program without built-In erase */
-#define DB_BUF1_PAGE_FASTPGM		0x98	/* Buffer 1 to main memory page program without built-In erase, Fast program */
-#define DB_BUF2_PAGE_PGM		0x89	/* Buffer 2 to main memory page program without built-In erase */
-#define DB_BUF2_PAGE_FASTPGM		0x99	/* Buffer 1 to main memory page program without built-In erase, Fast program */
-#define DB_PAGE_ERASE			0x81	/* Page Erase */
-#define DB_BLOCK_ERASE			0x50	/* Block Erase */
-#define DB_PAGE_PGM_BUF1		0x82	/* Main memory page through buffer 1 */
-#define DB_PAGE_FASTPGM_BUF1		0x92	/* Main memory page through buffer 1, Fast program */
-#define DB_PAGE_PGM_BUF2		0x85	/* Main memory page through buffer 2 */
-#define DB_PAGE_FastPGM_BUF2		0x95	/* Main memory page through buffer 2, Fast program */
-
-/* ADDITIONAL COMMANDS */
-#define DB_PAGE_2_BUF1_TRF		0x53	/* Main memory page to buffer 1 transfert */
-#define DB_PAGE_2_BUF2_TRF		0x55	/* Main memory page to buffer 2 transfert */
-#define DB_PAGE_2_BUF1_CMP		0x60	/* Main memory page to buffer 1 compare */
-#define DB_PAGE_2_BUF2_CMP		0x61	/* Main memory page to buffer 2 compare */
-#define DB_AUTO_PAGE_PGM_BUF1		0x58	/* Auto page rewrite throught buffer 1 */
-#define DB_AUTO_PAGE_PGM_BUF2		0x59	/* Auto page rewrite throught buffer 2 */
-
-/*-------------------------------------------------------------------------------------------------*/
-
-extern AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
-
-extern void AT91F_SpiInit(void);
-extern int AT91F_DataflashProbe(int i, AT91PS_DataflashDesc pDesc);
-extern int AT91F_DataFlashRead(AT91PS_DataFlash, unsigned long , unsigned long, char *);
-extern AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash ,unsigned char *, int, int);
-extern AT91S_DataFlashStatus AT91F_DataFlashErase(AT91PS_DataFlash pDataFlash);
-extern int AT91F_DataflashInit(void);
-extern void AT91F_DataflashPrintInfo(void);
-extern int read_dataflash(unsigned long addr, unsigned long size, char *result);
-extern int write_dataflash(unsigned long addr_dest, unsigned int addr_src, unsigned int size);
-extern int erase_dataflash(unsigned long addr_dest);
-
-#endif
diff --git a/target/linux/at91-2.6/image/dfboot/src/div0.c b/target/linux/at91-2.6/image/dfboot/src/div0.c
deleted file mode 100644
index d6fd90e..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/div0.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* Replacement (=dummy) for GNU/Linux division-by zero handler */
-void __div0 (void)
-{
-	while(-1);
-}
diff --git a/target/linux/at91-2.6/image/dfboot/src/elf32-littlearm.lds b/target/linux/at91-2.6/image/dfboot/src/elf32-littlearm.lds
deleted file mode 100644
index 4d4efb6..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/elf32-littlearm.lds
+++ /dev/null
@@ -1,19 +0,0 @@
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-        . = 0x00000000;
-
-        . = ALIGN(4);
-        .text : { *(.text) }
-
-        . = ALIGN(4);
-        .rodata : { *(.rodata) }
-
-        . = ALIGN(4);
-        .data : { *(.data) }
-
-        . = ALIGN(4);
-        .bss : { *(.bss) }
-}
\ No newline at end of file
diff --git a/target/linux/at91-2.6/image/dfboot/src/embedded_services.h b/target/linux/at91-2.6/image/dfboot/src/embedded_services.h
deleted file mode 100644
index 956b9ed..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/embedded_services.h
+++ /dev/null
@@ -1,500 +0,0 @@
-//*----------------------------------------------------------------------------
-//*      ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : embedded_sevices.h
-//* Object              : Header File with all the embedded software services definitions
-//*
-//* 1.0 24 Jan 2003 FB  : Creation
-//*----------------------------------------------------------------------------
-#ifndef embedded_sevices_h
-#define embedded_sevices_h
-
-#include "AT91RM9200.h"
-
-#define AT91C_BASE_ROM	(char *)0x00100000
-
-/* Return values */
-#define AT91C_BUFFER_SUCCESS		   0
-#define AT91C_BUFFER_ERROR_SHIFT      16
-#define AT91C_BUFFER_ERROR            (0x0F << AT91C_BUFFER_ERROR_SHIFT)
-
-#define AT91C_BUFFER_OVERFLOW         (0x01 << AT91C_BUFFER_ERROR_SHIFT)
-#define AT91C_BUFFER_UNDERRUN         (0x02 << AT91C_BUFFER_ERROR_SHIFT)
-
-typedef unsigned int AT91S_BufferStatus;
-
-struct _AT91S_Pipe;
-
-// This structure is a virtual object of a buffer
-typedef struct _AT91S_Buffer
-{
-	struct _AT91S_Pipe *pPipe;
-	void *pChild;
-
-	// Functions invoked by the pipe
-	AT91S_BufferStatus (*SetRdBuffer)     (struct _AT91S_Buffer *pSBuffer, char *pBuffer, unsigned int Size);
-	AT91S_BufferStatus (*SetWrBuffer)     (struct _AT91S_Buffer *pSBuffer, char const *pBuffer, unsigned int Size);
-	AT91S_BufferStatus (*RstRdBuffer)     (struct _AT91S_Buffer *pSBuffer);
-	AT91S_BufferStatus (*RstWrBuffer)     (struct _AT91S_Buffer *pSBuffer);
-	char (*MsgWritten)      (struct _AT91S_Buffer *pSBuffer, char const *pBuffer);
-	char (*MsgRead)         (struct _AT91S_Buffer *pSBuffer, char const *pBuffer);
-	// Functions invoked by the peripheral
-	AT91S_BufferStatus (*GetWrBuffer)     (struct _AT91S_Buffer *pSBuffer, char const **pData, unsigned int *pSize);
-	AT91S_BufferStatus (*GetRdBuffer)     (struct _AT91S_Buffer *pSBuffer, char **pData, unsigned int *pSize);
-	AT91S_BufferStatus (*EmptyWrBuffer)   (struct _AT91S_Buffer *pSBuffer, unsigned int size);
-	AT91S_BufferStatus (*FillRdBuffer)    (struct _AT91S_Buffer *pSBuffer, unsigned int size);
-	char (*IsWrEmpty)      (struct _AT91S_Buffer *pSBuffer);
-	char (*IsRdFull)       (struct _AT91S_Buffer *pSBuffer);
-} AT91S_Buffer, *AT91PS_Buffer;
-
-// ===========================================================================================
-// SimpleBuffer definition
-//
-// This structure is pointed by pRealBuffer field in the SBuffer
-// It contains usefull information for a real implementation of
-// a SBuffer object.
-// The application just create an instance of SSBUffer and SBuffer,
-// call OpenSimpleBuffer, and continue using SBuffer instance
-
-typedef struct _AT91S_SBuffer
-{
-	AT91S_Buffer parent;
-	char         *pRdBuffer;
-	char const   *pWrBuffer;
-	unsigned int szRdBuffer;
-	unsigned int szWrBuffer;
-	unsigned int stRdBuffer;
-	unsigned int stWrBuffer;
-} AT91S_SBuffer, *AT91PS_SBuffer;
-
-typedef AT91PS_Buffer (*AT91PF_OpenSBuffer) (AT91PS_SBuffer);
-
-// This function is called by the application
-extern AT91PS_Buffer AT91F_OpenSBuffer(AT91PS_SBuffer pBuffer);
-
-// Functions invoked by the pipe
-extern AT91S_BufferStatus AT91F_SbSetRdBuffer  (AT91PS_Buffer pBuffer, char *pData, unsigned int Size);
-extern AT91S_BufferStatus AT91F_SbSetWrBuffer  (AT91PS_Buffer pBuffer, char const *pData, unsigned int Size);
-extern AT91S_BufferStatus AT91F_SbRstRdBuffer  (AT91PS_Buffer pBuffer);
-extern AT91S_BufferStatus AT91F_SbRstWrBuffer  (AT91PS_Buffer pBuffer);
-extern char AT91F_SbMsgWritten   (AT91PS_Buffer pBuffer, char const *pMsg);
-extern char AT91F_SbMsgRead      (AT91PS_Buffer pBuffer, char const *pMsg);
-// Functions invoked by the peripheral
-extern AT91S_BufferStatus AT91F_SbGetWrBuffer  (AT91PS_Buffer pBuffer, char const **pData, unsigned int *pSize);
-extern AT91S_BufferStatus AT91F_SbGetRdBuffer  (AT91PS_Buffer pBuffer, char **pData, unsigned int *pSize);
-extern AT91S_BufferStatus AT91F_SbEmptyWrBuffer(AT91PS_Buffer pBuffer, unsigned int size);
-extern AT91S_BufferStatus AT91F_SbFillRdBuffer (AT91PS_Buffer pBuffer, unsigned int size);
-extern char AT91F_SbIsWrEmpty   (AT91PS_Buffer pBuffer);
-extern char AT91F_SbIsRdFull    (AT91PS_Buffer pBuffer);
-
-#ifdef DBG_DRV_BUFFER
-extern char const *AT91F_SbGetError(AT91S_BufferStatus errorNumber);
-#endif
-
-
-#define AT91C_OPEN_CTRLTEMPO_SUCCESS	0
-#define AT91C_ERROR_OPEN_CTRLTEMPO		1
-#define AT91C_START_OK					2
-#define AT91C_STOP_OK					3
-#define AT91C_TIMEOUT_REACHED			4
-
-typedef enum _AT91E_SvcTempo {
-	AT91E_SVCTEMPO_DIS,
-	AT91E_SVCTEMPO_EN
-} AT91E_SvcTempo;
-
-typedef unsigned int AT91S_TempoStatus;
-
-// AT91S_SvcTempo
-typedef struct _AT91S_SvcTempo
-{
-
-	// Methods:
-	AT91S_TempoStatus (*Start)  (
-		struct _AT91S_SvcTempo *pSvc,
-		unsigned int timeout,
-		unsigned int reload,
-		void (*callback) (AT91S_TempoStatus, void *),
-		void *pData);
-	AT91S_TempoStatus (*Stop)   (struct _AT91S_SvcTempo *pSvc);
-
-	struct _AT91S_SvcTempo *pPreviousTempo;
-	struct _AT91S_SvcTempo *pNextTempo;
-
-	// Data
-	unsigned int TickTempo;	//* timeout value
-	unsigned int ReloadTempo;//* Reload value for periodic execution
-	void (*TempoCallback)(AT91S_TempoStatus, void *);
-	void *pPrivateData;
-	AT91E_SvcTempo flag;
-} AT91S_SvcTempo, *AT91PS_SvcTempo;
-
-
-// AT91S_CtrlTempo
-typedef struct _AT91S_CtlTempo
-{
-	// Members:
-
-	// Start and stop for Timer	hardware
-	AT91S_TempoStatus (*CtlTempoStart)  (void *pTimer);
-	AT91S_TempoStatus (*CtlTempoStop)   (void *pTimer);
-
-	// Start and stop for Tempo service
-	AT91S_TempoStatus (*SvcTempoStart)  (
-		struct _AT91S_SvcTempo *pSvc,
-		unsigned int timeout,
-		unsigned int reload,
-		void (*callback) (AT91S_TempoStatus, void *),
-		void *pData);
-	AT91S_TempoStatus (*SvcTempoStop)   (struct _AT91S_SvcTempo *pSvc);
-	AT91S_TempoStatus (*CtlTempoSetTime)(struct _AT91S_CtlTempo *pCtrl, unsigned int NewTime);
-	AT91S_TempoStatus (*CtlTempoGetTime)(struct _AT91S_CtlTempo *pCtrl);
-	AT91S_TempoStatus (*CtlTempoIsStart)(struct _AT91S_CtlTempo *pCtrl);
-	AT91S_TempoStatus (*CtlTempoCreate) (
-								struct _AT91S_CtlTempo *pCtrl,
-								struct _AT91S_SvcTempo *pTempo);
-	AT91S_TempoStatus (*CtlTempoRemove) (
-								struct _AT91S_CtlTempo *pCtrl,
-								struct _AT91S_SvcTempo *pTempo);
-	AT91S_TempoStatus (*CtlTempoTick)   (struct _AT91S_CtlTempo *pCtrl);
-
-	// Data:
-
-	void *pPrivateData;     // Pointer to devived class
-	void const *pTimer;			// hardware
-	AT91PS_SvcTempo pFirstTempo;
-	AT91PS_SvcTempo pNewTempo;
-} AT91S_CtlTempo, *AT91PS_CtlTempo;
-typedef AT91S_TempoStatus (*AT91PF_OpenCtlTempo)   ( AT91PS_CtlTempo, void const *);
-
-// This function is called by the application.
-extern AT91S_TempoStatus AT91F_OpenCtlTempo( AT91PS_CtlTempo pCtrlTempo, void const *pTempoTimer );
-
-extern AT91S_TempoStatus AT91F_STStart   (void *);
-extern AT91S_TempoStatus AT91F_STStop    (void *);
-extern AT91S_TempoStatus AT91F_STSetTime (AT91PS_CtlTempo, unsigned int);
-extern AT91S_TempoStatus AT91F_STGetTime (AT91PS_CtlTempo);
-extern AT91S_TempoStatus AT91F_STIsStart (AT91PS_CtlTempo);
-extern AT91S_TempoStatus AT91F_CtlTempoCreate (AT91PS_CtlTempo, AT91PS_SvcTempo);
-extern AT91S_TempoStatus AT91F_CtlTempoRemove (AT91PS_CtlTempo, AT91PS_SvcTempo);
-extern AT91S_TempoStatus AT91F_CtlTempoTick   (AT91PS_CtlTempo);
-extern AT91S_TempoStatus AT91F_SvcTempoStart (
-		AT91PS_SvcTempo pSvc,
-		unsigned int timeout,
-		unsigned int reload,
-		void (*callback) (AT91S_TempoStatus, void *),
-		void *pData);
-extern AT91S_TempoStatus AT91F_SvcTempoStop (AT91PS_SvcTempo);
-
-
-// Following types are defined in another header files
-struct _AT91S_Buffer;
-
-// Constants:
-#define AT91C_COMMSVC_SUCCESS     0
-#define AT91C_COMMSVC_ERROR_SHIFT 8
-#define AT91C_COMMSVC_ERROR       (0x0f << AT91C_COMMSVC_ERROR_SHIFT)
-
-typedef unsigned int AT91S_SvcCommStatus;
-
-// AT91S_Service definition
-// This structure is an abstraction of a communication peripheral
-typedef struct _AT91S_Service
-{
-	// Methods:
-	AT91S_SvcCommStatus (*Reset)  (struct _AT91S_Service *pService);
-	AT91S_SvcCommStatus (*StartTx)(struct _AT91S_Service *pService);
-	AT91S_SvcCommStatus (*StartRx)(struct _AT91S_Service *pService);
-	AT91S_SvcCommStatus (*StopTx) (struct _AT91S_Service *pService);
-	AT91S_SvcCommStatus (*StopRx) (struct _AT91S_Service *pService);
-	char                (*TxReady)(struct _AT91S_Service *pService);
-	char                (*RxReady)(struct _AT91S_Service *pService);
-	// Data:
-	struct _AT91S_Buffer *pBuffer; // Link to a buffer object
-	void *pChild;
-} AT91S_SvcComm, *AT91PS_SvcComm;
-
-// Constants:
-#define AT91C_XMODEM_SOH         0x01         /* Start of Heading for 128 bytes */
-#define AT91C_XMODEM_STX         0x02         /* Start of heading for 1024 bytes */
-#define AT91C_XMODEM_EOT         0x04         /* End of transmission */
-#define AT91C_XMODEM_ACK         0x06         /* Acknowledge */
-#define AT91C_XMODEM_NAK         0x15         /* Negative Acknowledge */
-#define AT91C_XMODEM_CRCCHR      'C'
-
-#define AT91C_XMODEM_PACKET_SIZE 2                 // packet + packetCRC
-#define AT91C_XMODEM_CRC_SIZE    2                 // crcLSB + crcMSB
-#define AT91C_XMODEM_DATA_SIZE_SOH    128          // data 128 corresponding to SOH header
-#define AT91C_XMODEM_DATA_SIZE_STX    1024         // data 1024 corresponding to STX header
-
-//* Following structure is used by SPipe to refer to the USB device peripheral endpoint
-typedef struct _AT91PS_SvcXmodem {
-
-	// Public Methods:
-	AT91S_SvcCommStatus (*Handler) (struct _AT91PS_SvcXmodem *, unsigned int);
-	AT91S_SvcCommStatus (*StartTx) (struct _AT91PS_SvcXmodem *, unsigned int);
-	AT91S_SvcCommStatus (*StopTx)  (struct _AT91PS_SvcXmodem *, unsigned int);
-
-	// Private Methods:
-	AT91S_SvcCommStatus (*ReadHandler)  (struct _AT91PS_SvcXmodem *, unsigned int csr);
-	AT91S_SvcCommStatus (*WriteHandler) (struct _AT91PS_SvcXmodem *, unsigned int csr);
-	unsigned short      (*GetCrc)       (char *ptr, unsigned int count);
-	char                (*CheckHeader)  (unsigned char currentPacket, char *packet);
-	char                (*CheckData)    (struct _AT91PS_SvcXmodem *);
-
-	AT91S_SvcComm  parent;      // Base class
-	AT91PS_USART  pUsart;
-
-	AT91S_SvcTempo tempo; // Link to a AT91S_Tempo object
-
-	char          *pData;
-	unsigned int  dataSize;        // = XMODEM_DATA_STX or XMODEM_DATA_SOH
-	char          packetDesc[AT91C_XMODEM_PACKET_SIZE];
-	unsigned char packetId;         // Current packet
-	char          packetStatus;
-	char          isPacketDesc;
-	char          eot;            // end of transmition
-} AT91S_SvcXmodem, *AT91PS_SvcXmodem;
-
-typedef AT91PS_SvcComm      (*AT91PF_OpenSvcXmodem) ( AT91PS_SvcXmodem, AT91PS_USART, AT91PS_CtlTempo);
-
-// This function is called by the application.
-extern AT91PS_SvcComm AT91F_OpenSvcXmodem( AT91PS_SvcXmodem, AT91PS_USART, AT91PS_CtlTempo);
-
-extern unsigned short AT91F_SvcXmodemGetCrc     (char *ptr, unsigned int count);
-extern char           AT91F_SvcXmodemCheckHeader(unsigned char currentPacket, char *packet);
-extern char           AT91F_SvcXmodemCheckData  (AT91PS_SvcXmodem pSvcXmodem);
-extern AT91S_SvcCommStatus AT91F_SvcXmodemReadHandler(AT91PS_SvcXmodem pSvcXmodem, unsigned int csr);
-extern AT91S_SvcCommStatus AT91F_SvcXmodemWriteHandler(AT91PS_SvcXmodem pSvcXmodem, unsigned int csr);
-extern AT91S_SvcCommStatus AT91F_SvcXmodemStartTx(AT91PS_SvcComm pSvcComm);
-extern AT91S_SvcCommStatus AT91F_SvcXmodemStopTx(AT91PS_SvcComm pSvcComm);
-extern AT91S_SvcCommStatus AT91F_SvcXmodemStartRx(AT91PS_SvcComm pSvcComm);
-extern AT91S_SvcCommStatus AT91F_SvcXmodemStopRx(AT91PS_SvcComm pSvcComm);
-extern char AT91F_SvcXmodemTxReady(AT91PS_SvcComm pService);
-extern char AT91F_SvcXmodemRxReady(AT91PS_SvcComm pSvcComm);
-
-
-// Constants:
-#define AT91C_PIPE_SUCCESS	      0
-#define AT91C_PIPE_ERROR_SHIFT    8
-#define AT91C_PIPE_ERROR          (0x0F << AT91C_PIPE_ERROR_SHIFT)
-
-#define AT91C_PIPE_OPEN_FAILED    (1 << AT91C_PIPE_ERROR_SHIFT)
-#define AT91C_PIPE_WRITE_FAILED   (2 << AT91C_PIPE_ERROR_SHIFT)
-#define AT91C_PIPE_WRITE_ABORTED  (3 << AT91C_PIPE_ERROR_SHIFT)
-#define AT91C_PIPE_READ_FAILED    (4 << AT91C_PIPE_ERROR_SHIFT)
-#define AT91C_PIPE_READ_ABORTED   (5 << AT91C_PIPE_ERROR_SHIFT)
-#define AT91C_PIPE_ABORT_FAILED   (6 << AT91C_PIPE_ERROR_SHIFT)
-#define AT91C_PIPE_RESET_FAILED   (7 << AT91C_PIPE_ERROR_SHIFT)
-
-/* _AT91S_Pipe stucture */
-typedef unsigned int AT91S_PipeStatus;
-
-typedef struct _AT91S_Pipe
-{
-	// A pipe is linked with a peripheral and a buffer
-	AT91PS_SvcComm pSvcComm;
-	AT91PS_Buffer  pBuffer;
-
-	// Callback functions with their arguments
-	void (*WriteCallback) (AT91S_PipeStatus, void *);
-	void (*ReadCallback)  (AT91S_PipeStatus, void *);
-	void *pPrivateReadData;
-	void *pPrivateWriteData;
-
-	// Pipe methods
-	AT91S_PipeStatus (*Write) (
-		struct _AT91S_Pipe   *pPipe,
-		char const *         pData,
-		unsigned int         size,
-		void                 (*callback) (AT91S_PipeStatus, void *),
-		void                 *privateData);
-	AT91S_PipeStatus (*Read) (
-		struct _AT91S_Pipe  *pPipe,
-		char                *pData,
-		unsigned int        size,
-		void                (*callback) (AT91S_PipeStatus, void *),
-		void                *privateData);
-	AT91S_PipeStatus (*AbortWrite) (
-		struct _AT91S_Pipe  *pPipe);
-	AT91S_PipeStatus (*AbortRead) (
-		struct _AT91S_Pipe *pPipe);
-	AT91S_PipeStatus (*Reset) (
-		struct _AT91S_Pipe *pPipe);
-	char (*IsWritten) (
-		struct _AT91S_Pipe *pPipe,
-		char const *pVoid);
-	char (*IsReceived) (
-		struct _AT91S_Pipe *pPipe,
-		char const *pVoid);
-} AT91S_Pipe, *AT91PS_Pipe;
-
-// types used in AT91S_Pipe
-typedef AT91PS_Pipe (*AT91PF_OpenPipe)   (AT91PS_Pipe, AT91PS_SvcComm, AT91PS_Buffer);
-typedef void (*AT91PF_PipeWriteCallBack) (AT91S_PipeStatus, void *);
-typedef void (*AT91PF_PipeReadCallBack)  (AT91S_PipeStatus, void *);
-typedef AT91S_PipeStatus (*AT91PF_PipeWrite) (AT91PS_Pipe, char const *, unsigned int, void (*) (AT91S_PipeStatus, void *),	void *);
-typedef AT91S_PipeStatus (*AT91PF_PipeRead)  (AT91PS_Pipe, char const *, unsigned int, void (*) (AT91S_PipeStatus, void *),	void *);
-typedef AT91S_PipeStatus (*AT91PF_PipeAbortWrite) (AT91PS_Pipe);
-typedef AT91S_PipeStatus (*AT91PF_PipeAbortRead)  (AT91PS_Pipe);
-typedef AT91S_PipeStatus (*AT91PF_PipeReset)      (AT91PS_Pipe);
-typedef char (*AT91PF_PipeIsWritten)              (AT91PS_Pipe, char const *);
-typedef char (*AT91PF_PipeIsReceived)             (AT91PS_Pipe, char const *);
-
-// This function is called by the application
-extern AT91PS_Pipe AT91F_OpenPipe(
-	AT91PS_Pipe    pPipe,
-	AT91PS_SvcComm pSvcComm,
-	AT91PS_Buffer  pBuffer);
-
-// Following functions are called through AT91S_Pipe pointers
-
-extern AT91S_PipeStatus AT91F_PipeWrite(
-	AT91PS_Pipe pPipe,
-	char const *pVoid,
-	unsigned int size,
-	AT91PF_PipeWriteCallBack callback,
-	void *privateData);
-extern AT91S_PipeStatus AT91F_PipeRead(
-	AT91PS_Pipe pPipe,
-	char *pVoid,
-	unsigned int Size,
-	AT91PF_PipeReadCallBack callback,
-	void *privateData);
-extern AT91S_PipeStatus AT91F_PipeAbortWrite(AT91PS_Pipe pPipe);
-extern AT91S_PipeStatus AT91F_PipeAbortRead(AT91PS_Pipe pPipe);
-extern AT91S_PipeStatus AT91F_PipeReset(AT91PS_Pipe pPipe);
-extern char AT91F_PipeMsgWritten(AT91PS_Pipe pPipe, char const *pVoid);
-extern char AT91F_PipeMsgReceived(AT91PS_Pipe pPipe, char const *pVoid);
-
-#ifdef DBG_DRV_PIPE
-// This function parse the error number and return a string
-// describing the error message
-extern char const *AT91F_PipeGetError(AT91S_PipeStatus msgId);
-#endif
-
-extern const unsigned char bit_rev[256];
-
-extern void CalculateCrc32(const unsigned char *,unsigned int, unsigned int *);
-extern void CalculateCrc16(const unsigned char *, unsigned int , unsigned short *); 
-extern void CalculateCrcHdlc(const unsigned char *, unsigned int, unsigned short *);
-extern void CalculateCrc16ccitt(const unsigned char *, unsigned int , unsigned short *);
-
-typedef const unsigned char* AT91PS_SVC_CRC_BIT_REV ;
-
-typedef void  (*AT91PF_SVC_CRC32)   (const unsigned char *, unsigned int, unsigned int *);
-typedef void  (*AT91PF_SVC_CRC16)   (const unsigned char *, unsigned int, unsigned short *);
-typedef void  (*AT91PF_SVC_CRCHDLC) (const unsigned char *, unsigned int, unsigned short *);
-typedef	void  (*AT91PF_SVC_CRCCCITT)(const unsigned char *, unsigned int , unsigned short *);
-
-
-typedef short (*AT91PF_Sinus) (int angle);
-typedef const short * AT91PS_SINE_TAB;
-
-extern short AT91F_Sinus(int angle);
-extern const short AT91C_SINUS180_TAB[256];
-
-
-typedef void (TypeAICHandler) (void) ;
-
-
-// ROM BOOT Structure Element Definition (liv v2)
-typedef struct _AT91S_MEMCDesc
-{
-    AT91PS_MC		memc_base ;		/* Peripheral base */
-    unsigned char	periph_id ;		/* MC Peripheral Identifier */
-} AT91S_MEMCDesc, *AT91PS_MEMCDesc ;
-
-typedef struct _AT91S_Pio2Desc
-{
-   AT91PS_PIO      pio_base ;       /* Base Address */
-   unsigned char   periph_id ;      /* Peripheral Identifier */
-   unsigned char   pio_number ;     /* Total Pin Number */
-} AT91S_Pio2Desc, *AT91PS_Pio2Desc ;
-
-typedef struct _AT91S_SPIDesc
-{
-    AT91PS_SPI         		spi_base ;
-    const AT91PS_PIO        pio_base ;
-    unsigned char           periph_id ;
-    unsigned char           pin_spck ;
-    unsigned char           pin_miso ;
-    unsigned char           pin_mosi ;
-    unsigned char           pin_npcs[4] ;
-} AT91S_SPIDesc, *AT91PS_SPIDesc ;
-
-typedef struct _AT91S_USART2Desc
-{
-    AT91PS_USART           	usart_base ;   	/* Peripheral base */
-    const AT91PS_PIO   		pio_base ;     	/* IO controller descriptor */
-    unsigned int            pin_rxd ;       /* RXD pin number in the PIO */
-    unsigned int            pin_txd ;       /* TXD pin number in the PIO */
-    unsigned int            pin_sck ;       /* SCK pin number in the PIO */
-    unsigned int            pin_rts ;       /* RTS pin number in the PIO */
-    unsigned int            pin_cts ;       /* CTS pin number in the PIO */
-    unsigned int            pin_dtr ;       /* DTR pin number in the PIO */
-    unsigned int            pin_ri ;        /* RI pin number in the PIO */
-    unsigned int            pin_dsr ;       /* DSR pin number in the PIO */
-    unsigned int            pin_dcd ;       /* DCD pin number in the PIO */
-    unsigned int            periph_id ;     /* USART Peripheral Identifier */
-} AT91S_USART2Desc, *AT91PS_USART2Desc ;
-
-typedef struct _AT91S_TWIDesc
-{
-    AT91PS_TWI 				TWI_base ;
-    const AT91PS_PIO        pio_base ;
-    unsigned int			pin_sck ;
-    unsigned int			pin_sda ;
-    unsigned int 			periph_id;
-}AT91S_TWIDesc, *AT91PS_TWIDesc;
-
-typedef struct _AT91S_STDesc
-{
-    AT91PS_ST  		st_base ;          	/* Peripheral base address */
-    TypeAICHandler  *AsmSTHandler ;     /* Assembly interrupt handler */
-    unsigned char   PeriphId ;          /* Peripheral Identifier */
-} AT91S_STDesc, *AT91PS_STDesc;
-
-typedef struct _AT91S_RomBoot {
-	const unsigned int     version;
-	// Peripheral descriptors
-	const AT91S_MEMCDesc   MEMC_DESC;
-	const AT91S_STDesc     SYSTIMER_DESC;
-	const AT91S_Pio2Desc   PIOA_DESC;
-	const AT91S_Pio2Desc   PIOB_DESC;
-	const AT91S_USART2Desc DBGU_DESC;
-	const AT91S_USART2Desc USART0_DESC;
-	const AT91S_USART2Desc USART1_DESC;
-	const AT91S_USART2Desc USART2_DESC;
-	const AT91S_USART2Desc USART3_DESC;
-	const AT91S_TWIDesc    TWI_DESC;
-	const AT91S_SPIDesc    SPI_DESC;
-
-	// Objects entry
-	const AT91PF_OpenPipe      		OpenPipe;
-	const AT91PF_OpenSBuffer   		OpenSBuffer;
-	const unsigned int				reserved1;
-	const AT91PF_OpenSvcXmodem 		OpenSvcXmodem;
-	const AT91PF_OpenCtlTempo  		OpenCtlTempo;
-	const unsigned int				reserved2;
-	const unsigned int				reserved3;
-	const unsigned int				reserved4;
-	const AT91PF_SVC_CRC16			CRC16;
-	const AT91PF_SVC_CRCCCITT		CRCCCITT;
-	const AT91PF_SVC_CRCHDLC		CRCHDLC;
-	const AT91PF_SVC_CRC32			CRC32;
-	const AT91PS_SVC_CRC_BIT_REV	Bit_Reverse_Array;
-	const AT91PS_SINE_TAB			SineTab; 
-	const AT91PF_Sinus              Sine;
-} AT91S_RomBoot, *AT91PS_RomBoot;
-
-#define AT91C_ROM_BOOT_ADDRESS ((const AT91S_RomBoot *) ( *((unsigned int *) (AT91C_BASE_ROM + 0x20))) )
-
-#endif
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/include/AT91C_MCI_Device.h b/target/linux/at91-2.6/image/dfboot/src/include/AT91C_MCI_Device.h
deleted file mode 100644
index 43d5835..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/include/AT91C_MCI_Device.h
+++ /dev/null
@@ -1,379 +0,0 @@
-//*---------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*---------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*---------------------------------------------------------------------------
-//* File Name           : AT91C_MCI_Device.h
-//* Object              : Data Flash Atmel Description File
-//* Translator          :
-//*
-//* 1.0 26/11/02 FB		: Creation
-//*---------------------------------------------------------------------------
-
-#ifndef AT91C_MCI_Device_h
-#define AT91C_MCI_Device_h
-
-#include "AT91RM9200.h"
-#include "lib_AT91RM9200.h"
-
-typedef unsigned int AT91S_MCIDeviceStatus;
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define AT91C_CARD_REMOVED			0
-#define AT91C_MMC_CARD_INSERTED		1
-#define AT91C_SD_CARD_INSERTED		2
-
-#define AT91C_NO_ARGUMENT			0x0
-
-#define AT91C_FIRST_RCA				0xCAFE
-#define AT91C_MAX_MCI_CARDS			10
-
-#define AT91C_BUS_WIDTH_1BIT		0x00
-#define AT91C_BUS_WIDTH_4BITS		0x02
-
-/* Driver State */
-#define AT91C_MCI_IDLE       		0x0
-#define AT91C_MCI_TIMEOUT_ERROR		0x1
-#define AT91C_MCI_RX_SINGLE_BLOCK	0x2
-#define AT91C_MCI_RX_MULTIPLE_BLOCK	0x3
-#define AT91C_MCI_RX_STREAM			0x4
-#define AT91C_MCI_TX_SINGLE_BLOCK	0x5
-#define AT91C_MCI_TX_MULTIPLE_BLOCK	0x6
-#define AT91C_MCI_TX_STREAM 		0x7
-
-/* TimeOut */
-#define AT91C_TIMEOUT_CMDRDY		30
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-// MMC & SDCard Structures 
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-
-/*-----------------------------------------------*/
-/* SDCard Device Descriptor Structure Definition */
-/*-----------------------------------------------*/
-typedef struct	_AT91S_MciDeviceDesc
-{
-    volatile unsigned char	state;
-	unsigned char			SDCard_bus_width;
-
-} AT91S_MciDeviceDesc, *AT91PS_MciDeviceDesc;
-
-/*---------------------------------------------*/
-/* MMC & SDCard Structure Device Features	   */
-/*---------------------------------------------*/
-typedef struct	_AT91S_MciDeviceFeatures
-{
-    unsigned char	Card_Inserted;				// (0=AT91C_CARD_REMOVED) (1=AT91C_MMC_CARD_INSERTED) (2=AT91C_SD_CARD_INSERTED)
-    unsigned int 	Relative_Card_Address;		// RCA
-	unsigned int 	Max_Read_DataBlock_Length;	// 2^(READ_BL_LEN) in CSD 
-	unsigned int 	Max_Write_DataBlock_Length;	// 2^(WRITE_BL_LEN) in CSD
-	unsigned char	Read_Partial;				// READ_BL_PARTIAL
-	unsigned char	Write_Partial;				// WRITE_BL_PARTIAL
-	unsigned char	Erase_Block_Enable;			// ERASE_BLK_EN
-	unsigned char	Read_Block_Misalignment;	// READ_BLK_MISALIGN
-	unsigned char	Write_Block_Misalignment;	// WRITE_BLK_MISALIGN
-	unsigned char	Sector_Size;				// SECTOR_SIZE
-	unsigned int	Memory_Capacity;			// Size in bits of the device
-	
-}	AT91S_MciDeviceFeatures, *AT91PS_MciDeviceFeatures ;
-
-/*---------------------------------------------*/
-/* MCI Device Structure Definition 			   */
-/*---------------------------------------------*/
-typedef struct _AT91S_MciDevice
-{
-	AT91PS_MciDeviceDesc		 	pMCI_DeviceDesc;	// MCI device descriptor
-	AT91PS_MciDeviceFeatures		pMCI_DeviceFeatures;// Pointer on a MCI device features array  
-}AT91S_MciDevice, *AT91PS_MciDevice;
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-// MCI_CMD Register Value 
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-#define AT91C_POWER_ON_INIT						(0	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_INIT | AT91C_MCI_OPDCMD)
-
-/////////////////////////////////////////////////////////////////	
-// Class 0 & 1 commands: Basic commands and Read Stream commands
-/////////////////////////////////////////////////////////////////
-
-#define AT91C_GO_IDLE_STATE_CMD					(0 	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE )
-#define AT91C_MMC_GO_IDLE_STATE_CMD				(0 	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE  | AT91C_MCI_OPDCMD)
-#define AT91C_MMC_SEND_OP_COND_CMD				(1	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD)
-#define AT91C_ALL_SEND_CID_CMD					(2	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_136 )
-#define AT91C_MMC_ALL_SEND_CID_CMD				(2	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_136 | AT91C_MCI_OPDCMD)
-#define AT91C_SET_RELATIVE_ADDR_CMD				(3	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48		| AT91C_MCI_MAXLAT )
-#define AT91C_MMC_SET_RELATIVE_ADDR_CMD			(3	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48		| AT91C_MCI_MAXLAT | AT91C_MCI_OPDCMD)
-
-#define AT91C_SET_DSR_CMD						(4	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_NO		| AT91C_MCI_MAXLAT )	// no tested
-
-#define AT91C_SEL_DESEL_CARD_CMD				(7	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48  		| AT91C_MCI_MAXLAT )
-#define AT91C_SEND_CSD_CMD						(9	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_136 		| AT91C_MCI_MAXLAT )
-#define AT91C_SEND_CID_CMD						(10	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_136 		| AT91C_MCI_MAXLAT )
-#define AT91C_MMC_READ_DAT_UNTIL_STOP_CMD		(11	| AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRDIR	| AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT )
-
-#define AT91C_STOP_TRANSMISSION_CMD				(12	| AT91C_MCI_TRCMD_STOP 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48 		| AT91C_MCI_MAXLAT )
-#define AT91C_STOP_TRANSMISSION_SYNC_CMD		(12	| AT91C_MCI_TRCMD_STOP 	| AT91C_MCI_SPCMD_SYNC	| AT91C_MCI_RSPTYP_48 		| AT91C_MCI_MAXLAT )
-#define AT91C_SEND_STATUS_CMD					(13	| AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48 		| AT91C_MCI_MAXLAT )
-#define AT91C_GO_INACTIVE_STATE_CMD				(15	| AT91C_MCI_RSPTYP_NO )
-
-//*------------------------------------------------
-//* Class 2 commands: Block oriented Read commands
-//*------------------------------------------------
-
-#define AT91C_SET_BLOCKLEN_CMD					(16 | AT91C_MCI_TRCMD_NO 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48		| AT91C_MCI_MAXLAT )
-#define AT91C_READ_SINGLE_BLOCK_CMD				(17 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48 	| AT91C_MCI_TRCMD_START	| AT91C_MCI_TRTYP_BLOCK	| AT91C_MCI_TRDIR	| AT91C_MCI_MAXLAT)
-#define AT91C_READ_MULTIPLE_BLOCK_CMD			(18 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48 	| AT91C_MCI_TRCMD_START	| AT91C_MCI_TRTYP_MULTIPLE	| AT91C_MCI_TRDIR	| AT91C_MCI_MAXLAT)
-
-//*--------------------------------------------
-//* Class 3 commands: Sequential write commands
-//*--------------------------------------------
-
-#define AT91C_MMC_WRITE_DAT_UNTIL_STOP_CMD		(20 | AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48 & ~(AT91C_MCI_TRDIR) | AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT )	// MMC
-
-//*------------------------------------------------
-//* Class 4 commands: Block oriented write commands
-//*------------------------------------------------
-	
-#define AT91C_WRITE_BLOCK_CMD					(24 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_START	| (AT91C_MCI_TRTYP_BLOCK 	&  ~(AT91C_MCI_TRDIR))	| AT91C_MCI_MAXLAT)
-#define AT91C_WRITE_MULTIPLE_BLOCK_CMD			(25 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_START	| (AT91C_MCI_TRTYP_MULTIPLE	&  ~(AT91C_MCI_TRDIR)) 	| AT91C_MCI_MAXLAT)
-#define AT91C_PROGRAM_CSD_CMD					(27 | AT91C_MCI_RSPTYP_48 )
-
-
-//*----------------------------------------
-//* Class 6 commands: Group Write protect
-//*----------------------------------------
-
-#define AT91C_SET_WRITE_PROT_CMD				(28	| AT91C_MCI_RSPTYP_48 )
-#define AT91C_CLR_WRITE_PROT_CMD				(29	| AT91C_MCI_RSPTYP_48 )
-#define AT91C_SEND_WRITE_PROT_CMD				(30	| AT91C_MCI_RSPTYP_48 )
-
-
-//*----------------------------------------
-//* Class 5 commands: Erase commands
-//*----------------------------------------
-
-#define AT91C_TAG_SECTOR_START_CMD				(32 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO	| AT91C_MCI_MAXLAT)
-#define AT91C_TAG_SECTOR_END_CMD  				(33 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO	| AT91C_MCI_MAXLAT)
-#define AT91C_MMC_UNTAG_SECTOR_CMD				(34 | AT91C_MCI_RSPTYP_48 )
-#define AT91C_MMC_TAG_ERASE_GROUP_START_CMD		(35 | AT91C_MCI_RSPTYP_48 )
-#define AT91C_MMC_TAG_ERASE_GROUP_END_CMD		(36 | AT91C_MCI_RSPTYP_48 )
-#define AT91C_MMC_UNTAG_ERASE_GROUP_CMD			(37 | AT91C_MCI_RSPTYP_48 )
-#define AT91C_ERASE_CMD							(38 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO	| AT91C_MCI_MAXLAT )
-
-//*----------------------------------------
-//* Class 7 commands: Lock commands
-//*----------------------------------------
-
-#define AT91C_LOCK_UNLOCK						(42 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO	| AT91C_MCI_MAXLAT)	// no tested
-
-//*-----------------------------------------------
-// Class 8 commands: Application specific commands
-//*-----------------------------------------------
-
-#define AT91C_APP_CMD							(55 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)
-#define AT91C_GEN_CMD							(56 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)	// no tested
-
-#define AT91C_SDCARD_SET_BUS_WIDTH_CMD			(6 	| AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO	| AT91C_MCI_MAXLAT)
-#define AT91C_SDCARD_STATUS_CMD					(13 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO	| AT91C_MCI_MAXLAT)
-#define AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD		(22 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO	| AT91C_MCI_MAXLAT)
-#define AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD	(23 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO	| AT91C_MCI_MAXLAT)
-#define AT91C_SDCARD_APP_OP_COND_CMD			(41 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO )
-#define AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD	(42 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO	| AT91C_MCI_MAXLAT)
-#define AT91C_SDCARD_SEND_SCR_CMD				(51 | AT91C_MCI_SPCMD_NONE	| AT91C_MCI_RSPTYP_48	| AT91C_MCI_TRCMD_NO	| AT91C_MCI_MAXLAT)
-
-#define AT91C_SDCARD_APP_ALL_CMD				(AT91C_SDCARD_SET_BUS_WIDTH_CMD +\
-												AT91C_SDCARD_STATUS_CMD +\
-												AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD +\
-												AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\
-												AT91C_SDCARD_APP_OP_COND_CMD +\
-												AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD +\
-												AT91C_SDCARD_SEND_SCR_CMD)
-
-//*----------------------------------------
-//* Class 9 commands: IO Mode commands
-//*----------------------------------------
-
-#define AT91C_MMC_FAST_IO_CMD					(39 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT)
-#define AT91C_MMC_GO_IRQ_STATE_CMD				(40 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO	| AT91C_MCI_MAXLAT)
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-// Functions returnals
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-#define AT91C_CMD_SEND_OK					0		// Command ok
-#define AT91C_CMD_SEND_ERROR				-1		// Command failed
-#define AT91C_INIT_OK						2		// Init Successfull
-#define AT91C_INIT_ERROR					3		// Init Failed
-#define AT91C_READ_OK						4		// Read Successfull
-#define AT91C_READ_ERROR					5		// Read Failed
-#define AT91C_WRITE_OK						6		// Write Successfull
-#define AT91C_WRITE_ERROR					7		// Write Failed
-#define AT91C_ERASE_OK						8		// Erase Successfull
-#define AT91C_ERASE_ERROR					9		// Erase Failed
-#define AT91C_CARD_SELECTED_OK				10		// Card Selection Successfull
-#define AT91C_CARD_SELECTED_ERROR			11		// Card Selection Failed
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-// MCI_SR Errors
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-#define 	AT91C_MCI_SR_ERROR		(AT91C_MCI_UNRE |\
-									 AT91C_MCI_OVRE |\
-									 AT91C_MCI_DTOE |\
-									 AT91C_MCI_DCRCE |\
-									 AT91C_MCI_RTOE |\
-									 AT91C_MCI_RENDE |\
-									 AT91C_MCI_RCRCE |\
-									 AT91C_MCI_RDIRE |\
-									 AT91C_MCI_RINDE)
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-// OCR Register
-////////////////////////////////////////////////////////////////////////////////////////////////////
-#define AT91C_VDD_16_17					(1 << 4)
-#define AT91C_VDD_17_18					(1 << 5)
-#define AT91C_VDD_18_19					(1 << 6)
-#define AT91C_VDD_19_20					(1 << 7)
-#define AT91C_VDD_20_21					(1 << 8)
-#define AT91C_VDD_21_22					(1 << 9)
-#define AT91C_VDD_22_23					(1 << 10)
-#define AT91C_VDD_23_24					(1 << 11)
-#define AT91C_VDD_24_25					(1 << 12)
-#define AT91C_VDD_25_26					(1 << 13)
-#define AT91C_VDD_26_27					(1 << 14)
-#define AT91C_VDD_27_28					(1 << 15)
-#define AT91C_VDD_28_29					(1 << 16)
-#define AT91C_VDD_29_30					(1 << 17)
-#define AT91C_VDD_30_31					(1 << 18)
-#define AT91C_VDD_31_32					(1 << 19)
-#define AT91C_VDD_32_33					(1 << 20)
-#define AT91C_VDD_33_34					(1 << 21)
-#define AT91C_VDD_34_35					(1 << 22)
-#define AT91C_VDD_35_36					(1 << 23)
-#define AT91C_CARD_POWER_UP_BUSY		(1 << 31)
-
-#define AT91C_MMC_HOST_VOLTAGE_RANGE	(AT91C_VDD_27_28 +\
-										AT91C_VDD_28_29 +\
-										AT91C_VDD_29_30 +\
-										AT91C_VDD_30_31 +\
-										AT91C_VDD_31_32 +\
-										AT91C_VDD_32_33)
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-// CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1)
-////////////////////////////////////////////////////////////////////////////////////////////////////
-#define AT91C_SR_READY_FOR_DATA				(1 << 8)	// corresponds to buffer empty signalling on the bus
-#define AT91C_SR_IDLE						(0 << 9)
-#define AT91C_SR_READY						(1 << 9)
-#define AT91C_SR_IDENT						(2 << 9)
-#define AT91C_SR_STBY						(3 << 9)
-#define AT91C_SR_TRAN						(4 << 9)
-#define AT91C_SR_DATA						(5 << 9)
-#define AT91C_SR_RCV						(6 << 9)
-#define AT91C_SR_PRG						(7 << 9)
-#define AT91C_SR_DIS						(8 << 9)
-
-#define AT91C_SR_CARD_SELECTED				(AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN)
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-// MMC CSD register header File					
-// AT91C_CSD_xxx_S	for shift value
-// AT91C_CSD_xxx_M	for mask  value
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// First Response INT <=> CSD[3] : bits 0 to 31
-#define	AT91C_CSD_BIT0_S			0		// [0:0]			
-#define	AT91C_CSD_BIT0_M			0x01				
-#define	AT91C_CSD_CRC_S				1		// [7:1]
-#define	AT91C_CSD_CRC_M				0x7F
-#define	AT91C_CSD_MMC_ECC_S			8		// [9:8]		reserved for MMC compatibility
-#define	AT91C_CSD_MMC_ECC_M			0x03
-#define	AT91C_CSD_FILE_FMT_S		10		// [11:10]
-#define	AT91C_CSD_FILE_FMT_M		0x03
-#define	AT91C_CSD_TMP_WP_S			12		// [12:12]
-#define	AT91C_CSD_TMP_WP_M			0x01
-#define	AT91C_CSD_PERM_WP_S 		13		// [13:13]
-#define	AT91C_CSD_PERM_WP_M 		0x01
-#define	AT91C_CSD_COPY_S	 		14		// [14:14]
-#define	AT91C_CSD_COPY_M 			0x01
-#define	AT91C_CSD_FILE_FMT_GRP_S	15		// [15:15]
-#define	AT91C_CSD_FILE_FMT_GRP_M	0x01
-//	reserved						16		// [20:16]
-//	reserved						0x1F
-#define	AT91C_CSD_WBLOCK_P_S 		21		// [21:21]
-#define	AT91C_CSD_WBLOCK_P_M 		0x01
-#define	AT91C_CSD_WBLEN_S 			22		// [25:22]
-#define	AT91C_CSD_WBLEN_M 			0x0F
-#define	AT91C_CSD_R2W_F_S 			26		// [28:26]
-#define	AT91C_CSD_R2W_F_M 			0x07
-#define	AT91C_CSD_MMC_DEF_ECC_S		29		// [30:29]		reserved for MMC compatibility
-#define	AT91C_CSD_MMC_DEF_ECC_M		0x03
-#define	AT91C_CSD_WP_GRP_EN_S		31		// [31:31]
-#define	AT91C_CSD_WP_GRP_EN_M 		0x01
-
-// Seconde Response INT <=> CSD[2] : bits 32 to 63
-#define	AT91C_CSD_v21_WP_GRP_SIZE_S	0		// [38:32]				
-#define	AT91C_CSD_v21_WP_GRP_SIZE_M	0x7F				
-#define	AT91C_CSD_v21_SECT_SIZE_S	7		// [45:39]
-#define	AT91C_CSD_v21_SECT_SIZE_M	0x7F
-#define	AT91C_CSD_v21_ER_BLEN_EN_S	14		// [46:46]
-#define	AT91C_CSD_v21_ER_BLEN_EN_M	0x01
-
-#define	AT91C_CSD_v22_WP_GRP_SIZE_S	0		// [36:32]				
-#define	AT91C_CSD_v22_WP_GRP_SIZE_M	0x1F				
-#define	AT91C_CSD_v22_ER_GRP_SIZE_S	5		// [41:37]
-#define	AT91C_CSD_v22_ER_GRP_SIZE_M	0x1F
-#define	AT91C_CSD_v22_SECT_SIZE_S	10		// [46:42]
-#define	AT91C_CSD_v22_SECT_SIZE_M	0x1F
-
-#define	AT91C_CSD_C_SIZE_M_S		15		// [49:47]
-#define	AT91C_CSD_C_SIZE_M_M		0x07
-#define	AT91C_CSD_VDD_WMAX_S 		18		// [52:50]
-#define	AT91C_CSD_VDD_WMAX_M 		0x07
-#define	AT91C_CSD_VDD_WMIN_S	 	21		// [55:53]
-#define	AT91C_CSD_VDD_WMIN_M 		0x07
-#define	AT91C_CSD_RCUR_MAX_S 		24		// [58:56]
-#define	AT91C_CSD_RCUR_MAX_M 		0x07
-#define	AT91C_CSD_RCUR_MIN_S 		27		// [61:59]
-#define	AT91C_CSD_RCUR_MIN_M 		0x07
-#define	AT91C_CSD_CSIZE_L_S 		30		// [63:62] <=> 2 LSB of CSIZE
-#define	AT91C_CSD_CSIZE_L_M 		0x03
-
-// Third Response INT <=> CSD[1] : bits 64 to 95
-#define	AT91C_CSD_CSIZE_H_S 		0		// [73:64]	<=> 10 MSB of CSIZE
-#define	AT91C_CSD_CSIZE_H_M 		0x03FF
-// reserved							10		// [75:74]
-// reserved							0x03		
-#define	AT91C_CSD_DSR_I_S 			12		// [76:76]
-#define	AT91C_CSD_DSR_I_M 			0x01
-#define	AT91C_CSD_RD_B_MIS_S 		13		// [77:77]
-#define	AT91C_CSD_RD_B_MIS_M 		0x01
-#define	AT91C_CSD_WR_B_MIS_S 		14		// [78:78]
-#define	AT91C_CSD_WR_B_MIS_M 		0x01
-#define	AT91C_CSD_RD_B_PAR_S 		15		// [79:79]
-#define	AT91C_CSD_RD_B_PAR_M 		0x01
-#define	AT91C_CSD_RD_B_LEN_S 		16		// [83:80]
-#define	AT91C_CSD_RD_B_LEN_M 		0x0F
-#define	AT91C_CSD_CCC_S	 			20		// [95:84]
-#define	AT91C_CSD_CCC_M 			0x0FFF
-
-// Fourth Response INT <=> CSD[0] : bits 96 to 127
-#define	AT91C_CSD_TRANS_SPEED_S 	0		// [103:96]
-#define	AT91C_CSD_TRANS_SPEED_M 	0xFF
-#define	AT91C_CSD_NSAC_S 			8		// [111:104]
-#define	AT91C_CSD_NSAC_M 			0xFF
-#define	AT91C_CSD_TAAC_S 			16		// [119:112]
-#define	AT91C_CSD_TAAC_M 			0xFF
-//	reserved						24		// [121:120]
-//	reserved						0x03
-#define	AT91C_CSD_MMC_SPEC_VERS_S	26		// [125:122]	reserved for MMC compatibility
-#define	AT91C_CSD_MMC_SPEC_VERS_M	0x0F
-#define	AT91C_CSD_STRUCT_S			30		// [127:126]
-#define	AT91C_CSD_STRUCT_M 			0x03
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#endif
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200.h b/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200.h
deleted file mode 100644
index 0cd153b..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200.h
+++ /dev/null
@@ -1,2745 +0,0 @@
-// ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-// ----------------------------------------------------------------------------
-//  The software is delivered "AS IS" without warranty or condition of any
-//  kind, either express, implied or statutory. This includes without
-//  limitation any warranty or condition with respect to merchantability or
-//  fitness for any particular purpose, or against the infringements of
-//  intellectual property rights of others.
-// ----------------------------------------------------------------------------
-// File Name           : AT91RM9200.h
-// Object              : AT91RM9200 definitions
-// Generated           : AT91 SW Application Group  11/19/2003 (17:20:50)
-// 
-// CVS Reference       : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003//
-// CVS Reference       : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003//
-// CVS Reference       : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002//
-// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//
-// CVS Reference       : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
-// CVS Reference       : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002//
-// CVS Reference       : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003//
-// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//
-// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
-// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002//
-// CVS Reference       : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002//
-// CVS Reference       : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002//
-// CVS Reference       : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002//
-// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002//
-// CVS Reference       : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003//
-// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003//
-// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002//
-// CVS Reference       : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002//
-// CVS Reference       : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003//
-// CVS Reference       : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003//
-// CVS Reference       : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002//
-// CVS Reference       : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002//
-// CVS Reference       : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002//
-// ----------------------------------------------------------------------------
-
-#ifndef AT91RM9200_H
-#define AT91RM9200_H
-
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	// 
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	// 
-	AT91_REG	 DBGU_C1R; 	// Chip ID1 Register
-	AT91_REG	 DBGU_C2R; 	// Chip ID2 Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	// 
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	// 
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	// 
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	// 
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	// 
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pad Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	// 
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	// 
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[85]; 	// 
-	AT91_REG	 PIOB_PER; 	// PIO Enable Register
-	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOB_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved13[1]; 	// 
-	AT91_REG	 PIOB_OER; 	// Output Enable Register
-	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOB_OSR; 	// Output Status Register
-	AT91_REG	 Reserved14[1]; 	// 
-	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved15[1]; 	// 
-	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved16[1]; 	// 
-	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOB_PPUSR; 	// Pad Pull-up Status Register
-	AT91_REG	 Reserved17[1]; 	// 
-	AT91_REG	 PIOB_ASR; 	// Select A Register
-	AT91_REG	 PIOB_BSR; 	// Select B Register
-	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved18[9]; 	// 
-	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved19[85]; 	// 
-	AT91_REG	 PIOC_PER; 	// PIO Enable Register
-	AT91_REG	 PIOC_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOC_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved20[1]; 	// 
-	AT91_REG	 PIOC_OER; 	// Output Enable Register
-	AT91_REG	 PIOC_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOC_OSR; 	// Output Status Register
-	AT91_REG	 Reserved21[1]; 	// 
-	AT91_REG	 PIOC_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOC_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOC_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved22[1]; 	// 
-	AT91_REG	 PIOC_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOC_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOC_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOC_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOC_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOC_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOC_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOC_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved23[1]; 	// 
-	AT91_REG	 PIOC_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOC_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOC_PPUSR; 	// Pad Pull-up Status Register
-	AT91_REG	 Reserved24[1]; 	// 
-	AT91_REG	 PIOC_ASR; 	// Select A Register
-	AT91_REG	 PIOC_BSR; 	// Select B Register
-	AT91_REG	 PIOC_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved25[9]; 	// 
-	AT91_REG	 PIOC_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOC_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOC_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved26[85]; 	// 
-	AT91_REG	 PIOD_PER; 	// PIO Enable Register
-	AT91_REG	 PIOD_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOD_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved27[1]; 	// 
-	AT91_REG	 PIOD_OER; 	// Output Enable Register
-	AT91_REG	 PIOD_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOD_OSR; 	// Output Status Register
-	AT91_REG	 Reserved28[1]; 	// 
-	AT91_REG	 PIOD_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOD_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOD_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved29[1]; 	// 
-	AT91_REG	 PIOD_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOD_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOD_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOD_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOD_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOD_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOD_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOD_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOD_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOD_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOD_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved30[1]; 	// 
-	AT91_REG	 PIOD_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOD_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOD_PPUSR; 	// Pad Pull-up Status Register
-	AT91_REG	 Reserved31[1]; 	// 
-	AT91_REG	 PIOD_ASR; 	// Select A Register
-	AT91_REG	 PIOD_BSR; 	// Select B Register
-	AT91_REG	 PIOD_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved32[9]; 	// 
-	AT91_REG	 PIOD_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOD_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOD_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved33[85]; 	// 
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved34[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved35[1]; 	// 
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 CKGR_PLLAR; 	// PLL A Register
-	AT91_REG	 CKGR_PLLBR; 	// PLL B Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved36[3]; 	// 
-	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved37[36]; 	// 
-	AT91_REG	 ST_CR; 	// Control Register
-	AT91_REG	 ST_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 ST_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 ST_RTMR; 	// Real-time Mode Register
-	AT91_REG	 ST_SR; 	// Status Register
-	AT91_REG	 ST_IER; 	// Interrupt Enable Register
-	AT91_REG	 ST_IDR; 	// Interrupt Disable Register
-	AT91_REG	 ST_IMR; 	// Interrupt Mask Register
-	AT91_REG	 ST_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 ST_CRTR; 	// Current Real-time Register
-	AT91_REG	 Reserved38[54]; 	// 
-	AT91_REG	 RTC_CR; 	// Control Register
-	AT91_REG	 RTC_MR; 	// Mode Register
-	AT91_REG	 RTC_TIMR; 	// Time Register
-	AT91_REG	 RTC_CALR; 	// Calendar Register
-	AT91_REG	 RTC_TIMALR; 	// Time Alarm Register
-	AT91_REG	 RTC_CALALR; 	// Calendar Alarm Register
-	AT91_REG	 RTC_SR; 	// Status Register
-	AT91_REG	 RTC_SCCR; 	// Status Clear Command Register
-	AT91_REG	 RTC_IER; 	// Interrupt Enable Register
-	AT91_REG	 RTC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 RTC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 RTC_VER; 	// Valid Entry Register
-	AT91_REG	 Reserved39[52]; 	// 
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved40[1]; 	// 
-	AT91_REG	 MC_PUIA[16]; 	// MC Protection Unit Area
-	AT91_REG	 MC_PUP; 	// MC Protection Unit Peripherals
-	AT91_REG	 MC_PUER; 	// MC Protection Unit Enable Register
-	AT91_REG	 Reserved41[2]; 	// 
-	AT91_REG	 EBI_CSA; 	// Chip Select Assignment Register
-	AT91_REG	 EBI_CFGR; 	// Configuration Register
-	AT91_REG	 Reserved42[2]; 	// 
-	AT91_REG	 EBI_SMC2_CSR[8]; 	// SMC2 Chip Select Register
-	AT91_REG	 EBI_SDRC_MR; 	// SDRAM Controller Mode Register
-	AT91_REG	 EBI_SDRC_TR; 	// SDRAM Controller Refresh Timer Register
-	AT91_REG	 EBI_SDRC_CR; 	// SDRAM Controller Configuration Register
-	AT91_REG	 EBI_SDRC_SRR; 	// SDRAM Controller Self Refresh Register
-	AT91_REG	 EBI_SDRC_LPR; 	// SDRAM Controller Low Power Register
-	AT91_REG	 EBI_SDRC_IER; 	// SDRAM Controller Interrupt Enable Register
-	AT91_REG	 EBI_SDRC_IDR; 	// SDRAM Controller Interrupt Disable Register
-	AT91_REG	 EBI_SDRC_IMR; 	// SDRAM Controller Interrupt Mask Register
-	AT91_REG	 EBI_SDRC_ISR; 	// SDRAM Controller Interrupt Mask Register
-	AT91_REG	 Reserved43[3]; 	// 
-	AT91_REG	 EBI_BFC_MR; 	// BFC Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 MC_PUIA[16]; 	// MC Protection Unit Area
-	AT91_REG	 MC_PUP; 	// MC Protection Unit Peripherals
-	AT91_REG	 MC_PUER; 	// MC Protection Unit Enable Register
-} AT91S_MC, *AT91PS_MC;
-
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_MPU          ((unsigned int) 0x1 <<  2) // (MC) Memory protection Unit Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- 
-#define AT91C_MC_PROT         ((unsigned int) 0x3 <<  0) // (MC) Protection
-#define 	AT91C_MC_PROT_PNAUNA               ((unsigned int) 0x0) // (MC) Privilege: No Access, User: No Access
-#define 	AT91C_MC_PROT_PRWUNA               ((unsigned int) 0x1) // (MC) Privilege: Read/Write, User: No Access
-#define 	AT91C_MC_PROT_PRWURO               ((unsigned int) 0x2) // (MC) Privilege: Read/Write, User: Read Only
-#define 	AT91C_MC_PROT_PRWURW               ((unsigned int) 0x3) // (MC) Privilege: Read/Write, User: Read/Write
-#define AT91C_MC_SIZE         ((unsigned int) 0xF <<  4) // (MC) Internal Area Size
-#define 	AT91C_MC_SIZE_1KB                  ((unsigned int) 0x0 <<  4) // (MC) Area size 1KByte
-#define 	AT91C_MC_SIZE_2KB                  ((unsigned int) 0x1 <<  4) // (MC) Area size 2KByte
-#define 	AT91C_MC_SIZE_4KB                  ((unsigned int) 0x2 <<  4) // (MC) Area size 4KByte
-#define 	AT91C_MC_SIZE_8KB                  ((unsigned int) 0x3 <<  4) // (MC) Area size 8KByte
-#define 	AT91C_MC_SIZE_16KB                 ((unsigned int) 0x4 <<  4) // (MC) Area size 16KByte
-#define 	AT91C_MC_SIZE_32KB                 ((unsigned int) 0x5 <<  4) // (MC) Area size 32KByte
-#define 	AT91C_MC_SIZE_64KB                 ((unsigned int) 0x6 <<  4) // (MC) Area size 64KByte
-#define 	AT91C_MC_SIZE_128KB                ((unsigned int) 0x7 <<  4) // (MC) Area size 128KByte
-#define 	AT91C_MC_SIZE_256KB                ((unsigned int) 0x8 <<  4) // (MC) Area size 256KByte
-#define 	AT91C_MC_SIZE_512KB                ((unsigned int) 0x9 <<  4) // (MC) Area size 512KByte
-#define 	AT91C_MC_SIZE_1MB                  ((unsigned int) 0xA <<  4) // (MC) Area size 1MByte
-#define 	AT91C_MC_SIZE_2MB                  ((unsigned int) 0xB <<  4) // (MC) Area size 2MByte
-#define 	AT91C_MC_SIZE_4MB                  ((unsigned int) 0xC <<  4) // (MC) Area size 4MByte
-#define 	AT91C_MC_SIZE_8MB                  ((unsigned int) 0xD <<  4) // (MC) Area size 8MByte
-#define 	AT91C_MC_SIZE_16MB                 ((unsigned int) 0xE <<  4) // (MC) Area size 16MByte
-#define 	AT91C_MC_SIZE_64MB                 ((unsigned int) 0xF <<  4) // (MC) Area size 64MByte
-#define AT91C_MC_BA           ((unsigned int) 0x3FFFF << 10) // (MC) Internal Area Base Address
-// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- 
-// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- 
-#define AT91C_MC_PUEB         ((unsigned int) 0x1 <<  0) // (MC) Protection Unit enable Bit
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm and Parallel Load Interface
-// *****************************************************************************
-typedef struct _AT91S_RTC {
-	AT91_REG	 RTC_CR; 	// Control Register
-	AT91_REG	 RTC_MR; 	// Mode Register
-	AT91_REG	 RTC_TIMR; 	// Time Register
-	AT91_REG	 RTC_CALR; 	// Calendar Register
-	AT91_REG	 RTC_TIMALR; 	// Time Alarm Register
-	AT91_REG	 RTC_CALALR; 	// Calendar Alarm Register
-	AT91_REG	 RTC_SR; 	// Status Register
-	AT91_REG	 RTC_SCCR; 	// Status Clear Command Register
-	AT91_REG	 RTC_IER; 	// Interrupt Enable Register
-	AT91_REG	 RTC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 RTC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 RTC_VER; 	// Valid Entry Register
-} AT91S_RTC, *AT91PS_RTC;
-
-// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- 
-#define AT91C_RTC_UPDTIM      ((unsigned int) 0x1 <<  0) // (RTC) Update Request Time Register
-#define AT91C_RTC_UPDCAL      ((unsigned int) 0x1 <<  1) // (RTC) Update Request Calendar Register
-#define AT91C_RTC_TIMEVSEL    ((unsigned int) 0x3 <<  8) // (RTC) Time Event Selection
-#define 	AT91C_RTC_TIMEVSEL_MINUTE               ((unsigned int) 0x0 <<  8) // (RTC) Minute change.
-#define 	AT91C_RTC_TIMEVSEL_HOUR                 ((unsigned int) 0x1 <<  8) // (RTC) Hour change.
-#define 	AT91C_RTC_TIMEVSEL_DAY24                ((unsigned int) 0x2 <<  8) // (RTC) Every day at midnight.
-#define 	AT91C_RTC_TIMEVSEL_DAY12                ((unsigned int) 0x3 <<  8) // (RTC) Every day at noon.
-#define AT91C_RTC_CALEVSEL    ((unsigned int) 0x3 << 16) // (RTC) Calendar Event Selection
-#define 	AT91C_RTC_CALEVSEL_WEEK                 ((unsigned int) 0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).
-#define 	AT91C_RTC_CALEVSEL_MONTH                ((unsigned int) 0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).
-#define 	AT91C_RTC_CALEVSEL_YEAR                 ((unsigned int) 0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).
-// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- 
-#define AT91C_RTC_HRMOD       ((unsigned int) 0x1 <<  0) // (RTC) 12-24 hour Mode
-// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- 
-#define AT91C_RTC_SEC         ((unsigned int) 0x7F <<  0) // (RTC) Current Second
-#define AT91C_RTC_MIN         ((unsigned int) 0x7F <<  8) // (RTC) Current Minute
-#define AT91C_RTC_HOUR        ((unsigned int) 0x1F << 16) // (RTC) Current Hour
-#define AT91C_RTC_AMPM        ((unsigned int) 0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator
-// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- 
-#define AT91C_RTC_CENT        ((unsigned int) 0x3F <<  0) // (RTC) Current Century
-#define AT91C_RTC_YEAR        ((unsigned int) 0xFF <<  8) // (RTC) Current Year
-#define AT91C_RTC_MONTH       ((unsigned int) 0x1F << 16) // (RTC) Current Month
-#define AT91C_RTC_DAY         ((unsigned int) 0x7 << 21) // (RTC) Current Day
-#define AT91C_RTC_DATE        ((unsigned int) 0x3F << 24) // (RTC) Current Date
-// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- 
-#define AT91C_RTC_SECEN       ((unsigned int) 0x1 <<  7) // (RTC) Second Alarm Enable
-#define AT91C_RTC_MINEN       ((unsigned int) 0x1 << 15) // (RTC) Minute Alarm
-#define AT91C_RTC_HOUREN      ((unsigned int) 0x1 << 23) // (RTC) Current Hour
-// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- 
-#define AT91C_RTC_MONTHEN     ((unsigned int) 0x1 << 23) // (RTC) Month Alarm Enable
-#define AT91C_RTC_DATEEN      ((unsigned int) 0x1 << 31) // (RTC) Date Alarm Enable
-// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- 
-#define AT91C_RTC_ACKUPD      ((unsigned int) 0x1 <<  0) // (RTC) Acknowledge for Update
-#define AT91C_RTC_ALARM       ((unsigned int) 0x1 <<  1) // (RTC) Alarm Flag
-#define AT91C_RTC_SECEV       ((unsigned int) 0x1 <<  2) // (RTC) Second Event
-#define AT91C_RTC_TIMEV       ((unsigned int) 0x1 <<  3) // (RTC) Time Event
-#define AT91C_RTC_CALEV       ((unsigned int) 0x1 <<  4) // (RTC) Calendar event
-// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- 
-// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- 
-// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- 
-// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- 
-// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- 
-#define AT91C_RTC_NVTIM       ((unsigned int) 0x1 <<  0) // (RTC) Non valid Time
-#define AT91C_RTC_NVCAL       ((unsigned int) 0x1 <<  1) // (RTC) Non valid Calendar
-#define AT91C_RTC_NVTIMALR    ((unsigned int) 0x1 <<  2) // (RTC) Non valid time Alarm
-#define AT91C_RTC_NVCALALR    ((unsigned int) 0x1 <<  3) // (RTC) Nonvalid Calendar Alarm
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Timer Interface
-// *****************************************************************************
-typedef struct _AT91S_ST {
-	AT91_REG	 ST_CR; 	// Control Register
-	AT91_REG	 ST_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 ST_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 ST_RTMR; 	// Real-time Mode Register
-	AT91_REG	 ST_SR; 	// Status Register
-	AT91_REG	 ST_IER; 	// Interrupt Enable Register
-	AT91_REG	 ST_IDR; 	// Interrupt Disable Register
-	AT91_REG	 ST_IMR; 	// Interrupt Mask Register
-	AT91_REG	 ST_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 ST_CRTR; 	// Current Real-time Register
-} AT91S_ST, *AT91PS_ST;
-
-// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- 
-#define AT91C_ST_WDRST        ((unsigned int) 0x1 <<  0) // (ST) Watchdog Timer Restart
-// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- 
-#define AT91C_ST_PIV          ((unsigned int) 0xFFFF <<  0) // (ST) Watchdog Timer Restart
-// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- 
-#define AT91C_ST_WDV          ((unsigned int) 0xFFFF <<  0) // (ST) Watchdog Timer Restart
-#define AT91C_ST_RSTEN        ((unsigned int) 0x1 << 16) // (ST) Reset Enable
-#define AT91C_ST_EXTEN        ((unsigned int) 0x1 << 17) // (ST) External Signal Assertion Enable
-// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- 
-#define AT91C_ST_RTPRES       ((unsigned int) 0xFFFF <<  0) // (ST) Real-time Timer Prescaler Value
-// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- 
-#define AT91C_ST_PITS         ((unsigned int) 0x1 <<  0) // (ST) Period Interval Timer Interrupt
-#define AT91C_ST_WDOVF        ((unsigned int) 0x1 <<  1) // (ST) Watchdog Overflow
-#define AT91C_ST_RTTINC       ((unsigned int) 0x1 <<  2) // (ST) Real-time Timer Increment
-#define AT91C_ST_ALMS         ((unsigned int) 0x1 <<  3) // (ST) Alarm Status
-// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- 
-// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- 
-// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- 
-// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- 
-#define AT91C_ST_ALMV         ((unsigned int) 0xFFFFF <<  0) // (ST) Alarm Value Value
-// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- 
-#define AT91C_ST_CRTV         ((unsigned int) 0xFFFFF <<  0) // (ST) Current Real-time Value
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[5]; 	// 
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved2[3]; 	// 
-	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  1) // (PMC) USB Device Port Clock
-#define AT91C_PMC_MCKUDP      ((unsigned int) 0x1 <<  2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend
-#define AT91C_PMC_UHP         ((unsigned int) 0x1 <<  4) // (PMC) USB Host Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK4        ((unsigned int) 0x1 << 12) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK5        ((unsigned int) 0x1 << 13) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK6        ((unsigned int) 0x1 << 14) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK7        ((unsigned int) 0x1 << 15) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLLA_CLK             ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected
-#define 	AT91C_PMC_CSS_PLLB_CLK             ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-#define AT91C_PMC_MDIV        ((unsigned int) 0x3 <<  8) // (PMC) Master Clock Division
-#define 	AT91C_PMC_MDIV_1                    ((unsigned int) 0x0 <<  8) // (PMC) The master clock and the processor clock are the same
-#define 	AT91C_PMC_MDIV_2                    ((unsigned int) 0x1 <<  8) // (PMC) The processor clock is twice as fast as the master clock
-#define 	AT91C_PMC_MDIV_3                    ((unsigned int) 0x2 <<  8) // (PMC) The processor clock is three times faster than the master clock
-#define 	AT91C_PMC_MDIV_4                    ((unsigned int) 0x3 <<  8) // (PMC) The processor clock is four times faster than the master clock
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCKA       ((unsigned int) 0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCKB       ((unsigned int) 0x1 <<  2) // (PMC) PLL B Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK4RDY     ((unsigned int) 0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK5RDY     ((unsigned int) 0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK6RDY     ((unsigned int) 0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK7RDY     ((unsigned int) 0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 CKGR_PLLAR; 	// PLL A Register
-	AT91_REG	 CKGR_PLLBR; 	// PLL B Register
-} AT91S_CKGR, *AT91PS_CKGR;
-
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCTEST    ((unsigned int) 0x1 <<  1) // (CKGR) Oscillator Test
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- 
-#define AT91C_CKGR_DIVA       ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIVA_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIVA_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLACOUNT  ((unsigned int) 0x3F <<  8) // (CKGR) PLL A Counter
-#define AT91C_CKGR_OUTA       ((unsigned int) 0x3 << 14) // (CKGR) PLL A Output Frequency Range
-#define 	AT91C_CKGR_OUTA_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
-#define 	AT91C_CKGR_OUTA_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
-#define 	AT91C_CKGR_OUTA_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
-#define 	AT91C_CKGR_OUTA_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
-#define AT91C_CKGR_MULA       ((unsigned int) 0x7FF << 16) // (CKGR) PLL A Multiplier
-#define AT91C_CKGR_SRCA       ((unsigned int) 0x1 << 29) // (CKGR) PLL A Source
-// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIVB       ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIVB_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIVB_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLBCOUNT  ((unsigned int) 0x3F <<  8) // (CKGR) PLL B Counter
-#define AT91C_CKGR_OUTB       ((unsigned int) 0x3 << 14) // (CKGR) PLL B Output Frequency Range
-#define 	AT91C_CKGR_OUTB_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
-#define 	AT91C_CKGR_OUTB_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
-#define 	AT91C_CKGR_OUTB_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
-#define 	AT91C_CKGR_OUTB_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
-#define AT91C_CKGR_MULB       ((unsigned int) 0x7FF << 16) // (CKGR) PLL B Multiplier
-#define AT91C_CKGR_USB_96M    ((unsigned int) 0x1 << 28) // (CKGR) Divider for USB Ports
-#define AT91C_CKGR_USB_PLL    ((unsigned int) 0x1 << 29) // (CKGR) PLL Use
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	// 
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pad Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	// 
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	// 
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	// 
-	AT91_REG	 DBGU_C1R; 	// Chip ID1 Register
-	AT91_REG	 DBGU_C2R; 	// Chip ID2 Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       ((unsigned int) 0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    ((unsigned int) 0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	// 
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_DIV32       ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_SPENDRX     ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_SPENDTX     ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 SSC_RC0R; 	// Receive Compare 0 Register
-	AT91_REG	 SSC_RC1R; 	// Receive Compare 1 Register
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved2[44]; 	// 
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG         ((unsigned int) 0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
-#define 	AT91C_SSC_CKG_NONE                 ((unsigned int) 0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define 	AT91C_SSC_CKG_LOW                  ((unsigned int) 0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define 	AT91C_SSC_CKG_HIGH                 ((unsigned int) 0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STOP        ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTOUT      ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0         ((unsigned int) 0x1 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_CP1         ((unsigned int) 0x1 <<  9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	// 
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 US_XXR; 	// XON_XOFF Register
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved1[44]; 	// 
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (USART) Reset Status Bits
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 TWI_SMR; 	// Slave Mode Register
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved0[3]; 	// 
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
-
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SVEN        ((unsigned int) 0x1 <<  4) // (TWI) TWI Slave Transfer Enabled
-#define AT91C_TWI_SVDIS       ((unsigned int) 0x1 <<  5) // (TWI) TWI Slave Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
-#define AT91C_TWI_SADR        ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_SVREAD      ((unsigned int) 0x1 <<  3) // (TWI) Slave Read
-#define AT91C_TWI_SVACC       ((unsigned int) 0x1 <<  4) // (TWI) Slave Access
-#define AT91C_TWI_GCACC       ((unsigned int) 0x1 <<  5) // (TWI) General Call Access
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ARBLST      ((unsigned int) 0x1 <<  9) // (TWI) Arbitration Lost
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface
-// *****************************************************************************
-typedef struct _AT91S_MCI {
-	AT91_REG	 MCI_CR; 	// MCI Control Register
-	AT91_REG	 MCI_MR; 	// MCI Mode Register
-	AT91_REG	 MCI_DTOR; 	// MCI Data Timeout Register
-	AT91_REG	 MCI_SDCR; 	// MCI SD Card Register
-	AT91_REG	 MCI_ARGR; 	// MCI Argument Register
-	AT91_REG	 MCI_CMDR; 	// MCI Command Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 MCI_RSPR[4]; 	// MCI Response Register
-	AT91_REG	 MCI_RDR; 	// MCI Receive Data Register
-	AT91_REG	 MCI_TDR; 	// MCI Transmit Data Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 MCI_SR; 	// MCI Status Register
-	AT91_REG	 MCI_IER; 	// MCI Interrupt Enable Register
-	AT91_REG	 MCI_IDR; 	// MCI Interrupt Disable Register
-	AT91_REG	 MCI_IMR; 	// MCI Interrupt Mask Register
-	AT91_REG	 Reserved2[44]; 	// 
-	AT91_REG	 MCI_RPR; 	// Receive Pointer Register
-	AT91_REG	 MCI_RCR; 	// Receive Counter Register
-	AT91_REG	 MCI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 MCI_TCR; 	// Transmit Counter Register
-	AT91_REG	 MCI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 MCI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 MCI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 MCI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 MCI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 MCI_PTSR; 	// PDC Transfer Status Register
-} AT91S_MCI, *AT91PS_MCI;
-
-// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- 
-#define AT91C_MCI_MCIEN       ((unsigned int) 0x1 <<  0) // (MCI) Multimedia Interface Enable
-#define AT91C_MCI_MCIDIS      ((unsigned int) 0x1 <<  1) // (MCI) Multimedia Interface Disable
-#define AT91C_MCI_PWSEN       ((unsigned int) 0x1 <<  2) // (MCI) Power Save Mode Enable
-#define AT91C_MCI_PWSDIS      ((unsigned int) 0x1 <<  3) // (MCI) Power Save Mode Disable
-// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- 
-#define AT91C_MCI_CLKDIV      ((unsigned int) 0x1 <<  0) // (MCI) Clock Divider
-#define AT91C_MCI_PWSDIV      ((unsigned int) 0x1 <<  8) // (MCI) Power Saving Divider
-#define AT91C_MCI_PDCPADV     ((unsigned int) 0x1 << 14) // (MCI) PDC Padding Value
-#define AT91C_MCI_PDCMODE     ((unsigned int) 0x1 << 15) // (MCI) PDC Oriented Mode
-#define AT91C_MCI_BLKLEN      ((unsigned int) 0x1 << 18) // (MCI) Data Block Length
-// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- 
-#define AT91C_MCI_DTOCYC      ((unsigned int) 0x1 <<  0) // (MCI) Data Timeout Cycle Number
-#define AT91C_MCI_DTOMUL      ((unsigned int) 0x7 <<  4) // (MCI) Data Timeout Multiplier
-#define 	AT91C_MCI_DTOMUL_1                    ((unsigned int) 0x0 <<  4) // (MCI) DTOCYC x 1
-#define 	AT91C_MCI_DTOMUL_16                   ((unsigned int) 0x1 <<  4) // (MCI) DTOCYC x 16
-#define 	AT91C_MCI_DTOMUL_128                  ((unsigned int) 0x2 <<  4) // (MCI) DTOCYC x 128
-#define 	AT91C_MCI_DTOMUL_256                  ((unsigned int) 0x3 <<  4) // (MCI) DTOCYC x 256
-#define 	AT91C_MCI_DTOMUL_1024                 ((unsigned int) 0x4 <<  4) // (MCI) DTOCYC x 1024
-#define 	AT91C_MCI_DTOMUL_4096                 ((unsigned int) 0x5 <<  4) // (MCI) DTOCYC x 4096
-#define 	AT91C_MCI_DTOMUL_65536                ((unsigned int) 0x6 <<  4) // (MCI) DTOCYC x 65536
-#define 	AT91C_MCI_DTOMUL_1048576              ((unsigned int) 0x7 <<  4) // (MCI) DTOCYC x 1048576
-// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- 
-#define AT91C_MCI_SCDSEL      ((unsigned int) 0x1 <<  0) // (MCI) SD Card Selector
-#define AT91C_MCI_SCDBUS      ((unsigned int) 0x1 <<  7) // (MCI) SD Card Bus Width
-// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- 
-#define AT91C_MCI_CMDNB       ((unsigned int) 0x1F <<  0) // (MCI) Command Number
-#define AT91C_MCI_RSPTYP      ((unsigned int) 0x3 <<  6) // (MCI) Response Type
-#define 	AT91C_MCI_RSPTYP_NO                   ((unsigned int) 0x0 <<  6) // (MCI) No response
-#define 	AT91C_MCI_RSPTYP_48                   ((unsigned int) 0x1 <<  6) // (MCI) 48-bit response
-#define 	AT91C_MCI_RSPTYP_136                  ((unsigned int) 0x2 <<  6) // (MCI) 136-bit response
-#define AT91C_MCI_SPCMD       ((unsigned int) 0x7 <<  8) // (MCI) Special CMD
-#define 	AT91C_MCI_SPCMD_NONE                 ((unsigned int) 0x0 <<  8) // (MCI) Not a special CMD
-#define 	AT91C_MCI_SPCMD_INIT                 ((unsigned int) 0x1 <<  8) // (MCI) Initialization CMD
-#define 	AT91C_MCI_SPCMD_SYNC                 ((unsigned int) 0x2 <<  8) // (MCI) Synchronized CMD
-#define 	AT91C_MCI_SPCMD_IT_CMD               ((unsigned int) 0x4 <<  8) // (MCI) Interrupt command
-#define 	AT91C_MCI_SPCMD_IT_REP               ((unsigned int) 0x5 <<  8) // (MCI) Interrupt response
-#define AT91C_MCI_OPDCMD      ((unsigned int) 0x1 << 11) // (MCI) Open Drain Command
-#define AT91C_MCI_MAXLAT      ((unsigned int) 0x1 << 12) // (MCI) Maximum Latency for Command to respond
-#define AT91C_MCI_TRCMD       ((unsigned int) 0x3 << 16) // (MCI) Transfer CMD
-#define 	AT91C_MCI_TRCMD_NO                   ((unsigned int) 0x0 << 16) // (MCI) No transfer
-#define 	AT91C_MCI_TRCMD_START                ((unsigned int) 0x1 << 16) // (MCI) Start transfer
-#define 	AT91C_MCI_TRCMD_STOP                 ((unsigned int) 0x2 << 16) // (MCI) Stop transfer
-#define AT91C_MCI_TRDIR       ((unsigned int) 0x1 << 18) // (MCI) Transfer Direction
-#define AT91C_MCI_TRTYP       ((unsigned int) 0x3 << 19) // (MCI) Transfer Type
-#define 	AT91C_MCI_TRTYP_BLOCK                ((unsigned int) 0x0 << 19) // (MCI) Block Transfer type
-#define 	AT91C_MCI_TRTYP_MULTIPLE             ((unsigned int) 0x1 << 19) // (MCI) Multiple Block transfer type
-#define 	AT91C_MCI_TRTYP_STREAM               ((unsigned int) 0x2 << 19) // (MCI) Stream transfer type
-// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- 
-#define AT91C_MCI_CMDRDY      ((unsigned int) 0x1 <<  0) // (MCI) Command Ready flag
-#define AT91C_MCI_RXRDY       ((unsigned int) 0x1 <<  1) // (MCI) RX Ready flag
-#define AT91C_MCI_TXRDY       ((unsigned int) 0x1 <<  2) // (MCI) TX Ready flag
-#define AT91C_MCI_BLKE        ((unsigned int) 0x1 <<  3) // (MCI) Data Block Transfer Ended flag
-#define AT91C_MCI_DTIP        ((unsigned int) 0x1 <<  4) // (MCI) Data Transfer in Progress flag
-#define AT91C_MCI_NOTBUSY     ((unsigned int) 0x1 <<  5) // (MCI) Data Line Not Busy flag
-#define AT91C_MCI_ENDRX       ((unsigned int) 0x1 <<  6) // (MCI) End of RX Buffer flag
-#define AT91C_MCI_ENDTX       ((unsigned int) 0x1 <<  7) // (MCI) End of TX Buffer flag
-#define AT91C_MCI_RXBUFF      ((unsigned int) 0x1 << 14) // (MCI) RX Buffer Full flag
-#define AT91C_MCI_TXBUFE      ((unsigned int) 0x1 << 15) // (MCI) TX Buffer Empty flag
-#define AT91C_MCI_RINDE       ((unsigned int) 0x1 << 16) // (MCI) Response Index Error flag
-#define AT91C_MCI_RDIRE       ((unsigned int) 0x1 << 17) // (MCI) Response Direction Error flag
-#define AT91C_MCI_RCRCE       ((unsigned int) 0x1 << 18) // (MCI) Response CRC Error flag
-#define AT91C_MCI_RENDE       ((unsigned int) 0x1 << 19) // (MCI) Response End Bit Error flag
-#define AT91C_MCI_RTOE        ((unsigned int) 0x1 << 20) // (MCI) Response Time-out Error flag
-#define AT91C_MCI_DCRCE       ((unsigned int) 0x1 << 21) // (MCI) data CRC Error flag
-#define AT91C_MCI_DTOE        ((unsigned int) 0x1 << 22) // (MCI) Data timeout Error flag
-#define AT91C_MCI_OVRE        ((unsigned int) 0x1 << 30) // (MCI) Overrun flag
-#define AT91C_MCI_UNRE        ((unsigned int) 0x1 << 31) // (MCI) Underrun flag
-// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- 
-// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- 
-// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 UDP_CSR[8]; 	// Endpoint Control and Status Register
-	AT91_REG	 UDP_FDR[8]; 	// Endpoint FIFO Data Register
-} AT91S_UDP, *AT91PS_UDP;
-
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  2) // (UDP) Remote Wake Up Enable
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_EPINT6      ((unsigned int) 0x1 <<  6) // (UDP) Endpoint 6 Interrupt
-#define AT91C_UDP_EPINT7      ((unsigned int) 0x1 <<  7) // (UDP) Endpoint 7 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-#define AT91C_UDP_EP6         ((unsigned int) 0x1 <<  6) // (UDP) Reset Endpoint 6
-#define AT91C_UDP_EP7         ((unsigned int) 0x1 <<  7) // (UDP) Reset Endpoint 7
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_NONE                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_RISING               ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_FALLING              ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_BOTH                 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRCS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	// 
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x1 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x1 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x1 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA2                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Host Interface
-// *****************************************************************************
-typedef struct _AT91S_UHP {
-	AT91_REG	 UHP_HcRevision; 	// Revision
-	AT91_REG	 UHP_HcControl; 	// Operating modes for the Host Controller
-	AT91_REG	 UHP_HcCommandStatus; 	// Command & status Register
-	AT91_REG	 UHP_HcInterruptStatus; 	// Interrupt Status Register
-	AT91_REG	 UHP_HcInterruptEnable; 	// Interrupt Enable Register
-	AT91_REG	 UHP_HcInterruptDisable; 	// Interrupt Disable Register
-	AT91_REG	 UHP_HcHCCA; 	// Pointer to the Host Controller Communication Area
-	AT91_REG	 UHP_HcPeriodCurrentED; 	// Current Isochronous or Interrupt Endpoint Descriptor
-	AT91_REG	 UHP_HcControlHeadED; 	// First Endpoint Descriptor of the Control list
-	AT91_REG	 UHP_HcControlCurrentED; 	// Endpoint Control and Status Register
-	AT91_REG	 UHP_HcBulkHeadED; 	// First endpoint register of the Bulk list
-	AT91_REG	 UHP_HcBulkCurrentED; 	// Current endpoint of the Bulk list
-	AT91_REG	 UHP_HcBulkDoneHead; 	// Last completed transfer descriptor
-	AT91_REG	 UHP_HcFmInterval; 	// Bit time between 2 consecutive SOFs
-	AT91_REG	 UHP_HcFmRemaining; 	// Bit time remaining in the current Frame
-	AT91_REG	 UHP_HcFmNumber; 	// Frame number
-	AT91_REG	 UHP_HcPeriodicStart; 	// Periodic Start
-	AT91_REG	 UHP_HcLSThreshold; 	// LS Threshold
-	AT91_REG	 UHP_HcRhDescriptorA; 	// Root Hub characteristics A
-	AT91_REG	 UHP_HcRhDescriptorB; 	// Root Hub characteristics B
-	AT91_REG	 UHP_HcRhStatus; 	// Root Hub Status register
-	AT91_REG	 UHP_HcRhPortStatus[2]; 	// Root Hub Port Status Register
-} AT91S_UHP, *AT91PS_UHP;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
-	AT91_REG	 EMAC_CTL; 	// Network Control Register
-	AT91_REG	 EMAC_CFG; 	// Network Configuration Register
-	AT91_REG	 EMAC_SR; 	// Network Status Register
-	AT91_REG	 EMAC_TAR; 	// Transmit Address Register
-	AT91_REG	 EMAC_TCR; 	// Transmit Control Register
-	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
-	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 EMAC_RSR; 	// Receive Status Register
-	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
-	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
-	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 EMAC_FRA; 	// Frames Transmitted OK Register
-	AT91_REG	 EMAC_SCOL; 	// Single Collision Frame Register
-	AT91_REG	 EMAC_MCOL; 	// Multiple Collision Frame Register
-	AT91_REG	 EMAC_OK; 	// Frames Received OK Register
-	AT91_REG	 EMAC_SEQE; 	// Frame Check Sequence Error Register
-	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
-	AT91_REG	 EMAC_DTE; 	// Deferred Transmission Frame Register
-	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
-	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
-	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
-	AT91_REG	 EMAC_TUE; 	// Transmit Underrun Error Register
-	AT91_REG	 EMAC_CDE; 	// Code Error Register
-	AT91_REG	 EMAC_ELR; 	// Excessive Length Error Register
-	AT91_REG	 EMAC_RJB; 	// Receive Jabber Register
-	AT91_REG	 EMAC_USF; 	// Undersize Frame Register
-	AT91_REG	 EMAC_SQEE; 	// SQE Test Error Register
-	AT91_REG	 EMAC_DRFC; 	// Discarded RX Frame Register
-	AT91_REG	 Reserved2[3]; 	// 
-	AT91_REG	 EMAC_HSH; 	// Hash Address High[63:32]
-	AT91_REG	 EMAC_HSL; 	// Hash Address Low[31:0]
-	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Low, First 4 bytes
-	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 High, Last 2 bytes
-	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Low, First 4 bytes
-	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 High, Last 2 bytes
-	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Low, First 4 bytes
-	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 High, Last 2 bytes
-	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Low, First 4 bytes
-	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 High, Last 2 bytesr
-} AT91S_EMAC, *AT91PS_EMAC;
-
-// -------- EMAC_CTL : (EMAC Offset: 0x0)  -------- 
-#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LBL        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
-#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
-#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
-#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
-#define AT91C_EMAC_CSR        ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
-#define AT91C_EMAC_ISR        ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
-#define AT91C_EMAC_WES        ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
-#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
-// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- 
-#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
-#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
-#define AT91C_EMAC_BR         ((unsigned int) 0x1 <<  2) // (EMAC) Bit rate. 
-#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
-#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
-#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash enable
-#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
-#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
-#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
-#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
-#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_RMII       ((unsigned int) 0x1 << 13) // (EMAC) 
-// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- 
-#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- 
-#define AT91C_EMAC_LEN        ((unsigned int) 0x7FF <<  0) // (EMAC) 
-#define AT91C_EMAC_NCRC       ((unsigned int) 0x1 << 15) // (EMAC) 
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- 
-#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RLE        ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TXIDLE     ((unsigned int) 0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_BNQ        ((unsigned int) 0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-#define AT91C_EMAC_DONE       ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_RCOM       ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RBNA       ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TOVR       ((unsigned int) 0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_TUND       ((unsigned int) 0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_RTRY       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_TBRE       ((unsigned int) 0x1 <<  6) // (EMAC) 
-#define AT91C_EMAC_TCOM       ((unsigned int) 0x1 <<  7) // (EMAC) 
-#define AT91C_EMAC_TIDLE      ((unsigned int) 0x1 <<  8) // (EMAC) 
-#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
-#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
-#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
-#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
-#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
-#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
-#define AT91C_EMAC_HIGH       ((unsigned int) 0x1 << 30) // (EMAC) 
-#define AT91C_EMAC_LOW        ((unsigned int) 0x1 << 31) // (EMAC) 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR External Bus Interface
-// *****************************************************************************
-typedef struct _AT91S_EBI {
-	AT91_REG	 EBI_CSA; 	// Chip Select Assignment Register
-	AT91_REG	 EBI_CFGR; 	// Configuration Register
-} AT91S_EBI, *AT91PS_EBI;
-
-// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- 
-#define AT91C_EBI_CS0A        ((unsigned int) 0x1 <<  0) // (EBI) Chip Select 0 Assignment
-#define 	AT91C_EBI_CS0A_SMC                  ((unsigned int) 0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller.
-#define 	AT91C_EBI_CS0A_BFC                  ((unsigned int) 0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller.
-#define AT91C_EBI_CS1A        ((unsigned int) 0x1 <<  1) // (EBI) Chip Select 1 Assignment
-#define 	AT91C_EBI_CS1A_SMC                  ((unsigned int) 0x0 <<  1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller.
-#define 	AT91C_EBI_CS1A_SDRAMC               ((unsigned int) 0x1 <<  1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller.
-#define AT91C_EBI_CS3A        ((unsigned int) 0x1 <<  3) // (EBI) Chip Select 3 Assignment
-#define 	AT91C_EBI_CS3A_SMC                  ((unsigned int) 0x0 <<  3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2.
-#define 	AT91C_EBI_CS3A_SMC_SmartMedia       ((unsigned int) 0x1 <<  3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
-#define AT91C_EBI_CS4A        ((unsigned int) 0x1 <<  4) // (EBI) Chip Select 4 Assignment
-#define 	AT91C_EBI_CS4A_SMC                  ((unsigned int) 0x0 <<  4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2.
-#define 	AT91C_EBI_CS4A_SMC_CompactFlash     ((unsigned int) 0x1 <<  4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.
-// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- 
-#define AT91C_EBI_DBPUC       ((unsigned int) 0x1 <<  0) // (EBI) Data Bus Pull-Up Configuration
-#define AT91C_EBI_EBSEN       ((unsigned int) 0x1 <<  1) // (EBI) Bus Sharing Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface
-// *****************************************************************************
-typedef struct _AT91S_SMC2 {
-	AT91_REG	 SMC2_CSR[8]; 	// SMC2 Chip Select Register
-} AT91S_SMC2, *AT91PS_SMC2;
-
-// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- 
-#define AT91C_SMC2_NWS        ((unsigned int) 0x7F <<  0) // (SMC2) Number of Wait States
-#define AT91C_SMC2_WSEN       ((unsigned int) 0x1 <<  7) // (SMC2) Wait State Enable
-#define AT91C_SMC2_TDF        ((unsigned int) 0xF <<  8) // (SMC2) Data Float Time
-#define AT91C_SMC2_BAT        ((unsigned int) 0x1 << 12) // (SMC2) Byte Access Type
-#define AT91C_SMC2_DBW        ((unsigned int) 0x1 << 13) // (SMC2) Data Bus Width
-#define 	AT91C_SMC2_DBW_16                   ((unsigned int) 0x1 << 13) // (SMC2) 16-bit.
-#define 	AT91C_SMC2_DBW_8                    ((unsigned int) 0x2 << 13) // (SMC2) 8-bit.
-#define AT91C_SMC2_DRP        ((unsigned int) 0x1 << 15) // (SMC2) Data Read Protocol
-#define AT91C_SMC2_ACSS       ((unsigned int) 0x3 << 16) // (SMC2) Address to Chip Select Setup
-#define 	AT91C_SMC2_ACSS_STANDARD             ((unsigned int) 0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end.
-#define 	AT91C_SMC2_ACSS_1_CYCLE              ((unsigned int) 0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access.
-#define 	AT91C_SMC2_ACSS_2_CYCLES             ((unsigned int) 0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access.
-#define 	AT91C_SMC2_ACSS_3_CYCLES             ((unsigned int) 0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access.
-#define AT91C_SMC2_RWSETUP    ((unsigned int) 0x7 << 24) // (SMC2) Read and Write Signal Setup Time
-#define AT91C_SMC2_RWHOLD     ((unsigned int) 0x7 << 29) // (SMC2) Read and Write Signal Hold Time
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SDRC {
-	AT91_REG	 SDRC_MR; 	// SDRAM Controller Mode Register
-	AT91_REG	 SDRC_TR; 	// SDRAM Controller Refresh Timer Register
-	AT91_REG	 SDRC_CR; 	// SDRAM Controller Configuration Register
-	AT91_REG	 SDRC_SRR; 	// SDRAM Controller Self Refresh Register
-	AT91_REG	 SDRC_LPR; 	// SDRAM Controller Low Power Register
-	AT91_REG	 SDRC_IER; 	// SDRAM Controller Interrupt Enable Register
-	AT91_REG	 SDRC_IDR; 	// SDRAM Controller Interrupt Disable Register
-	AT91_REG	 SDRC_IMR; 	// SDRAM Controller Interrupt Mask Register
-	AT91_REG	 SDRC_ISR; 	// SDRAM Controller Interrupt Mask Register
-} AT91S_SDRC, *AT91PS_SDRC;
-
-// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- 
-#define AT91C_SDRC_MODE       ((unsigned int) 0xF <<  0) // (SDRC) Mode
-#define 	AT91C_SDRC_MODE_NORMAL_CMD           ((unsigned int) 0x0) // (SDRC) Normal Mode
-#define 	AT91C_SDRC_MODE_NOP_CMD              ((unsigned int) 0x1) // (SDRC) NOP Command
-#define 	AT91C_SDRC_MODE_PRCGALL_CMD          ((unsigned int) 0x2) // (SDRC) All Banks Precharge Command
-#define 	AT91C_SDRC_MODE_LMR_CMD              ((unsigned int) 0x3) // (SDRC) Load Mode Register Command
-#define 	AT91C_SDRC_MODE_RFSH_CMD             ((unsigned int) 0x4) // (SDRC) Refresh Command
-#define AT91C_SDRC_DBW        ((unsigned int) 0x1 <<  4) // (SDRC) Data Bus Width
-#define 	AT91C_SDRC_DBW_32_BITS              ((unsigned int) 0x0 <<  4) // (SDRC) 32 Bits datas bus
-#define 	AT91C_SDRC_DBW_16_BITS              ((unsigned int) 0x1 <<  4) // (SDRC) 16 Bits datas bus
-// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- 
-#define AT91C_SDRC_COUNT      ((unsigned int) 0xFFF <<  0) // (SDRC) Refresh Counter
-// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- 
-#define AT91C_SDRC_NC         ((unsigned int) 0x3 <<  0) // (SDRC) Number of Column Bits
-#define 	AT91C_SDRC_NC_8                    ((unsigned int) 0x0) // (SDRC) 8 Bits
-#define 	AT91C_SDRC_NC_9                    ((unsigned int) 0x1) // (SDRC) 9 Bits
-#define 	AT91C_SDRC_NC_10                   ((unsigned int) 0x2) // (SDRC) 10 Bits
-#define 	AT91C_SDRC_NC_11                   ((unsigned int) 0x3) // (SDRC) 11 Bits
-#define AT91C_SDRC_NR         ((unsigned int) 0x3 <<  2) // (SDRC) Number of Row Bits
-#define 	AT91C_SDRC_NR_11                   ((unsigned int) 0x0 <<  2) // (SDRC) 11 Bits
-#define 	AT91C_SDRC_NR_12                   ((unsigned int) 0x1 <<  2) // (SDRC) 12 Bits
-#define 	AT91C_SDRC_NR_13                   ((unsigned int) 0x2 <<  2) // (SDRC) 13 Bits
-#define AT91C_SDRC_NB         ((unsigned int) 0x1 <<  4) // (SDRC) Number of Banks
-#define 	AT91C_SDRC_NB_2_BANKS              ((unsigned int) 0x0 <<  4) // (SDRC) 2 banks
-#define 	AT91C_SDRC_NB_4_BANKS              ((unsigned int) 0x1 <<  4) // (SDRC) 4 banks
-#define AT91C_SDRC_CAS        ((unsigned int) 0x3 <<  5) // (SDRC) CAS Latency
-#define 	AT91C_SDRC_CAS_2                    ((unsigned int) 0x2 <<  5) // (SDRC) 2 cycles
-#define AT91C_SDRC_TWR        ((unsigned int) 0xF <<  7) // (SDRC) Number of Write Recovery Time Cycles
-#define AT91C_SDRC_TRC        ((unsigned int) 0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles
-#define AT91C_SDRC_TRP        ((unsigned int) 0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles
-#define AT91C_SDRC_TRCD       ((unsigned int) 0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles
-#define AT91C_SDRC_TRAS       ((unsigned int) 0xF << 23) // (SDRC) Number of RAS Active Time Cycles
-#define AT91C_SDRC_TXSR       ((unsigned int) 0xF << 27) // (SDRC) Number of Command Recovery Time Cycles
-// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- 
-#define AT91C_SDRC_SRCB       ((unsigned int) 0x1 <<  0) // (SDRC) Self-refresh Command Bit
-// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- 
-#define AT91C_SDRC_LPCB       ((unsigned int) 0x1 <<  0) // (SDRC) Low-power Command Bit
-// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- 
-#define AT91C_SDRC_RES        ((unsigned int) 0x1 <<  0) // (SDRC) Refresh Error Status
-// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- 
-// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- 
-// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Burst Flash Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_BFC {
-	AT91_REG	 BFC_MR; 	// BFC Mode Register
-} AT91S_BFC, *AT91PS_BFC;
-
-// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- 
-#define AT91C_BFC_BFCOM       ((unsigned int) 0x3 <<  0) // (BFC) Burst Flash Controller Operating Mode
-#define 	AT91C_BFC_BFCOM_DISABLED             ((unsigned int) 0x0) // (BFC) NPCS0 is driven by the SMC or remains high.
-#define 	AT91C_BFC_BFCOM_ASYNC                ((unsigned int) 0x1) // (BFC) Asynchronous
-#define 	AT91C_BFC_BFCOM_BURST_READ           ((unsigned int) 0x2) // (BFC) Burst Read
-#define AT91C_BFC_BFCC        ((unsigned int) 0x3 <<  2) // (BFC) Burst Flash Controller Operating Mode
-#define 	AT91C_BFC_BFCC_MCK                  ((unsigned int) 0x1 <<  2) // (BFC) Master Clock.
-#define 	AT91C_BFC_BFCC_MCK_DIV_2            ((unsigned int) 0x2 <<  2) // (BFC) Master Clock divided by 2.
-#define 	AT91C_BFC_BFCC_MCK_DIV_4            ((unsigned int) 0x3 <<  2) // (BFC) Master Clock divided by 4.
-#define AT91C_BFC_AVL         ((unsigned int) 0xF <<  4) // (BFC) Address Valid Latency
-#define AT91C_BFC_PAGES       ((unsigned int) 0x7 <<  8) // (BFC) Page Size
-#define 	AT91C_BFC_PAGES_NO_PAGE              ((unsigned int) 0x0 <<  8) // (BFC) No page handling.
-#define 	AT91C_BFC_PAGES_16                   ((unsigned int) 0x1 <<  8) // (BFC) 16 bytes page size.
-#define 	AT91C_BFC_PAGES_32                   ((unsigned int) 0x2 <<  8) // (BFC) 32 bytes page size.
-#define 	AT91C_BFC_PAGES_64                   ((unsigned int) 0x3 <<  8) // (BFC) 64 bytes page size.
-#define 	AT91C_BFC_PAGES_128                  ((unsigned int) 0x4 <<  8) // (BFC) 128 bytes page size.
-#define 	AT91C_BFC_PAGES_256                  ((unsigned int) 0x5 <<  8) // (BFC) 256 bytes page size.
-#define 	AT91C_BFC_PAGES_512                  ((unsigned int) 0x6 <<  8) // (BFC) 512 bytes page size.
-#define 	AT91C_BFC_PAGES_1024                 ((unsigned int) 0x7 <<  8) // (BFC) 1024 bytes page size.
-#define AT91C_BFC_OEL         ((unsigned int) 0x3 << 12) // (BFC) Output Enable Latency
-#define AT91C_BFC_BAAEN       ((unsigned int) 0x1 << 16) // (BFC) Burst Address Advance Enable
-#define AT91C_BFC_BFOEH       ((unsigned int) 0x1 << 17) // (BFC) Burst Flash Output Enable Handling
-#define AT91C_BFC_MUXEN       ((unsigned int) 0x1 << 18) // (BFC) Multiplexed Bus Enable
-#define AT91C_BFC_RDYEN       ((unsigned int) 0x1 << 19) // (BFC) Ready Enable Mode
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91RM9200
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ========== 
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_PUER   ((AT91_REG *) 	0xFFFFFF54) // (MC) MC Protection Unit Enable Register
-#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_PUP    ((AT91_REG *) 	0xFFFFFF50) // (MC) MC Protection Unit Peripherals
-#define AT91C_MC_PUIA   ((AT91_REG *) 	0xFFFFFF10) // (MC) MC Protection Unit Area
-#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-// ========== Register definition for RTC peripheral ========== 
-#define AT91C_RTC_IMR   ((AT91_REG *) 	0xFFFFFE28) // (RTC) Interrupt Mask Register
-#define AT91C_RTC_IER   ((AT91_REG *) 	0xFFFFFE20) // (RTC) Interrupt Enable Register
-#define AT91C_RTC_SR    ((AT91_REG *) 	0xFFFFFE18) // (RTC) Status Register
-#define AT91C_RTC_TIMALR ((AT91_REG *) 	0xFFFFFE10) // (RTC) Time Alarm Register
-#define AT91C_RTC_TIMR  ((AT91_REG *) 	0xFFFFFE08) // (RTC) Time Register
-#define AT91C_RTC_CR    ((AT91_REG *) 	0xFFFFFE00) // (RTC) Control Register
-#define AT91C_RTC_VER   ((AT91_REG *) 	0xFFFFFE2C) // (RTC) Valid Entry Register
-#define AT91C_RTC_IDR   ((AT91_REG *) 	0xFFFFFE24) // (RTC) Interrupt Disable Register
-#define AT91C_RTC_SCCR  ((AT91_REG *) 	0xFFFFFE1C) // (RTC) Status Clear Command Register
-#define AT91C_RTC_CALALR ((AT91_REG *) 	0xFFFFFE14) // (RTC) Calendar Alarm Register
-#define AT91C_RTC_CALR  ((AT91_REG *) 	0xFFFFFE0C) // (RTC) Calendar Register
-#define AT91C_RTC_MR    ((AT91_REG *) 	0xFFFFFE04) // (RTC) Mode Register
-// ========== Register definition for ST peripheral ========== 
-#define AT91C_ST_CRTR   ((AT91_REG *) 	0xFFFFFD24) // (ST) Current Real-time Register
-#define AT91C_ST_IMR    ((AT91_REG *) 	0xFFFFFD1C) // (ST) Interrupt Mask Register
-#define AT91C_ST_IER    ((AT91_REG *) 	0xFFFFFD14) // (ST) Interrupt Enable Register
-#define AT91C_ST_RTMR   ((AT91_REG *) 	0xFFFFFD0C) // (ST) Real-time Mode Register
-#define AT91C_ST_PIMR   ((AT91_REG *) 	0xFFFFFD04) // (ST) Period Interval Mode Register
-#define AT91C_ST_RTAR   ((AT91_REG *) 	0xFFFFFD20) // (ST) Real-time Alarm Register
-#define AT91C_ST_IDR    ((AT91_REG *) 	0xFFFFFD18) // (ST) Interrupt Disable Register
-#define AT91C_ST_SR     ((AT91_REG *) 	0xFFFFFD10) // (ST) Status Register
-#define AT91C_ST_WDMR   ((AT91_REG *) 	0xFFFFFD08) // (ST) Watchdog Mode Register
-#define AT91C_ST_CR     ((AT91_REG *) 	0xFFFFFD00) // (ST) Control Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_PLLBR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL B Register
-#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-#define AT91C_CKGR_PLLAR ((AT91_REG *) 	0xFFFFFC28) // (CKGR) PLL A Register
-#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-// ========== Register definition for PIOD peripheral ========== 
-#define AT91C_PIOD_PDSR ((AT91_REG *) 	0xFFFFFA3C) // (PIOD) Pin Data Status Register
-#define AT91C_PIOD_CODR ((AT91_REG *) 	0xFFFFFA34) // (PIOD) Clear Output Data Register
-#define AT91C_PIOD_OWER ((AT91_REG *) 	0xFFFFFAA0) // (PIOD) Output Write Enable Register
-#define AT91C_PIOD_MDER ((AT91_REG *) 	0xFFFFFA50) // (PIOD) Multi-driver Enable Register
-#define AT91C_PIOD_IMR  ((AT91_REG *) 	0xFFFFFA48) // (PIOD) Interrupt Mask Register
-#define AT91C_PIOD_IER  ((AT91_REG *) 	0xFFFFFA40) // (PIOD) Interrupt Enable Register
-#define AT91C_PIOD_ODSR ((AT91_REG *) 	0xFFFFFA38) // (PIOD) Output Data Status Register
-#define AT91C_PIOD_SODR ((AT91_REG *) 	0xFFFFFA30) // (PIOD) Set Output Data Register
-#define AT91C_PIOD_PER  ((AT91_REG *) 	0xFFFFFA00) // (PIOD) PIO Enable Register
-#define AT91C_PIOD_OWDR ((AT91_REG *) 	0xFFFFFAA4) // (PIOD) Output Write Disable Register
-#define AT91C_PIOD_PPUER ((AT91_REG *) 	0xFFFFFA64) // (PIOD) Pull-up Enable Register
-#define AT91C_PIOD_MDDR ((AT91_REG *) 	0xFFFFFA54) // (PIOD) Multi-driver Disable Register
-#define AT91C_PIOD_ISR  ((AT91_REG *) 	0xFFFFFA4C) // (PIOD) Interrupt Status Register
-#define AT91C_PIOD_IDR  ((AT91_REG *) 	0xFFFFFA44) // (PIOD) Interrupt Disable Register
-#define AT91C_PIOD_PDR  ((AT91_REG *) 	0xFFFFFA04) // (PIOD) PIO Disable Register
-#define AT91C_PIOD_ODR  ((AT91_REG *) 	0xFFFFFA14) // (PIOD) Output Disable Registerr
-#define AT91C_PIOD_OWSR ((AT91_REG *) 	0xFFFFFAA8) // (PIOD) Output Write Status Register
-#define AT91C_PIOD_ABSR ((AT91_REG *) 	0xFFFFFA78) // (PIOD) AB Select Status Register
-#define AT91C_PIOD_ASR  ((AT91_REG *) 	0xFFFFFA70) // (PIOD) Select A Register
-#define AT91C_PIOD_PPUSR ((AT91_REG *) 	0xFFFFFA68) // (PIOD) Pad Pull-up Status Register
-#define AT91C_PIOD_PPUDR ((AT91_REG *) 	0xFFFFFA60) // (PIOD) Pull-up Disable Register
-#define AT91C_PIOD_MDSR ((AT91_REG *) 	0xFFFFFA58) // (PIOD) Multi-driver Status Register
-#define AT91C_PIOD_PSR  ((AT91_REG *) 	0xFFFFFA08) // (PIOD) PIO Status Register
-#define AT91C_PIOD_OER  ((AT91_REG *) 	0xFFFFFA10) // (PIOD) Output Enable Register
-#define AT91C_PIOD_OSR  ((AT91_REG *) 	0xFFFFFA18) // (PIOD) Output Status Register
-#define AT91C_PIOD_IFER ((AT91_REG *) 	0xFFFFFA20) // (PIOD) Input Filter Enable Register
-#define AT91C_PIOD_BSR  ((AT91_REG *) 	0xFFFFFA74) // (PIOD) Select B Register
-#define AT91C_PIOD_IFDR ((AT91_REG *) 	0xFFFFFA24) // (PIOD) Input Filter Disable Register
-#define AT91C_PIOD_IFSR ((AT91_REG *) 	0xFFFFFA28) // (PIOD) Input Filter Status Register
-// ========== Register definition for PIOC peripheral ========== 
-#define AT91C_PIOC_IFDR ((AT91_REG *) 	0xFFFFF824) // (PIOC) Input Filter Disable Register
-#define AT91C_PIOC_ODR  ((AT91_REG *) 	0xFFFFF814) // (PIOC) Output Disable Registerr
-#define AT91C_PIOC_ABSR ((AT91_REG *) 	0xFFFFF878) // (PIOC) AB Select Status Register
-#define AT91C_PIOC_SODR ((AT91_REG *) 	0xFFFFF830) // (PIOC) Set Output Data Register
-#define AT91C_PIOC_IFSR ((AT91_REG *) 	0xFFFFF828) // (PIOC) Input Filter Status Register
-#define AT91C_PIOC_CODR ((AT91_REG *) 	0xFFFFF834) // (PIOC) Clear Output Data Register
-#define AT91C_PIOC_ODSR ((AT91_REG *) 	0xFFFFF838) // (PIOC) Output Data Status Register
-#define AT91C_PIOC_IER  ((AT91_REG *) 	0xFFFFF840) // (PIOC) Interrupt Enable Register
-#define AT91C_PIOC_IMR  ((AT91_REG *) 	0xFFFFF848) // (PIOC) Interrupt Mask Register
-#define AT91C_PIOC_OWDR ((AT91_REG *) 	0xFFFFF8A4) // (PIOC) Output Write Disable Register
-#define AT91C_PIOC_MDDR ((AT91_REG *) 	0xFFFFF854) // (PIOC) Multi-driver Disable Register
-#define AT91C_PIOC_PDSR ((AT91_REG *) 	0xFFFFF83C) // (PIOC) Pin Data Status Register
-#define AT91C_PIOC_IDR  ((AT91_REG *) 	0xFFFFF844) // (PIOC) Interrupt Disable Register
-#define AT91C_PIOC_ISR  ((AT91_REG *) 	0xFFFFF84C) // (PIOC) Interrupt Status Register
-#define AT91C_PIOC_PDR  ((AT91_REG *) 	0xFFFFF804) // (PIOC) PIO Disable Register
-#define AT91C_PIOC_OWSR ((AT91_REG *) 	0xFFFFF8A8) // (PIOC) Output Write Status Register
-#define AT91C_PIOC_OWER ((AT91_REG *) 	0xFFFFF8A0) // (PIOC) Output Write Enable Register
-#define AT91C_PIOC_ASR  ((AT91_REG *) 	0xFFFFF870) // (PIOC) Select A Register
-#define AT91C_PIOC_PPUSR ((AT91_REG *) 	0xFFFFF868) // (PIOC) Pad Pull-up Status Register
-#define AT91C_PIOC_PPUDR ((AT91_REG *) 	0xFFFFF860) // (PIOC) Pull-up Disable Register
-#define AT91C_PIOC_MDSR ((AT91_REG *) 	0xFFFFF858) // (PIOC) Multi-driver Status Register
-#define AT91C_PIOC_MDER ((AT91_REG *) 	0xFFFFF850) // (PIOC) Multi-driver Enable Register
-#define AT91C_PIOC_IFER ((AT91_REG *) 	0xFFFFF820) // (PIOC) Input Filter Enable Register
-#define AT91C_PIOC_OSR  ((AT91_REG *) 	0xFFFFF818) // (PIOC) Output Status Register
-#define AT91C_PIOC_OER  ((AT91_REG *) 	0xFFFFF810) // (PIOC) Output Enable Register
-#define AT91C_PIOC_PSR  ((AT91_REG *) 	0xFFFFF808) // (PIOC) PIO Status Register
-#define AT91C_PIOC_PER  ((AT91_REG *) 	0xFFFFF800) // (PIOC) PIO Enable Register
-#define AT91C_PIOC_BSR  ((AT91_REG *) 	0xFFFFF874) // (PIOC) Select B Register
-#define AT91C_PIOC_PPUER ((AT91_REG *) 	0xFFFFF864) // (PIOC) Pull-up Enable Register
-// ========== Register definition for PIOB peripheral ========== 
-#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pad Pull-up Status Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
-#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pad Pull-up Status Register
-#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_C2R  ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID2 Register
-#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_C1R  ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID1 Register
-#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-// ========== Register definition for PDC_SPI peripheral ========== 
-#define AT91C_SPI_PTCR  ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TNPR  ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-#define AT91C_SPI_RNPR  ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_TPR   ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_RPR   ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_PTSR  ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_TNCR  ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR  ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TCR   ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR   ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI) Receive Counter Register
-// ========== Register definition for SPI peripheral ========== 
-#define AT91C_SPI_CSR   ((AT91_REG *) 	0xFFFE0030) // (SPI) Chip Select Register
-#define AT91C_SPI_IDR   ((AT91_REG *) 	0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_SR    ((AT91_REG *) 	0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_RDR   ((AT91_REG *) 	0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CR    ((AT91_REG *) 	0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_IMR   ((AT91_REG *) 	0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_IER   ((AT91_REG *) 	0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_TDR   ((AT91_REG *) 	0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_MR    ((AT91_REG *) 	0xFFFE0004) // (SPI) Mode Register
-// ========== Register definition for PDC_SSC2 peripheral ========== 
-#define AT91C_SSC2_PTCR ((AT91_REG *) 	0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register
-#define AT91C_SSC2_TNPR ((AT91_REG *) 	0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register
-#define AT91C_SSC2_RNPR ((AT91_REG *) 	0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register
-#define AT91C_SSC2_TPR  ((AT91_REG *) 	0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register
-#define AT91C_SSC2_RPR  ((AT91_REG *) 	0xFFFD8100) // (PDC_SSC2) Receive Pointer Register
-#define AT91C_SSC2_PTSR ((AT91_REG *) 	0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register
-#define AT91C_SSC2_TNCR ((AT91_REG *) 	0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register
-#define AT91C_SSC2_RNCR ((AT91_REG *) 	0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register
-#define AT91C_SSC2_TCR  ((AT91_REG *) 	0xFFFD810C) // (PDC_SSC2) Transmit Counter Register
-#define AT91C_SSC2_RCR  ((AT91_REG *) 	0xFFFD8104) // (PDC_SSC2) Receive Counter Register
-// ========== Register definition for SSC2 peripheral ========== 
-#define AT91C_SSC2_IMR  ((AT91_REG *) 	0xFFFD804C) // (SSC2) Interrupt Mask Register
-#define AT91C_SSC2_IER  ((AT91_REG *) 	0xFFFD8044) // (SSC2) Interrupt Enable Register
-#define AT91C_SSC2_RC1R ((AT91_REG *) 	0xFFFD803C) // (SSC2) Receive Compare 1 Register
-#define AT91C_SSC2_TSHR ((AT91_REG *) 	0xFFFD8034) // (SSC2) Transmit Sync Holding Register
-#define AT91C_SSC2_CMR  ((AT91_REG *) 	0xFFFD8004) // (SSC2) Clock Mode Register
-#define AT91C_SSC2_IDR  ((AT91_REG *) 	0xFFFD8048) // (SSC2) Interrupt Disable Register
-#define AT91C_SSC2_TCMR ((AT91_REG *) 	0xFFFD8018) // (SSC2) Transmit Clock Mode Register
-#define AT91C_SSC2_RCMR ((AT91_REG *) 	0xFFFD8010) // (SSC2) Receive Clock ModeRegister
-#define AT91C_SSC2_CR   ((AT91_REG *) 	0xFFFD8000) // (SSC2) Control Register
-#define AT91C_SSC2_RFMR ((AT91_REG *) 	0xFFFD8014) // (SSC2) Receive Frame Mode Register
-#define AT91C_SSC2_TFMR ((AT91_REG *) 	0xFFFD801C) // (SSC2) Transmit Frame Mode Register
-#define AT91C_SSC2_THR  ((AT91_REG *) 	0xFFFD8024) // (SSC2) Transmit Holding Register
-#define AT91C_SSC2_SR   ((AT91_REG *) 	0xFFFD8040) // (SSC2) Status Register
-#define AT91C_SSC2_RC0R ((AT91_REG *) 	0xFFFD8038) // (SSC2) Receive Compare 0 Register
-#define AT91C_SSC2_RSHR ((AT91_REG *) 	0xFFFD8030) // (SSC2) Receive Sync Holding Register
-#define AT91C_SSC2_RHR  ((AT91_REG *) 	0xFFFD8020) // (SSC2) Receive Holding Register
-// ========== Register definition for PDC_SSC1 peripheral ========== 
-#define AT91C_SSC1_PTCR ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register
-#define AT91C_SSC1_TNPR ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register
-#define AT91C_SSC1_RNPR ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register
-#define AT91C_SSC1_TPR  ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register
-#define AT91C_SSC1_RPR  ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC1) Receive Pointer Register
-#define AT91C_SSC1_PTSR ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register
-#define AT91C_SSC1_TNCR ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register
-#define AT91C_SSC1_RNCR ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register
-#define AT91C_SSC1_TCR  ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC1) Transmit Counter Register
-#define AT91C_SSC1_RCR  ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC1) Receive Counter Register
-// ========== Register definition for SSC1 peripheral ========== 
-#define AT91C_SSC1_RFMR ((AT91_REG *) 	0xFFFD4014) // (SSC1) Receive Frame Mode Register
-#define AT91C_SSC1_CMR  ((AT91_REG *) 	0xFFFD4004) // (SSC1) Clock Mode Register
-#define AT91C_SSC1_IDR  ((AT91_REG *) 	0xFFFD4048) // (SSC1) Interrupt Disable Register
-#define AT91C_SSC1_SR   ((AT91_REG *) 	0xFFFD4040) // (SSC1) Status Register
-#define AT91C_SSC1_RC0R ((AT91_REG *) 	0xFFFD4038) // (SSC1) Receive Compare 0 Register
-#define AT91C_SSC1_RSHR ((AT91_REG *) 	0xFFFD4030) // (SSC1) Receive Sync Holding Register
-#define AT91C_SSC1_RHR  ((AT91_REG *) 	0xFFFD4020) // (SSC1) Receive Holding Register
-#define AT91C_SSC1_TCMR ((AT91_REG *) 	0xFFFD4018) // (SSC1) Transmit Clock Mode Register
-#define AT91C_SSC1_RCMR ((AT91_REG *) 	0xFFFD4010) // (SSC1) Receive Clock ModeRegister
-#define AT91C_SSC1_CR   ((AT91_REG *) 	0xFFFD4000) // (SSC1) Control Register
-#define AT91C_SSC1_IMR  ((AT91_REG *) 	0xFFFD404C) // (SSC1) Interrupt Mask Register
-#define AT91C_SSC1_IER  ((AT91_REG *) 	0xFFFD4044) // (SSC1) Interrupt Enable Register
-#define AT91C_SSC1_RC1R ((AT91_REG *) 	0xFFFD403C) // (SSC1) Receive Compare 1 Register
-#define AT91C_SSC1_TSHR ((AT91_REG *) 	0xFFFD4034) // (SSC1) Transmit Sync Holding Register
-#define AT91C_SSC1_THR  ((AT91_REG *) 	0xFFFD4024) // (SSC1) Transmit Holding Register
-#define AT91C_SSC1_TFMR ((AT91_REG *) 	0xFFFD401C) // (SSC1) Transmit Frame Mode Register
-// ========== Register definition for PDC_SSC0 peripheral ========== 
-#define AT91C_SSC0_PTCR ((AT91_REG *) 	0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register
-#define AT91C_SSC0_TNPR ((AT91_REG *) 	0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register
-#define AT91C_SSC0_RNPR ((AT91_REG *) 	0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register
-#define AT91C_SSC0_TPR  ((AT91_REG *) 	0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register
-#define AT91C_SSC0_RPR  ((AT91_REG *) 	0xFFFD0100) // (PDC_SSC0) Receive Pointer Register
-#define AT91C_SSC0_PTSR ((AT91_REG *) 	0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register
-#define AT91C_SSC0_TNCR ((AT91_REG *) 	0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register
-#define AT91C_SSC0_RNCR ((AT91_REG *) 	0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register
-#define AT91C_SSC0_TCR  ((AT91_REG *) 	0xFFFD010C) // (PDC_SSC0) Transmit Counter Register
-#define AT91C_SSC0_RCR  ((AT91_REG *) 	0xFFFD0104) // (PDC_SSC0) Receive Counter Register
-// ========== Register definition for SSC0 peripheral ========== 
-#define AT91C_SSC0_IMR  ((AT91_REG *) 	0xFFFD004C) // (SSC0) Interrupt Mask Register
-#define AT91C_SSC0_IER  ((AT91_REG *) 	0xFFFD0044) // (SSC0) Interrupt Enable Register
-#define AT91C_SSC0_RC1R ((AT91_REG *) 	0xFFFD003C) // (SSC0) Receive Compare 1 Register
-#define AT91C_SSC0_TSHR ((AT91_REG *) 	0xFFFD0034) // (SSC0) Transmit Sync Holding Register
-#define AT91C_SSC0_THR  ((AT91_REG *) 	0xFFFD0024) // (SSC0) Transmit Holding Register
-#define AT91C_SSC0_TFMR ((AT91_REG *) 	0xFFFD001C) // (SSC0) Transmit Frame Mode Register
-#define AT91C_SSC0_RFMR ((AT91_REG *) 	0xFFFD0014) // (SSC0) Receive Frame Mode Register
-#define AT91C_SSC0_CMR  ((AT91_REG *) 	0xFFFD0004) // (SSC0) Clock Mode Register
-#define AT91C_SSC0_IDR  ((AT91_REG *) 	0xFFFD0048) // (SSC0) Interrupt Disable Register
-#define AT91C_SSC0_SR   ((AT91_REG *) 	0xFFFD0040) // (SSC0) Status Register
-#define AT91C_SSC0_RC0R ((AT91_REG *) 	0xFFFD0038) // (SSC0) Receive Compare 0 Register
-#define AT91C_SSC0_RSHR ((AT91_REG *) 	0xFFFD0030) // (SSC0) Receive Sync Holding Register
-#define AT91C_SSC0_RHR  ((AT91_REG *) 	0xFFFD0020) // (SSC0) Receive Holding Register
-#define AT91C_SSC0_TCMR ((AT91_REG *) 	0xFFFD0018) // (SSC0) Transmit Clock Mode Register
-#define AT91C_SSC0_RCMR ((AT91_REG *) 	0xFFFD0010) // (SSC0) Receive Clock ModeRegister
-#define AT91C_SSC0_CR   ((AT91_REG *) 	0xFFFD0000) // (SSC0) Control Register
-// ========== Register definition for PDC_US3 peripheral ========== 
-#define AT91C_US3_PTSR  ((AT91_REG *) 	0xFFFCC124) // (PDC_US3) PDC Transfer Status Register
-#define AT91C_US3_TNCR  ((AT91_REG *) 	0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register
-#define AT91C_US3_RNCR  ((AT91_REG *) 	0xFFFCC114) // (PDC_US3) Receive Next Counter Register
-#define AT91C_US3_TCR   ((AT91_REG *) 	0xFFFCC10C) // (PDC_US3) Transmit Counter Register
-#define AT91C_US3_RCR   ((AT91_REG *) 	0xFFFCC104) // (PDC_US3) Receive Counter Register
-#define AT91C_US3_PTCR  ((AT91_REG *) 	0xFFFCC120) // (PDC_US3) PDC Transfer Control Register
-#define AT91C_US3_TNPR  ((AT91_REG *) 	0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register
-#define AT91C_US3_RNPR  ((AT91_REG *) 	0xFFFCC110) // (PDC_US3) Receive Next Pointer Register
-#define AT91C_US3_TPR   ((AT91_REG *) 	0xFFFCC108) // (PDC_US3) Transmit Pointer Register
-#define AT91C_US3_RPR   ((AT91_REG *) 	0xFFFCC100) // (PDC_US3) Receive Pointer Register
-// ========== Register definition for US3 peripheral ========== 
-#define AT91C_US3_IF    ((AT91_REG *) 	0xFFFCC04C) // (US3) IRDA_FILTER Register
-#define AT91C_US3_NER   ((AT91_REG *) 	0xFFFCC044) // (US3) Nb Errors Register
-#define AT91C_US3_RTOR  ((AT91_REG *) 	0xFFFCC024) // (US3) Receiver Time-out Register
-#define AT91C_US3_THR   ((AT91_REG *) 	0xFFFCC01C) // (US3) Transmitter Holding Register
-#define AT91C_US3_CSR   ((AT91_REG *) 	0xFFFCC014) // (US3) Channel Status Register
-#define AT91C_US3_IDR   ((AT91_REG *) 	0xFFFCC00C) // (US3) Interrupt Disable Register
-#define AT91C_US3_MR    ((AT91_REG *) 	0xFFFCC004) // (US3) Mode Register
-#define AT91C_US3_XXR   ((AT91_REG *) 	0xFFFCC048) // (US3) XON_XOFF Register
-#define AT91C_US3_FIDI  ((AT91_REG *) 	0xFFFCC040) // (US3) FI_DI_Ratio Register
-#define AT91C_US3_TTGR  ((AT91_REG *) 	0xFFFCC028) // (US3) Transmitter Time-guard Register
-#define AT91C_US3_BRGR  ((AT91_REG *) 	0xFFFCC020) // (US3) Baud Rate Generator Register
-#define AT91C_US3_RHR   ((AT91_REG *) 	0xFFFCC018) // (US3) Receiver Holding Register
-#define AT91C_US3_IMR   ((AT91_REG *) 	0xFFFCC010) // (US3) Interrupt Mask Register
-#define AT91C_US3_IER   ((AT91_REG *) 	0xFFFCC008) // (US3) Interrupt Enable Register
-#define AT91C_US3_CR    ((AT91_REG *) 	0xFFFCC000) // (US3) Control Register
-// ========== Register definition for PDC_US2 peripheral ========== 
-#define AT91C_US2_PTSR  ((AT91_REG *) 	0xFFFC8124) // (PDC_US2) PDC Transfer Status Register
-#define AT91C_US2_TNCR  ((AT91_REG *) 	0xFFFC811C) // (PDC_US2) Transmit Next Counter Register
-#define AT91C_US2_RNCR  ((AT91_REG *) 	0xFFFC8114) // (PDC_US2) Receive Next Counter Register
-#define AT91C_US2_TCR   ((AT91_REG *) 	0xFFFC810C) // (PDC_US2) Transmit Counter Register
-#define AT91C_US2_PTCR  ((AT91_REG *) 	0xFFFC8120) // (PDC_US2) PDC Transfer Control Register
-#define AT91C_US2_RCR   ((AT91_REG *) 	0xFFFC8104) // (PDC_US2) Receive Counter Register
-#define AT91C_US2_TNPR  ((AT91_REG *) 	0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register
-#define AT91C_US2_RPR   ((AT91_REG *) 	0xFFFC8100) // (PDC_US2) Receive Pointer Register
-#define AT91C_US2_TPR   ((AT91_REG *) 	0xFFFC8108) // (PDC_US2) Transmit Pointer Register
-#define AT91C_US2_RNPR  ((AT91_REG *) 	0xFFFC8110) // (PDC_US2) Receive Next Pointer Register
-// ========== Register definition for US2 peripheral ========== 
-#define AT91C_US2_XXR   ((AT91_REG *) 	0xFFFC8048) // (US2) XON_XOFF Register
-#define AT91C_US2_FIDI  ((AT91_REG *) 	0xFFFC8040) // (US2) FI_DI_Ratio Register
-#define AT91C_US2_TTGR  ((AT91_REG *) 	0xFFFC8028) // (US2) Transmitter Time-guard Register
-#define AT91C_US2_BRGR  ((AT91_REG *) 	0xFFFC8020) // (US2) Baud Rate Generator Register
-#define AT91C_US2_RHR   ((AT91_REG *) 	0xFFFC8018) // (US2) Receiver Holding Register
-#define AT91C_US2_IMR   ((AT91_REG *) 	0xFFFC8010) // (US2) Interrupt Mask Register
-#define AT91C_US2_IER   ((AT91_REG *) 	0xFFFC8008) // (US2) Interrupt Enable Register
-#define AT91C_US2_CR    ((AT91_REG *) 	0xFFFC8000) // (US2) Control Register
-#define AT91C_US2_IF    ((AT91_REG *) 	0xFFFC804C) // (US2) IRDA_FILTER Register
-#define AT91C_US2_NER   ((AT91_REG *) 	0xFFFC8044) // (US2) Nb Errors Register
-#define AT91C_US2_RTOR  ((AT91_REG *) 	0xFFFC8024) // (US2) Receiver Time-out Register
-#define AT91C_US2_THR   ((AT91_REG *) 	0xFFFC801C) // (US2) Transmitter Holding Register
-#define AT91C_US2_CSR   ((AT91_REG *) 	0xFFFC8014) // (US2) Channel Status Register
-#define AT91C_US2_IDR   ((AT91_REG *) 	0xFFFC800C) // (US2) Interrupt Disable Register
-#define AT91C_US2_MR    ((AT91_REG *) 	0xFFFC8004) // (US2) Mode Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_XXR   ((AT91_REG *) 	0xFFFC4048) // (US1) XON_XOFF Register
-#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_XXR   ((AT91_REG *) 	0xFFFC0048) // (US0) XON_XOFF Register
-#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_SMR   ((AT91_REG *) 	0xFFFB8008) // (TWI) Slave Mode Register
-#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-// ========== Register definition for PDC_MCI peripheral ========== 
-#define AT91C_MCI_PTCR  ((AT91_REG *) 	0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register
-#define AT91C_MCI_TNPR  ((AT91_REG *) 	0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register
-#define AT91C_MCI_RNPR  ((AT91_REG *) 	0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register
-#define AT91C_MCI_TPR   ((AT91_REG *) 	0xFFFB4108) // (PDC_MCI) Transmit Pointer Register
-#define AT91C_MCI_RPR   ((AT91_REG *) 	0xFFFB4100) // (PDC_MCI) Receive Pointer Register
-#define AT91C_MCI_PTSR  ((AT91_REG *) 	0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register
-#define AT91C_MCI_TNCR  ((AT91_REG *) 	0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register
-#define AT91C_MCI_RNCR  ((AT91_REG *) 	0xFFFB4114) // (PDC_MCI) Receive Next Counter Register
-#define AT91C_MCI_TCR   ((AT91_REG *) 	0xFFFB410C) // (PDC_MCI) Transmit Counter Register
-#define AT91C_MCI_RCR   ((AT91_REG *) 	0xFFFB4104) // (PDC_MCI) Receive Counter Register
-// ========== Register definition for MCI peripheral ========== 
-#define AT91C_MCI_IDR   ((AT91_REG *) 	0xFFFB4048) // (MCI) MCI Interrupt Disable Register
-#define AT91C_MCI_SR    ((AT91_REG *) 	0xFFFB4040) // (MCI) MCI Status Register
-#define AT91C_MCI_RDR   ((AT91_REG *) 	0xFFFB4030) // (MCI) MCI Receive Data Register
-#define AT91C_MCI_RSPR  ((AT91_REG *) 	0xFFFB4020) // (MCI) MCI Response Register
-#define AT91C_MCI_ARGR  ((AT91_REG *) 	0xFFFB4010) // (MCI) MCI Argument Register
-#define AT91C_MCI_DTOR  ((AT91_REG *) 	0xFFFB4008) // (MCI) MCI Data Timeout Register
-#define AT91C_MCI_CR    ((AT91_REG *) 	0xFFFB4000) // (MCI) MCI Control Register
-#define AT91C_MCI_IMR   ((AT91_REG *) 	0xFFFB404C) // (MCI) MCI Interrupt Mask Register
-#define AT91C_MCI_IER   ((AT91_REG *) 	0xFFFB4044) // (MCI) MCI Interrupt Enable Register
-#define AT91C_MCI_TDR   ((AT91_REG *) 	0xFFFB4034) // (MCI) MCI Transmit Data Register
-#define AT91C_MCI_CMDR  ((AT91_REG *) 	0xFFFB4014) // (MCI) MCI Command Register
-#define AT91C_MCI_SDCR  ((AT91_REG *) 	0xFFFB400C) // (MCI) MCI SD Card Register
-#define AT91C_MCI_MR    ((AT91_REG *) 	0xFFFB4004) // (MCI) MCI Mode Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-// ========== Register definition for TC5 peripheral ========== 
-#define AT91C_TC5_CMR   ((AT91_REG *) 	0xFFFA4084) // (TC5) Channel Mode Register
-#define AT91C_TC5_IDR   ((AT91_REG *) 	0xFFFA40A8) // (TC5) Interrupt Disable Register
-#define AT91C_TC5_SR    ((AT91_REG *) 	0xFFFA40A0) // (TC5) Status Register
-#define AT91C_TC5_RB    ((AT91_REG *) 	0xFFFA4098) // (TC5) Register B
-#define AT91C_TC5_CV    ((AT91_REG *) 	0xFFFA4090) // (TC5) Counter Value
-#define AT91C_TC5_CCR   ((AT91_REG *) 	0xFFFA4080) // (TC5) Channel Control Register
-#define AT91C_TC5_IMR   ((AT91_REG *) 	0xFFFA40AC) // (TC5) Interrupt Mask Register
-#define AT91C_TC5_IER   ((AT91_REG *) 	0xFFFA40A4) // (TC5) Interrupt Enable Register
-#define AT91C_TC5_RC    ((AT91_REG *) 	0xFFFA409C) // (TC5) Register C
-#define AT91C_TC5_RA    ((AT91_REG *) 	0xFFFA4094) // (TC5) Register A
-// ========== Register definition for TC4 peripheral ========== 
-#define AT91C_TC4_IMR   ((AT91_REG *) 	0xFFFA406C) // (TC4) Interrupt Mask Register
-#define AT91C_TC4_IER   ((AT91_REG *) 	0xFFFA4064) // (TC4) Interrupt Enable Register
-#define AT91C_TC4_RC    ((AT91_REG *) 	0xFFFA405C) // (TC4) Register C
-#define AT91C_TC4_RA    ((AT91_REG *) 	0xFFFA4054) // (TC4) Register A
-#define AT91C_TC4_CMR   ((AT91_REG *) 	0xFFFA4044) // (TC4) Channel Mode Register
-#define AT91C_TC4_IDR   ((AT91_REG *) 	0xFFFA4068) // (TC4) Interrupt Disable Register
-#define AT91C_TC4_SR    ((AT91_REG *) 	0xFFFA4060) // (TC4) Status Register
-#define AT91C_TC4_RB    ((AT91_REG *) 	0xFFFA4058) // (TC4) Register B
-#define AT91C_TC4_CV    ((AT91_REG *) 	0xFFFA4050) // (TC4) Counter Value
-#define AT91C_TC4_CCR   ((AT91_REG *) 	0xFFFA4040) // (TC4) Channel Control Register
-// ========== Register definition for TC3 peripheral ========== 
-#define AT91C_TC3_IMR   ((AT91_REG *) 	0xFFFA402C) // (TC3) Interrupt Mask Register
-#define AT91C_TC3_CV    ((AT91_REG *) 	0xFFFA4010) // (TC3) Counter Value
-#define AT91C_TC3_CCR   ((AT91_REG *) 	0xFFFA4000) // (TC3) Channel Control Register
-#define AT91C_TC3_IER   ((AT91_REG *) 	0xFFFA4024) // (TC3) Interrupt Enable Register
-#define AT91C_TC3_CMR   ((AT91_REG *) 	0xFFFA4004) // (TC3) Channel Mode Register
-#define AT91C_TC3_RA    ((AT91_REG *) 	0xFFFA4014) // (TC3) Register A
-#define AT91C_TC3_RC    ((AT91_REG *) 	0xFFFA401C) // (TC3) Register C
-#define AT91C_TC3_IDR   ((AT91_REG *) 	0xFFFA4028) // (TC3) Interrupt Disable Register
-#define AT91C_TC3_RB    ((AT91_REG *) 	0xFFFA4018) // (TC3) Register B
-#define AT91C_TC3_SR    ((AT91_REG *) 	0xFFFA4020) // (TC3) Status Register
-// ========== Register definition for TCB1 peripheral ========== 
-#define AT91C_TCB1_BCR  ((AT91_REG *) 	0xFFFA4140) // (TCB1) TC Block Control Register
-#define AT91C_TCB1_BMR  ((AT91_REG *) 	0xFFFA4144) // (TCB1) TC Block Mode Register
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register
-#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register
-#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register
-#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-// ========== Register definition for TCB0 peripheral ========== 
-#define AT91C_TCB0_BMR  ((AT91_REG *) 	0xFFFA00C4) // (TCB0) TC Block Mode Register
-#define AT91C_TCB0_BCR  ((AT91_REG *) 	0xFFFA00C0) // (TCB0) TC Block Control Register
-// ========== Register definition for UHP peripheral ========== 
-#define AT91C_UHP_HcRhDescriptorA ((AT91_REG *) 	0x00300048) // (UHP) Root Hub characteristics A
-#define AT91C_UHP_HcRhPortStatus ((AT91_REG *) 	0x00300054) // (UHP) Root Hub Port Status Register
-#define AT91C_UHP_HcRhDescriptorB ((AT91_REG *) 	0x0030004C) // (UHP) Root Hub characteristics B
-#define AT91C_UHP_HcControl ((AT91_REG *) 	0x00300004) // (UHP) Operating modes for the Host Controller
-#define AT91C_UHP_HcInterruptStatus ((AT91_REG *) 	0x0030000C) // (UHP) Interrupt Status Register
-#define AT91C_UHP_HcRhStatus ((AT91_REG *) 	0x00300050) // (UHP) Root Hub Status register
-#define AT91C_UHP_HcRevision ((AT91_REG *) 	0x00300000) // (UHP) Revision
-#define AT91C_UHP_HcCommandStatus ((AT91_REG *) 	0x00300008) // (UHP) Command & status Register
-#define AT91C_UHP_HcInterruptEnable ((AT91_REG *) 	0x00300010) // (UHP) Interrupt Enable Register
-#define AT91C_UHP_HcHCCA ((AT91_REG *) 	0x00300018) // (UHP) Pointer to the Host Controller Communication Area
-#define AT91C_UHP_HcControlHeadED ((AT91_REG *) 	0x00300020) // (UHP) First Endpoint Descriptor of the Control list
-#define AT91C_UHP_HcInterruptDisable ((AT91_REG *) 	0x00300014) // (UHP) Interrupt Disable Register
-#define AT91C_UHP_HcPeriodCurrentED ((AT91_REG *) 	0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
-#define AT91C_UHP_HcControlCurrentED ((AT91_REG *) 	0x00300024) // (UHP) Endpoint Control and Status Register
-#define AT91C_UHP_HcBulkCurrentED ((AT91_REG *) 	0x0030002C) // (UHP) Current endpoint of the Bulk list
-#define AT91C_UHP_HcFmInterval ((AT91_REG *) 	0x00300034) // (UHP) Bit time between 2 consecutive SOFs
-#define AT91C_UHP_HcBulkHeadED ((AT91_REG *) 	0x00300028) // (UHP) First endpoint register of the Bulk list
-#define AT91C_UHP_HcBulkDoneHead ((AT91_REG *) 	0x00300030) // (UHP) Last completed transfer descriptor
-#define AT91C_UHP_HcFmRemaining ((AT91_REG *) 	0x00300038) // (UHP) Bit time remaining in the current Frame
-#define AT91C_UHP_HcPeriodicStart ((AT91_REG *) 	0x00300040) // (UHP) Periodic Start
-#define AT91C_UHP_HcLSThreshold ((AT91_REG *) 	0x00300044) // (UHP) LS Threshold
-#define AT91C_UHP_HcFmNumber ((AT91_REG *) 	0x0030003C) // (UHP) Frame number
-// ========== Register definition for EMAC peripheral ========== 
-#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFBC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFBC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_HSH  ((AT91_REG *) 	0xFFFBC090) // (EMAC) Hash Address High[63:32]
-#define AT91C_EMAC_MCOL ((AT91_REG *) 	0xFFFBC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFBC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes
-#define AT91C_EMAC_HSL  ((AT91_REG *) 	0xFFFBC094) // (EMAC) Hash Address Low[31:0]
-#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFBC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_OK   ((AT91_REG *) 	0xFFFBC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_CFG  ((AT91_REG *) 	0xFFFBC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes
-#define AT91C_EMAC_SEQE ((AT91_REG *) 	0xFFFBC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFBC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_ELR  ((AT91_REG *) 	0xFFFBC070) // (EMAC) Excessive Length Error Register
-#define AT91C_EMAC_SR   ((AT91_REG *) 	0xFFFBC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFBC064) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_RJB  ((AT91_REG *) 	0xFFFBC074) // (EMAC) Receive Jabber Register
-#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFBC078) // (EMAC) Undersize Frame Register
-#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFBC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes
-#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFBC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_FRA  ((AT91_REG *) 	0xFFFBC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes
-#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes
-#define AT91C_EMAC_SCOL ((AT91_REG *) 	0xFFFBC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFBC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_TAR  ((AT91_REG *) 	0xFFFBC00C) // (EMAC) Transmit Address Register
-#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes
-#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes
-#define AT91C_EMAC_TUE  ((AT91_REG *) 	0xFFFBC068) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_DTE  ((AT91_REG *) 	0xFFFBC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TCR  ((AT91_REG *) 	0xFFFBC010) // (EMAC) Transmit Control Register
-#define AT91C_EMAC_CTL  ((AT91_REG *) 	0xFFFBC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr
-#define AT91C_EMAC_CDE  ((AT91_REG *) 	0xFFFBC06C) // (EMAC) Code Error Register
-#define AT91C_EMAC_SQEE ((AT91_REG *) 	0xFFFBC07C) // (EMAC) SQE Test Error Register
-#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFBC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_DRFC ((AT91_REG *) 	0xFFFBC080) // (EMAC) Discarded RX Frame Register
-// ========== Register definition for EBI peripheral ========== 
-#define AT91C_EBI_CFGR  ((AT91_REG *) 	0xFFFFFF64) // (EBI) Configuration Register
-#define AT91C_EBI_CSA   ((AT91_REG *) 	0xFFFFFF60) // (EBI) Chip Select Assignment Register
-// ========== Register definition for SMC2 peripheral ========== 
-#define AT91C_SMC2_CSR  ((AT91_REG *) 	0xFFFFFF70) // (SMC2) SMC2 Chip Select Register
-// ========== Register definition for SDRC peripheral ========== 
-#define AT91C_SDRC_IMR  ((AT91_REG *) 	0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register
-#define AT91C_SDRC_IER  ((AT91_REG *) 	0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register
-#define AT91C_SDRC_SRR  ((AT91_REG *) 	0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register
-#define AT91C_SDRC_TR   ((AT91_REG *) 	0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register
-#define AT91C_SDRC_ISR  ((AT91_REG *) 	0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register
-#define AT91C_SDRC_IDR  ((AT91_REG *) 	0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register
-#define AT91C_SDRC_LPR  ((AT91_REG *) 	0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register
-#define AT91C_SDRC_CR   ((AT91_REG *) 	0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register
-#define AT91C_SDRC_MR   ((AT91_REG *) 	0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register
-// ========== Register definition for BFC peripheral ========== 
-#define AT91C_BFC_MR    ((AT91_REG *) 	0xFFFFFFC0) // (BFC) BFC Mode Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91RM9200
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_MISO     ((unsigned int) AT91C_PIO_PA0) //  SPI Master In Slave
-#define AT91C_PA0_PCK3     ((unsigned int) AT91C_PIO_PA0) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_MOSI     ((unsigned int) AT91C_PIO_PA1) //  SPI Master Out Slave
-#define AT91C_PA1_PCK0     ((unsigned int) AT91C_PIO_PA1) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_ETX1     ((unsigned int) AT91C_PIO_PA10) //  Ethernet MAC Transmit Data 1
-#define AT91C_PA10_MCDB1    ((unsigned int) AT91C_PIO_PA10) //  Multimedia Card B Data 1
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PA11_MCDB2    ((unsigned int) AT91C_PIO_PA11) //  Multimedia Card B Data 2
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_ERX0     ((unsigned int) AT91C_PIO_PA12) //  Ethernet MAC Receive Data 0
-#define AT91C_PA12_MCDB3    ((unsigned int) AT91C_PIO_PA12) //  Multimedia Card B Data 3
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_ERX1     ((unsigned int) AT91C_PIO_PA13) //  Ethernet MAC Receive Data 1
-#define AT91C_PA13_TCLK0    ((unsigned int) AT91C_PIO_PA13) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_ERXER    ((unsigned int) AT91C_PIO_PA14) //  Ethernet MAC Receive Error
-#define AT91C_PA14_TCLK1    ((unsigned int) AT91C_PIO_PA14) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_EMDC     ((unsigned int) AT91C_PIO_PA15) //  Ethernet MAC Management Data Clock
-#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_EMDIO    ((unsigned int) AT91C_PIO_PA16) //  Ethernet MAC Management Data Input/Output
-#define AT91C_PA16_IRQ6     ((unsigned int) AT91C_PIO_PA16) //  AIC Interrupt input 6
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TXD0     ((unsigned int) AT91C_PIO_PA17) //  USART 0 Transmit Data
-#define AT91C_PA17_TIOA0    ((unsigned int) AT91C_PIO_PA17) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RXD0     ((unsigned int) AT91C_PIO_PA18) //  USART 0 Receive Data
-#define AT91C_PA18_TIOB0    ((unsigned int) AT91C_PIO_PA18) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_SCK0     ((unsigned int) AT91C_PIO_PA19) //  USART 0 Serial Clock
-#define AT91C_PA19_TIOA1    ((unsigned int) AT91C_PIO_PA19) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SPCK     ((unsigned int) AT91C_PIO_PA2) //  SPI Serial Clock
-#define AT91C_PA2_IRQ4     ((unsigned int) AT91C_PIO_PA2) //  AIC Interrupt Input 4
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CTS0     ((unsigned int) AT91C_PIO_PA20) //  USART 0 Clear To Send
-#define AT91C_PA20_TIOB1    ((unsigned int) AT91C_PIO_PA20) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RTS0     ((unsigned int) AT91C_PIO_PA21) //  Usart 0 Ready To Send
-#define AT91C_PA21_TIOA2    ((unsigned int) AT91C_PIO_PA21) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_RXD2     ((unsigned int) AT91C_PIO_PA22) //  USART 2 Receive Data
-#define AT91C_PA22_TIOB2    ((unsigned int) AT91C_PIO_PA22) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TXD2     ((unsigned int) AT91C_PIO_PA23) //  USART 2 Transmit Data
-#define AT91C_PA23_IRQ3     ((unsigned int) AT91C_PIO_PA23) //  Interrupt input 3
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_SCK2     ((unsigned int) AT91C_PIO_PA24) //  USART2 Serial Clock
-#define AT91C_PA24_PCK1     ((unsigned int) AT91C_PIO_PA24) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_TWD      ((unsigned int) AT91C_PIO_PA25) //  TWI Two-wire Serial Data
-#define AT91C_PA25_IRQ2     ((unsigned int) AT91C_PIO_PA25) //  Interrupt input 2
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_TWCK     ((unsigned int) AT91C_PIO_PA26) //  TWI Two-wire Serial Clock
-#define AT91C_PA26_IRQ1     ((unsigned int) AT91C_PIO_PA26) //  Interrupt input 1
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_MCCK     ((unsigned int) AT91C_PIO_PA27) //  Multimedia Card Clock
-#define AT91C_PA27_TCLK3    ((unsigned int) AT91C_PIO_PA27) //  Timer Counter 3 External Clock Input
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_MCCDA    ((unsigned int) AT91C_PIO_PA28) //  Multimedia Card A Command
-#define AT91C_PA28_TCLK4    ((unsigned int) AT91C_PIO_PA28) //  Timer Counter 4 external Clock Input
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_MCDA0    ((unsigned int) AT91C_PIO_PA29) //  Multimedia Card A Data 0
-#define AT91C_PA29_TCLK5    ((unsigned int) AT91C_PIO_PA29) //  Timer Counter 5 external clock input
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_NPCS0    ((unsigned int) AT91C_PIO_PA3) //  SPI Peripheral Chip Select 0
-#define AT91C_PA3_IRQ5     ((unsigned int) AT91C_PIO_PA3) //  AIC Interrupt Input 5
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_DRXD     ((unsigned int) AT91C_PIO_PA30) //  DBGU Debug Receive Data
-#define AT91C_PA30_CTS2     ((unsigned int) AT91C_PIO_PA30) //  Usart 2 Clear To Send
-#define AT91C_PIO_PA31       ((unsigned int) 1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_DTXD     ((unsigned int) AT91C_PIO_PA31) //  DBGU Debug Transmit Data
-#define AT91C_PA31_RTS2     ((unsigned int) AT91C_PIO_PA31) //  USART 2 Ready To Send
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_NPCS1    ((unsigned int) AT91C_PIO_PA4) //  SPI Peripheral Chip Select 1
-#define AT91C_PA4_PCK1     ((unsigned int) AT91C_PIO_PA4) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_NPCS2    ((unsigned int) AT91C_PIO_PA5) //  SPI Peripheral Chip Select 2
-#define AT91C_PA5_TXD3     ((unsigned int) AT91C_PIO_PA5) //  USART 3 Transmit Data
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_NPCS3    ((unsigned int) AT91C_PIO_PA6) //  SPI Peripheral Chip Select 3
-#define AT91C_PA6_RXD3     ((unsigned int) AT91C_PIO_PA6) //  USART 3 Receive Data
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PA7_PCK2     ((unsigned int) AT91C_PIO_PA7) //  PMC Programmable Clock 2
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_ETXEN    ((unsigned int) AT91C_PIO_PA8) //  Ethernet MAC Transmit Enable
-#define AT91C_PA8_MCCDB    ((unsigned int) AT91C_PIO_PA8) //  Multimedia Card B Command
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_ETX0     ((unsigned int) AT91C_PIO_PA9) //  Ethernet MAC Transmit Data 0
-#define AT91C_PA9_MCDB0    ((unsigned int) AT91C_PIO_PA9) //  Multimedia Card B Data 0
-#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_TF0      ((unsigned int) AT91C_PIO_PB0) //  SSC Transmit Frame Sync 0
-#define AT91C_PB0_TIOB3    ((unsigned int) AT91C_PIO_PB0) //  Timer Counter 3 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_TK0      ((unsigned int) AT91C_PIO_PB1) //  SSC Transmit Clock 0
-#define AT91C_PB1_CTS3     ((unsigned int) AT91C_PIO_PB1) //  USART 3 Clear To Send
-#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_RK1      ((unsigned int) AT91C_PIO_PB10) //  SSC Receive Clock 1
-#define AT91C_PB10_TIOA5    ((unsigned int) AT91C_PIO_PB10) //  Timer Counter 5 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_RF1      ((unsigned int) AT91C_PIO_PB11) //  SSC Receive Frame Sync 1
-#define AT91C_PB11_TIOB5    ((unsigned int) AT91C_PIO_PB11) //  Timer Counter 5 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_TF2      ((unsigned int) AT91C_PIO_PB12) //  SSC Transmit Frame Sync 2
-#define AT91C_PB12_ETX2     ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmit Data 2
-#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_TK2      ((unsigned int) AT91C_PIO_PB13) //  SSC Transmit Clock 2
-#define AT91C_PB13_ETX3     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Transmit Data 3
-#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_TD2      ((unsigned int) AT91C_PIO_PB14) //  SSC Transmit Data 2
-#define AT91C_PB14_ETXER    ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_RD2      ((unsigned int) AT91C_PIO_PB15) //  SSC Receive Data 2
-#define AT91C_PB15_ERX2     ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data 2
-#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_RK2      ((unsigned int) AT91C_PIO_PB16) //  SSC Receive Clock 2
-#define AT91C_PB16_ERX3     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Receive Data 3
-#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_RF2      ((unsigned int) AT91C_PIO_PB17) //  SSC Receive Frame Sync 2
-#define AT91C_PB17_ERXDV    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_RI1      ((unsigned int) AT91C_PIO_PB18) //  USART 1 Ring Indicator
-#define AT91C_PB18_ECOL     ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Collision Detected
-#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_DTR1     ((unsigned int) AT91C_PIO_PB19) //  USART 1 Data Terminal ready
-#define AT91C_PB19_ERXCK    ((unsigned int) AT91C_PIO_PB19) //  Ethernet MAC Receive Clock
-#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_TD0      ((unsigned int) AT91C_PIO_PB2) //  SSC Transmit data
-#define AT91C_PB2_SCK3     ((unsigned int) AT91C_PIO_PB2) //  USART 3 Serial Clock
-#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_TXD1     ((unsigned int) AT91C_PIO_PB20) //  USART 1 Transmit Data
-#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_RXD1     ((unsigned int) AT91C_PIO_PB21) //  USART 1 Receive Data
-#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_SCK1     ((unsigned int) AT91C_PIO_PB22) //  USART1 Serial Clock
-#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_CTS1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Clear To Send
-#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_DSR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Set ready
-#define AT91C_PB25_EF100    ((unsigned int) AT91C_PIO_PB25) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_RTS1     ((unsigned int) AT91C_PIO_PB26) //  Usart 0 Ready To Send
-#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_PCK0     ((unsigned int) AT91C_PIO_PB27) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_FIQ      ((unsigned int) AT91C_PIO_PB28) //  AIC Fast Interrupt Input
-#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_IRQ0     ((unsigned int) AT91C_PIO_PB29) //  Interrupt input 0
-#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_RD0      ((unsigned int) AT91C_PIO_PB3) //  SSC Receive Data
-#define AT91C_PB3_MCDA1    ((unsigned int) AT91C_PIO_PB3) //  Multimedia Card A Data 1
-#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_RK0      ((unsigned int) AT91C_PIO_PB4) //  SSC Receive Clock
-#define AT91C_PB4_MCDA2    ((unsigned int) AT91C_PIO_PB4) //  Multimedia Card A Data 2
-#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_RF0      ((unsigned int) AT91C_PIO_PB5) //  SSC Receive Frame Sync 0
-#define AT91C_PB5_MCDA3    ((unsigned int) AT91C_PIO_PB5) //  Multimedia Card A Data 3
-#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_TF1      ((unsigned int) AT91C_PIO_PB6) //  SSC Transmit Frame Sync 1
-#define AT91C_PB6_TIOA3    ((unsigned int) AT91C_PIO_PB6) //  Timer Counter 4 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_TK1      ((unsigned int) AT91C_PIO_PB7) //  SSC Transmit Clock 1
-#define AT91C_PB7_TIOB3    ((unsigned int) AT91C_PIO_PB7) //  Timer Counter 3 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_TD1      ((unsigned int) AT91C_PIO_PB8) //  SSC Transmit Data 1
-#define AT91C_PB8_TIOA4    ((unsigned int) AT91C_PIO_PB8) //  Timer Counter 4 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_RD1      ((unsigned int) AT91C_PIO_PB9) //  SSC Receive Data 1
-#define AT91C_PB9_TIOB4    ((unsigned int) AT91C_PIO_PB9) //  Timer Counter 4 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PC0        ((unsigned int) 1 <<  0) // Pin Controlled by PC0
-#define AT91C_PC0_BFCK     ((unsigned int) AT91C_PIO_PC0) //  Burst Flash Clock
-#define AT91C_PIO_PC1        ((unsigned int) 1 <<  1) // Pin Controlled by PC1
-#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) //  Burst Flash Ready
-#define AT91C_PIO_PC10       ((unsigned int) 1 << 10) // Pin Controlled by PC10
-#define AT91C_PC10_NCS4_CFCS ((unsigned int) AT91C_PIO_PC10) //  Compact Flash Chip Select
-#define AT91C_PIO_PC11       ((unsigned int) 1 << 11) // Pin Controlled by PC11
-#define AT91C_PC11_NCS5_CFCE1 ((unsigned int) AT91C_PIO_PC11) //  Chip Select 5 / Compact Flash Chip Enable 1
-#define AT91C_PIO_PC12       ((unsigned int) 1 << 12) // Pin Controlled by PC12
-#define AT91C_PC12_NCS6_CFCE2 ((unsigned int) AT91C_PIO_PC12) //  Chip Select 6 / Compact Flash Chip Enable 2
-#define AT91C_PIO_PC13       ((unsigned int) 1 << 13) // Pin Controlled by PC13
-#define AT91C_PC13_NCS7     ((unsigned int) AT91C_PIO_PC13) //  Chip Select 7
-#define AT91C_PIO_PC14       ((unsigned int) 1 << 14) // Pin Controlled by PC14
-#define AT91C_PIO_PC15       ((unsigned int) 1 << 15) // Pin Controlled by PC15
-#define AT91C_PIO_PC16       ((unsigned int) 1 << 16) // Pin Controlled by PC16
-#define AT91C_PC16_D16      ((unsigned int) AT91C_PIO_PC16) //  Data Bus [16]
-#define AT91C_PIO_PC17       ((unsigned int) 1 << 17) // Pin Controlled by PC17
-#define AT91C_PC17_D17      ((unsigned int) AT91C_PIO_PC17) //  Data Bus [17]
-#define AT91C_PIO_PC18       ((unsigned int) 1 << 18) // Pin Controlled by PC18
-#define AT91C_PC18_D18      ((unsigned int) AT91C_PIO_PC18) //  Data Bus [18]
-#define AT91C_PIO_PC19       ((unsigned int) 1 << 19) // Pin Controlled by PC19
-#define AT91C_PC19_D19      ((unsigned int) AT91C_PIO_PC19) //  Data Bus [19]
-#define AT91C_PIO_PC2        ((unsigned int) 1 <<  2) // Pin Controlled by PC2
-#define AT91C_PC2_BFAVD    ((unsigned int) AT91C_PIO_PC2) //  Burst Flash Address Valid
-#define AT91C_PIO_PC20       ((unsigned int) 1 << 20) // Pin Controlled by PC20
-#define AT91C_PC20_D20      ((unsigned int) AT91C_PIO_PC20) //  Data Bus [20]
-#define AT91C_PIO_PC21       ((unsigned int) 1 << 21) // Pin Controlled by PC21
-#define AT91C_PC21_D21      ((unsigned int) AT91C_PIO_PC21) //  Data Bus [21]
-#define AT91C_PIO_PC22       ((unsigned int) 1 << 22) // Pin Controlled by PC22
-#define AT91C_PC22_D22      ((unsigned int) AT91C_PIO_PC22) //  Data Bus [22]
-#define AT91C_PIO_PC23       ((unsigned int) 1 << 23) // Pin Controlled by PC23
-#define AT91C_PC23_D23      ((unsigned int) AT91C_PIO_PC23) //  Data Bus [23]
-#define AT91C_PIO_PC24       ((unsigned int) 1 << 24) // Pin Controlled by PC24
-#define AT91C_PC24_D24      ((unsigned int) AT91C_PIO_PC24) //  Data Bus [24]
-#define AT91C_PIO_PC25       ((unsigned int) 1 << 25) // Pin Controlled by PC25
-#define AT91C_PC25_D25      ((unsigned int) AT91C_PIO_PC25) //  Data Bus [25]
-#define AT91C_PIO_PC26       ((unsigned int) 1 << 26) // Pin Controlled by PC26
-#define AT91C_PC26_D26      ((unsigned int) AT91C_PIO_PC26) //  Data Bus [26]
-#define AT91C_PIO_PC27       ((unsigned int) 1 << 27) // Pin Controlled by PC27
-#define AT91C_PC27_D27      ((unsigned int) AT91C_PIO_PC27) //  Data Bus [27]
-#define AT91C_PIO_PC28       ((unsigned int) 1 << 28) // Pin Controlled by PC28
-#define AT91C_PC28_D28      ((unsigned int) AT91C_PIO_PC28) //  Data Bus [28]
-#define AT91C_PIO_PC29       ((unsigned int) 1 << 29) // Pin Controlled by PC29
-#define AT91C_PC29_D29      ((unsigned int) AT91C_PIO_PC29) //  Data Bus [29]
-#define AT91C_PIO_PC3        ((unsigned int) 1 <<  3) // Pin Controlled by PC3
-#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) //  Burst Flash Address Advance / SmartMedia Write Enable
-#define AT91C_PIO_PC30       ((unsigned int) 1 << 30) // Pin Controlled by PC30
-#define AT91C_PC30_D30      ((unsigned int) AT91C_PIO_PC30) //  Data Bus [30]
-#define AT91C_PIO_PC31       ((unsigned int) 1 << 31) // Pin Controlled by PC31
-#define AT91C_PC31_D31      ((unsigned int) AT91C_PIO_PC31) //  Data Bus [31]
-#define AT91C_PIO_PC4        ((unsigned int) 1 <<  4) // Pin Controlled by PC4
-#define AT91C_PC4_BFOE     ((unsigned int) AT91C_PIO_PC4) //  Burst Flash Output Enable
-#define AT91C_PIO_PC5        ((unsigned int) 1 <<  5) // Pin Controlled by PC5
-#define AT91C_PC5_BFWE     ((unsigned int) AT91C_PIO_PC5) //  Burst Flash Write Enable
-#define AT91C_PIO_PC6        ((unsigned int) 1 <<  6) // Pin Controlled by PC6
-#define AT91C_PC6_NWAIT    ((unsigned int) AT91C_PIO_PC6) //  NWAIT
-#define AT91C_PIO_PC7        ((unsigned int) 1 <<  7) // Pin Controlled by PC7
-#define AT91C_PC7_A23      ((unsigned int) AT91C_PIO_PC7) //  Address Bus[23]
-#define AT91C_PIO_PC8        ((unsigned int) 1 <<  8) // Pin Controlled by PC8
-#define AT91C_PC8_A24      ((unsigned int) AT91C_PIO_PC8) //  Address Bus[24]
-#define AT91C_PIO_PC9        ((unsigned int) 1 <<  9) // Pin Controlled by PC9
-#define AT91C_PC9_A25_CFRNW ((unsigned int) AT91C_PIO_PC9) //  Address Bus[25] /  Compact Flash Read Not Write
-#define AT91C_PIO_PD0        ((unsigned int) 1 <<  0) // Pin Controlled by PD0
-#define AT91C_PD0_ETX0     ((unsigned int) AT91C_PIO_PD0) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PD1        ((unsigned int) 1 <<  1) // Pin Controlled by PD1
-#define AT91C_PD1_ETX1     ((unsigned int) AT91C_PIO_PD1) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PD10       ((unsigned int) 1 << 10) // Pin Controlled by PD10
-#define AT91C_PD10_PCK3     ((unsigned int) AT91C_PIO_PD10) //  PMC Programmable Clock Output 3
-#define AT91C_PD10_TPS1     ((unsigned int) AT91C_PIO_PD10) //  ETM ARM9 pipeline status 1
-#define AT91C_PIO_PD11       ((unsigned int) 1 << 11) // Pin Controlled by PD11
-#define AT91C_PD11_         ((unsigned int) AT91C_PIO_PD11) //  
-#define AT91C_PD11_TPS2     ((unsigned int) AT91C_PIO_PD11) //  ETM ARM9 pipeline status 2
-#define AT91C_PIO_PD12       ((unsigned int) 1 << 12) // Pin Controlled by PD12
-#define AT91C_PD12_         ((unsigned int) AT91C_PIO_PD12) //  
-#define AT91C_PD12_TPK0     ((unsigned int) AT91C_PIO_PD12) //  ETM Trace Packet 0
-#define AT91C_PIO_PD13       ((unsigned int) 1 << 13) // Pin Controlled by PD13
-#define AT91C_PD13_         ((unsigned int) AT91C_PIO_PD13) //  
-#define AT91C_PD13_TPK1     ((unsigned int) AT91C_PIO_PD13) //  ETM Trace Packet 1
-#define AT91C_PIO_PD14       ((unsigned int) 1 << 14) // Pin Controlled by PD14
-#define AT91C_PD14_         ((unsigned int) AT91C_PIO_PD14) //  
-#define AT91C_PD14_TPK2     ((unsigned int) AT91C_PIO_PD14) //  ETM Trace Packet 2
-#define AT91C_PIO_PD15       ((unsigned int) 1 << 15) // Pin Controlled by PD15
-#define AT91C_PD15_TD0      ((unsigned int) AT91C_PIO_PD15) //  SSC Transmit data
-#define AT91C_PD15_TPK3     ((unsigned int) AT91C_PIO_PD15) //  ETM Trace Packet 3
-#define AT91C_PIO_PD16       ((unsigned int) 1 << 16) // Pin Controlled by PD16
-#define AT91C_PD16_TD1      ((unsigned int) AT91C_PIO_PD16) //  SSC Transmit Data 1
-#define AT91C_PD16_TPK4     ((unsigned int) AT91C_PIO_PD16) //  ETM Trace Packet 4
-#define AT91C_PIO_PD17       ((unsigned int) 1 << 17) // Pin Controlled by PD17
-#define AT91C_PD17_TD2      ((unsigned int) AT91C_PIO_PD17) //  SSC Transmit Data 2
-#define AT91C_PD17_TPK5     ((unsigned int) AT91C_PIO_PD17) //  ETM Trace Packet 5
-#define AT91C_PIO_PD18       ((unsigned int) 1 << 18) // Pin Controlled by PD18
-#define AT91C_PD18_NPCS1    ((unsigned int) AT91C_PIO_PD18) //  SPI Peripheral Chip Select 1
-#define AT91C_PD18_TPK6     ((unsigned int) AT91C_PIO_PD18) //  ETM Trace Packet 6
-#define AT91C_PIO_PD19       ((unsigned int) 1 << 19) // Pin Controlled by PD19
-#define AT91C_PD19_NPCS2    ((unsigned int) AT91C_PIO_PD19) //  SPI Peripheral Chip Select 2
-#define AT91C_PD19_TPK7     ((unsigned int) AT91C_PIO_PD19) //  ETM Trace Packet 7
-#define AT91C_PIO_PD2        ((unsigned int) 1 <<  2) // Pin Controlled by PD2
-#define AT91C_PD2_ETX2     ((unsigned int) AT91C_PIO_PD2) //  Ethernet MAC Transmit Data 2
-#define AT91C_PIO_PD20       ((unsigned int) 1 << 20) // Pin Controlled by PD20
-#define AT91C_PD20_NPCS3    ((unsigned int) AT91C_PIO_PD20) //  SPI Peripheral Chip Select 3
-#define AT91C_PD20_TPK8     ((unsigned int) AT91C_PIO_PD20) //  ETM Trace Packet 8
-#define AT91C_PIO_PD21       ((unsigned int) 1 << 21) // Pin Controlled by PD21
-#define AT91C_PD21_RTS0     ((unsigned int) AT91C_PIO_PD21) //  Usart 0 Ready To Send
-#define AT91C_PD21_TPK9     ((unsigned int) AT91C_PIO_PD21) //  ETM Trace Packet 9
-#define AT91C_PIO_PD22       ((unsigned int) 1 << 22) // Pin Controlled by PD22
-#define AT91C_PD22_RTS1     ((unsigned int) AT91C_PIO_PD22) //  Usart 0 Ready To Send
-#define AT91C_PD22_TPK10    ((unsigned int) AT91C_PIO_PD22) //  ETM Trace Packet 10
-#define AT91C_PIO_PD23       ((unsigned int) 1 << 23) // Pin Controlled by PD23
-#define AT91C_PD23_RTS2     ((unsigned int) AT91C_PIO_PD23) //  USART 2 Ready To Send
-#define AT91C_PD23_TPK11    ((unsigned int) AT91C_PIO_PD23) //  ETM Trace Packet 11
-#define AT91C_PIO_PD24       ((unsigned int) 1 << 24) // Pin Controlled by PD24
-#define AT91C_PD24_RTS3     ((unsigned int) AT91C_PIO_PD24) //  USART 3 Ready To Send
-#define AT91C_PD24_TPK12    ((unsigned int) AT91C_PIO_PD24) //  ETM Trace Packet 12
-#define AT91C_PIO_PD25       ((unsigned int) 1 << 25) // Pin Controlled by PD25
-#define AT91C_PD25_DTR1     ((unsigned int) AT91C_PIO_PD25) //  USART 1 Data Terminal ready
-#define AT91C_PD25_TPK13    ((unsigned int) AT91C_PIO_PD25) //  ETM Trace Packet 13
-#define AT91C_PIO_PD26       ((unsigned int) 1 << 26) // Pin Controlled by PD26
-#define AT91C_PD26_TPK14    ((unsigned int) AT91C_PIO_PD26) //  ETM Trace Packet 14
-#define AT91C_PIO_PD27       ((unsigned int) 1 << 27) // Pin Controlled by PD27
-#define AT91C_PD27_TPK15    ((unsigned int) AT91C_PIO_PD27) //  ETM Trace Packet 15
-#define AT91C_PIO_PD3        ((unsigned int) 1 <<  3) // Pin Controlled by PD3
-#define AT91C_PD3_ETX3     ((unsigned int) AT91C_PIO_PD3) //  Ethernet MAC Transmit Data 3
-#define AT91C_PIO_PD4        ((unsigned int) 1 <<  4) // Pin Controlled by PD4
-#define AT91C_PD4_ETXEN    ((unsigned int) AT91C_PIO_PD4) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PD5        ((unsigned int) 1 <<  5) // Pin Controlled by PD5
-#define AT91C_PD5_ETXER    ((unsigned int) AT91C_PIO_PD5) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PIO_PD6        ((unsigned int) 1 <<  6) // Pin Controlled by PD6
-#define AT91C_PD6_DTXD     ((unsigned int) AT91C_PIO_PD6) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PD7        ((unsigned int) 1 <<  7) // Pin Controlled by PD7
-#define AT91C_PD7_PCK0     ((unsigned int) AT91C_PIO_PD7) //  PMC Programmable Clock Output 0
-#define AT91C_PD7_TSYNC    ((unsigned int) AT91C_PIO_PD7) //  ETM Synchronization signal
-#define AT91C_PIO_PD8        ((unsigned int) 1 <<  8) // Pin Controlled by PD8
-#define AT91C_PD8_PCK1     ((unsigned int) AT91C_PIO_PD8) //  PMC Programmable Clock Output 1
-#define AT91C_PD8_TCLK     ((unsigned int) AT91C_PIO_PD8) //  ETM Trace Clock signal
-#define AT91C_PIO_PD9        ((unsigned int) 1 <<  9) // Pin Controlled by PD9
-#define AT91C_PD9_PCK2     ((unsigned int) AT91C_PIO_PD9) //  PMC Programmable Clock 2
-#define AT91C_PD9_TPS0     ((unsigned int) AT91C_PIO_PD9) //  ETM ARM9 pipeline status 0
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91RM9200
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A 
-#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
-#define AT91C_ID_PIOC   ((unsigned int)  4) // Parallel IO Controller C
-#define AT91C_ID_PIOD   ((unsigned int)  5) // Parallel IO Controller D
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_US2    ((unsigned int)  8) // USART 2
-#define AT91C_ID_US3    ((unsigned int)  9) // USART 3
-#define AT91C_ID_MCI    ((unsigned int) 10) // Multimedia Card Interface
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TWI    ((unsigned int) 12) // Two-Wire Interface
-#define AT91C_ID_SPI    ((unsigned int) 13) // Serial Peripheral Interface
-#define AT91C_ID_SSC0   ((unsigned int) 14) // Serial Synchronous Controller 0
-#define AT91C_ID_SSC1   ((unsigned int) 15) // Serial Synchronous Controller 1
-#define AT91C_ID_SSC2   ((unsigned int) 16) // Serial Synchronous Controller 2
-#define AT91C_ID_TC0    ((unsigned int) 17) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 18) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 19) // Timer Counter 2
-#define AT91C_ID_TC3    ((unsigned int) 20) // Timer Counter 3
-#define AT91C_ID_TC4    ((unsigned int) 21) // Timer Counter 4
-#define AT91C_ID_TC5    ((unsigned int) 22) // Timer Counter 5
-#define AT91C_ID_UHP    ((unsigned int) 23) // USB Host port
-#define AT91C_ID_EMAC   ((unsigned int) 24) // Ethernet MAC
-#define AT91C_ID_IRQ0   ((unsigned int) 25) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 26) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ID_IRQ2   ((unsigned int) 27) // Advanced Interrupt Controller (IRQ2)
-#define AT91C_ID_IRQ3   ((unsigned int) 28) // Advanced Interrupt Controller (IRQ3)
-#define AT91C_ID_IRQ4   ((unsigned int) 29) // Advanced Interrupt Controller (IRQ4)
-#define AT91C_ID_IRQ5   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ5)
-#define AT91C_ID_IRQ6   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ6)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91RM9200
-// *****************************************************************************
-#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_RTC       ((AT91PS_RTC) 	0xFFFFFE00) // (RTC) Base Address
-#define AT91C_BASE_ST        ((AT91PS_ST) 	0xFFFFFD00) // (ST) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PIOD      ((AT91PS_PIO) 	0xFFFFFA00) // (PIOD) Base Address
-#define AT91C_BASE_PIOC      ((AT91PS_PIO) 	0xFFFFF800) // (PIOC) Base Address
-#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_SPI   ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI       ((AT91PS_SPI) 	0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_SSC2  ((AT91PS_PDC) 	0xFFFD8100) // (PDC_SSC2) Base Address
-#define AT91C_BASE_SSC2      ((AT91PS_SSC) 	0xFFFD8000) // (SSC2) Base Address
-#define AT91C_BASE_PDC_SSC1  ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC1) Base Address
-#define AT91C_BASE_SSC1      ((AT91PS_SSC) 	0xFFFD4000) // (SSC1) Base Address
-#define AT91C_BASE_PDC_SSC0  ((AT91PS_PDC) 	0xFFFD0100) // (PDC_SSC0) Base Address
-#define AT91C_BASE_SSC0      ((AT91PS_SSC) 	0xFFFD0000) // (SSC0) Base Address
-#define AT91C_BASE_PDC_US3   ((AT91PS_PDC) 	0xFFFCC100) // (PDC_US3) Base Address
-#define AT91C_BASE_US3       ((AT91PS_USART) 	0xFFFCC000) // (US3) Base Address
-#define AT91C_BASE_PDC_US2   ((AT91PS_PDC) 	0xFFFC8100) // (PDC_US2) Base Address
-#define AT91C_BASE_US2       ((AT91PS_USART) 	0xFFFC8000) // (US2) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PDC_MCI   ((AT91PS_PDC) 	0xFFFB4100) // (PDC_MCI) Base Address
-#define AT91C_BASE_MCI       ((AT91PS_MCI) 	0xFFFB4000) // (MCI) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC5       ((AT91PS_TC) 	0xFFFA4080) // (TC5) Base Address
-#define AT91C_BASE_TC4       ((AT91PS_TC) 	0xFFFA4040) // (TC4) Base Address
-#define AT91C_BASE_TC3       ((AT91PS_TC) 	0xFFFA4000) // (TC3) Base Address
-#define AT91C_BASE_TCB1      ((AT91PS_TCB) 	0xFFFA4080) // (TCB1) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TCB0      ((AT91PS_TCB) 	0xFFFA0000) // (TCB0) Base Address
-#define AT91C_BASE_UHP       ((AT91PS_UHP) 	0x00300000) // (UHP) Base Address
-#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFBC000) // (EMAC) Base Address
-#define AT91C_BASE_EBI       ((AT91PS_EBI) 	0xFFFFFF60) // (EBI) Base Address
-#define AT91C_BASE_SMC2      ((AT91PS_SMC2) 	0xFFFFFF70) // (SMC2) Base Address
-#define AT91C_BASE_SDRC      ((AT91PS_SDRC) 	0xFFFFFF90) // (SDRC) Base Address
-#define AT91C_BASE_BFC       ((AT91PS_BFC) 	0xFFFFFFC0) // (BFC) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91RM9200
-// *****************************************************************************
-#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)
-#define AT91C_IROM 	 ((char *) 	0x00100000) // Internal ROM base address
-#define AT91C_IROM_SIZE	 ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)
-
-#endif
diff --git a/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200.inc b/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200.inc
deleted file mode 100644
index 670e023..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200.inc
+++ /dev/null
@@ -1,2437 +0,0 @@
-;- ----------------------------------------------------------------------------
-;-          ATMEL Microcontroller Software Support  -  ROUSSET  -
-;- ----------------------------------------------------------------------------
-;-  The software is delivered "AS IS" without warranty or condition of any
-;-  kind, either express, implied or statutory. This includes without
-;-  limitation any warranty or condition with respect to merchantability or
-;-  fitness for any particular purpose, or against the infringements of
-;-  intellectual property rights of others.
-;- ----------------------------------------------------------------------------
-;- File Name           : AT91RM9200.h
-;- Object              : AT91RM9200 definitions
-;- Generated           : AT91 SW Application Group  11/19/2003 (17:20:51)
-;- 
-;- CVS Reference       : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003//
-;- CVS Reference       : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003//
-;- CVS Reference       : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002//
-;- CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//
-;- CVS Reference       : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
-;- CVS Reference       : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002//
-;- CVS Reference       : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003//
-;- CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//
-;- CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
-;- CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002//
-;- CVS Reference       : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002//
-;- CVS Reference       : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002//
-;- CVS Reference       : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002//
-;- CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002//
-;- CVS Reference       : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003//
-;- CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003//
-;- CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002//
-;- CVS Reference       : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002//
-;- CVS Reference       : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003//
-;- CVS Reference       : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003//
-;- CVS Reference       : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002//
-;- CVS Reference       : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002//
-;- CVS Reference       : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002//
-;- ----------------------------------------------------------------------------
-
-;- Hardware register definition
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR System Peripherals
-;- *****************************************************************************
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_MC
-MC_RCR          #  4 ;- MC Remap Control Register
-MC_ASR          #  4 ;- MC Abort Status Register
-MC_AASR         #  4 ;- MC Abort Address Status Register
-                #  4 ;- Reserved
-MC_PUIA         # 64 ;- MC Protection Unit Area
-MC_PUP          #  4 ;- MC Protection Unit Peripherals
-MC_PUER         #  4 ;- MC Protection Unit Enable Register
-;- -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-AT91C_MC_RCB              EQU (0x1:SHL:0) ;- (MC) Remap Command Bit
-;- -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-AT91C_MC_UNDADD           EQU (0x1:SHL:0) ;- (MC) Undefined Addess Abort Status
-AT91C_MC_MISADD           EQU (0x1:SHL:1) ;- (MC) Misaligned Addess Abort Status
-AT91C_MC_MPU              EQU (0x1:SHL:2) ;- (MC) Memory protection Unit Abort Status
-AT91C_MC_ABTSZ            EQU (0x3:SHL:8) ;- (MC) Abort Size Status
-AT91C_MC_ABTSZ_BYTE       EQU (0x0:SHL:8) ;- (MC) Byte
-AT91C_MC_ABTSZ_HWORD      EQU (0x1:SHL:8) ;- (MC) Half-word
-AT91C_MC_ABTSZ_WORD       EQU (0x2:SHL:8) ;- (MC) Word
-AT91C_MC_ABTTYP           EQU (0x3:SHL:10) ;- (MC) Abort Type Status
-AT91C_MC_ABTTYP_DATAR     EQU (0x0:SHL:10) ;- (MC) Data Read
-AT91C_MC_ABTTYP_DATAW     EQU (0x1:SHL:10) ;- (MC) Data Write
-AT91C_MC_ABTTYP_FETCH     EQU (0x2:SHL:10) ;- (MC) Code Fetch
-AT91C_MC_MST0             EQU (0x1:SHL:16) ;- (MC) Master 0 Abort Source
-AT91C_MC_MST1             EQU (0x1:SHL:17) ;- (MC) Master 1 Abort Source
-AT91C_MC_SVMST0           EQU (0x1:SHL:24) ;- (MC) Saved Master 0 Abort Source
-AT91C_MC_SVMST1           EQU (0x1:SHL:25) ;- (MC) Saved Master 1 Abort Source
-;- -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- 
-AT91C_MC_PROT             EQU (0x3:SHL:0) ;- (MC) Protection
-AT91C_MC_PROT_PNAUNA      EQU (0x0) ;- (MC) Privilege: No Access, User: No Access
-AT91C_MC_PROT_PRWUNA      EQU (0x1) ;- (MC) Privilege: Read/Write, User: No Access
-AT91C_MC_PROT_PRWURO      EQU (0x2) ;- (MC) Privilege: Read/Write, User: Read Only
-AT91C_MC_PROT_PRWURW      EQU (0x3) ;- (MC) Privilege: Read/Write, User: Read/Write
-AT91C_MC_SIZE             EQU (0xF:SHL:4) ;- (MC) Internal Area Size
-AT91C_MC_SIZE_1KB         EQU (0x0:SHL:4) ;- (MC) Area size 1KByte
-AT91C_MC_SIZE_2KB         EQU (0x1:SHL:4) ;- (MC) Area size 2KByte
-AT91C_MC_SIZE_4KB         EQU (0x2:SHL:4) ;- (MC) Area size 4KByte
-AT91C_MC_SIZE_8KB         EQU (0x3:SHL:4) ;- (MC) Area size 8KByte
-AT91C_MC_SIZE_16KB        EQU (0x4:SHL:4) ;- (MC) Area size 16KByte
-AT91C_MC_SIZE_32KB        EQU (0x5:SHL:4) ;- (MC) Area size 32KByte
-AT91C_MC_SIZE_64KB        EQU (0x6:SHL:4) ;- (MC) Area size 64KByte
-AT91C_MC_SIZE_128KB       EQU (0x7:SHL:4) ;- (MC) Area size 128KByte
-AT91C_MC_SIZE_256KB       EQU (0x8:SHL:4) ;- (MC) Area size 256KByte
-AT91C_MC_SIZE_512KB       EQU (0x9:SHL:4) ;- (MC) Area size 512KByte
-AT91C_MC_SIZE_1MB         EQU (0xA:SHL:4) ;- (MC) Area size 1MByte
-AT91C_MC_SIZE_2MB         EQU (0xB:SHL:4) ;- (MC) Area size 2MByte
-AT91C_MC_SIZE_4MB         EQU (0xC:SHL:4) ;- (MC) Area size 4MByte
-AT91C_MC_SIZE_8MB         EQU (0xD:SHL:4) ;- (MC) Area size 8MByte
-AT91C_MC_SIZE_16MB        EQU (0xE:SHL:4) ;- (MC) Area size 16MByte
-AT91C_MC_SIZE_64MB        EQU (0xF:SHL:4) ;- (MC) Area size 64MByte
-AT91C_MC_BA               EQU (0x3FFFF:SHL:10) ;- (MC) Internal Area Base Address
-;- -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- 
-;- -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- 
-AT91C_MC_PUEB             EQU (0x1:SHL:0) ;- (MC) Protection Unit enable Bit
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm and Parallel Load Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_RTC
-RTC_CR          #  4 ;- Control Register
-RTC_MR          #  4 ;- Mode Register
-RTC_TIMR        #  4 ;- Time Register
-RTC_CALR        #  4 ;- Calendar Register
-RTC_TIMALR      #  4 ;- Time Alarm Register
-RTC_CALALR      #  4 ;- Calendar Alarm Register
-RTC_SR          #  4 ;- Status Register
-RTC_SCCR        #  4 ;- Status Clear Command Register
-RTC_IER         #  4 ;- Interrupt Enable Register
-RTC_IDR         #  4 ;- Interrupt Disable Register
-RTC_IMR         #  4 ;- Interrupt Mask Register
-RTC_VER         #  4 ;- Valid Entry Register
-;- -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- 
-AT91C_RTC_UPDTIM          EQU (0x1:SHL:0) ;- (RTC) Update Request Time Register
-AT91C_RTC_UPDCAL          EQU (0x1:SHL:1) ;- (RTC) Update Request Calendar Register
-AT91C_RTC_TIMEVSEL        EQU (0x3:SHL:8) ;- (RTC) Time Event Selection
-AT91C_RTC_TIMEVSEL_MINUTE EQU (0x0:SHL:8) ;- (RTC) Minute change.
-AT91C_RTC_TIMEVSEL_HOUR   EQU (0x1:SHL:8) ;- (RTC) Hour change.
-AT91C_RTC_TIMEVSEL_DAY24  EQU (0x2:SHL:8) ;- (RTC) Every day at midnight.
-AT91C_RTC_TIMEVSEL_DAY12  EQU (0x3:SHL:8) ;- (RTC) Every day at noon.
-AT91C_RTC_CALEVSEL        EQU (0x3:SHL:16) ;- (RTC) Calendar Event Selection
-AT91C_RTC_CALEVSEL_WEEK   EQU (0x0:SHL:16) ;- (RTC) Week change (every Monday at time 00:00:00).
-AT91C_RTC_CALEVSEL_MONTH  EQU (0x1:SHL:16) ;- (RTC) Month change (every 01 of each month at time 00:00:00).
-AT91C_RTC_CALEVSEL_YEAR   EQU (0x2:SHL:16) ;- (RTC) Year change (every January 1 at time 00:00:00).
-;- -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- 
-AT91C_RTC_HRMOD           EQU (0x1:SHL:0) ;- (RTC) 12-24 hour Mode
-;- -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- 
-AT91C_RTC_SEC             EQU (0x7F:SHL:0) ;- (RTC) Current Second
-AT91C_RTC_MIN             EQU (0x7F:SHL:8) ;- (RTC) Current Minute
-AT91C_RTC_HOUR            EQU (0x1F:SHL:16) ;- (RTC) Current Hour
-AT91C_RTC_AMPM            EQU (0x1:SHL:22) ;- (RTC) Ante Meridiem, Post Meridiem Indicator
-;- -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- 
-AT91C_RTC_CENT            EQU (0x3F:SHL:0) ;- (RTC) Current Century
-AT91C_RTC_YEAR            EQU (0xFF:SHL:8) ;- (RTC) Current Year
-AT91C_RTC_MONTH           EQU (0x1F:SHL:16) ;- (RTC) Current Month
-AT91C_RTC_DAY             EQU (0x7:SHL:21) ;- (RTC) Current Day
-AT91C_RTC_DATE            EQU (0x3F:SHL:24) ;- (RTC) Current Date
-;- -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- 
-AT91C_RTC_SECEN           EQU (0x1:SHL:7) ;- (RTC) Second Alarm Enable
-AT91C_RTC_MINEN           EQU (0x1:SHL:15) ;- (RTC) Minute Alarm
-AT91C_RTC_HOUREN          EQU (0x1:SHL:23) ;- (RTC) Current Hour
-;- -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- 
-AT91C_RTC_MONTHEN         EQU (0x1:SHL:23) ;- (RTC) Month Alarm Enable
-AT91C_RTC_DATEEN          EQU (0x1:SHL:31) ;- (RTC) Date Alarm Enable
-;- -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- 
-AT91C_RTC_ACKUPD          EQU (0x1:SHL:0) ;- (RTC) Acknowledge for Update
-AT91C_RTC_ALARM           EQU (0x1:SHL:1) ;- (RTC) Alarm Flag
-AT91C_RTC_SECEV           EQU (0x1:SHL:2) ;- (RTC) Second Event
-AT91C_RTC_TIMEV           EQU (0x1:SHL:3) ;- (RTC) Time Event
-AT91C_RTC_CALEV           EQU (0x1:SHL:4) ;- (RTC) Calendar event
-;- -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- 
-;- -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- 
-;- -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- 
-;- -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- 
-;- -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- 
-AT91C_RTC_NVTIM           EQU (0x1:SHL:0) ;- (RTC) Non valid Time
-AT91C_RTC_NVCAL           EQU (0x1:SHL:1) ;- (RTC) Non valid Calendar
-AT91C_RTC_NVTIMALR        EQU (0x1:SHL:2) ;- (RTC) Non valid time Alarm
-AT91C_RTC_NVCALALR        EQU (0x1:SHL:3) ;- (RTC) Nonvalid Calendar Alarm
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR System Timer Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_ST
-ST_CR           #  4 ;- Control Register
-ST_PIMR         #  4 ;- Period Interval Mode Register
-ST_WDMR         #  4 ;- Watchdog Mode Register
-ST_RTMR         #  4 ;- Real-time Mode Register
-ST_SR           #  4 ;- Status Register
-ST_IER          #  4 ;- Interrupt Enable Register
-ST_IDR          #  4 ;- Interrupt Disable Register
-ST_IMR          #  4 ;- Interrupt Mask Register
-ST_RTAR         #  4 ;- Real-time Alarm Register
-ST_CRTR         #  4 ;- Current Real-time Register
-;- -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- 
-AT91C_ST_WDRST            EQU (0x1:SHL:0) ;- (ST) Watchdog Timer Restart
-;- -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- 
-AT91C_ST_PIV              EQU (0xFFFF:SHL:0) ;- (ST) Watchdog Timer Restart
-;- -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- 
-AT91C_ST_WDV              EQU (0xFFFF:SHL:0) ;- (ST) Watchdog Timer Restart
-AT91C_ST_RSTEN            EQU (0x1:SHL:16) ;- (ST) Reset Enable
-AT91C_ST_EXTEN            EQU (0x1:SHL:17) ;- (ST) External Signal Assertion Enable
-;- -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- 
-AT91C_ST_RTPRES           EQU (0xFFFF:SHL:0) ;- (ST) Real-time Timer Prescaler Value
-;- -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- 
-AT91C_ST_PITS             EQU (0x1:SHL:0) ;- (ST) Period Interval Timer Interrupt
-AT91C_ST_WDOVF            EQU (0x1:SHL:1) ;- (ST) Watchdog Overflow
-AT91C_ST_RTTINC           EQU (0x1:SHL:2) ;- (ST) Real-time Timer Increment
-AT91C_ST_ALMS             EQU (0x1:SHL:3) ;- (ST) Alarm Status
-;- -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- 
-;- -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- 
-;- -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- 
-;- -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- 
-AT91C_ST_ALMV             EQU (0xFFFFF:SHL:0) ;- (ST) Alarm Value Value
-;- -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- 
-AT91C_ST_CRTV             EQU (0xFFFFF:SHL:0) ;- (ST) Current Real-time Value
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Power Management Controler
-;- *****************************************************************************
-                ^ 0 ;- AT91S_PMC
-PMC_SCER        #  4 ;- System Clock Enable Register
-PMC_SCDR        #  4 ;- System Clock Disable Register
-PMC_SCSR        #  4 ;- System Clock Status Register
-                #  4 ;- Reserved
-PMC_PCER        #  4 ;- Peripheral Clock Enable Register
-PMC_PCDR        #  4 ;- Peripheral Clock Disable Register
-PMC_PCSR        #  4 ;- Peripheral Clock Status Register
-                # 20 ;- Reserved
-PMC_MCKR        #  4 ;- Master Clock Register
-                # 12 ;- Reserved
-PMC_PCKR        # 32 ;- Programmable Clock Register
-PMC_IER         #  4 ;- Interrupt Enable Register
-PMC_IDR         #  4 ;- Interrupt Disable Register
-PMC_SR          #  4 ;- Status Register
-PMC_IMR         #  4 ;- Interrupt Mask Register
-;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-AT91C_PMC_PCK             EQU (0x1:SHL:0) ;- (PMC) Processor Clock
-AT91C_PMC_UDP             EQU (0x1:SHL:1) ;- (PMC) USB Device Port Clock
-AT91C_PMC_MCKUDP          EQU (0x1:SHL:2) ;- (PMC) USB Device Port Master Clock Automatic Disable on Suspend
-AT91C_PMC_UHP             EQU (0x1:SHL:4) ;- (PMC) USB Host Port Clock
-AT91C_PMC_PCK0            EQU (0x1:SHL:8) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK1            EQU (0x1:SHL:9) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK2            EQU (0x1:SHL:10) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK3            EQU (0x1:SHL:11) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK4            EQU (0x1:SHL:12) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK5            EQU (0x1:SHL:13) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK6            EQU (0x1:SHL:14) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK7            EQU (0x1:SHL:15) ;- (PMC) Programmable Clock Output
-;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-AT91C_PMC_CSS             EQU (0x3:SHL:0) ;- (PMC) Programmable Clock Selection
-AT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected
-AT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected
-AT91C_PMC_CSS_PLLA_CLK    EQU (0x2) ;- (PMC) Clock from PLL A is selected
-AT91C_PMC_CSS_PLLB_CLK    EQU (0x3) ;- (PMC) Clock from PLL B is selected
-AT91C_PMC_PRES            EQU (0x7:SHL:2) ;- (PMC) Programmable Clock Prescaler
-AT91C_PMC_PRES_CLK        EQU (0x0:SHL:2) ;- (PMC) Selected clock
-AT91C_PMC_PRES_CLK_2      EQU (0x1:SHL:2) ;- (PMC) Selected clock divided by 2
-AT91C_PMC_PRES_CLK_4      EQU (0x2:SHL:2) ;- (PMC) Selected clock divided by 4
-AT91C_PMC_PRES_CLK_8      EQU (0x3:SHL:2) ;- (PMC) Selected clock divided by 8
-AT91C_PMC_PRES_CLK_16     EQU (0x4:SHL:2) ;- (PMC) Selected clock divided by 16
-AT91C_PMC_PRES_CLK_32     EQU (0x5:SHL:2) ;- (PMC) Selected clock divided by 32
-AT91C_PMC_PRES_CLK_64     EQU (0x6:SHL:2) ;- (PMC) Selected clock divided by 64
-AT91C_PMC_MDIV            EQU (0x3:SHL:8) ;- (PMC) Master Clock Division
-AT91C_PMC_MDIV_1          EQU (0x0:SHL:8) ;- (PMC) The master clock and the processor clock are the same
-AT91C_PMC_MDIV_2          EQU (0x1:SHL:8) ;- (PMC) The processor clock is twice as fast as the master clock
-AT91C_PMC_MDIV_3          EQU (0x2:SHL:8) ;- (PMC) The processor clock is three times faster than the master clock
-AT91C_PMC_MDIV_4          EQU (0x3:SHL:8) ;- (PMC) The processor clock is four times faster than the master clock
-;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-AT91C_PMC_MOSCS           EQU (0x1:SHL:0) ;- (PMC) MOSC Status/Enable/Disable/Mask
-AT91C_PMC_LOCKA           EQU (0x1:SHL:1) ;- (PMC) PLL A Status/Enable/Disable/Mask
-AT91C_PMC_LOCKB           EQU (0x1:SHL:2) ;- (PMC) PLL B Status/Enable/Disable/Mask
-AT91C_PMC_MCKRDY          EQU (0x1:SHL:3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK0RDY         EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK1RDY         EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK2RDY         EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK3RDY         EQU (0x1:SHL:11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK4RDY         EQU (0x1:SHL:12) ;- (PMC) PCK4_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK5RDY         EQU (0x1:SHL:13) ;- (PMC) PCK5_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK6RDY         EQU (0x1:SHL:14) ;- (PMC) PCK6_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK7RDY         EQU (0x1:SHL:15) ;- (PMC) PCK7_RDY Status/Enable/Disable/Mask
-;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-;- *****************************************************************************
-                ^ 0 ;- AT91S_CKGR
-CKGR_MOR        #  4 ;- Main Oscillator Register
-CKGR_MCFR       #  4 ;- Main Clock  Frequency Register
-CKGR_PLLAR      #  4 ;- PLL A Register
-CKGR_PLLBR      #  4 ;- PLL B Register
-;- -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-AT91C_CKGR_MOSCEN         EQU (0x1:SHL:0) ;- (CKGR) Main Oscillator Enable
-AT91C_CKGR_OSCTEST        EQU (0x1:SHL:1) ;- (CKGR) Oscillator Test
-AT91C_CKGR_OSCOUNT        EQU (0xFF:SHL:8) ;- (CKGR) Main Oscillator Start-up Time
-;- -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-AT91C_CKGR_MAINF          EQU (0xFFFF:SHL:0) ;- (CKGR) Main Clock Frequency
-AT91C_CKGR_MAINRDY        EQU (0x1:SHL:16) ;- (CKGR) Main Clock Ready
-;- -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- 
-AT91C_CKGR_DIVA           EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected
-AT91C_CKGR_DIVA_0         EQU (0x0) ;- (CKGR) Divider output is 0
-AT91C_CKGR_DIVA_BYPASS    EQU (0x1) ;- (CKGR) Divider is bypassed
-AT91C_CKGR_PLLACOUNT      EQU (0x3F:SHL:8) ;- (CKGR) PLL A Counter
-AT91C_CKGR_OUTA           EQU (0x3:SHL:14) ;- (CKGR) PLL A Output Frequency Range
-AT91C_CKGR_OUTA_0         EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet
-AT91C_CKGR_OUTA_1         EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet
-AT91C_CKGR_OUTA_2         EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet
-AT91C_CKGR_OUTA_3         EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet
-AT91C_CKGR_MULA           EQU (0x7FF:SHL:16) ;- (CKGR) PLL A Multiplier
-AT91C_CKGR_SRCA           EQU (0x1:SHL:29) ;- (CKGR) PLL A Source
-;- -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- 
-AT91C_CKGR_DIVB           EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected
-AT91C_CKGR_DIVB_0         EQU (0x0) ;- (CKGR) Divider output is 0
-AT91C_CKGR_DIVB_BYPASS    EQU (0x1) ;- (CKGR) Divider is bypassed
-AT91C_CKGR_PLLBCOUNT      EQU (0x3F:SHL:8) ;- (CKGR) PLL B Counter
-AT91C_CKGR_OUTB           EQU (0x3:SHL:14) ;- (CKGR) PLL B Output Frequency Range
-AT91C_CKGR_OUTB_0         EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet
-AT91C_CKGR_OUTB_1         EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet
-AT91C_CKGR_OUTB_2         EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet
-AT91C_CKGR_OUTB_3         EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet
-AT91C_CKGR_MULB           EQU (0x7FF:SHL:16) ;- (CKGR) PLL B Multiplier
-AT91C_CKGR_USB_96M        EQU (0x1:SHL:28) ;- (CKGR) Divider for USB Ports
-AT91C_CKGR_USB_PLL        EQU (0x1:SHL:29) ;- (CKGR) PLL Use
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-;- *****************************************************************************
-                ^ 0 ;- AT91S_PIO
-PIO_PER         #  4 ;- PIO Enable Register
-PIO_PDR         #  4 ;- PIO Disable Register
-PIO_PSR         #  4 ;- PIO Status Register
-                #  4 ;- Reserved
-PIO_OER         #  4 ;- Output Enable Register
-PIO_ODR         #  4 ;- Output Disable Registerr
-PIO_OSR         #  4 ;- Output Status Register
-                #  4 ;- Reserved
-PIO_IFER        #  4 ;- Input Filter Enable Register
-PIO_IFDR        #  4 ;- Input Filter Disable Register
-PIO_IFSR        #  4 ;- Input Filter Status Register
-                #  4 ;- Reserved
-PIO_SODR        #  4 ;- Set Output Data Register
-PIO_CODR        #  4 ;- Clear Output Data Register
-PIO_ODSR        #  4 ;- Output Data Status Register
-PIO_PDSR        #  4 ;- Pin Data Status Register
-PIO_IER         #  4 ;- Interrupt Enable Register
-PIO_IDR         #  4 ;- Interrupt Disable Register
-PIO_IMR         #  4 ;- Interrupt Mask Register
-PIO_ISR         #  4 ;- Interrupt Status Register
-PIO_MDER        #  4 ;- Multi-driver Enable Register
-PIO_MDDR        #  4 ;- Multi-driver Disable Register
-PIO_MDSR        #  4 ;- Multi-driver Status Register
-                #  4 ;- Reserved
-PIO_PPUDR       #  4 ;- Pull-up Disable Register
-PIO_PPUER       #  4 ;- Pull-up Enable Register
-PIO_PPUSR       #  4 ;- Pad Pull-up Status Register
-                #  4 ;- Reserved
-PIO_ASR         #  4 ;- Select A Register
-PIO_BSR         #  4 ;- Select B Register
-PIO_ABSR        #  4 ;- AB Select Status Register
-                # 36 ;- Reserved
-PIO_OWER        #  4 ;- Output Write Enable Register
-PIO_OWDR        #  4 ;- Output Write Disable Register
-PIO_OWSR        #  4 ;- Output Write Status Register
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Debug Unit
-;- *****************************************************************************
-                ^ 0 ;- AT91S_DBGU
-DBGU_CR         #  4 ;- Control Register
-DBGU_MR         #  4 ;- Mode Register
-DBGU_IER        #  4 ;- Interrupt Enable Register
-DBGU_IDR        #  4 ;- Interrupt Disable Register
-DBGU_IMR        #  4 ;- Interrupt Mask Register
-DBGU_CSR        #  4 ;- Channel Status Register
-DBGU_RHR        #  4 ;- Receiver Holding Register
-DBGU_THR        #  4 ;- Transmitter Holding Register
-DBGU_BRGR       #  4 ;- Baud Rate Generator Register
-                # 28 ;- Reserved
-DBGU_C1R        #  4 ;- Chip ID1 Register
-DBGU_C2R        #  4 ;- Chip ID2 Register
-DBGU_FNTR       #  4 ;- Force NTRST Register
-                # 180 ;- Reserved
-DBGU_RPR        #  4 ;- Receive Pointer Register
-DBGU_RCR        #  4 ;- Receive Counter Register
-DBGU_TPR        #  4 ;- Transmit Pointer Register
-DBGU_TCR        #  4 ;- Transmit Counter Register
-DBGU_RNPR       #  4 ;- Receive Next Pointer Register
-DBGU_RNCR       #  4 ;- Receive Next Counter Register
-DBGU_TNPR       #  4 ;- Transmit Next Pointer Register
-DBGU_TNCR       #  4 ;- Transmit Next Counter Register
-DBGU_PTCR       #  4 ;- PDC Transfer Control Register
-DBGU_PTSR       #  4 ;- PDC Transfer Status Register
-;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-AT91C_US_RSTRX            EQU (0x1:SHL:2) ;- (DBGU) Reset Receiver
-AT91C_US_RSTTX            EQU (0x1:SHL:3) ;- (DBGU) Reset Transmitter
-AT91C_US_RXEN             EQU (0x1:SHL:4) ;- (DBGU) Receiver Enable
-AT91C_US_RXDIS            EQU (0x1:SHL:5) ;- (DBGU) Receiver Disable
-AT91C_US_TXEN             EQU (0x1:SHL:6) ;- (DBGU) Transmitter Enable
-AT91C_US_TXDIS            EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable
-;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-AT91C_US_PAR              EQU (0x7:SHL:9) ;- (DBGU) Parity type
-AT91C_US_PAR_EVEN         EQU (0x0:SHL:9) ;- (DBGU) Even Parity
-AT91C_US_PAR_ODD          EQU (0x1:SHL:9) ;- (DBGU) Odd Parity
-AT91C_US_PAR_SPACE        EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space)
-AT91C_US_PAR_MARK         EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark)
-AT91C_US_PAR_NONE         EQU (0x4:SHL:9) ;- (DBGU) No Parity
-AT91C_US_PAR_MULTI_DROP   EQU (0x6:SHL:9) ;- (DBGU) Multi-drop mode
-AT91C_US_CHMODE           EQU (0x3:SHL:14) ;- (DBGU) Channel Mode
-AT91C_US_CHMODE_NORMAL    EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-AT91C_US_CHMODE_AUTO      EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-AT91C_US_CHMODE_LOCAL     EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-AT91C_US_CHMODE_REMOTE    EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-AT91C_US_RXRDY            EQU (0x1:SHL:0) ;- (DBGU) RXRDY Interrupt
-AT91C_US_TXRDY            EQU (0x1:SHL:1) ;- (DBGU) TXRDY Interrupt
-AT91C_US_ENDRX            EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer Interrupt
-AT91C_US_ENDTX            EQU (0x1:SHL:4) ;- (DBGU) End of Transmit Interrupt
-AT91C_US_OVRE             EQU (0x1:SHL:5) ;- (DBGU) Overrun Interrupt
-AT91C_US_FRAME            EQU (0x1:SHL:6) ;- (DBGU) Framing Error Interrupt
-AT91C_US_PARE             EQU (0x1:SHL:7) ;- (DBGU) Parity Error Interrupt
-AT91C_US_TXEMPTY          EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY Interrupt
-AT91C_US_TXBUFE           EQU (0x1:SHL:11) ;- (DBGU) TXBUFE Interrupt
-AT91C_US_RXBUFF           EQU (0x1:SHL:12) ;- (DBGU) RXBUFF Interrupt
-AT91C_US_COMM_TX          EQU (0x1:SHL:30) ;- (DBGU) COMM_TX Interrupt
-AT91C_US_COMM_RX          EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt
-;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-AT91C_US_FORCE_NTRST      EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
-;- *****************************************************************************
-                ^ 0 ;- AT91S_PDC
-PDC_RPR         #  4 ;- Receive Pointer Register
-PDC_RCR         #  4 ;- Receive Counter Register
-PDC_TPR         #  4 ;- Transmit Pointer Register
-PDC_TCR         #  4 ;- Transmit Counter Register
-PDC_RNPR        #  4 ;- Receive Next Pointer Register
-PDC_RNCR        #  4 ;- Receive Next Counter Register
-PDC_TNPR        #  4 ;- Transmit Next Pointer Register
-PDC_TNCR        #  4 ;- Transmit Next Counter Register
-PDC_PTCR        #  4 ;- PDC Transfer Control Register
-PDC_PTSR        #  4 ;- PDC Transfer Status Register
-;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-AT91C_PDC_RXTEN           EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer Enable
-AT91C_PDC_RXTDIS          EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer Disable
-AT91C_PDC_TXTEN           EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer Enable
-AT91C_PDC_TXTDIS          EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable
-;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-;- *****************************************************************************
-                ^ 0 ;- AT91S_AIC
-AIC_SMR         # 128 ;- Source Mode Register
-AIC_SVR         # 128 ;- Source Vector Register
-AIC_IVR         #  4 ;- IRQ Vector Register
-AIC_FVR         #  4 ;- FIQ Vector Register
-AIC_ISR         #  4 ;- Interrupt Status Register
-AIC_IPR         #  4 ;- Interrupt Pending Register
-AIC_IMR         #  4 ;- Interrupt Mask Register
-AIC_CISR        #  4 ;- Core Interrupt Status Register
-                #  8 ;- Reserved
-AIC_IECR        #  4 ;- Interrupt Enable Command Register
-AIC_IDCR        #  4 ;- Interrupt Disable Command Register
-AIC_ICCR        #  4 ;- Interrupt Clear Command Register
-AIC_ISCR        #  4 ;- Interrupt Set Command Register
-AIC_EOICR       #  4 ;- End of Interrupt Command Register
-AIC_SPU         #  4 ;- Spurious Vector Register
-AIC_DCR         #  4 ;- Debug Control Register (Protect)
-                #  4 ;- Reserved
-AIC_FFER        #  4 ;- Fast Forcing Enable Register
-AIC_FFDR        #  4 ;- Fast Forcing Disable Register
-AIC_FFSR        #  4 ;- Fast Forcing Status Register
-;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-AT91C_AIC_PRIOR           EQU (0x7:SHL:0) ;- (AIC) Priority Level
-AT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level
-AT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level
-AT91C_AIC_SRCTYPE         EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type
-AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label Level Sensitive
-AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Edge triggered
-AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) External Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) External Sources Code Label Positive Edge triggered
-;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-AT91C_AIC_NFIQ            EQU (0x1:SHL:0) ;- (AIC) NFIQ Status
-AT91C_AIC_NIRQ            EQU (0x1:SHL:1) ;- (AIC) NIRQ Status
-;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-AT91C_AIC_DCR_PROT        EQU (0x1:SHL:0) ;- (AIC) Protection Mode
-AT91C_AIC_DCR_GMSK        EQU (0x1:SHL:1) ;- (AIC) General Mask
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_SPI
-SPI_CR          #  4 ;- Control Register
-SPI_MR          #  4 ;- Mode Register
-SPI_RDR         #  4 ;- Receive Data Register
-SPI_TDR         #  4 ;- Transmit Data Register
-SPI_SR          #  4 ;- Status Register
-SPI_IER         #  4 ;- Interrupt Enable Register
-SPI_IDR         #  4 ;- Interrupt Disable Register
-SPI_IMR         #  4 ;- Interrupt Mask Register
-                # 16 ;- Reserved
-SPI_CSR         # 16 ;- Chip Select Register
-                # 192 ;- Reserved
-SPI_RPR         #  4 ;- Receive Pointer Register
-SPI_RCR         #  4 ;- Receive Counter Register
-SPI_TPR         #  4 ;- Transmit Pointer Register
-SPI_TCR         #  4 ;- Transmit Counter Register
-SPI_RNPR        #  4 ;- Receive Next Pointer Register
-SPI_RNCR        #  4 ;- Receive Next Counter Register
-SPI_TNPR        #  4 ;- Transmit Next Pointer Register
-SPI_TNCR        #  4 ;- Transmit Next Counter Register
-SPI_PTCR        #  4 ;- PDC Transfer Control Register
-SPI_PTSR        #  4 ;- PDC Transfer Status Register
-;- -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-AT91C_SPI_SPIEN           EQU (0x1:SHL:0) ;- (SPI) SPI Enable
-AT91C_SPI_SPIDIS          EQU (0x1:SHL:1) ;- (SPI) SPI Disable
-AT91C_SPI_SWRST           EQU (0x1:SHL:7) ;- (SPI) SPI Software reset
-;- -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-AT91C_SPI_MSTR            EQU (0x1:SHL:0) ;- (SPI) Master/Slave Mode
-AT91C_SPI_PS              EQU (0x1:SHL:1) ;- (SPI) Peripheral Select
-AT91C_SPI_PS_FIXED        EQU (0x0:SHL:1) ;- (SPI) Fixed Peripheral Select
-AT91C_SPI_PS_VARIABLE     EQU (0x1:SHL:1) ;- (SPI) Variable Peripheral Select
-AT91C_SPI_PCSDEC          EQU (0x1:SHL:2) ;- (SPI) Chip Select Decode
-AT91C_SPI_DIV32           EQU (0x1:SHL:3) ;- (SPI) Clock Selection
-AT91C_SPI_MODFDIS         EQU (0x1:SHL:4) ;- (SPI) Mode Fault Detection
-AT91C_SPI_LLB             EQU (0x1:SHL:7) ;- (SPI) Clock Selection
-AT91C_SPI_PCS             EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select
-AT91C_SPI_DLYBCS          EQU (0xFF:SHL:24) ;- (SPI) Delay Between Chip Selects
-;- -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-AT91C_SPI_RD              EQU (0xFFFF:SHL:0) ;- (SPI) Receive Data
-AT91C_SPI_RPCS            EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status
-;- -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-AT91C_SPI_TD              EQU (0xFFFF:SHL:0) ;- (SPI) Transmit Data
-AT91C_SPI_TPCS            EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status
-;- -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-AT91C_SPI_RDRF            EQU (0x1:SHL:0) ;- (SPI) Receive Data Register Full
-AT91C_SPI_TDRE            EQU (0x1:SHL:1) ;- (SPI) Transmit Data Register Empty
-AT91C_SPI_MODF            EQU (0x1:SHL:2) ;- (SPI) Mode Fault Error
-AT91C_SPI_OVRES           EQU (0x1:SHL:3) ;- (SPI) Overrun Error Status
-AT91C_SPI_SPENDRX         EQU (0x1:SHL:4) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_SPENDTX         EQU (0x1:SHL:5) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_RXBUFF          EQU (0x1:SHL:6) ;- (SPI) RXBUFF Interrupt
-AT91C_SPI_TXBUFE          EQU (0x1:SHL:7) ;- (SPI) TXBUFE Interrupt
-AT91C_SPI_SPIENS          EQU (0x1:SHL:16) ;- (SPI) Enable Status
-;- -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-;- -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-;- -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-;- -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-AT91C_SPI_CPOL            EQU (0x1:SHL:0) ;- (SPI) Clock Polarity
-AT91C_SPI_NCPHA           EQU (0x1:SHL:1) ;- (SPI) Clock Phase
-AT91C_SPI_BITS            EQU (0xF:SHL:4) ;- (SPI) Bits Per Transfer
-AT91C_SPI_BITS_8          EQU (0x0:SHL:4) ;- (SPI) 8 Bits Per transfer
-AT91C_SPI_BITS_9          EQU (0x1:SHL:4) ;- (SPI) 9 Bits Per transfer
-AT91C_SPI_BITS_10         EQU (0x2:SHL:4) ;- (SPI) 10 Bits Per transfer
-AT91C_SPI_BITS_11         EQU (0x3:SHL:4) ;- (SPI) 11 Bits Per transfer
-AT91C_SPI_BITS_12         EQU (0x4:SHL:4) ;- (SPI) 12 Bits Per transfer
-AT91C_SPI_BITS_13         EQU (0x5:SHL:4) ;- (SPI) 13 Bits Per transfer
-AT91C_SPI_BITS_14         EQU (0x6:SHL:4) ;- (SPI) 14 Bits Per transfer
-AT91C_SPI_BITS_15         EQU (0x7:SHL:4) ;- (SPI) 15 Bits Per transfer
-AT91C_SPI_BITS_16         EQU (0x8:SHL:4) ;- (SPI) 16 Bits Per transfer
-AT91C_SPI_SCBR            EQU (0xFF:SHL:8) ;- (SPI) Serial Clock Baud Rate
-AT91C_SPI_DLYBS           EQU (0xFF:SHL:16) ;- (SPI) Serial Clock Baud Rate
-AT91C_SPI_DLYBCT          EQU (0xFF:SHL:24) ;- (SPI) Delay Between Consecutive Transfers
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_SSC
-SSC_CR          #  4 ;- Control Register
-SSC_CMR         #  4 ;- Clock Mode Register
-                #  8 ;- Reserved
-SSC_RCMR        #  4 ;- Receive Clock ModeRegister
-SSC_RFMR        #  4 ;- Receive Frame Mode Register
-SSC_TCMR        #  4 ;- Transmit Clock Mode Register
-SSC_TFMR        #  4 ;- Transmit Frame Mode Register
-SSC_RHR         #  4 ;- Receive Holding Register
-SSC_THR         #  4 ;- Transmit Holding Register
-                #  8 ;- Reserved
-SSC_RSHR        #  4 ;- Receive Sync Holding Register
-SSC_TSHR        #  4 ;- Transmit Sync Holding Register
-SSC_RC0R        #  4 ;- Receive Compare 0 Register
-SSC_RC1R        #  4 ;- Receive Compare 1 Register
-SSC_SR          #  4 ;- Status Register
-SSC_IER         #  4 ;- Interrupt Enable Register
-SSC_IDR         #  4 ;- Interrupt Disable Register
-SSC_IMR         #  4 ;- Interrupt Mask Register
-                # 176 ;- Reserved
-SSC_RPR         #  4 ;- Receive Pointer Register
-SSC_RCR         #  4 ;- Receive Counter Register
-SSC_TPR         #  4 ;- Transmit Pointer Register
-SSC_TCR         #  4 ;- Transmit Counter Register
-SSC_RNPR        #  4 ;- Receive Next Pointer Register
-SSC_RNCR        #  4 ;- Receive Next Counter Register
-SSC_TNPR        #  4 ;- Transmit Next Pointer Register
-SSC_TNCR        #  4 ;- Transmit Next Counter Register
-SSC_PTCR        #  4 ;- PDC Transfer Control Register
-SSC_PTSR        #  4 ;- PDC Transfer Status Register
-;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-AT91C_SSC_RXEN            EQU (0x1:SHL:0) ;- (SSC) Receive Enable
-AT91C_SSC_RXDIS           EQU (0x1:SHL:1) ;- (SSC) Receive Disable
-AT91C_SSC_TXEN            EQU (0x1:SHL:8) ;- (SSC) Transmit Enable
-AT91C_SSC_TXDIS           EQU (0x1:SHL:9) ;- (SSC) Transmit Disable
-AT91C_SSC_SWRST           EQU (0x1:SHL:15) ;- (SSC) Software Reset
-;- -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-AT91C_SSC_CKS             EQU (0x3:SHL:0) ;- (SSC) Receive/Transmit Clock Selection
-AT91C_SSC_CKS_DIV         EQU (0x0) ;- (SSC) Divided Clock
-AT91C_SSC_CKS_TK          EQU (0x1) ;- (SSC) TK Clock signal
-AT91C_SSC_CKS_RK          EQU (0x2) ;- (SSC) RK pin
-AT91C_SSC_CKO             EQU (0x7:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
-AT91C_SSC_CKO_NONE        EQU (0x0:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-AT91C_SSC_CKO_CONTINOUS   EQU (0x1:SHL:2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
-AT91C_SSC_CKO_DATA_TX     EQU (0x2:SHL:2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-AT91C_SSC_CKI             EQU (0x1:SHL:5) ;- (SSC) Receive/Transmit Clock Inversion
-AT91C_SSC_CKG             EQU (0x3:SHL:6) ;- (SSC) Receive/Transmit Clock Gating Selection
-AT91C_SSC_CKG_NONE        EQU (0x0:SHL:6) ;- (SSC) Receive/Transmit Clock Gating: None, continuous clock
-AT91C_SSC_CKG_LOW         EQU (0x1:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF Low
-AT91C_SSC_CKG_HIGH        EQU (0x2:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF High
-AT91C_SSC_START           EQU (0xF:SHL:8) ;- (SSC) Receive/Transmit Start Selection
-AT91C_SSC_START_CONTINOUS EQU (0x0:SHL:8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-AT91C_SSC_START_TX        EQU (0x1:SHL:8) ;- (SSC) Transmit/Receive start
-AT91C_SSC_START_LOW_RF    EQU (0x2:SHL:8) ;- (SSC) Detection of a low level on RF input
-AT91C_SSC_START_HIGH_RF   EQU (0x3:SHL:8) ;- (SSC) Detection of a high level on RF input
-AT91C_SSC_START_FALL_RF   EQU (0x4:SHL:8) ;- (SSC) Detection of a falling edge on RF input
-AT91C_SSC_START_RISE_RF   EQU (0x5:SHL:8) ;- (SSC) Detection of a rising edge on RF input
-AT91C_SSC_START_LEVEL_RF  EQU (0x6:SHL:8) ;- (SSC) Detection of any level change on RF input
-AT91C_SSC_START_EDGE_RF   EQU (0x7:SHL:8) ;- (SSC) Detection of any edge on RF input
-AT91C_SSC_START_0         EQU (0x8:SHL:8) ;- (SSC) Compare 0
-AT91C_SSC_STOP            EQU (0x1:SHL:12) ;- (SSC) Receive Stop Selection
-AT91C_SSC_STTOUT          EQU (0x1:SHL:15) ;- (SSC) Receive/Transmit Start Output Selection
-AT91C_SSC_STTDLY          EQU (0xFF:SHL:16) ;- (SSC) Receive/Transmit Start Delay
-AT91C_SSC_PERIOD          EQU (0xFF:SHL:24) ;- (SSC) Receive/Transmit Period Divider Selection
-;- -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-AT91C_SSC_DATLEN          EQU (0x1F:SHL:0) ;- (SSC) Data Length
-AT91C_SSC_LOOP            EQU (0x1:SHL:5) ;- (SSC) Loop Mode
-AT91C_SSC_MSBF            EQU (0x1:SHL:7) ;- (SSC) Most Significant Bit First
-AT91C_SSC_DATNB           EQU (0xF:SHL:8) ;- (SSC) Data Number per Frame
-AT91C_SSC_FSLEN           EQU (0xF:SHL:16) ;- (SSC) Receive/Transmit Frame Sync length
-AT91C_SSC_FSOS            EQU (0x7:SHL:20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
-AT91C_SSC_FSOS_NONE       EQU (0x0:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-AT91C_SSC_FSOS_NEGATIVE   EQU (0x1:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-AT91C_SSC_FSOS_POSITIVE   EQU (0x2:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-AT91C_SSC_FSOS_LOW        EQU (0x3:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-AT91C_SSC_FSOS_HIGH       EQU (0x4:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-AT91C_SSC_FSOS_TOGGLE     EQU (0x5:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-AT91C_SSC_FSEDGE          EQU (0x1:SHL:24) ;- (SSC) Frame Sync Edge Detection
-;- -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-;- -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-AT91C_SSC_DATDEF          EQU (0x1:SHL:5) ;- (SSC) Data Default Value
-AT91C_SSC_FSDEN           EQU (0x1:SHL:23) ;- (SSC) Frame Sync Data Enable
-;- -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-AT91C_SSC_TXRDY           EQU (0x1:SHL:0) ;- (SSC) Transmit Ready
-AT91C_SSC_TXEMPTY         EQU (0x1:SHL:1) ;- (SSC) Transmit Empty
-AT91C_SSC_ENDTX           EQU (0x1:SHL:2) ;- (SSC) End Of Transmission
-AT91C_SSC_TXBUFE          EQU (0x1:SHL:3) ;- (SSC) Transmit Buffer Empty
-AT91C_SSC_RXRDY           EQU (0x1:SHL:4) ;- (SSC) Receive Ready
-AT91C_SSC_OVRUN           EQU (0x1:SHL:5) ;- (SSC) Receive Overrun
-AT91C_SSC_ENDRX           EQU (0x1:SHL:6) ;- (SSC) End of Reception
-AT91C_SSC_RXBUFF          EQU (0x1:SHL:7) ;- (SSC) Receive Buffer Full
-AT91C_SSC_CP0             EQU (0x1:SHL:8) ;- (SSC) Compare 0
-AT91C_SSC_CP1             EQU (0x1:SHL:9) ;- (SSC) Compare 1
-AT91C_SSC_TXSYN           EQU (0x1:SHL:10) ;- (SSC) Transmit Sync
-AT91C_SSC_RXSYN           EQU (0x1:SHL:11) ;- (SSC) Receive Sync
-AT91C_SSC_TXENA           EQU (0x1:SHL:16) ;- (SSC) Transmit Enable
-AT91C_SSC_RXENA           EQU (0x1:SHL:17) ;- (SSC) Receive Enable
-;- -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-;- -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-;- -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Usart
-;- *****************************************************************************
-                ^ 0 ;- AT91S_USART
-US_CR           #  4 ;- Control Register
-US_MR           #  4 ;- Mode Register
-US_IER          #  4 ;- Interrupt Enable Register
-US_IDR          #  4 ;- Interrupt Disable Register
-US_IMR          #  4 ;- Interrupt Mask Register
-US_CSR          #  4 ;- Channel Status Register
-US_RHR          #  4 ;- Receiver Holding Register
-US_THR          #  4 ;- Transmitter Holding Register
-US_BRGR         #  4 ;- Baud Rate Generator Register
-US_RTOR         #  4 ;- Receiver Time-out Register
-US_TTGR         #  4 ;- Transmitter Time-guard Register
-                # 20 ;- Reserved
-US_FIDI         #  4 ;- FI_DI_Ratio Register
-US_NER          #  4 ;- Nb Errors Register
-US_XXR          #  4 ;- XON_XOFF Register
-US_IF           #  4 ;- IRDA_FILTER Register
-                # 176 ;- Reserved
-US_RPR          #  4 ;- Receive Pointer Register
-US_RCR          #  4 ;- Receive Counter Register
-US_TPR          #  4 ;- Transmit Pointer Register
-US_TCR          #  4 ;- Transmit Counter Register
-US_RNPR         #  4 ;- Receive Next Pointer Register
-US_RNCR         #  4 ;- Receive Next Counter Register
-US_TNPR         #  4 ;- Transmit Next Pointer Register
-US_TNCR         #  4 ;- Transmit Next Counter Register
-US_PTCR         #  4 ;- PDC Transfer Control Register
-US_PTSR         #  4 ;- PDC Transfer Status Register
-;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-AT91C_US_RSTSTA           EQU (0x1:SHL:8) ;- (USART) Reset Status Bits
-AT91C_US_STTBRK           EQU (0x1:SHL:9) ;- (USART) Start Break
-AT91C_US_STPBRK           EQU (0x1:SHL:10) ;- (USART) Stop Break
-AT91C_US_STTTO            EQU (0x1:SHL:11) ;- (USART) Start Time-out
-AT91C_US_SENDA            EQU (0x1:SHL:12) ;- (USART) Send Address
-AT91C_US_RSTIT            EQU (0x1:SHL:13) ;- (USART) Reset Iterations
-AT91C_US_RSTNACK          EQU (0x1:SHL:14) ;- (USART) Reset Non Acknowledge
-AT91C_US_RETTO            EQU (0x1:SHL:15) ;- (USART) Rearm Time-out
-AT91C_US_DTREN            EQU (0x1:SHL:16) ;- (USART) Data Terminal ready Enable
-AT91C_US_DTRDIS           EQU (0x1:SHL:17) ;- (USART) Data Terminal ready Disable
-AT91C_US_RTSEN            EQU (0x1:SHL:18) ;- (USART) Request to Send enable
-AT91C_US_RTSDIS           EQU (0x1:SHL:19) ;- (USART) Request to Send Disable
-;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-AT91C_US_USMODE           EQU (0xF:SHL:0) ;- (USART) Usart mode
-AT91C_US_USMODE_NORMAL    EQU (0x0) ;- (USART) Normal
-AT91C_US_USMODE_RS485     EQU (0x1) ;- (USART) RS485
-AT91C_US_USMODE_HWHSH     EQU (0x2) ;- (USART) Hardware Handshaking
-AT91C_US_USMODE_MODEM     EQU (0x3) ;- (USART) Modem
-AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
-AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
-AT91C_US_USMODE_IRDA      EQU (0x8) ;- (USART) IrDA
-AT91C_US_USMODE_SWHSH     EQU (0xC) ;- (USART) Software Handshaking
-AT91C_US_CLKS             EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CLKS_CLOCK       EQU (0x0:SHL:4) ;- (USART) Clock
-AT91C_US_CLKS_FDIV1       EQU (0x1:SHL:4) ;- (USART) fdiv1
-AT91C_US_CLKS_SLOW        EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM)
-AT91C_US_CLKS_EXT         EQU (0x3:SHL:4) ;- (USART) External (SCK)
-AT91C_US_CHRL             EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CHRL_5_BITS      EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits
-AT91C_US_CHRL_6_BITS      EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits
-AT91C_US_CHRL_7_BITS      EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits
-AT91C_US_CHRL_8_BITS      EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits
-AT91C_US_SYNC             EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select
-AT91C_US_NBSTOP           EQU (0x3:SHL:12) ;- (USART) Number of Stop bits
-AT91C_US_NBSTOP_1_BIT     EQU (0x0:SHL:12) ;- (USART) 1 stop bit
-AT91C_US_NBSTOP_15_BIT    EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-AT91C_US_NBSTOP_2_BIT     EQU (0x2:SHL:12) ;- (USART) 2 stop bits
-AT91C_US_MSBF             EQU (0x1:SHL:16) ;- (USART) Bit Order
-AT91C_US_MODE9            EQU (0x1:SHL:17) ;- (USART) 9-bit Character length
-AT91C_US_CKLO             EQU (0x1:SHL:18) ;- (USART) Clock Output Select
-AT91C_US_OVER             EQU (0x1:SHL:19) ;- (USART) Over Sampling Mode
-AT91C_US_INACK            EQU (0x1:SHL:20) ;- (USART) Inhibit Non Acknowledge
-AT91C_US_DSNACK           EQU (0x1:SHL:21) ;- (USART) Disable Successive NACK
-AT91C_US_MAX_ITER         EQU (0x1:SHL:24) ;- (USART) Number of Repetitions
-AT91C_US_FILTER           EQU (0x1:SHL:28) ;- (USART) Receive Line Filter
-;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-AT91C_US_RXBRK            EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break
-AT91C_US_TIMEOUT          EQU (0x1:SHL:8) ;- (USART) Receiver Time-out
-AT91C_US_ITERATION        EQU (0x1:SHL:10) ;- (USART) Max number of Repetitions Reached
-AT91C_US_NACK             EQU (0x1:SHL:13) ;- (USART) Non Acknowledge
-AT91C_US_RIIC             EQU (0x1:SHL:16) ;- (USART) Ring INdicator Input Change Flag
-AT91C_US_DSRIC            EQU (0x1:SHL:17) ;- (USART) Data Set Ready Input Change Flag
-AT91C_US_DCDIC            EQU (0x1:SHL:18) ;- (USART) Data Carrier Flag
-AT91C_US_CTSIC            EQU (0x1:SHL:19) ;- (USART) Clear To Send Input Change Flag
-;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-AT91C_US_RI               EQU (0x1:SHL:20) ;- (USART) Image of RI Input
-AT91C_US_DSR              EQU (0x1:SHL:21) ;- (USART) Image of DSR Input
-AT91C_US_DCD              EQU (0x1:SHL:22) ;- (USART) Image of DCD Input
-AT91C_US_CTS              EQU (0x1:SHL:23) ;- (USART) Image of CTS Input
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Two-wire Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_TWI
-TWI_CR          #  4 ;- Control Register
-TWI_MMR         #  4 ;- Master Mode Register
-TWI_SMR         #  4 ;- Slave Mode Register
-TWI_IADR        #  4 ;- Internal Address Register
-TWI_CWGR        #  4 ;- Clock Waveform Generator Register
-                # 12 ;- Reserved
-TWI_SR          #  4 ;- Status Register
-TWI_IER         #  4 ;- Interrupt Enable Register
-TWI_IDR         #  4 ;- Interrupt Disable Register
-TWI_IMR         #  4 ;- Interrupt Mask Register
-TWI_RHR         #  4 ;- Receive Holding Register
-TWI_THR         #  4 ;- Transmit Holding Register
-;- -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-AT91C_TWI_START           EQU (0x1:SHL:0) ;- (TWI) Send a START Condition
-AT91C_TWI_STOP            EQU (0x1:SHL:1) ;- (TWI) Send a STOP Condition
-AT91C_TWI_MSEN            EQU (0x1:SHL:2) ;- (TWI) TWI Master Transfer Enabled
-AT91C_TWI_MSDIS           EQU (0x1:SHL:3) ;- (TWI) TWI Master Transfer Disabled
-AT91C_TWI_SVEN            EQU (0x1:SHL:4) ;- (TWI) TWI Slave Transfer Enabled
-AT91C_TWI_SVDIS           EQU (0x1:SHL:5) ;- (TWI) TWI Slave Transfer Disabled
-AT91C_TWI_SWRST           EQU (0x1:SHL:7) ;- (TWI) Software Reset
-;- -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-AT91C_TWI_IADRSZ          EQU (0x3:SHL:8) ;- (TWI) Internal Device Address Size
-AT91C_TWI_IADRSZ_NO       EQU (0x0:SHL:8) ;- (TWI) No internal device address
-AT91C_TWI_IADRSZ_1_BYTE   EQU (0x1:SHL:8) ;- (TWI) One-byte internal device address
-AT91C_TWI_IADRSZ_2_BYTE   EQU (0x2:SHL:8) ;- (TWI) Two-byte internal device address
-AT91C_TWI_IADRSZ_3_BYTE   EQU (0x3:SHL:8) ;- (TWI) Three-byte internal device address
-AT91C_TWI_MREAD           EQU (0x1:SHL:12) ;- (TWI) Master Read Direction
-AT91C_TWI_DADR            EQU (0x7F:SHL:16) ;- (TWI) Device Address
-;- -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
-AT91C_TWI_SADR            EQU (0x7F:SHL:16) ;- (TWI) Slave Device Address
-;- -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-AT91C_TWI_CLDIV           EQU (0xFF:SHL:0) ;- (TWI) Clock Low Divider
-AT91C_TWI_CHDIV           EQU (0xFF:SHL:8) ;- (TWI) Clock High Divider
-AT91C_TWI_CKDIV           EQU (0x7:SHL:16) ;- (TWI) Clock Divider
-;- -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-AT91C_TWI_TXCOMP          EQU (0x1:SHL:0) ;- (TWI) Transmission Completed
-AT91C_TWI_RXRDY           EQU (0x1:SHL:1) ;- (TWI) Receive holding register ReaDY
-AT91C_TWI_TXRDY           EQU (0x1:SHL:2) ;- (TWI) Transmit holding register ReaDY
-AT91C_TWI_SVREAD          EQU (0x1:SHL:3) ;- (TWI) Slave Read
-AT91C_TWI_SVACC           EQU (0x1:SHL:4) ;- (TWI) Slave Access
-AT91C_TWI_GCACC           EQU (0x1:SHL:5) ;- (TWI) General Call Access
-AT91C_TWI_OVRE            EQU (0x1:SHL:6) ;- (TWI) Overrun Error
-AT91C_TWI_UNRE            EQU (0x1:SHL:7) ;- (TWI) Underrun Error
-AT91C_TWI_NACK            EQU (0x1:SHL:8) ;- (TWI) Not Acknowledged
-AT91C_TWI_ARBLST          EQU (0x1:SHL:9) ;- (TWI) Arbitration Lost
-;- -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-;- -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-;- -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Multimedia Card Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_MCI
-MCI_CR          #  4 ;- MCI Control Register
-MCI_MR          #  4 ;- MCI Mode Register
-MCI_DTOR        #  4 ;- MCI Data Timeout Register
-MCI_SDCR        #  4 ;- MCI SD Card Register
-MCI_ARGR        #  4 ;- MCI Argument Register
-MCI_CMDR        #  4 ;- MCI Command Register
-                #  8 ;- Reserved
-MCI_RSPR        # 16 ;- MCI Response Register
-MCI_RDR         #  4 ;- MCI Receive Data Register
-MCI_TDR         #  4 ;- MCI Transmit Data Register
-                #  8 ;- Reserved
-MCI_SR          #  4 ;- MCI Status Register
-MCI_IER         #  4 ;- MCI Interrupt Enable Register
-MCI_IDR         #  4 ;- MCI Interrupt Disable Register
-MCI_IMR         #  4 ;- MCI Interrupt Mask Register
-                # 176 ;- Reserved
-MCI_RPR         #  4 ;- Receive Pointer Register
-MCI_RCR         #  4 ;- Receive Counter Register
-MCI_TPR         #  4 ;- Transmit Pointer Register
-MCI_TCR         #  4 ;- Transmit Counter Register
-MCI_RNPR        #  4 ;- Receive Next Pointer Register
-MCI_RNCR        #  4 ;- Receive Next Counter Register
-MCI_TNPR        #  4 ;- Transmit Next Pointer Register
-MCI_TNCR        #  4 ;- Transmit Next Counter Register
-MCI_PTCR        #  4 ;- PDC Transfer Control Register
-MCI_PTSR        #  4 ;- PDC Transfer Status Register
-;- -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- 
-AT91C_MCI_MCIEN           EQU (0x1:SHL:0) ;- (MCI) Multimedia Interface Enable
-AT91C_MCI_MCIDIS          EQU (0x1:SHL:1) ;- (MCI) Multimedia Interface Disable
-AT91C_MCI_PWSEN           EQU (0x1:SHL:2) ;- (MCI) Power Save Mode Enable
-AT91C_MCI_PWSDIS          EQU (0x1:SHL:3) ;- (MCI) Power Save Mode Disable
-;- -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- 
-AT91C_MCI_CLKDIV          EQU (0x1:SHL:0) ;- (MCI) Clock Divider
-AT91C_MCI_PWSDIV          EQU (0x1:SHL:8) ;- (MCI) Power Saving Divider
-AT91C_MCI_PDCPADV         EQU (0x1:SHL:14) ;- (MCI) PDC Padding Value
-AT91C_MCI_PDCMODE         EQU (0x1:SHL:15) ;- (MCI) PDC Oriented Mode
-AT91C_MCI_BLKLEN          EQU (0x1:SHL:18) ;- (MCI) Data Block Length
-;- -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- 
-AT91C_MCI_DTOCYC          EQU (0x1:SHL:0) ;- (MCI) Data Timeout Cycle Number
-AT91C_MCI_DTOMUL          EQU (0x7:SHL:4) ;- (MCI) Data Timeout Multiplier
-AT91C_MCI_DTOMUL_1        EQU (0x0:SHL:4) ;- (MCI) DTOCYC x 1
-AT91C_MCI_DTOMUL_16       EQU (0x1:SHL:4) ;- (MCI) DTOCYC x 16
-AT91C_MCI_DTOMUL_128      EQU (0x2:SHL:4) ;- (MCI) DTOCYC x 128
-AT91C_MCI_DTOMUL_256      EQU (0x3:SHL:4) ;- (MCI) DTOCYC x 256
-AT91C_MCI_DTOMUL_1024     EQU (0x4:SHL:4) ;- (MCI) DTOCYC x 1024
-AT91C_MCI_DTOMUL_4096     EQU (0x5:SHL:4) ;- (MCI) DTOCYC x 4096
-AT91C_MCI_DTOMUL_65536    EQU (0x6:SHL:4) ;- (MCI) DTOCYC x 65536
-AT91C_MCI_DTOMUL_1048576  EQU (0x7:SHL:4) ;- (MCI) DTOCYC x 1048576
-;- -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- 
-AT91C_MCI_SCDSEL          EQU (0x1:SHL:0) ;- (MCI) SD Card Selector
-AT91C_MCI_SCDBUS          EQU (0x1:SHL:7) ;- (MCI) SD Card Bus Width
-;- -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- 
-AT91C_MCI_CMDNB           EQU (0x1F:SHL:0) ;- (MCI) Command Number
-AT91C_MCI_RSPTYP          EQU (0x3:SHL:6) ;- (MCI) Response Type
-AT91C_MCI_RSPTYP_NO       EQU (0x0:SHL:6) ;- (MCI) No response
-AT91C_MCI_RSPTYP_48       EQU (0x1:SHL:6) ;- (MCI) 48-bit response
-AT91C_MCI_RSPTYP_136      EQU (0x2:SHL:6) ;- (MCI) 136-bit response
-AT91C_MCI_SPCMD           EQU (0x7:SHL:8) ;- (MCI) Special CMD
-AT91C_MCI_SPCMD_NONE      EQU (0x0:SHL:8) ;- (MCI) Not a special CMD
-AT91C_MCI_SPCMD_INIT      EQU (0x1:SHL:8) ;- (MCI) Initialization CMD
-AT91C_MCI_SPCMD_SYNC      EQU (0x2:SHL:8) ;- (MCI) Synchronized CMD
-AT91C_MCI_SPCMD_IT_CMD    EQU (0x4:SHL:8) ;- (MCI) Interrupt command
-AT91C_MCI_SPCMD_IT_REP    EQU (0x5:SHL:8) ;- (MCI) Interrupt response
-AT91C_MCI_OPDCMD          EQU (0x1:SHL:11) ;- (MCI) Open Drain Command
-AT91C_MCI_MAXLAT          EQU (0x1:SHL:12) ;- (MCI) Maximum Latency for Command to respond
-AT91C_MCI_TRCMD           EQU (0x3:SHL:16) ;- (MCI) Transfer CMD
-AT91C_MCI_TRCMD_NO        EQU (0x0:SHL:16) ;- (MCI) No transfer
-AT91C_MCI_TRCMD_START     EQU (0x1:SHL:16) ;- (MCI) Start transfer
-AT91C_MCI_TRCMD_STOP      EQU (0x2:SHL:16) ;- (MCI) Stop transfer
-AT91C_MCI_TRDIR           EQU (0x1:SHL:18) ;- (MCI) Transfer Direction
-AT91C_MCI_TRTYP           EQU (0x3:SHL:19) ;- (MCI) Transfer Type
-AT91C_MCI_TRTYP_BLOCK     EQU (0x0:SHL:19) ;- (MCI) Block Transfer type
-AT91C_MCI_TRTYP_MULTIPLE  EQU (0x1:SHL:19) ;- (MCI) Multiple Block transfer type
-AT91C_MCI_TRTYP_STREAM    EQU (0x2:SHL:19) ;- (MCI) Stream transfer type
-;- -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- 
-AT91C_MCI_CMDRDY          EQU (0x1:SHL:0) ;- (MCI) Command Ready flag
-AT91C_MCI_RXRDY           EQU (0x1:SHL:1) ;- (MCI) RX Ready flag
-AT91C_MCI_TXRDY           EQU (0x1:SHL:2) ;- (MCI) TX Ready flag
-AT91C_MCI_BLKE            EQU (0x1:SHL:3) ;- (MCI) Data Block Transfer Ended flag
-AT91C_MCI_DTIP            EQU (0x1:SHL:4) ;- (MCI) Data Transfer in Progress flag
-AT91C_MCI_NOTBUSY         EQU (0x1:SHL:5) ;- (MCI) Data Line Not Busy flag
-AT91C_MCI_ENDRX           EQU (0x1:SHL:6) ;- (MCI) End of RX Buffer flag
-AT91C_MCI_ENDTX           EQU (0x1:SHL:7) ;- (MCI) End of TX Buffer flag
-AT91C_MCI_RXBUFF          EQU (0x1:SHL:14) ;- (MCI) RX Buffer Full flag
-AT91C_MCI_TXBUFE          EQU (0x1:SHL:15) ;- (MCI) TX Buffer Empty flag
-AT91C_MCI_RINDE           EQU (0x1:SHL:16) ;- (MCI) Response Index Error flag
-AT91C_MCI_RDIRE           EQU (0x1:SHL:17) ;- (MCI) Response Direction Error flag
-AT91C_MCI_RCRCE           EQU (0x1:SHL:18) ;- (MCI) Response CRC Error flag
-AT91C_MCI_RENDE           EQU (0x1:SHL:19) ;- (MCI) Response End Bit Error flag
-AT91C_MCI_RTOE            EQU (0x1:SHL:20) ;- (MCI) Response Time-out Error flag
-AT91C_MCI_DCRCE           EQU (0x1:SHL:21) ;- (MCI) data CRC Error flag
-AT91C_MCI_DTOE            EQU (0x1:SHL:22) ;- (MCI) Data timeout Error flag
-AT91C_MCI_OVRE            EQU (0x1:SHL:30) ;- (MCI) Overrun flag
-AT91C_MCI_UNRE            EQU (0x1:SHL:31) ;- (MCI) Underrun flag
-;- -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- 
-;- -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- 
-;- -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- 
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR USB Device Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_UDP
-UDP_NUM         #  4 ;- Frame Number Register
-UDP_GLBSTATE    #  4 ;- Global State Register
-UDP_FADDR       #  4 ;- Function Address Register
-                #  4 ;- Reserved
-UDP_IER         #  4 ;- Interrupt Enable Register
-UDP_IDR         #  4 ;- Interrupt Disable Register
-UDP_IMR         #  4 ;- Interrupt Mask Register
-UDP_ISR         #  4 ;- Interrupt Status Register
-UDP_ICR         #  4 ;- Interrupt Clear Register
-                #  4 ;- Reserved
-UDP_RSTEP       #  4 ;- Reset Endpoint Register
-                #  4 ;- Reserved
-UDP_CSR         # 32 ;- Endpoint Control and Status Register
-UDP_FDR         # 32 ;- Endpoint FIFO Data Register
-;- -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-AT91C_UDP_FRM_NUM         EQU (0x7FF:SHL:0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
-AT91C_UDP_FRM_ERR         EQU (0x1:SHL:16) ;- (UDP) Frame Error
-AT91C_UDP_FRM_OK          EQU (0x1:SHL:17) ;- (UDP) Frame OK
-;- -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-AT91C_UDP_FADDEN          EQU (0x1:SHL:0) ;- (UDP) Function Address Enable
-AT91C_UDP_CONFG           EQU (0x1:SHL:1) ;- (UDP) Configured
-AT91C_UDP_RMWUPE          EQU (0x1:SHL:2) ;- (UDP) Remote Wake Up Enable
-AT91C_UDP_RSMINPR         EQU (0x1:SHL:3) ;- (UDP) A Resume Has Been Sent to the Host
-;- -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-AT91C_UDP_FADD            EQU (0xFF:SHL:0) ;- (UDP) Function Address Value
-AT91C_UDP_FEN             EQU (0x1:SHL:8) ;- (UDP) Function Enable
-;- -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-AT91C_UDP_EPINT0          EQU (0x1:SHL:0) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT1          EQU (0x1:SHL:1) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT2          EQU (0x1:SHL:2) ;- (UDP) Endpoint 2 Interrupt
-AT91C_UDP_EPINT3          EQU (0x1:SHL:3) ;- (UDP) Endpoint 3 Interrupt
-AT91C_UDP_EPINT4          EQU (0x1:SHL:4) ;- (UDP) Endpoint 4 Interrupt
-AT91C_UDP_EPINT5          EQU (0x1:SHL:5) ;- (UDP) Endpoint 5 Interrupt
-AT91C_UDP_EPINT6          EQU (0x1:SHL:6) ;- (UDP) Endpoint 6 Interrupt
-AT91C_UDP_EPINT7          EQU (0x1:SHL:7) ;- (UDP) Endpoint 7 Interrupt
-AT91C_UDP_RXSUSP          EQU (0x1:SHL:8) ;- (UDP) USB Suspend Interrupt
-AT91C_UDP_RXRSM           EQU (0x1:SHL:9) ;- (UDP) USB Resume Interrupt
-AT91C_UDP_EXTRSM          EQU (0x1:SHL:10) ;- (UDP) USB External Resume Interrupt
-AT91C_UDP_SOFINT          EQU (0x1:SHL:11) ;- (UDP) USB Start Of frame Interrupt
-AT91C_UDP_WAKEUP          EQU (0x1:SHL:13) ;- (UDP) USB Resume Interrupt
-;- -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-;- -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-;- -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-AT91C_UDP_ENDBUSRES       EQU (0x1:SHL:12) ;- (UDP) USB End Of Bus Reset Interrupt
-;- -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-;- -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-AT91C_UDP_EP0             EQU (0x1:SHL:0) ;- (UDP) Reset Endpoint 0
-AT91C_UDP_EP1             EQU (0x1:SHL:1) ;- (UDP) Reset Endpoint 1
-AT91C_UDP_EP2             EQU (0x1:SHL:2) ;- (UDP) Reset Endpoint 2
-AT91C_UDP_EP3             EQU (0x1:SHL:3) ;- (UDP) Reset Endpoint 3
-AT91C_UDP_EP4             EQU (0x1:SHL:4) ;- (UDP) Reset Endpoint 4
-AT91C_UDP_EP5             EQU (0x1:SHL:5) ;- (UDP) Reset Endpoint 5
-AT91C_UDP_EP6             EQU (0x1:SHL:6) ;- (UDP) Reset Endpoint 6
-AT91C_UDP_EP7             EQU (0x1:SHL:7) ;- (UDP) Reset Endpoint 7
-;- -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-AT91C_UDP_TXCOMP          EQU (0x1:SHL:0) ;- (UDP) Generates an IN packet with data previously written in the DPR
-AT91C_UDP_RX_DATA_BK0     EQU (0x1:SHL:1) ;- (UDP) Receive Data Bank 0
-AT91C_UDP_RXSETUP         EQU (0x1:SHL:2) ;- (UDP) Sends STALL to the Host (Control endpoints)
-AT91C_UDP_ISOERROR        EQU (0x1:SHL:3) ;- (UDP) Isochronous error (Isochronous endpoints)
-AT91C_UDP_TXPKTRDY        EQU (0x1:SHL:4) ;- (UDP) Transmit Packet Ready
-AT91C_UDP_FORCESTALL      EQU (0x1:SHL:5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-AT91C_UDP_RX_DATA_BK1     EQU (0x1:SHL:6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-AT91C_UDP_DIR             EQU (0x1:SHL:7) ;- (UDP) Transfer Direction
-AT91C_UDP_EPTYPE          EQU (0x7:SHL:8) ;- (UDP) Endpoint type
-AT91C_UDP_EPTYPE_CTRL     EQU (0x0:SHL:8) ;- (UDP) Control
-AT91C_UDP_EPTYPE_ISO_OUT  EQU (0x1:SHL:8) ;- (UDP) Isochronous OUT
-AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2:SHL:8) ;- (UDP) Bulk OUT
-AT91C_UDP_EPTYPE_INT_OUT  EQU (0x3:SHL:8) ;- (UDP) Interrupt OUT
-AT91C_UDP_EPTYPE_ISO_IN   EQU (0x5:SHL:8) ;- (UDP) Isochronous IN
-AT91C_UDP_EPTYPE_BULK_IN  EQU (0x6:SHL:8) ;- (UDP) Bulk IN
-AT91C_UDP_EPTYPE_INT_IN   EQU (0x7:SHL:8) ;- (UDP) Interrupt IN
-AT91C_UDP_DTGLE           EQU (0x1:SHL:11) ;- (UDP) Data Toggle
-AT91C_UDP_EPEDS           EQU (0x1:SHL:15) ;- (UDP) Endpoint Enable Disable
-AT91C_UDP_RXBYTECNT       EQU (0x7FF:SHL:16) ;- (UDP) Number Of Bytes Available in the FIFO
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_TC
-TC_CCR          #  4 ;- Channel Control Register
-TC_CMR          #  4 ;- Channel Mode Register
-                #  8 ;- Reserved
-TC_CV           #  4 ;- Counter Value
-TC_RA           #  4 ;- Register A
-TC_RB           #  4 ;- Register B
-TC_RC           #  4 ;- Register C
-TC_SR           #  4 ;- Status Register
-TC_IER          #  4 ;- Interrupt Enable Register
-TC_IDR          #  4 ;- Interrupt Disable Register
-TC_IMR          #  4 ;- Interrupt Mask Register
-;- -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-AT91C_TC_CLKEN            EQU (0x1:SHL:0) ;- (TC) Counter Clock Enable Command
-AT91C_TC_CLKDIS           EQU (0x1:SHL:1) ;- (TC) Counter Clock Disable Command
-AT91C_TC_SWTRG            EQU (0x1:SHL:2) ;- (TC) Software Trigger Command
-;- -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-AT91C_TC_CPCSTOP          EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RC Compare
-AT91C_TC_CPCDIS           EQU (0x1:SHL:7) ;- (TC) Counter Clock Disable with RC Compare
-AT91C_TC_EEVTEDG          EQU (0x3:SHL:8) ;- (TC) External Event Edge Selection
-AT91C_TC_EEVTEDG_NONE     EQU (0x0:SHL:8) ;- (TC) Edge: None
-AT91C_TC_EEVTEDG_RISING   EQU (0x1:SHL:8) ;- (TC) Edge: rising edge
-AT91C_TC_EEVTEDG_FALLING  EQU (0x2:SHL:8) ;- (TC) Edge: falling edge
-AT91C_TC_EEVTEDG_BOTH     EQU (0x3:SHL:8) ;- (TC) Edge: each edge
-AT91C_TC_EEVT             EQU (0x3:SHL:10) ;- (TC) External Event  Selection
-AT91C_TC_EEVT_NONE        EQU (0x0:SHL:10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
-AT91C_TC_EEVT_RISING      EQU (0x1:SHL:10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
-AT91C_TC_EEVT_FALLING     EQU (0x2:SHL:10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
-AT91C_TC_EEVT_BOTH        EQU (0x3:SHL:10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
-AT91C_TC_ENETRG           EQU (0x1:SHL:12) ;- (TC) External Event Trigger enable
-AT91C_TC_WAVESEL          EQU (0x3:SHL:13) ;- (TC) Waveform  Selection
-AT91C_TC_WAVESEL_UP       EQU (0x0:SHL:13) ;- (TC) UP mode without atomatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN   EQU (0x1:SHL:13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UP_AUTO  EQU (0x2:SHL:13) ;- (TC) UP mode with automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3:SHL:13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
-AT91C_TC_CPCTRG           EQU (0x1:SHL:14) ;- (TC) RC Compare Trigger Enable
-AT91C_TC_WAVE             EQU (0x1:SHL:15) ;- (TC) 
-AT91C_TC_ACPA             EQU (0x3:SHL:16) ;- (TC) RA Compare Effect on TIOA
-AT91C_TC_ACPA_NONE        EQU (0x0:SHL:16) ;- (TC) Effect: none
-AT91C_TC_ACPA_SET         EQU (0x1:SHL:16) ;- (TC) Effect: set
-AT91C_TC_ACPA_CLEAR       EQU (0x2:SHL:16) ;- (TC) Effect: clear
-AT91C_TC_ACPA_TOGGLE      EQU (0x3:SHL:16) ;- (TC) Effect: toggle
-AT91C_TC_ACPC             EQU (0x3:SHL:18) ;- (TC) RC Compare Effect on TIOA
-AT91C_TC_ACPC_NONE        EQU (0x0:SHL:18) ;- (TC) Effect: none
-AT91C_TC_ACPC_SET         EQU (0x1:SHL:18) ;- (TC) Effect: set
-AT91C_TC_ACPC_CLEAR       EQU (0x2:SHL:18) ;- (TC) Effect: clear
-AT91C_TC_ACPC_TOGGLE      EQU (0x3:SHL:18) ;- (TC) Effect: toggle
-AT91C_TC_AEEVT            EQU (0x3:SHL:20) ;- (TC) External Event Effect on TIOA
-AT91C_TC_AEEVT_NONE       EQU (0x0:SHL:20) ;- (TC) Effect: none
-AT91C_TC_AEEVT_SET        EQU (0x1:SHL:20) ;- (TC) Effect: set
-AT91C_TC_AEEVT_CLEAR      EQU (0x2:SHL:20) ;- (TC) Effect: clear
-AT91C_TC_AEEVT_TOGGLE     EQU (0x3:SHL:20) ;- (TC) Effect: toggle
-AT91C_TC_ASWTRG           EQU (0x3:SHL:22) ;- (TC) Software Trigger Effect on TIOA
-AT91C_TC_ASWTRG_NONE      EQU (0x0:SHL:22) ;- (TC) Effect: none
-AT91C_TC_ASWTRG_SET       EQU (0x1:SHL:22) ;- (TC) Effect: set
-AT91C_TC_ASWTRG_CLEAR     EQU (0x2:SHL:22) ;- (TC) Effect: clear
-AT91C_TC_ASWTRG_TOGGLE    EQU (0x3:SHL:22) ;- (TC) Effect: toggle
-AT91C_TC_BCPB             EQU (0x3:SHL:24) ;- (TC) RB Compare Effect on TIOB
-AT91C_TC_BCPB_NONE        EQU (0x0:SHL:24) ;- (TC) Effect: none
-AT91C_TC_BCPB_SET         EQU (0x1:SHL:24) ;- (TC) Effect: set
-AT91C_TC_BCPB_CLEAR       EQU (0x2:SHL:24) ;- (TC) Effect: clear
-AT91C_TC_BCPB_TOGGLE      EQU (0x3:SHL:24) ;- (TC) Effect: toggle
-AT91C_TC_BCPC             EQU (0x3:SHL:26) ;- (TC) RC Compare Effect on TIOB
-AT91C_TC_BCPC_NONE        EQU (0x0:SHL:26) ;- (TC) Effect: none
-AT91C_TC_BCPC_SET         EQU (0x1:SHL:26) ;- (TC) Effect: set
-AT91C_TC_BCPC_CLEAR       EQU (0x2:SHL:26) ;- (TC) Effect: clear
-AT91C_TC_BCPC_TOGGLE      EQU (0x3:SHL:26) ;- (TC) Effect: toggle
-AT91C_TC_BEEVT            EQU (0x3:SHL:28) ;- (TC) External Event Effect on TIOB
-AT91C_TC_BEEVT_NONE       EQU (0x0:SHL:28) ;- (TC) Effect: none
-AT91C_TC_BEEVT_SET        EQU (0x1:SHL:28) ;- (TC) Effect: set
-AT91C_TC_BEEVT_CLEAR      EQU (0x2:SHL:28) ;- (TC) Effect: clear
-AT91C_TC_BEEVT_TOGGLE     EQU (0x3:SHL:28) ;- (TC) Effect: toggle
-AT91C_TC_BSWTRG           EQU (0x3:SHL:30) ;- (TC) Software Trigger Effect on TIOB
-AT91C_TC_BSWTRG_NONE      EQU (0x0:SHL:30) ;- (TC) Effect: none
-AT91C_TC_BSWTRG_SET       EQU (0x1:SHL:30) ;- (TC) Effect: set
-AT91C_TC_BSWTRG_CLEAR     EQU (0x2:SHL:30) ;- (TC) Effect: clear
-AT91C_TC_BSWTRG_TOGGLE    EQU (0x3:SHL:30) ;- (TC) Effect: toggle
-;- -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-AT91C_TC_COVFS            EQU (0x1:SHL:0) ;- (TC) Counter Overflow
-AT91C_TC_LOVRS            EQU (0x1:SHL:1) ;- (TC) Load Overrun
-AT91C_TC_CPAS             EQU (0x1:SHL:2) ;- (TC) RA Compare
-AT91C_TC_CPBS             EQU (0x1:SHL:3) ;- (TC) RB Compare
-AT91C_TC_CPCS             EQU (0x1:SHL:4) ;- (TC) RC Compare
-AT91C_TC_LDRAS            EQU (0x1:SHL:5) ;- (TC) RA Loading
-AT91C_TC_LDRBS            EQU (0x1:SHL:6) ;- (TC) RB Loading
-AT91C_TC_ETRCS            EQU (0x1:SHL:7) ;- (TC) External Trigger
-AT91C_TC_ETRGS            EQU (0x1:SHL:16) ;- (TC) Clock Enabling
-AT91C_TC_MTIOA            EQU (0x1:SHL:17) ;- (TC) TIOA Mirror
-AT91C_TC_MTIOB            EQU (0x1:SHL:18) ;- (TC) TIOA Mirror
-;- -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-;- -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-;- -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_TCB
-TCB_TC0         # 48 ;- TC Channel 0
-                # 16 ;- Reserved
-TCB_TC1         # 48 ;- TC Channel 1
-                # 16 ;- Reserved
-TCB_TC2         # 48 ;- TC Channel 2
-                # 16 ;- Reserved
-TCB_BCR         #  4 ;- TC Block Control Register
-TCB_BMR         #  4 ;- TC Block Mode Register
-;- -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-AT91C_TCB_SYNC            EQU (0x1:SHL:0) ;- (TCB) Synchro Command
-;- -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-AT91C_TCB_TC0XC0S         EQU (0x1:SHL:0) ;- (TCB) External Clock Signal 0 Selection
-AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0
-AT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0
-AT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0
-AT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0
-AT91C_TCB_TC1XC1S         EQU (0x1:SHL:2) ;- (TCB) External Clock Signal 1 Selection
-AT91C_TCB_TC1XC1S_TCLK1   EQU (0x0:SHL:2) ;- (TCB) TCLK1 connected to XC1
-AT91C_TCB_TC1XC1S_NONE    EQU (0x1:SHL:2) ;- (TCB) None signal connected to XC1
-AT91C_TCB_TC1XC1S_TIOA0   EQU (0x2:SHL:2) ;- (TCB) TIOA0 connected to XC1
-AT91C_TCB_TC1XC1S_TIOA2   EQU (0x3:SHL:2) ;- (TCB) TIOA2 connected to XC1
-AT91C_TCB_TC2XC2S         EQU (0x1:SHL:4) ;- (TCB) External Clock Signal 2 Selection
-AT91C_TCB_TC2XC2S_TCLK2   EQU (0x0:SHL:4) ;- (TCB) TCLK2 connected to XC2
-AT91C_TCB_TC2XC2S_NONE    EQU (0x1:SHL:4) ;- (TCB) None signal connected to XC2
-AT91C_TCB_TC2XC2S_TIOA0   EQU (0x2:SHL:4) ;- (TCB) TIOA0 connected to XC2
-AT91C_TCB_TC2XC2S_TIOA2   EQU (0x3:SHL:4) ;- (TCB) TIOA2 connected to XC2
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR USB Host Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_UHP
-UHP_HcRevision  #  4 ;- Revision
-UHP_HcControl   #  4 ;- Operating modes for the Host Controller
-UHP_HcCommandStatus #  4 ;- Command & status Register
-UHP_HcInterruptStatus #  4 ;- Interrupt Status Register
-UHP_HcInterruptEnable #  4 ;- Interrupt Enable Register
-UHP_HcInterruptDisable #  4 ;- Interrupt Disable Register
-UHP_HcHCCA      #  4 ;- Pointer to the Host Controller Communication Area
-UHP_HcPeriodCurrentED #  4 ;- Current Isochronous or Interrupt Endpoint Descriptor
-UHP_HcControlHeadED #  4 ;- First Endpoint Descriptor of the Control list
-UHP_HcControlCurrentED #  4 ;- Endpoint Control and Status Register
-UHP_HcBulkHeadED #  4 ;- First endpoint register of the Bulk list
-UHP_HcBulkCurrentED #  4 ;- Current endpoint of the Bulk list
-UHP_HcBulkDoneHead #  4 ;- Last completed transfer descriptor
-UHP_HcFmInterval #  4 ;- Bit time between 2 consecutive SOFs
-UHP_HcFmRemaining #  4 ;- Bit time remaining in the current Frame
-UHP_HcFmNumber  #  4 ;- Frame number
-UHP_HcPeriodicStart #  4 ;- Periodic Start
-UHP_HcLSThreshold #  4 ;- LS Threshold
-UHP_HcRhDescriptorA #  4 ;- Root Hub characteristics A
-UHP_HcRhDescriptorB #  4 ;- Root Hub characteristics B
-UHP_HcRhStatus  #  4 ;- Root Hub Status register
-UHP_HcRhPortStatus #  8 ;- Root Hub Port Status Register
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Ethernet MAC
-;- *****************************************************************************
-                ^ 0 ;- AT91S_EMAC
-EMAC_CTL        #  4 ;- Network Control Register
-EMAC_CFG        #  4 ;- Network Configuration Register
-EMAC_SR         #  4 ;- Network Status Register
-EMAC_TAR        #  4 ;- Transmit Address Register
-EMAC_TCR        #  4 ;- Transmit Control Register
-EMAC_TSR        #  4 ;- Transmit Status Register
-EMAC_RBQP       #  4 ;- Receive Buffer Queue Pointer
-                #  4 ;- Reserved
-EMAC_RSR        #  4 ;- Receive Status Register
-EMAC_ISR        #  4 ;- Interrupt Status Register
-EMAC_IER        #  4 ;- Interrupt Enable Register
-EMAC_IDR        #  4 ;- Interrupt Disable Register
-EMAC_IMR        #  4 ;- Interrupt Mask Register
-EMAC_MAN        #  4 ;- PHY Maintenance Register
-                #  8 ;- Reserved
-EMAC_FRA        #  4 ;- Frames Transmitted OK Register
-EMAC_SCOL       #  4 ;- Single Collision Frame Register
-EMAC_MCOL       #  4 ;- Multiple Collision Frame Register
-EMAC_OK         #  4 ;- Frames Received OK Register
-EMAC_SEQE       #  4 ;- Frame Check Sequence Error Register
-EMAC_ALE        #  4 ;- Alignment Error Register
-EMAC_DTE        #  4 ;- Deferred Transmission Frame Register
-EMAC_LCOL       #  4 ;- Late Collision Register
-EMAC_ECOL       #  4 ;- Excessive Collision Register
-EMAC_CSE        #  4 ;- Carrier Sense Error Register
-EMAC_TUE        #  4 ;- Transmit Underrun Error Register
-EMAC_CDE        #  4 ;- Code Error Register
-EMAC_ELR        #  4 ;- Excessive Length Error Register
-EMAC_RJB        #  4 ;- Receive Jabber Register
-EMAC_USF        #  4 ;- Undersize Frame Register
-EMAC_SQEE       #  4 ;- SQE Test Error Register
-EMAC_DRFC       #  4 ;- Discarded RX Frame Register
-                # 12 ;- Reserved
-EMAC_HSH        #  4 ;- Hash Address High[63:32]
-EMAC_HSL        #  4 ;- Hash Address Low[31:0]
-EMAC_SA1L       #  4 ;- Specific Address 1 Low, First 4 bytes
-EMAC_SA1H       #  4 ;- Specific Address 1 High, Last 2 bytes
-EMAC_SA2L       #  4 ;- Specific Address 2 Low, First 4 bytes
-EMAC_SA2H       #  4 ;- Specific Address 2 High, Last 2 bytes
-EMAC_SA3L       #  4 ;- Specific Address 3 Low, First 4 bytes
-EMAC_SA3H       #  4 ;- Specific Address 3 High, Last 2 bytes
-EMAC_SA4L       #  4 ;- Specific Address 4 Low, First 4 bytes
-EMAC_SA4H       #  4 ;- Specific Address 4 High, Last 2 bytesr
-;- -------- EMAC_CTL : (EMAC Offset: 0x0)  -------- 
-AT91C_EMAC_LB             EQU (0x1:SHL:0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-AT91C_EMAC_LBL            EQU (0x1:SHL:1) ;- (EMAC) Loopback local. 
-AT91C_EMAC_RE             EQU (0x1:SHL:2) ;- (EMAC) Receive enable. 
-AT91C_EMAC_TE             EQU (0x1:SHL:3) ;- (EMAC) Transmit enable. 
-AT91C_EMAC_MPE            EQU (0x1:SHL:4) ;- (EMAC) Management port enable. 
-AT91C_EMAC_CSR            EQU (0x1:SHL:5) ;- (EMAC) Clear statistics registers. 
-AT91C_EMAC_ISR            EQU (0x1:SHL:6) ;- (EMAC) Increment statistics registers. 
-AT91C_EMAC_WES            EQU (0x1:SHL:7) ;- (EMAC) Write enable for statistics registers. 
-AT91C_EMAC_BP             EQU (0x1:SHL:8) ;- (EMAC) Back pressure. 
-;- -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- 
-AT91C_EMAC_SPD            EQU (0x1:SHL:0) ;- (EMAC) Speed. 
-AT91C_EMAC_FD             EQU (0x1:SHL:1) ;- (EMAC) Full duplex. 
-AT91C_EMAC_BR             EQU (0x1:SHL:2) ;- (EMAC) Bit rate. 
-AT91C_EMAC_CAF            EQU (0x1:SHL:4) ;- (EMAC) Copy all frames. 
-AT91C_EMAC_NBC            EQU (0x1:SHL:5) ;- (EMAC) No broadcast. 
-AT91C_EMAC_MTI            EQU (0x1:SHL:6) ;- (EMAC) Multicast hash enable
-AT91C_EMAC_UNI            EQU (0x1:SHL:7) ;- (EMAC) Unicast hash enable. 
-AT91C_EMAC_BIG            EQU (0x1:SHL:8) ;- (EMAC) Receive 1522 bytes. 
-AT91C_EMAC_EAE            EQU (0x1:SHL:9) ;- (EMAC) External address match enable. 
-AT91C_EMAC_CLK            EQU (0x3:SHL:10) ;- (EMAC) 
-AT91C_EMAC_CLK_HCLK_8     EQU (0x0:SHL:10) ;- (EMAC) HCLK divided by 8
-AT91C_EMAC_CLK_HCLK_16    EQU (0x1:SHL:10) ;- (EMAC) HCLK divided by 16
-AT91C_EMAC_CLK_HCLK_32    EQU (0x2:SHL:10) ;- (EMAC) HCLK divided by 32
-AT91C_EMAC_CLK_HCLK_64    EQU (0x3:SHL:10) ;- (EMAC) HCLK divided by 64
-AT91C_EMAC_RTY            EQU (0x1:SHL:12) ;- (EMAC) 
-AT91C_EMAC_RMII           EQU (0x1:SHL:13) ;- (EMAC) 
-;- -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- 
-AT91C_EMAC_MDIO           EQU (0x1:SHL:1) ;- (EMAC) 
-AT91C_EMAC_IDLE           EQU (0x1:SHL:2) ;- (EMAC) 
-;- -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- 
-AT91C_EMAC_LEN            EQU (0x7FF:SHL:0) ;- (EMAC) 
-AT91C_EMAC_NCRC           EQU (0x1:SHL:15) ;- (EMAC) 
-;- -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- 
-AT91C_EMAC_OVR            EQU (0x1:SHL:0) ;- (EMAC) 
-AT91C_EMAC_COL            EQU (0x1:SHL:1) ;- (EMAC) 
-AT91C_EMAC_RLE            EQU (0x1:SHL:2) ;- (EMAC) 
-AT91C_EMAC_TXIDLE         EQU (0x1:SHL:3) ;- (EMAC) 
-AT91C_EMAC_BNQ            EQU (0x1:SHL:4) ;- (EMAC) 
-AT91C_EMAC_COMP           EQU (0x1:SHL:5) ;- (EMAC) 
-AT91C_EMAC_UND            EQU (0x1:SHL:6) ;- (EMAC) 
-;- -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-AT91C_EMAC_BNA            EQU (0x1:SHL:0) ;- (EMAC) 
-AT91C_EMAC_REC            EQU (0x1:SHL:1) ;- (EMAC) 
-;- -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-AT91C_EMAC_DONE           EQU (0x1:SHL:0) ;- (EMAC) 
-AT91C_EMAC_RCOM           EQU (0x1:SHL:1) ;- (EMAC) 
-AT91C_EMAC_RBNA           EQU (0x1:SHL:2) ;- (EMAC) 
-AT91C_EMAC_TOVR           EQU (0x1:SHL:3) ;- (EMAC) 
-AT91C_EMAC_TUND           EQU (0x1:SHL:4) ;- (EMAC) 
-AT91C_EMAC_RTRY           EQU (0x1:SHL:5) ;- (EMAC) 
-AT91C_EMAC_TBRE           EQU (0x1:SHL:6) ;- (EMAC) 
-AT91C_EMAC_TCOM           EQU (0x1:SHL:7) ;- (EMAC) 
-AT91C_EMAC_TIDLE          EQU (0x1:SHL:8) ;- (EMAC) 
-AT91C_EMAC_LINK           EQU (0x1:SHL:9) ;- (EMAC) 
-AT91C_EMAC_ROVR           EQU (0x1:SHL:10) ;- (EMAC) 
-AT91C_EMAC_HRESP          EQU (0x1:SHL:11) ;- (EMAC) 
-;- -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-;- -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-;- -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-;- -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-AT91C_EMAC_DATA           EQU (0xFFFF:SHL:0) ;- (EMAC) 
-AT91C_EMAC_CODE           EQU (0x3:SHL:16) ;- (EMAC) 
-AT91C_EMAC_REGA           EQU (0x1F:SHL:18) ;- (EMAC) 
-AT91C_EMAC_PHYA           EQU (0x1F:SHL:23) ;- (EMAC) 
-AT91C_EMAC_RW             EQU (0x3:SHL:28) ;- (EMAC) 
-AT91C_EMAC_HIGH           EQU (0x1:SHL:30) ;- (EMAC) 
-AT91C_EMAC_LOW            EQU (0x1:SHL:31) ;- (EMAC) 
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR External Bus Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_EBI
-EBI_CSA         #  4 ;- Chip Select Assignment Register
-EBI_CFGR        #  4 ;- Configuration Register
-;- -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- 
-AT91C_EBI_CS0A            EQU (0x1:SHL:0) ;- (EBI) Chip Select 0 Assignment
-AT91C_EBI_CS0A_SMC        EQU (0x0) ;- (EBI) Chip Select 0 is assigned to the Static Memory Controller.
-AT91C_EBI_CS0A_BFC        EQU (0x1) ;- (EBI) Chip Select 0 is assigned to the Burst Flash Controller.
-AT91C_EBI_CS1A            EQU (0x1:SHL:1) ;- (EBI) Chip Select 1 Assignment
-AT91C_EBI_CS1A_SMC        EQU (0x0:SHL:1) ;- (EBI) Chip Select 1 is assigned to the Static Memory Controller.
-AT91C_EBI_CS1A_SDRAMC     EQU (0x1:SHL:1) ;- (EBI) Chip Select 1 is assigned to the SDRAM Controller.
-AT91C_EBI_CS3A            EQU (0x1:SHL:3) ;- (EBI) Chip Select 3 Assignment
-AT91C_EBI_CS3A_SMC        EQU (0x0:SHL:3) ;- (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2.
-AT91C_EBI_CS3A_SMC_SmartMedia EQU (0x1:SHL:3) ;- (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
-AT91C_EBI_CS4A            EQU (0x1:SHL:4) ;- (EBI) Chip Select 4 Assignment
-AT91C_EBI_CS4A_SMC        EQU (0x0:SHL:4) ;- (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2.
-AT91C_EBI_CS4A_SMC_CompactFlash EQU (0x1:SHL:4) ;- (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.
-;- -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- 
-AT91C_EBI_DBPUC           EQU (0x1:SHL:0) ;- (EBI) Data Bus Pull-Up Configuration
-AT91C_EBI_EBSEN           EQU (0x1:SHL:1) ;- (EBI) Bus Sharing Enable
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_SMC2
-SMC2_CSR        # 32 ;- SMC2 Chip Select Register
-;- -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- 
-AT91C_SMC2_NWS            EQU (0x7F:SHL:0) ;- (SMC2) Number of Wait States
-AT91C_SMC2_WSEN           EQU (0x1:SHL:7) ;- (SMC2) Wait State Enable
-AT91C_SMC2_TDF            EQU (0xF:SHL:8) ;- (SMC2) Data Float Time
-AT91C_SMC2_BAT            EQU (0x1:SHL:12) ;- (SMC2) Byte Access Type
-AT91C_SMC2_DBW            EQU (0x1:SHL:13) ;- (SMC2) Data Bus Width
-AT91C_SMC2_DBW_16         EQU (0x1:SHL:13) ;- (SMC2) 16-bit.
-AT91C_SMC2_DBW_8          EQU (0x2:SHL:13) ;- (SMC2) 8-bit.
-AT91C_SMC2_DRP            EQU (0x1:SHL:15) ;- (SMC2) Data Read Protocol
-AT91C_SMC2_ACSS           EQU (0x3:SHL:16) ;- (SMC2) Address to Chip Select Setup
-AT91C_SMC2_ACSS_STANDARD  EQU (0x0:SHL:16) ;- (SMC2) Standard, asserted at the beginning of the access and deasserted at the end.
-AT91C_SMC2_ACSS_1_CYCLE   EQU (0x1:SHL:16) ;- (SMC2) One cycle less at the beginning and the end of the access.
-AT91C_SMC2_ACSS_2_CYCLES  EQU (0x2:SHL:16) ;- (SMC2) Two cycles less at the beginning and the end of the access.
-AT91C_SMC2_ACSS_3_CYCLES  EQU (0x3:SHL:16) ;- (SMC2) Three cycles less at the beginning and the end of the access.
-AT91C_SMC2_RWSETUP        EQU (0x7:SHL:24) ;- (SMC2) Read and Write Signal Setup Time
-AT91C_SMC2_RWHOLD         EQU (0x7:SHL:29) ;- (SMC2) Read and Write Signal Hold Time
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_SDRC
-SDRC_MR         #  4 ;- SDRAM Controller Mode Register
-SDRC_TR         #  4 ;- SDRAM Controller Refresh Timer Register
-SDRC_CR         #  4 ;- SDRAM Controller Configuration Register
-SDRC_SRR        #  4 ;- SDRAM Controller Self Refresh Register
-SDRC_LPR        #  4 ;- SDRAM Controller Low Power Register
-SDRC_IER        #  4 ;- SDRAM Controller Interrupt Enable Register
-SDRC_IDR        #  4 ;- SDRAM Controller Interrupt Disable Register
-SDRC_IMR        #  4 ;- SDRAM Controller Interrupt Mask Register
-SDRC_ISR        #  4 ;- SDRAM Controller Interrupt Mask Register
-;- -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- 
-AT91C_SDRC_MODE           EQU (0xF:SHL:0) ;- (SDRC) Mode
-AT91C_SDRC_MODE_NORMAL_CMD EQU (0x0) ;- (SDRC) Normal Mode
-AT91C_SDRC_MODE_NOP_CMD   EQU (0x1) ;- (SDRC) NOP Command
-AT91C_SDRC_MODE_PRCGALL_CMD EQU (0x2) ;- (SDRC) All Banks Precharge Command
-AT91C_SDRC_MODE_LMR_CMD   EQU (0x3) ;- (SDRC) Load Mode Register Command
-AT91C_SDRC_MODE_RFSH_CMD  EQU (0x4) ;- (SDRC) Refresh Command
-AT91C_SDRC_DBW            EQU (0x1:SHL:4) ;- (SDRC) Data Bus Width
-AT91C_SDRC_DBW_32_BITS    EQU (0x0:SHL:4) ;- (SDRC) 32 Bits datas bus
-AT91C_SDRC_DBW_16_BITS    EQU (0x1:SHL:4) ;- (SDRC) 16 Bits datas bus
-;- -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- 
-AT91C_SDRC_COUNT          EQU (0xFFF:SHL:0) ;- (SDRC) Refresh Counter
-;- -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- 
-AT91C_SDRC_NC             EQU (0x3:SHL:0) ;- (SDRC) Number of Column Bits
-AT91C_SDRC_NC_8           EQU (0x0) ;- (SDRC) 8 Bits
-AT91C_SDRC_NC_9           EQU (0x1) ;- (SDRC) 9 Bits
-AT91C_SDRC_NC_10          EQU (0x2) ;- (SDRC) 10 Bits
-AT91C_SDRC_NC_11          EQU (0x3) ;- (SDRC) 11 Bits
-AT91C_SDRC_NR             EQU (0x3:SHL:2) ;- (SDRC) Number of Row Bits
-AT91C_SDRC_NR_11          EQU (0x0:SHL:2) ;- (SDRC) 11 Bits
-AT91C_SDRC_NR_12          EQU (0x1:SHL:2) ;- (SDRC) 12 Bits
-AT91C_SDRC_NR_13          EQU (0x2:SHL:2) ;- (SDRC) 13 Bits
-AT91C_SDRC_NB             EQU (0x1:SHL:4) ;- (SDRC) Number of Banks
-AT91C_SDRC_NB_2_BANKS     EQU (0x0:SHL:4) ;- (SDRC) 2 banks
-AT91C_SDRC_NB_4_BANKS     EQU (0x1:SHL:4) ;- (SDRC) 4 banks
-AT91C_SDRC_CAS            EQU (0x3:SHL:5) ;- (SDRC) CAS Latency
-AT91C_SDRC_CAS_2          EQU (0x2:SHL:5) ;- (SDRC) 2 cycles
-AT91C_SDRC_TWR            EQU (0xF:SHL:7) ;- (SDRC) Number of Write Recovery Time Cycles
-AT91C_SDRC_TRC            EQU (0xF:SHL:11) ;- (SDRC) Number of RAS Cycle Time Cycles
-AT91C_SDRC_TRP            EQU (0xF:SHL:15) ;- (SDRC) Number of RAS Precharge Time Cycles
-AT91C_SDRC_TRCD           EQU (0xF:SHL:19) ;- (SDRC) Number of RAS to CAS Delay Cycles
-AT91C_SDRC_TRAS           EQU (0xF:SHL:23) ;- (SDRC) Number of RAS Active Time Cycles
-AT91C_SDRC_TXSR           EQU (0xF:SHL:27) ;- (SDRC) Number of Command Recovery Time Cycles
-;- -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- 
-AT91C_SDRC_SRCB           EQU (0x1:SHL:0) ;- (SDRC) Self-refresh Command Bit
-;- -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- 
-AT91C_SDRC_LPCB           EQU (0x1:SHL:0) ;- (SDRC) Low-power Command Bit
-;- -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- 
-AT91C_SDRC_RES            EQU (0x1:SHL:0) ;- (SDRC) Refresh Error Status
-;- -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- 
-;- -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- 
-;- -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- 
-
-;- *****************************************************************************
-;-              SOFTWARE API DEFINITION  FOR Burst Flash Controller Interface
-;- *****************************************************************************
-                ^ 0 ;- AT91S_BFC
-BFC_MR          #  4 ;- BFC Mode Register
-;- -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- 
-AT91C_BFC_BFCOM           EQU (0x3:SHL:0) ;- (BFC) Burst Flash Controller Operating Mode
-AT91C_BFC_BFCOM_DISABLED  EQU (0x0) ;- (BFC) NPCS0 is driven by the SMC or remains high.
-AT91C_BFC_BFCOM_ASYNC     EQU (0x1) ;- (BFC) Asynchronous
-AT91C_BFC_BFCOM_BURST_READ EQU (0x2) ;- (BFC) Burst Read
-AT91C_BFC_BFCC            EQU (0x3:SHL:2) ;- (BFC) Burst Flash Controller Operating Mode
-AT91C_BFC_BFCC_MCK        EQU (0x1:SHL:2) ;- (BFC) Master Clock.
-AT91C_BFC_BFCC_MCK_DIV_2  EQU (0x2:SHL:2) ;- (BFC) Master Clock divided by 2.
-AT91C_BFC_BFCC_MCK_DIV_4  EQU (0x3:SHL:2) ;- (BFC) Master Clock divided by 4.
-AT91C_BFC_AVL             EQU (0xF:SHL:4) ;- (BFC) Address Valid Latency
-AT91C_BFC_PAGES           EQU (0x7:SHL:8) ;- (BFC) Page Size
-AT91C_BFC_PAGES_NO_PAGE   EQU (0x0:SHL:8) ;- (BFC) No page handling.
-AT91C_BFC_PAGES_16        EQU (0x1:SHL:8) ;- (BFC) 16 bytes page size.
-AT91C_BFC_PAGES_32        EQU (0x2:SHL:8) ;- (BFC) 32 bytes page size.
-AT91C_BFC_PAGES_64        EQU (0x3:SHL:8) ;- (BFC) 64 bytes page size.
-AT91C_BFC_PAGES_128       EQU (0x4:SHL:8) ;- (BFC) 128 bytes page size.
-AT91C_BFC_PAGES_256       EQU (0x5:SHL:8) ;- (BFC) 256 bytes page size.
-AT91C_BFC_PAGES_512       EQU (0x6:SHL:8) ;- (BFC) 512 bytes page size.
-AT91C_BFC_PAGES_1024      EQU (0x7:SHL:8) ;- (BFC) 1024 bytes page size.
-AT91C_BFC_OEL             EQU (0x3:SHL:12) ;- (BFC) Output Enable Latency
-AT91C_BFC_BAAEN           EQU (0x1:SHL:16) ;- (BFC) Burst Address Advance Enable
-AT91C_BFC_BFOEH           EQU (0x1:SHL:17) ;- (BFC) Burst Flash Output Enable Handling
-AT91C_BFC_MUXEN           EQU (0x1:SHL:18) ;- (BFC) Multiplexed Bus Enable
-AT91C_BFC_RDYEN           EQU (0x1:SHL:19) ;- (BFC) Ready Enable Mode
-
-;- *****************************************************************************
-;-               REGISTER ADDRESS DEFINITION FOR AT91RM9200
-;- *****************************************************************************
-;- ========== Register definition for SYS peripheral ========== 
-;- ========== Register definition for MC peripheral ========== 
-AT91C_MC_PUER             EQU (0xFFFFFF54) ;- (MC) MC Protection Unit Enable Register
-AT91C_MC_ASR              EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
-AT91C_MC_PUP              EQU (0xFFFFFF50) ;- (MC) MC Protection Unit Peripherals
-AT91C_MC_PUIA             EQU (0xFFFFFF10) ;- (MC) MC Protection Unit Area
-AT91C_MC_AASR             EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
-AT91C_MC_RCR              EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
-;- ========== Register definition for RTC peripheral ========== 
-AT91C_RTC_IMR             EQU (0xFFFFFE28) ;- (RTC) Interrupt Mask Register
-AT91C_RTC_IER             EQU (0xFFFFFE20) ;- (RTC) Interrupt Enable Register
-AT91C_RTC_SR              EQU (0xFFFFFE18) ;- (RTC) Status Register
-AT91C_RTC_TIMALR          EQU (0xFFFFFE10) ;- (RTC) Time Alarm Register
-AT91C_RTC_TIMR            EQU (0xFFFFFE08) ;- (RTC) Time Register
-AT91C_RTC_CR              EQU (0xFFFFFE00) ;- (RTC) Control Register
-AT91C_RTC_VER             EQU (0xFFFFFE2C) ;- (RTC) Valid Entry Register
-AT91C_RTC_IDR             EQU (0xFFFFFE24) ;- (RTC) Interrupt Disable Register
-AT91C_RTC_SCCR            EQU (0xFFFFFE1C) ;- (RTC) Status Clear Command Register
-AT91C_RTC_CALALR          EQU (0xFFFFFE14) ;- (RTC) Calendar Alarm Register
-AT91C_RTC_CALR            EQU (0xFFFFFE0C) ;- (RTC) Calendar Register
-AT91C_RTC_MR              EQU (0xFFFFFE04) ;- (RTC) Mode Register
-;- ========== Register definition for ST peripheral ========== 
-AT91C_ST_CRTR             EQU (0xFFFFFD24) ;- (ST) Current Real-time Register
-AT91C_ST_IMR              EQU (0xFFFFFD1C) ;- (ST) Interrupt Mask Register
-AT91C_ST_IER              EQU (0xFFFFFD14) ;- (ST) Interrupt Enable Register
-AT91C_ST_RTMR             EQU (0xFFFFFD0C) ;- (ST) Real-time Mode Register
-AT91C_ST_PIMR             EQU (0xFFFFFD04) ;- (ST) Period Interval Mode Register
-AT91C_ST_RTAR             EQU (0xFFFFFD20) ;- (ST) Real-time Alarm Register
-AT91C_ST_IDR              EQU (0xFFFFFD18) ;- (ST) Interrupt Disable Register
-AT91C_ST_SR               EQU (0xFFFFFD10) ;- (ST) Status Register
-AT91C_ST_WDMR             EQU (0xFFFFFD08) ;- (ST) Watchdog Mode Register
-AT91C_ST_CR               EQU (0xFFFFFD00) ;- (ST) Control Register
-;- ========== Register definition for PMC peripheral ========== 
-AT91C_PMC_SCSR            EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
-AT91C_PMC_SCER            EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
-AT91C_PMC_IMR             EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
-AT91C_PMC_IDR             EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
-AT91C_PMC_PCDR            EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
-AT91C_PMC_SCDR            EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
-AT91C_PMC_SR              EQU (0xFFFFFC68) ;- (PMC) Status Register
-AT91C_PMC_IER             EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
-AT91C_PMC_MCKR            EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
-AT91C_PMC_PCER            EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
-AT91C_PMC_PCSR            EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
-AT91C_PMC_PCKR            EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
-;- ========== Register definition for CKGR peripheral ========== 
-AT91C_CKGR_PLLBR          EQU (0xFFFFFC2C) ;- (CKGR) PLL B Register
-AT91C_CKGR_MCFR           EQU (0xFFFFFC24) ;- (CKGR) Main Clock  Frequency Register
-AT91C_CKGR_PLLAR          EQU (0xFFFFFC28) ;- (CKGR) PLL A Register
-AT91C_CKGR_MOR            EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
-;- ========== Register definition for PIOD peripheral ========== 
-AT91C_PIOD_PDSR           EQU (0xFFFFFA3C) ;- (PIOD) Pin Data Status Register
-AT91C_PIOD_CODR           EQU (0xFFFFFA34) ;- (PIOD) Clear Output Data Register
-AT91C_PIOD_OWER           EQU (0xFFFFFAA0) ;- (PIOD) Output Write Enable Register
-AT91C_PIOD_MDER           EQU (0xFFFFFA50) ;- (PIOD) Multi-driver Enable Register
-AT91C_PIOD_IMR            EQU (0xFFFFFA48) ;- (PIOD) Interrupt Mask Register
-AT91C_PIOD_IER            EQU (0xFFFFFA40) ;- (PIOD) Interrupt Enable Register
-AT91C_PIOD_ODSR           EQU (0xFFFFFA38) ;- (PIOD) Output Data Status Register
-AT91C_PIOD_SODR           EQU (0xFFFFFA30) ;- (PIOD) Set Output Data Register
-AT91C_PIOD_PER            EQU (0xFFFFFA00) ;- (PIOD) PIO Enable Register
-AT91C_PIOD_OWDR           EQU (0xFFFFFAA4) ;- (PIOD) Output Write Disable Register
-AT91C_PIOD_PPUER          EQU (0xFFFFFA64) ;- (PIOD) Pull-up Enable Register
-AT91C_PIOD_MDDR           EQU (0xFFFFFA54) ;- (PIOD) Multi-driver Disable Register
-AT91C_PIOD_ISR            EQU (0xFFFFFA4C) ;- (PIOD) Interrupt Status Register
-AT91C_PIOD_IDR            EQU (0xFFFFFA44) ;- (PIOD) Interrupt Disable Register
-AT91C_PIOD_PDR            EQU (0xFFFFFA04) ;- (PIOD) PIO Disable Register
-AT91C_PIOD_ODR            EQU (0xFFFFFA14) ;- (PIOD) Output Disable Registerr
-AT91C_PIOD_OWSR           EQU (0xFFFFFAA8) ;- (PIOD) Output Write Status Register
-AT91C_PIOD_ABSR           EQU (0xFFFFFA78) ;- (PIOD) AB Select Status Register
-AT91C_PIOD_ASR            EQU (0xFFFFFA70) ;- (PIOD) Select A Register
-AT91C_PIOD_PPUSR          EQU (0xFFFFFA68) ;- (PIOD) Pad Pull-up Status Register
-AT91C_PIOD_PPUDR          EQU (0xFFFFFA60) ;- (PIOD) Pull-up Disable Register
-AT91C_PIOD_MDSR           EQU (0xFFFFFA58) ;- (PIOD) Multi-driver Status Register
-AT91C_PIOD_PSR            EQU (0xFFFFFA08) ;- (PIOD) PIO Status Register
-AT91C_PIOD_OER            EQU (0xFFFFFA10) ;- (PIOD) Output Enable Register
-AT91C_PIOD_OSR            EQU (0xFFFFFA18) ;- (PIOD) Output Status Register
-AT91C_PIOD_IFER           EQU (0xFFFFFA20) ;- (PIOD) Input Filter Enable Register
-AT91C_PIOD_BSR            EQU (0xFFFFFA74) ;- (PIOD) Select B Register
-AT91C_PIOD_IFDR           EQU (0xFFFFFA24) ;- (PIOD) Input Filter Disable Register
-AT91C_PIOD_IFSR           EQU (0xFFFFFA28) ;- (PIOD) Input Filter Status Register
-;- ========== Register definition for PIOC peripheral ========== 
-AT91C_PIOC_IFDR           EQU (0xFFFFF824) ;- (PIOC) Input Filter Disable Register
-AT91C_PIOC_ODR            EQU (0xFFFFF814) ;- (PIOC) Output Disable Registerr
-AT91C_PIOC_ABSR           EQU (0xFFFFF878) ;- (PIOC) AB Select Status Register
-AT91C_PIOC_SODR           EQU (0xFFFFF830) ;- (PIOC) Set Output Data Register
-AT91C_PIOC_IFSR           EQU (0xFFFFF828) ;- (PIOC) Input Filter Status Register
-AT91C_PIOC_CODR           EQU (0xFFFFF834) ;- (PIOC) Clear Output Data Register
-AT91C_PIOC_ODSR           EQU (0xFFFFF838) ;- (PIOC) Output Data Status Register
-AT91C_PIOC_IER            EQU (0xFFFFF840) ;- (PIOC) Interrupt Enable Register
-AT91C_PIOC_IMR            EQU (0xFFFFF848) ;- (PIOC) Interrupt Mask Register
-AT91C_PIOC_OWDR           EQU (0xFFFFF8A4) ;- (PIOC) Output Write Disable Register
-AT91C_PIOC_MDDR           EQU (0xFFFFF854) ;- (PIOC) Multi-driver Disable Register
-AT91C_PIOC_PDSR           EQU (0xFFFFF83C) ;- (PIOC) Pin Data Status Register
-AT91C_PIOC_IDR            EQU (0xFFFFF844) ;- (PIOC) Interrupt Disable Register
-AT91C_PIOC_ISR            EQU (0xFFFFF84C) ;- (PIOC) Interrupt Status Register
-AT91C_PIOC_PDR            EQU (0xFFFFF804) ;- (PIOC) PIO Disable Register
-AT91C_PIOC_OWSR           EQU (0xFFFFF8A8) ;- (PIOC) Output Write Status Register
-AT91C_PIOC_OWER           EQU (0xFFFFF8A0) ;- (PIOC) Output Write Enable Register
-AT91C_PIOC_ASR            EQU (0xFFFFF870) ;- (PIOC) Select A Register
-AT91C_PIOC_PPUSR          EQU (0xFFFFF868) ;- (PIOC) Pad Pull-up Status Register
-AT91C_PIOC_PPUDR          EQU (0xFFFFF860) ;- (PIOC) Pull-up Disable Register
-AT91C_PIOC_MDSR           EQU (0xFFFFF858) ;- (PIOC) Multi-driver Status Register
-AT91C_PIOC_MDER           EQU (0xFFFFF850) ;- (PIOC) Multi-driver Enable Register
-AT91C_PIOC_IFER           EQU (0xFFFFF820) ;- (PIOC) Input Filter Enable Register
-AT91C_PIOC_OSR            EQU (0xFFFFF818) ;- (PIOC) Output Status Register
-AT91C_PIOC_OER            EQU (0xFFFFF810) ;- (PIOC) Output Enable Register
-AT91C_PIOC_PSR            EQU (0xFFFFF808) ;- (PIOC) PIO Status Register
-AT91C_PIOC_PER            EQU (0xFFFFF800) ;- (PIOC) PIO Enable Register
-AT91C_PIOC_BSR            EQU (0xFFFFF874) ;- (PIOC) Select B Register
-AT91C_PIOC_PPUER          EQU (0xFFFFF864) ;- (PIOC) Pull-up Enable Register
-;- ========== Register definition for PIOB peripheral ========== 
-AT91C_PIOB_OWSR           EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
-AT91C_PIOB_PPUSR          EQU (0xFFFFF668) ;- (PIOB) Pad Pull-up Status Register
-AT91C_PIOB_PPUDR          EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
-AT91C_PIOB_MDSR           EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
-AT91C_PIOB_MDER           EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
-AT91C_PIOB_IMR            EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
-AT91C_PIOB_OSR            EQU (0xFFFFF618) ;- (PIOB) Output Status Register
-AT91C_PIOB_OER            EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
-AT91C_PIOB_PSR            EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
-AT91C_PIOB_PER            EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
-AT91C_PIOB_BSR            EQU (0xFFFFF674) ;- (PIOB) Select B Register
-AT91C_PIOB_PPUER          EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
-AT91C_PIOB_IFDR           EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
-AT91C_PIOB_ODR            EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
-AT91C_PIOB_ABSR           EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
-AT91C_PIOB_ASR            EQU (0xFFFFF670) ;- (PIOB) Select A Register
-AT91C_PIOB_IFER           EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
-AT91C_PIOB_IFSR           EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
-AT91C_PIOB_SODR           EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
-AT91C_PIOB_ODSR           EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
-AT91C_PIOB_CODR           EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
-AT91C_PIOB_PDSR           EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
-AT91C_PIOB_OWER           EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
-AT91C_PIOB_IER            EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
-AT91C_PIOB_OWDR           EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
-AT91C_PIOB_MDDR           EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
-AT91C_PIOB_ISR            EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
-AT91C_PIOB_IDR            EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
-AT91C_PIOB_PDR            EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
-;- ========== Register definition for PIOA peripheral ========== 
-AT91C_PIOA_IMR            EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
-AT91C_PIOA_IER            EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
-AT91C_PIOA_OWDR           EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
-AT91C_PIOA_ISR            EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
-AT91C_PIOA_PPUDR          EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
-AT91C_PIOA_MDSR           EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
-AT91C_PIOA_MDER           EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
-AT91C_PIOA_PER            EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
-AT91C_PIOA_PSR            EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
-AT91C_PIOA_OER            EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
-AT91C_PIOA_BSR            EQU (0xFFFFF474) ;- (PIOA) Select B Register
-AT91C_PIOA_PPUER          EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
-AT91C_PIOA_MDDR           EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
-AT91C_PIOA_PDR            EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
-AT91C_PIOA_ODR            EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
-AT91C_PIOA_IFDR           EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
-AT91C_PIOA_ABSR           EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
-AT91C_PIOA_ASR            EQU (0xFFFFF470) ;- (PIOA) Select A Register
-AT91C_PIOA_PPUSR          EQU (0xFFFFF468) ;- (PIOA) Pad Pull-up Status Register
-AT91C_PIOA_ODSR           EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
-AT91C_PIOA_SODR           EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
-AT91C_PIOA_IFSR           EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
-AT91C_PIOA_IFER           EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
-AT91C_PIOA_OSR            EQU (0xFFFFF418) ;- (PIOA) Output Status Register
-AT91C_PIOA_IDR            EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
-AT91C_PIOA_PDSR           EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
-AT91C_PIOA_CODR           EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
-AT91C_PIOA_OWSR           EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
-AT91C_PIOA_OWER           EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
-;- ========== Register definition for DBGU peripheral ========== 
-AT91C_DBGU_C2R            EQU (0xFFFFF244) ;- (DBGU) Chip ID2 Register
-AT91C_DBGU_THR            EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
-AT91C_DBGU_CSR            EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
-AT91C_DBGU_IDR            EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
-AT91C_DBGU_MR             EQU (0xFFFFF204) ;- (DBGU) Mode Register
-AT91C_DBGU_FNTR           EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
-AT91C_DBGU_C1R            EQU (0xFFFFF240) ;- (DBGU) Chip ID1 Register
-AT91C_DBGU_BRGR           EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
-AT91C_DBGU_RHR            EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
-AT91C_DBGU_IMR            EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
-AT91C_DBGU_IER            EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
-AT91C_DBGU_CR             EQU (0xFFFFF200) ;- (DBGU) Control Register
-;- ========== Register definition for PDC_DBGU peripheral ========== 
-AT91C_DBGU_TNCR           EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
-AT91C_DBGU_RNCR           EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
-AT91C_DBGU_PTCR           EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
-AT91C_DBGU_PTSR           EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
-AT91C_DBGU_RCR            EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
-AT91C_DBGU_TCR            EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
-AT91C_DBGU_RPR            EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
-AT91C_DBGU_TPR            EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
-AT91C_DBGU_RNPR           EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
-AT91C_DBGU_TNPR           EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
-;- ========== Register definition for AIC peripheral ========== 
-AT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
-AT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
-AT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode Register
-AT91C_AIC_ISCR            EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
-AT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
-AT91C_AIC_DCR             EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
-AT91C_AIC_FFER            EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
-AT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector Register
-AT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
-AT91C_AIC_FFDR            EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
-AT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
-AT91C_AIC_FFSR            EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
-AT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
-AT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
-AT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
-AT91C_AIC_IDCR            EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
-AT91C_AIC_CISR            EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
-AT91C_AIC_IPR             EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
-;- ========== Register definition for PDC_SPI peripheral ========== 
-AT91C_SPI_PTCR            EQU (0xFFFE0120) ;- (PDC_SPI) PDC Transfer Control Register
-AT91C_SPI_TNPR            EQU (0xFFFE0118) ;- (PDC_SPI) Transmit Next Pointer Register
-AT91C_SPI_RNPR            EQU (0xFFFE0110) ;- (PDC_SPI) Receive Next Pointer Register
-AT91C_SPI_TPR             EQU (0xFFFE0108) ;- (PDC_SPI) Transmit Pointer Register
-AT91C_SPI_RPR             EQU (0xFFFE0100) ;- (PDC_SPI) Receive Pointer Register
-AT91C_SPI_PTSR            EQU (0xFFFE0124) ;- (PDC_SPI) PDC Transfer Status Register
-AT91C_SPI_TNCR            EQU (0xFFFE011C) ;- (PDC_SPI) Transmit Next Counter Register
-AT91C_SPI_RNCR            EQU (0xFFFE0114) ;- (PDC_SPI) Receive Next Counter Register
-AT91C_SPI_TCR             EQU (0xFFFE010C) ;- (PDC_SPI) Transmit Counter Register
-AT91C_SPI_RCR             EQU (0xFFFE0104) ;- (PDC_SPI) Receive Counter Register
-;- ========== Register definition for SPI peripheral ========== 
-AT91C_SPI_CSR             EQU (0xFFFE0030) ;- (SPI) Chip Select Register
-AT91C_SPI_IDR             EQU (0xFFFE0018) ;- (SPI) Interrupt Disable Register
-AT91C_SPI_SR              EQU (0xFFFE0010) ;- (SPI) Status Register
-AT91C_SPI_RDR             EQU (0xFFFE0008) ;- (SPI) Receive Data Register
-AT91C_SPI_CR              EQU (0xFFFE0000) ;- (SPI) Control Register
-AT91C_SPI_IMR             EQU (0xFFFE001C) ;- (SPI) Interrupt Mask Register
-AT91C_SPI_IER             EQU (0xFFFE0014) ;- (SPI) Interrupt Enable Register
-AT91C_SPI_TDR             EQU (0xFFFE000C) ;- (SPI) Transmit Data Register
-AT91C_SPI_MR              EQU (0xFFFE0004) ;- (SPI) Mode Register
-;- ========== Register definition for PDC_SSC2 peripheral ========== 
-AT91C_SSC2_PTCR           EQU (0xFFFD8120) ;- (PDC_SSC2) PDC Transfer Control Register
-AT91C_SSC2_TNPR           EQU (0xFFFD8118) ;- (PDC_SSC2) Transmit Next Pointer Register
-AT91C_SSC2_RNPR           EQU (0xFFFD8110) ;- (PDC_SSC2) Receive Next Pointer Register
-AT91C_SSC2_TPR            EQU (0xFFFD8108) ;- (PDC_SSC2) Transmit Pointer Register
-AT91C_SSC2_RPR            EQU (0xFFFD8100) ;- (PDC_SSC2) Receive Pointer Register
-AT91C_SSC2_PTSR           EQU (0xFFFD8124) ;- (PDC_SSC2) PDC Transfer Status Register
-AT91C_SSC2_TNCR           EQU (0xFFFD811C) ;- (PDC_SSC2) Transmit Next Counter Register
-AT91C_SSC2_RNCR           EQU (0xFFFD8114) ;- (PDC_SSC2) Receive Next Counter Register
-AT91C_SSC2_TCR            EQU (0xFFFD810C) ;- (PDC_SSC2) Transmit Counter Register
-AT91C_SSC2_RCR            EQU (0xFFFD8104) ;- (PDC_SSC2) Receive Counter Register
-;- ========== Register definition for SSC2 peripheral ========== 
-AT91C_SSC2_IMR            EQU (0xFFFD804C) ;- (SSC2) Interrupt Mask Register
-AT91C_SSC2_IER            EQU (0xFFFD8044) ;- (SSC2) Interrupt Enable Register
-AT91C_SSC2_RC1R           EQU (0xFFFD803C) ;- (SSC2) Receive Compare 1 Register
-AT91C_SSC2_TSHR           EQU (0xFFFD8034) ;- (SSC2) Transmit Sync Holding Register
-AT91C_SSC2_CMR            EQU (0xFFFD8004) ;- (SSC2) Clock Mode Register
-AT91C_SSC2_IDR            EQU (0xFFFD8048) ;- (SSC2) Interrupt Disable Register
-AT91C_SSC2_TCMR           EQU (0xFFFD8018) ;- (SSC2) Transmit Clock Mode Register
-AT91C_SSC2_RCMR           EQU (0xFFFD8010) ;- (SSC2) Receive Clock ModeRegister
-AT91C_SSC2_CR             EQU (0xFFFD8000) ;- (SSC2) Control Register
-AT91C_SSC2_RFMR           EQU (0xFFFD8014) ;- (SSC2) Receive Frame Mode Register
-AT91C_SSC2_TFMR           EQU (0xFFFD801C) ;- (SSC2) Transmit Frame Mode Register
-AT91C_SSC2_THR            EQU (0xFFFD8024) ;- (SSC2) Transmit Holding Register
-AT91C_SSC2_SR             EQU (0xFFFD8040) ;- (SSC2) Status Register
-AT91C_SSC2_RC0R           EQU (0xFFFD8038) ;- (SSC2) Receive Compare 0 Register
-AT91C_SSC2_RSHR           EQU (0xFFFD8030) ;- (SSC2) Receive Sync Holding Register
-AT91C_SSC2_RHR            EQU (0xFFFD8020) ;- (SSC2) Receive Holding Register
-;- ========== Register definition for PDC_SSC1 peripheral ========== 
-AT91C_SSC1_PTCR           EQU (0xFFFD4120) ;- (PDC_SSC1) PDC Transfer Control Register
-AT91C_SSC1_TNPR           EQU (0xFFFD4118) ;- (PDC_SSC1) Transmit Next Pointer Register
-AT91C_SSC1_RNPR           EQU (0xFFFD4110) ;- (PDC_SSC1) Receive Next Pointer Register
-AT91C_SSC1_TPR            EQU (0xFFFD4108) ;- (PDC_SSC1) Transmit Pointer Register
-AT91C_SSC1_RPR            EQU (0xFFFD4100) ;- (PDC_SSC1) Receive Pointer Register
-AT91C_SSC1_PTSR           EQU (0xFFFD4124) ;- (PDC_SSC1) PDC Transfer Status Register
-AT91C_SSC1_TNCR           EQU (0xFFFD411C) ;- (PDC_SSC1) Transmit Next Counter Register
-AT91C_SSC1_RNCR           EQU (0xFFFD4114) ;- (PDC_SSC1) Receive Next Counter Register
-AT91C_SSC1_TCR            EQU (0xFFFD410C) ;- (PDC_SSC1) Transmit Counter Register
-AT91C_SSC1_RCR            EQU (0xFFFD4104) ;- (PDC_SSC1) Receive Counter Register
-;- ========== Register definition for SSC1 peripheral ========== 
-AT91C_SSC1_RFMR           EQU (0xFFFD4014) ;- (SSC1) Receive Frame Mode Register
-AT91C_SSC1_CMR            EQU (0xFFFD4004) ;- (SSC1) Clock Mode Register
-AT91C_SSC1_IDR            EQU (0xFFFD4048) ;- (SSC1) Interrupt Disable Register
-AT91C_SSC1_SR             EQU (0xFFFD4040) ;- (SSC1) Status Register
-AT91C_SSC1_RC0R           EQU (0xFFFD4038) ;- (SSC1) Receive Compare 0 Register
-AT91C_SSC1_RSHR           EQU (0xFFFD4030) ;- (SSC1) Receive Sync Holding Register
-AT91C_SSC1_RHR            EQU (0xFFFD4020) ;- (SSC1) Receive Holding Register
-AT91C_SSC1_TCMR           EQU (0xFFFD4018) ;- (SSC1) Transmit Clock Mode Register
-AT91C_SSC1_RCMR           EQU (0xFFFD4010) ;- (SSC1) Receive Clock ModeRegister
-AT91C_SSC1_CR             EQU (0xFFFD4000) ;- (SSC1) Control Register
-AT91C_SSC1_IMR            EQU (0xFFFD404C) ;- (SSC1) Interrupt Mask Register
-AT91C_SSC1_IER            EQU (0xFFFD4044) ;- (SSC1) Interrupt Enable Register
-AT91C_SSC1_RC1R           EQU (0xFFFD403C) ;- (SSC1) Receive Compare 1 Register
-AT91C_SSC1_TSHR           EQU (0xFFFD4034) ;- (SSC1) Transmit Sync Holding Register
-AT91C_SSC1_THR            EQU (0xFFFD4024) ;- (SSC1) Transmit Holding Register
-AT91C_SSC1_TFMR           EQU (0xFFFD401C) ;- (SSC1) Transmit Frame Mode Register
-;- ========== Register definition for PDC_SSC0 peripheral ========== 
-AT91C_SSC0_PTCR           EQU (0xFFFD0120) ;- (PDC_SSC0) PDC Transfer Control Register
-AT91C_SSC0_TNPR           EQU (0xFFFD0118) ;- (PDC_SSC0) Transmit Next Pointer Register
-AT91C_SSC0_RNPR           EQU (0xFFFD0110) ;- (PDC_SSC0) Receive Next Pointer Register
-AT91C_SSC0_TPR            EQU (0xFFFD0108) ;- (PDC_SSC0) Transmit Pointer Register
-AT91C_SSC0_RPR            EQU (0xFFFD0100) ;- (PDC_SSC0) Receive Pointer Register
-AT91C_SSC0_PTSR           EQU (0xFFFD0124) ;- (PDC_SSC0) PDC Transfer Status Register
-AT91C_SSC0_TNCR           EQU (0xFFFD011C) ;- (PDC_SSC0) Transmit Next Counter Register
-AT91C_SSC0_RNCR           EQU (0xFFFD0114) ;- (PDC_SSC0) Receive Next Counter Register
-AT91C_SSC0_TCR            EQU (0xFFFD010C) ;- (PDC_SSC0) Transmit Counter Register
-AT91C_SSC0_RCR            EQU (0xFFFD0104) ;- (PDC_SSC0) Receive Counter Register
-;- ========== Register definition for SSC0 peripheral ========== 
-AT91C_SSC0_IMR            EQU (0xFFFD004C) ;- (SSC0) Interrupt Mask Register
-AT91C_SSC0_IER            EQU (0xFFFD0044) ;- (SSC0) Interrupt Enable Register
-AT91C_SSC0_RC1R           EQU (0xFFFD003C) ;- (SSC0) Receive Compare 1 Register
-AT91C_SSC0_TSHR           EQU (0xFFFD0034) ;- (SSC0) Transmit Sync Holding Register
-AT91C_SSC0_THR            EQU (0xFFFD0024) ;- (SSC0) Transmit Holding Register
-AT91C_SSC0_TFMR           EQU (0xFFFD001C) ;- (SSC0) Transmit Frame Mode Register
-AT91C_SSC0_RFMR           EQU (0xFFFD0014) ;- (SSC0) Receive Frame Mode Register
-AT91C_SSC0_CMR            EQU (0xFFFD0004) ;- (SSC0) Clock Mode Register
-AT91C_SSC0_IDR            EQU (0xFFFD0048) ;- (SSC0) Interrupt Disable Register
-AT91C_SSC0_SR             EQU (0xFFFD0040) ;- (SSC0) Status Register
-AT91C_SSC0_RC0R           EQU (0xFFFD0038) ;- (SSC0) Receive Compare 0 Register
-AT91C_SSC0_RSHR           EQU (0xFFFD0030) ;- (SSC0) Receive Sync Holding Register
-AT91C_SSC0_RHR            EQU (0xFFFD0020) ;- (SSC0) Receive Holding Register
-AT91C_SSC0_TCMR           EQU (0xFFFD0018) ;- (SSC0) Transmit Clock Mode Register
-AT91C_SSC0_RCMR           EQU (0xFFFD0010) ;- (SSC0) Receive Clock ModeRegister
-AT91C_SSC0_CR             EQU (0xFFFD0000) ;- (SSC0) Control Register
-;- ========== Register definition for PDC_US3 peripheral ========== 
-AT91C_US3_PTSR            EQU (0xFFFCC124) ;- (PDC_US3) PDC Transfer Status Register
-AT91C_US3_TNCR            EQU (0xFFFCC11C) ;- (PDC_US3) Transmit Next Counter Register
-AT91C_US3_RNCR            EQU (0xFFFCC114) ;- (PDC_US3) Receive Next Counter Register
-AT91C_US3_TCR             EQU (0xFFFCC10C) ;- (PDC_US3) Transmit Counter Register
-AT91C_US3_RCR             EQU (0xFFFCC104) ;- (PDC_US3) Receive Counter Register
-AT91C_US3_PTCR            EQU (0xFFFCC120) ;- (PDC_US3) PDC Transfer Control Register
-AT91C_US3_TNPR            EQU (0xFFFCC118) ;- (PDC_US3) Transmit Next Pointer Register
-AT91C_US3_RNPR            EQU (0xFFFCC110) ;- (PDC_US3) Receive Next Pointer Register
-AT91C_US3_TPR             EQU (0xFFFCC108) ;- (PDC_US3) Transmit Pointer Register
-AT91C_US3_RPR             EQU (0xFFFCC100) ;- (PDC_US3) Receive Pointer Register
-;- ========== Register definition for US3 peripheral ========== 
-AT91C_US3_IF              EQU (0xFFFCC04C) ;- (US3) IRDA_FILTER Register
-AT91C_US3_NER             EQU (0xFFFCC044) ;- (US3) Nb Errors Register
-AT91C_US3_RTOR            EQU (0xFFFCC024) ;- (US3) Receiver Time-out Register
-AT91C_US3_THR             EQU (0xFFFCC01C) ;- (US3) Transmitter Holding Register
-AT91C_US3_CSR             EQU (0xFFFCC014) ;- (US3) Channel Status Register
-AT91C_US3_IDR             EQU (0xFFFCC00C) ;- (US3) Interrupt Disable Register
-AT91C_US3_MR              EQU (0xFFFCC004) ;- (US3) Mode Register
-AT91C_US3_XXR             EQU (0xFFFCC048) ;- (US3) XON_XOFF Register
-AT91C_US3_FIDI            EQU (0xFFFCC040) ;- (US3) FI_DI_Ratio Register
-AT91C_US3_TTGR            EQU (0xFFFCC028) ;- (US3) Transmitter Time-guard Register
-AT91C_US3_BRGR            EQU (0xFFFCC020) ;- (US3) Baud Rate Generator Register
-AT91C_US3_RHR             EQU (0xFFFCC018) ;- (US3) Receiver Holding Register
-AT91C_US3_IMR             EQU (0xFFFCC010) ;- (US3) Interrupt Mask Register
-AT91C_US3_IER             EQU (0xFFFCC008) ;- (US3) Interrupt Enable Register
-AT91C_US3_CR              EQU (0xFFFCC000) ;- (US3) Control Register
-;- ========== Register definition for PDC_US2 peripheral ========== 
-AT91C_US2_PTSR            EQU (0xFFFC8124) ;- (PDC_US2) PDC Transfer Status Register
-AT91C_US2_TNCR            EQU (0xFFFC811C) ;- (PDC_US2) Transmit Next Counter Register
-AT91C_US2_RNCR            EQU (0xFFFC8114) ;- (PDC_US2) Receive Next Counter Register
-AT91C_US2_TCR             EQU (0xFFFC810C) ;- (PDC_US2) Transmit Counter Register
-AT91C_US2_PTCR            EQU (0xFFFC8120) ;- (PDC_US2) PDC Transfer Control Register
-AT91C_US2_RCR             EQU (0xFFFC8104) ;- (PDC_US2) Receive Counter Register
-AT91C_US2_TNPR            EQU (0xFFFC8118) ;- (PDC_US2) Transmit Next Pointer Register
-AT91C_US2_RPR             EQU (0xFFFC8100) ;- (PDC_US2) Receive Pointer Register
-AT91C_US2_TPR             EQU (0xFFFC8108) ;- (PDC_US2) Transmit Pointer Register
-AT91C_US2_RNPR            EQU (0xFFFC8110) ;- (PDC_US2) Receive Next Pointer Register
-;- ========== Register definition for US2 peripheral ========== 
-AT91C_US2_XXR             EQU (0xFFFC8048) ;- (US2) XON_XOFF Register
-AT91C_US2_FIDI            EQU (0xFFFC8040) ;- (US2) FI_DI_Ratio Register
-AT91C_US2_TTGR            EQU (0xFFFC8028) ;- (US2) Transmitter Time-guard Register
-AT91C_US2_BRGR            EQU (0xFFFC8020) ;- (US2) Baud Rate Generator Register
-AT91C_US2_RHR             EQU (0xFFFC8018) ;- (US2) Receiver Holding Register
-AT91C_US2_IMR             EQU (0xFFFC8010) ;- (US2) Interrupt Mask Register
-AT91C_US2_IER             EQU (0xFFFC8008) ;- (US2) Interrupt Enable Register
-AT91C_US2_CR              EQU (0xFFFC8000) ;- (US2) Control Register
-AT91C_US2_IF              EQU (0xFFFC804C) ;- (US2) IRDA_FILTER Register
-AT91C_US2_NER             EQU (0xFFFC8044) ;- (US2) Nb Errors Register
-AT91C_US2_RTOR            EQU (0xFFFC8024) ;- (US2) Receiver Time-out Register
-AT91C_US2_THR             EQU (0xFFFC801C) ;- (US2) Transmitter Holding Register
-AT91C_US2_CSR             EQU (0xFFFC8014) ;- (US2) Channel Status Register
-AT91C_US2_IDR             EQU (0xFFFC800C) ;- (US2) Interrupt Disable Register
-AT91C_US2_MR              EQU (0xFFFC8004) ;- (US2) Mode Register
-;- ========== Register definition for PDC_US1 peripheral ========== 
-AT91C_US1_PTSR            EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
-AT91C_US1_TNCR            EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
-AT91C_US1_RNCR            EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
-AT91C_US1_TCR             EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
-AT91C_US1_RCR             EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
-AT91C_US1_PTCR            EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
-AT91C_US1_TNPR            EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
-AT91C_US1_RNPR            EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
-AT91C_US1_TPR             EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
-AT91C_US1_RPR             EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
-;- ========== Register definition for US1 peripheral ========== 
-AT91C_US1_XXR             EQU (0xFFFC4048) ;- (US1) XON_XOFF Register
-AT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
-AT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
-AT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
-AT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register
-AT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
-AT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
-AT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register
-AT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
-AT91C_US1_FIDI            EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
-AT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
-AT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
-AT91C_US1_IF              EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
-AT91C_US1_NER             EQU (0xFFFC4044) ;- (US1) Nb Errors Register
-AT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register
-;- ========== Register definition for PDC_US0 peripheral ========== 
-AT91C_US0_PTCR            EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
-AT91C_US0_TNPR            EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
-AT91C_US0_RNPR            EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
-AT91C_US0_TPR             EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
-AT91C_US0_RPR             EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
-AT91C_US0_PTSR            EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
-AT91C_US0_TNCR            EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
-AT91C_US0_RNCR            EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
-AT91C_US0_TCR             EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
-AT91C_US0_RCR             EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
-;- ========== Register definition for US0 peripheral ========== 
-AT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
-AT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
-AT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
-AT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
-AT91C_US0_NER             EQU (0xFFFC0044) ;- (US0) Nb Errors Register
-AT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
-AT91C_US0_XXR             EQU (0xFFFC0048) ;- (US0) XON_XOFF Register
-AT91C_US0_FIDI            EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
-AT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register
-AT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
-AT91C_US0_IF              EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
-AT91C_US0_MR              EQU (0xFFFC0004) ;- (US0) Mode Register
-AT91C_US0_IDR             EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
-AT91C_US0_CSR             EQU (0xFFFC0014) ;- (US0) Channel Status Register
-AT91C_US0_THR             EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
-;- ========== Register definition for TWI peripheral ========== 
-AT91C_TWI_RHR             EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
-AT91C_TWI_IDR             EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
-AT91C_TWI_SR              EQU (0xFFFB8020) ;- (TWI) Status Register
-AT91C_TWI_CWGR            EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
-AT91C_TWI_SMR             EQU (0xFFFB8008) ;- (TWI) Slave Mode Register
-AT91C_TWI_CR              EQU (0xFFFB8000) ;- (TWI) Control Register
-AT91C_TWI_THR             EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
-AT91C_TWI_IMR             EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
-AT91C_TWI_IER             EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
-AT91C_TWI_IADR            EQU (0xFFFB800C) ;- (TWI) Internal Address Register
-AT91C_TWI_MMR             EQU (0xFFFB8004) ;- (TWI) Master Mode Register
-;- ========== Register definition for PDC_MCI peripheral ========== 
-AT91C_MCI_PTCR            EQU (0xFFFB4120) ;- (PDC_MCI) PDC Transfer Control Register
-AT91C_MCI_TNPR            EQU (0xFFFB4118) ;- (PDC_MCI) Transmit Next Pointer Register
-AT91C_MCI_RNPR            EQU (0xFFFB4110) ;- (PDC_MCI) Receive Next Pointer Register
-AT91C_MCI_TPR             EQU (0xFFFB4108) ;- (PDC_MCI) Transmit Pointer Register
-AT91C_MCI_RPR             EQU (0xFFFB4100) ;- (PDC_MCI) Receive Pointer Register
-AT91C_MCI_PTSR            EQU (0xFFFB4124) ;- (PDC_MCI) PDC Transfer Status Register
-AT91C_MCI_TNCR            EQU (0xFFFB411C) ;- (PDC_MCI) Transmit Next Counter Register
-AT91C_MCI_RNCR            EQU (0xFFFB4114) ;- (PDC_MCI) Receive Next Counter Register
-AT91C_MCI_TCR             EQU (0xFFFB410C) ;- (PDC_MCI) Transmit Counter Register
-AT91C_MCI_RCR             EQU (0xFFFB4104) ;- (PDC_MCI) Receive Counter Register
-;- ========== Register definition for MCI peripheral ========== 
-AT91C_MCI_IDR             EQU (0xFFFB4048) ;- (MCI) MCI Interrupt Disable Register
-AT91C_MCI_SR              EQU (0xFFFB4040) ;- (MCI) MCI Status Register
-AT91C_MCI_RDR             EQU (0xFFFB4030) ;- (MCI) MCI Receive Data Register
-AT91C_MCI_RSPR            EQU (0xFFFB4020) ;- (MCI) MCI Response Register
-AT91C_MCI_ARGR            EQU (0xFFFB4010) ;- (MCI) MCI Argument Register
-AT91C_MCI_DTOR            EQU (0xFFFB4008) ;- (MCI) MCI Data Timeout Register
-AT91C_MCI_CR              EQU (0xFFFB4000) ;- (MCI) MCI Control Register
-AT91C_MCI_IMR             EQU (0xFFFB404C) ;- (MCI) MCI Interrupt Mask Register
-AT91C_MCI_IER             EQU (0xFFFB4044) ;- (MCI) MCI Interrupt Enable Register
-AT91C_MCI_TDR             EQU (0xFFFB4034) ;- (MCI) MCI Transmit Data Register
-AT91C_MCI_CMDR            EQU (0xFFFB4014) ;- (MCI) MCI Command Register
-AT91C_MCI_SDCR            EQU (0xFFFB400C) ;- (MCI) MCI SD Card Register
-AT91C_MCI_MR              EQU (0xFFFB4004) ;- (MCI) MCI Mode Register
-;- ========== Register definition for UDP peripheral ========== 
-AT91C_UDP_ISR             EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
-AT91C_UDP_IDR             EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
-AT91C_UDP_GLBSTATE        EQU (0xFFFB0004) ;- (UDP) Global State Register
-AT91C_UDP_FDR             EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
-AT91C_UDP_CSR             EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
-AT91C_UDP_RSTEP           EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
-AT91C_UDP_ICR             EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
-AT91C_UDP_IMR             EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
-AT91C_UDP_IER             EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
-AT91C_UDP_FADDR           EQU (0xFFFB0008) ;- (UDP) Function Address Register
-AT91C_UDP_NUM             EQU (0xFFFB0000) ;- (UDP) Frame Number Register
-;- ========== Register definition for TC5 peripheral ========== 
-AT91C_TC5_CMR             EQU (0xFFFA4084) ;- (TC5) Channel Mode Register
-AT91C_TC5_IDR             EQU (0xFFFA40A8) ;- (TC5) Interrupt Disable Register
-AT91C_TC5_SR              EQU (0xFFFA40A0) ;- (TC5) Status Register
-AT91C_TC5_RB              EQU (0xFFFA4098) ;- (TC5) Register B
-AT91C_TC5_CV              EQU (0xFFFA4090) ;- (TC5) Counter Value
-AT91C_TC5_CCR             EQU (0xFFFA4080) ;- (TC5) Channel Control Register
-AT91C_TC5_IMR             EQU (0xFFFA40AC) ;- (TC5) Interrupt Mask Register
-AT91C_TC5_IER             EQU (0xFFFA40A4) ;- (TC5) Interrupt Enable Register
-AT91C_TC5_RC              EQU (0xFFFA409C) ;- (TC5) Register C
-AT91C_TC5_RA              EQU (0xFFFA4094) ;- (TC5) Register A
-;- ========== Register definition for TC4 peripheral ========== 
-AT91C_TC4_IMR             EQU (0xFFFA406C) ;- (TC4) Interrupt Mask Register
-AT91C_TC4_IER             EQU (0xFFFA4064) ;- (TC4) Interrupt Enable Register
-AT91C_TC4_RC              EQU (0xFFFA405C) ;- (TC4) Register C
-AT91C_TC4_RA              EQU (0xFFFA4054) ;- (TC4) Register A
-AT91C_TC4_CMR             EQU (0xFFFA4044) ;- (TC4) Channel Mode Register
-AT91C_TC4_IDR             EQU (0xFFFA4068) ;- (TC4) Interrupt Disable Register
-AT91C_TC4_SR              EQU (0xFFFA4060) ;- (TC4) Status Register
-AT91C_TC4_RB              EQU (0xFFFA4058) ;- (TC4) Register B
-AT91C_TC4_CV              EQU (0xFFFA4050) ;- (TC4) Counter Value
-AT91C_TC4_CCR             EQU (0xFFFA4040) ;- (TC4) Channel Control Register
-;- ========== Register definition for TC3 peripheral ========== 
-AT91C_TC3_IMR             EQU (0xFFFA402C) ;- (TC3) Interrupt Mask Register
-AT91C_TC3_CV              EQU (0xFFFA4010) ;- (TC3) Counter Value
-AT91C_TC3_CCR             EQU (0xFFFA4000) ;- (TC3) Channel Control Register
-AT91C_TC3_IER             EQU (0xFFFA4024) ;- (TC3) Interrupt Enable Register
-AT91C_TC3_CMR             EQU (0xFFFA4004) ;- (TC3) Channel Mode Register
-AT91C_TC3_RA              EQU (0xFFFA4014) ;- (TC3) Register A
-AT91C_TC3_RC              EQU (0xFFFA401C) ;- (TC3) Register C
-AT91C_TC3_IDR             EQU (0xFFFA4028) ;- (TC3) Interrupt Disable Register
-AT91C_TC3_RB              EQU (0xFFFA4018) ;- (TC3) Register B
-AT91C_TC3_SR              EQU (0xFFFA4020) ;- (TC3) Status Register
-;- ========== Register definition for TCB1 peripheral ========== 
-AT91C_TCB1_BCR            EQU (0xFFFA4140) ;- (TCB1) TC Block Control Register
-AT91C_TCB1_BMR            EQU (0xFFFA4144) ;- (TCB1) TC Block Mode Register
-;- ========== Register definition for TC2 peripheral ========== 
-AT91C_TC2_IMR             EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
-AT91C_TC2_IER             EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
-AT91C_TC2_RC              EQU (0xFFFA009C) ;- (TC2) Register C
-AT91C_TC2_RA              EQU (0xFFFA0094) ;- (TC2) Register A
-AT91C_TC2_CMR             EQU (0xFFFA0084) ;- (TC2) Channel Mode Register
-AT91C_TC2_IDR             EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
-AT91C_TC2_SR              EQU (0xFFFA00A0) ;- (TC2) Status Register
-AT91C_TC2_RB              EQU (0xFFFA0098) ;- (TC2) Register B
-AT91C_TC2_CV              EQU (0xFFFA0090) ;- (TC2) Counter Value
-AT91C_TC2_CCR             EQU (0xFFFA0080) ;- (TC2) Channel Control Register
-;- ========== Register definition for TC1 peripheral ========== 
-AT91C_TC1_IMR             EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
-AT91C_TC1_IER             EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
-AT91C_TC1_RC              EQU (0xFFFA005C) ;- (TC1) Register C
-AT91C_TC1_RA              EQU (0xFFFA0054) ;- (TC1) Register A
-AT91C_TC1_CMR             EQU (0xFFFA0044) ;- (TC1) Channel Mode Register
-AT91C_TC1_IDR             EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
-AT91C_TC1_SR              EQU (0xFFFA0060) ;- (TC1) Status Register
-AT91C_TC1_RB              EQU (0xFFFA0058) ;- (TC1) Register B
-AT91C_TC1_CV              EQU (0xFFFA0050) ;- (TC1) Counter Value
-AT91C_TC1_CCR             EQU (0xFFFA0040) ;- (TC1) Channel Control Register
-;- ========== Register definition for TC0 peripheral ========== 
-AT91C_TC0_IMR             EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
-AT91C_TC0_IER             EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
-AT91C_TC0_RC              EQU (0xFFFA001C) ;- (TC0) Register C
-AT91C_TC0_RA              EQU (0xFFFA0014) ;- (TC0) Register A
-AT91C_TC0_CMR             EQU (0xFFFA0004) ;- (TC0) Channel Mode Register
-AT91C_TC0_IDR             EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
-AT91C_TC0_SR              EQU (0xFFFA0020) ;- (TC0) Status Register
-AT91C_TC0_RB              EQU (0xFFFA0018) ;- (TC0) Register B
-AT91C_TC0_CV              EQU (0xFFFA0010) ;- (TC0) Counter Value
-AT91C_TC0_CCR             EQU (0xFFFA0000) ;- (TC0) Channel Control Register
-;- ========== Register definition for TCB0 peripheral ========== 
-AT91C_TCB0_BMR            EQU (0xFFFA00C4) ;- (TCB0) TC Block Mode Register
-AT91C_TCB0_BCR            EQU (0xFFFA00C0) ;- (TCB0) TC Block Control Register
-;- ========== Register definition for UHP peripheral ========== 
-AT91C_UHP_HcRhDescriptorA EQU (0x00300048) ;- (UHP) Root Hub characteristics A
-AT91C_UHP_HcRhPortStatus  EQU (0x00300054) ;- (UHP) Root Hub Port Status Register
-AT91C_UHP_HcRhDescriptorB EQU (0x0030004C) ;- (UHP) Root Hub characteristics B
-AT91C_UHP_HcControl       EQU (0x00300004) ;- (UHP) Operating modes for the Host Controller
-AT91C_UHP_HcInterruptStatus EQU (0x0030000C) ;- (UHP) Interrupt Status Register
-AT91C_UHP_HcRhStatus      EQU (0x00300050) ;- (UHP) Root Hub Status register
-AT91C_UHP_HcRevision      EQU (0x00300000) ;- (UHP) Revision
-AT91C_UHP_HcCommandStatus EQU (0x00300008) ;- (UHP) Command & status Register
-AT91C_UHP_HcInterruptEnable EQU (0x00300010) ;- (UHP) Interrupt Enable Register
-AT91C_UHP_HcHCCA          EQU (0x00300018) ;- (UHP) Pointer to the Host Controller Communication Area
-AT91C_UHP_HcControlHeadED EQU (0x00300020) ;- (UHP) First Endpoint Descriptor of the Control list
-AT91C_UHP_HcInterruptDisable EQU (0x00300014) ;- (UHP) Interrupt Disable Register
-AT91C_UHP_HcPeriodCurrentED EQU (0x0030001C) ;- (UHP) Current Isochronous or Interrupt Endpoint Descriptor
-AT91C_UHP_HcControlCurrentED EQU (0x00300024) ;- (UHP) Endpoint Control and Status Register
-AT91C_UHP_HcBulkCurrentED EQU (0x0030002C) ;- (UHP) Current endpoint of the Bulk list
-AT91C_UHP_HcFmInterval    EQU (0x00300034) ;- (UHP) Bit time between 2 consecutive SOFs
-AT91C_UHP_HcBulkHeadED    EQU (0x00300028) ;- (UHP) First endpoint register of the Bulk list
-AT91C_UHP_HcBulkDoneHead  EQU (0x00300030) ;- (UHP) Last completed transfer descriptor
-AT91C_UHP_HcFmRemaining   EQU (0x00300038) ;- (UHP) Bit time remaining in the current Frame
-AT91C_UHP_HcPeriodicStart EQU (0x00300040) ;- (UHP) Periodic Start
-AT91C_UHP_HcLSThreshold   EQU (0x00300044) ;- (UHP) LS Threshold
-AT91C_UHP_HcFmNumber      EQU (0x0030003C) ;- (UHP) Frame number
-;- ========== Register definition for EMAC peripheral ========== 
-AT91C_EMAC_RSR            EQU (0xFFFBC020) ;- (EMAC) Receive Status Register
-AT91C_EMAC_MAN            EQU (0xFFFBC034) ;- (EMAC) PHY Maintenance Register
-AT91C_EMAC_HSH            EQU (0xFFFBC090) ;- (EMAC) Hash Address High[63:32]
-AT91C_EMAC_MCOL           EQU (0xFFFBC048) ;- (EMAC) Multiple Collision Frame Register
-AT91C_EMAC_IER            EQU (0xFFFBC028) ;- (EMAC) Interrupt Enable Register
-AT91C_EMAC_SA2H           EQU (0xFFFBC0A4) ;- (EMAC) Specific Address 2 High, Last 2 bytes
-AT91C_EMAC_HSL            EQU (0xFFFBC094) ;- (EMAC) Hash Address Low[31:0]
-AT91C_EMAC_LCOL           EQU (0xFFFBC05C) ;- (EMAC) Late Collision Register
-AT91C_EMAC_OK             EQU (0xFFFBC04C) ;- (EMAC) Frames Received OK Register
-AT91C_EMAC_CFG            EQU (0xFFFBC004) ;- (EMAC) Network Configuration Register
-AT91C_EMAC_SA3L           EQU (0xFFFBC0A8) ;- (EMAC) Specific Address 3 Low, First 4 bytes
-AT91C_EMAC_SEQE           EQU (0xFFFBC050) ;- (EMAC) Frame Check Sequence Error Register
-AT91C_EMAC_ECOL           EQU (0xFFFBC060) ;- (EMAC) Excessive Collision Register
-AT91C_EMAC_ELR            EQU (0xFFFBC070) ;- (EMAC) Excessive Length Error Register
-AT91C_EMAC_SR             EQU (0xFFFBC008) ;- (EMAC) Network Status Register
-AT91C_EMAC_RBQP           EQU (0xFFFBC018) ;- (EMAC) Receive Buffer Queue Pointer
-AT91C_EMAC_CSE            EQU (0xFFFBC064) ;- (EMAC) Carrier Sense Error Register
-AT91C_EMAC_RJB            EQU (0xFFFBC074) ;- (EMAC) Receive Jabber Register
-AT91C_EMAC_USF            EQU (0xFFFBC078) ;- (EMAC) Undersize Frame Register
-AT91C_EMAC_IDR            EQU (0xFFFBC02C) ;- (EMAC) Interrupt Disable Register
-AT91C_EMAC_SA1L           EQU (0xFFFBC098) ;- (EMAC) Specific Address 1 Low, First 4 bytes
-AT91C_EMAC_IMR            EQU (0xFFFBC030) ;- (EMAC) Interrupt Mask Register
-AT91C_EMAC_FRA            EQU (0xFFFBC040) ;- (EMAC) Frames Transmitted OK Register
-AT91C_EMAC_SA3H           EQU (0xFFFBC0AC) ;- (EMAC) Specific Address 3 High, Last 2 bytes
-AT91C_EMAC_SA1H           EQU (0xFFFBC09C) ;- (EMAC) Specific Address 1 High, Last 2 bytes
-AT91C_EMAC_SCOL           EQU (0xFFFBC044) ;- (EMAC) Single Collision Frame Register
-AT91C_EMAC_ALE            EQU (0xFFFBC054) ;- (EMAC) Alignment Error Register
-AT91C_EMAC_TAR            EQU (0xFFFBC00C) ;- (EMAC) Transmit Address Register
-AT91C_EMAC_SA4L           EQU (0xFFFBC0B0) ;- (EMAC) Specific Address 4 Low, First 4 bytes
-AT91C_EMAC_SA2L           EQU (0xFFFBC0A0) ;- (EMAC) Specific Address 2 Low, First 4 bytes
-AT91C_EMAC_TUE            EQU (0xFFFBC068) ;- (EMAC) Transmit Underrun Error Register
-AT91C_EMAC_DTE            EQU (0xFFFBC058) ;- (EMAC) Deferred Transmission Frame Register
-AT91C_EMAC_TCR            EQU (0xFFFBC010) ;- (EMAC) Transmit Control Register
-AT91C_EMAC_CTL            EQU (0xFFFBC000) ;- (EMAC) Network Control Register
-AT91C_EMAC_SA4H           EQU (0xFFFBC0B4) ;- (EMAC) Specific Address 4 High, Last 2 bytesr
-AT91C_EMAC_CDE            EQU (0xFFFBC06C) ;- (EMAC) Code Error Register
-AT91C_EMAC_SQEE           EQU (0xFFFBC07C) ;- (EMAC) SQE Test Error Register
-AT91C_EMAC_TSR            EQU (0xFFFBC014) ;- (EMAC) Transmit Status Register
-AT91C_EMAC_DRFC           EQU (0xFFFBC080) ;- (EMAC) Discarded RX Frame Register
-;- ========== Register definition for EBI peripheral ========== 
-AT91C_EBI_CFGR            EQU (0xFFFFFF64) ;- (EBI) Configuration Register
-AT91C_EBI_CSA             EQU (0xFFFFFF60) ;- (EBI) Chip Select Assignment Register
-;- ========== Register definition for SMC2 peripheral ========== 
-AT91C_SMC2_CSR            EQU (0xFFFFFF70) ;- (SMC2) SMC2 Chip Select Register
-;- ========== Register definition for SDRC peripheral ========== 
-AT91C_SDRC_IMR            EQU (0xFFFFFFAC) ;- (SDRC) SDRAM Controller Interrupt Mask Register
-AT91C_SDRC_IER            EQU (0xFFFFFFA4) ;- (SDRC) SDRAM Controller Interrupt Enable Register
-AT91C_SDRC_SRR            EQU (0xFFFFFF9C) ;- (SDRC) SDRAM Controller Self Refresh Register
-AT91C_SDRC_TR             EQU (0xFFFFFF94) ;- (SDRC) SDRAM Controller Refresh Timer Register
-AT91C_SDRC_ISR            EQU (0xFFFFFFB0) ;- (SDRC) SDRAM Controller Interrupt Mask Register
-AT91C_SDRC_IDR            EQU (0xFFFFFFA8) ;- (SDRC) SDRAM Controller Interrupt Disable Register
-AT91C_SDRC_LPR            EQU (0xFFFFFFA0) ;- (SDRC) SDRAM Controller Low Power Register
-AT91C_SDRC_CR             EQU (0xFFFFFF98) ;- (SDRC) SDRAM Controller Configuration Register
-AT91C_SDRC_MR             EQU (0xFFFFFF90) ;- (SDRC) SDRAM Controller Mode Register
-;- ========== Register definition for BFC peripheral ========== 
-AT91C_BFC_MR              EQU (0xFFFFFFC0) ;- (BFC) BFC Mode Register
-
-;- *****************************************************************************
-;-               PIO DEFINITIONS FOR AT91RM9200
-;- *****************************************************************************
-AT91C_PIO_PA0             EQU (1:SHL:0) ;- Pin Controlled by PA0
-AT91C_PA0_MISO            EQU (AT91C_PIO_PA0) ;-  SPI Master In Slave
-AT91C_PA0_PCK3            EQU (AT91C_PIO_PA0) ;-  PMC Programmable Clock Output 3
-AT91C_PIO_PA1             EQU (1:SHL:1) ;- Pin Controlled by PA1
-AT91C_PA1_MOSI            EQU (AT91C_PIO_PA1) ;-  SPI Master Out Slave
-AT91C_PA1_PCK0            EQU (AT91C_PIO_PA1) ;-  PMC Programmable Clock Output 0
-AT91C_PIO_PA10            EQU (1:SHL:10) ;- Pin Controlled by PA10
-AT91C_PA10_ETX1           EQU (AT91C_PIO_PA10) ;-  Ethernet MAC Transmit Data 1
-AT91C_PA10_MCDB1          EQU (AT91C_PIO_PA10) ;-  Multimedia Card B Data 1
-AT91C_PIO_PA11            EQU (1:SHL:11) ;- Pin Controlled by PA11
-AT91C_PA11_ECRS_ECRSDV    EQU (AT91C_PIO_PA11) ;-  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-AT91C_PA11_MCDB2          EQU (AT91C_PIO_PA11) ;-  Multimedia Card B Data 2
-AT91C_PIO_PA12            EQU (1:SHL:12) ;- Pin Controlled by PA12
-AT91C_PA12_ERX0           EQU (AT91C_PIO_PA12) ;-  Ethernet MAC Receive Data 0
-AT91C_PA12_MCDB3          EQU (AT91C_PIO_PA12) ;-  Multimedia Card B Data 3
-AT91C_PIO_PA13            EQU (1:SHL:13) ;- Pin Controlled by PA13
-AT91C_PA13_ERX1           EQU (AT91C_PIO_PA13) ;-  Ethernet MAC Receive Data 1
-AT91C_PA13_TCLK0          EQU (AT91C_PIO_PA13) ;-  Timer Counter 0 external clock input
-AT91C_PIO_PA14            EQU (1:SHL:14) ;- Pin Controlled by PA14
-AT91C_PA14_ERXER          EQU (AT91C_PIO_PA14) ;-  Ethernet MAC Receive Error
-AT91C_PA14_TCLK1          EQU (AT91C_PIO_PA14) ;-  Timer Counter 1 external clock input
-AT91C_PIO_PA15            EQU (1:SHL:15) ;- Pin Controlled by PA15
-AT91C_PA15_EMDC           EQU (AT91C_PIO_PA15) ;-  Ethernet MAC Management Data Clock
-AT91C_PA15_TCLK2          EQU (AT91C_PIO_PA15) ;-  Timer Counter 2 external clock input
-AT91C_PIO_PA16            EQU (1:SHL:16) ;- Pin Controlled by PA16
-AT91C_PA16_EMDIO          EQU (AT91C_PIO_PA16) ;-  Ethernet MAC Management Data Input/Output
-AT91C_PA16_IRQ6           EQU (AT91C_PIO_PA16) ;-  AIC Interrupt input 6
-AT91C_PIO_PA17            EQU (1:SHL:17) ;- Pin Controlled by PA17
-AT91C_PA17_TXD0           EQU (AT91C_PIO_PA17) ;-  USART 0 Transmit Data
-AT91C_PA17_TIOA0          EQU (AT91C_PIO_PA17) ;-  Timer Counter 0 Multipurpose Timer I/O Pin A
-AT91C_PIO_PA18            EQU (1:SHL:18) ;- Pin Controlled by PA18
-AT91C_PA18_RXD0           EQU (AT91C_PIO_PA18) ;-  USART 0 Receive Data
-AT91C_PA18_TIOB0          EQU (AT91C_PIO_PA18) ;-  Timer Counter 0 Multipurpose Timer I/O Pin B
-AT91C_PIO_PA19            EQU (1:SHL:19) ;- Pin Controlled by PA19
-AT91C_PA19_SCK0           EQU (AT91C_PIO_PA19) ;-  USART 0 Serial Clock
-AT91C_PA19_TIOA1          EQU (AT91C_PIO_PA19) ;-  Timer Counter 1 Multipurpose Timer I/O Pin A
-AT91C_PIO_PA2             EQU (1:SHL:2) ;- Pin Controlled by PA2
-AT91C_PA2_SPCK            EQU (AT91C_PIO_PA2) ;-  SPI Serial Clock
-AT91C_PA2_IRQ4            EQU (AT91C_PIO_PA2) ;-  AIC Interrupt Input 4
-AT91C_PIO_PA20            EQU (1:SHL:20) ;- Pin Controlled by PA20
-AT91C_PA20_CTS0           EQU (AT91C_PIO_PA20) ;-  USART 0 Clear To Send
-AT91C_PA20_TIOB1          EQU (AT91C_PIO_PA20) ;-  Timer Counter 1 Multipurpose Timer I/O Pin B
-AT91C_PIO_PA21            EQU (1:SHL:21) ;- Pin Controlled by PA21
-AT91C_PA21_RTS0           EQU (AT91C_PIO_PA21) ;-  Usart 0 Ready To Send
-AT91C_PA21_TIOA2          EQU (AT91C_PIO_PA21) ;-  Timer Counter 2 Multipurpose Timer I/O Pin A
-AT91C_PIO_PA22            EQU (1:SHL:22) ;- Pin Controlled by PA22
-AT91C_PA22_RXD2           EQU (AT91C_PIO_PA22) ;-  USART 2 Receive Data
-AT91C_PA22_TIOB2          EQU (AT91C_PIO_PA22) ;-  Timer Counter 2 Multipurpose Timer I/O Pin B
-AT91C_PIO_PA23            EQU (1:SHL:23) ;- Pin Controlled by PA23
-AT91C_PA23_TXD2           EQU (AT91C_PIO_PA23) ;-  USART 2 Transmit Data
-AT91C_PA23_IRQ3           EQU (AT91C_PIO_PA23) ;-  Interrupt input 3
-AT91C_PIO_PA24            EQU (1:SHL:24) ;- Pin Controlled by PA24
-AT91C_PA24_SCK2           EQU (AT91C_PIO_PA24) ;-  USART2 Serial Clock
-AT91C_PA24_PCK1           EQU (AT91C_PIO_PA24) ;-  PMC Programmable Clock Output 1
-AT91C_PIO_PA25            EQU (1:SHL:25) ;- Pin Controlled by PA25
-AT91C_PA25_TWD            EQU (AT91C_PIO_PA25) ;-  TWI Two-wire Serial Data
-AT91C_PA25_IRQ2           EQU (AT91C_PIO_PA25) ;-  Interrupt input 2
-AT91C_PIO_PA26            EQU (1:SHL:26) ;- Pin Controlled by PA26
-AT91C_PA26_TWCK           EQU (AT91C_PIO_PA26) ;-  TWI Two-wire Serial Clock
-AT91C_PA26_IRQ1           EQU (AT91C_PIO_PA26) ;-  Interrupt input 1
-AT91C_PIO_PA27            EQU (1:SHL:27) ;- Pin Controlled by PA27
-AT91C_PA27_MCCK           EQU (AT91C_PIO_PA27) ;-  Multimedia Card Clock
-AT91C_PA27_TCLK3          EQU (AT91C_PIO_PA27) ;-  Timer Counter 3 External Clock Input
-AT91C_PIO_PA28            EQU (1:SHL:28) ;- Pin Controlled by PA28
-AT91C_PA28_MCCDA          EQU (AT91C_PIO_PA28) ;-  Multimedia Card A Command
-AT91C_PA28_TCLK4          EQU (AT91C_PIO_PA28) ;-  Timer Counter 4 external Clock Input
-AT91C_PIO_PA29            EQU (1:SHL:29) ;- Pin Controlled by PA29
-AT91C_PA29_MCDA0          EQU (AT91C_PIO_PA29) ;-  Multimedia Card A Data 0
-AT91C_PA29_TCLK5          EQU (AT91C_PIO_PA29) ;-  Timer Counter 5 external clock input
-AT91C_PIO_PA3             EQU (1:SHL:3) ;- Pin Controlled by PA3
-AT91C_PA3_NPCS0           EQU (AT91C_PIO_PA3) ;-  SPI Peripheral Chip Select 0
-AT91C_PA3_IRQ5            EQU (AT91C_PIO_PA3) ;-  AIC Interrupt Input 5
-AT91C_PIO_PA30            EQU (1:SHL:30) ;- Pin Controlled by PA30
-AT91C_PA30_DRXD           EQU (AT91C_PIO_PA30) ;-  DBGU Debug Receive Data
-AT91C_PA30_CTS2           EQU (AT91C_PIO_PA30) ;-  Usart 2 Clear To Send
-AT91C_PIO_PA31            EQU (1:SHL:31) ;- Pin Controlled by PA31
-AT91C_PA31_DTXD           EQU (AT91C_PIO_PA31) ;-  DBGU Debug Transmit Data
-AT91C_PA31_RTS2           EQU (AT91C_PIO_PA31) ;-  USART 2 Ready To Send
-AT91C_PIO_PA4             EQU (1:SHL:4) ;- Pin Controlled by PA4
-AT91C_PA4_NPCS1           EQU (AT91C_PIO_PA4) ;-  SPI Peripheral Chip Select 1
-AT91C_PA4_PCK1            EQU (AT91C_PIO_PA4) ;-  PMC Programmable Clock Output 1
-AT91C_PIO_PA5             EQU (1:SHL:5) ;- Pin Controlled by PA5
-AT91C_PA5_NPCS2           EQU (AT91C_PIO_PA5) ;-  SPI Peripheral Chip Select 2
-AT91C_PA5_TXD3            EQU (AT91C_PIO_PA5) ;-  USART 3 Transmit Data
-AT91C_PIO_PA6             EQU (1:SHL:6) ;- Pin Controlled by PA6
-AT91C_PA6_NPCS3           EQU (AT91C_PIO_PA6) ;-  SPI Peripheral Chip Select 3
-AT91C_PA6_RXD3            EQU (AT91C_PIO_PA6) ;-  USART 3 Receive Data
-AT91C_PIO_PA7             EQU (1:SHL:7) ;- Pin Controlled by PA7
-AT91C_PA7_ETXCK_EREFCK    EQU (AT91C_PIO_PA7) ;-  Ethernet MAC Transmit Clock/Reference Clock
-AT91C_PA7_PCK2            EQU (AT91C_PIO_PA7) ;-  PMC Programmable Clock 2
-AT91C_PIO_PA8             EQU (1:SHL:8) ;- Pin Controlled by PA8
-AT91C_PA8_ETXEN           EQU (AT91C_PIO_PA8) ;-  Ethernet MAC Transmit Enable
-AT91C_PA8_MCCDB           EQU (AT91C_PIO_PA8) ;-  Multimedia Card B Command
-AT91C_PIO_PA9             EQU (1:SHL:9) ;- Pin Controlled by PA9
-AT91C_PA9_ETX0            EQU (AT91C_PIO_PA9) ;-  Ethernet MAC Transmit Data 0
-AT91C_PA9_MCDB0           EQU (AT91C_PIO_PA9) ;-  Multimedia Card B Data 0
-AT91C_PIO_PB0             EQU (1:SHL:0) ;- Pin Controlled by PB0
-AT91C_PB0_TF0             EQU (AT91C_PIO_PB0) ;-  SSC Transmit Frame Sync 0
-AT91C_PB0_TIOB3           EQU (AT91C_PIO_PB0) ;-  Timer Counter 3 Multipurpose Timer I/O Pin B
-AT91C_PIO_PB1             EQU (1:SHL:1) ;- Pin Controlled by PB1
-AT91C_PB1_TK0             EQU (AT91C_PIO_PB1) ;-  SSC Transmit Clock 0
-AT91C_PB1_CTS3            EQU (AT91C_PIO_PB1) ;-  USART 3 Clear To Send
-AT91C_PIO_PB10            EQU (1:SHL:10) ;- Pin Controlled by PB10
-AT91C_PB10_RK1            EQU (AT91C_PIO_PB10) ;-  SSC Receive Clock 1
-AT91C_PB10_TIOA5          EQU (AT91C_PIO_PB10) ;-  Timer Counter 5 Multipurpose Timer I/O Pin A
-AT91C_PIO_PB11            EQU (1:SHL:11) ;- Pin Controlled by PB11
-AT91C_PB11_RF1            EQU (AT91C_PIO_PB11) ;-  SSC Receive Frame Sync 1
-AT91C_PB11_TIOB5          EQU (AT91C_PIO_PB11) ;-  Timer Counter 5 Multipurpose Timer I/O Pin B
-AT91C_PIO_PB12            EQU (1:SHL:12) ;- Pin Controlled by PB12
-AT91C_PB12_TF2            EQU (AT91C_PIO_PB12) ;-  SSC Transmit Frame Sync 2
-AT91C_PB12_ETX2           EQU (AT91C_PIO_PB12) ;-  Ethernet MAC Transmit Data 2
-AT91C_PIO_PB13            EQU (1:SHL:13) ;- Pin Controlled by PB13
-AT91C_PB13_TK2            EQU (AT91C_PIO_PB13) ;-  SSC Transmit Clock 2
-AT91C_PB13_ETX3           EQU (AT91C_PIO_PB13) ;-  Ethernet MAC Transmit Data 3
-AT91C_PIO_PB14            EQU (1:SHL:14) ;- Pin Controlled by PB14
-AT91C_PB14_TD2            EQU (AT91C_PIO_PB14) ;-  SSC Transmit Data 2
-AT91C_PB14_ETXER          EQU (AT91C_PIO_PB14) ;-  Ethernet MAC Transmikt Coding Error
-AT91C_PIO_PB15            EQU (1:SHL:15) ;- Pin Controlled by PB15
-AT91C_PB15_RD2            EQU (AT91C_PIO_PB15) ;-  SSC Receive Data 2
-AT91C_PB15_ERX2           EQU (AT91C_PIO_PB15) ;-  Ethernet MAC Receive Data 2
-AT91C_PIO_PB16            EQU (1:SHL:16) ;- Pin Controlled by PB16
-AT91C_PB16_RK2            EQU (AT91C_PIO_PB16) ;-  SSC Receive Clock 2
-AT91C_PB16_ERX3           EQU (AT91C_PIO_PB16) ;-  Ethernet MAC Receive Data 3
-AT91C_PIO_PB17            EQU (1:SHL:17) ;- Pin Controlled by PB17
-AT91C_PB17_RF2            EQU (AT91C_PIO_PB17) ;-  SSC Receive Frame Sync 2
-AT91C_PB17_ERXDV          EQU (AT91C_PIO_PB17) ;-  Ethernet MAC Receive Data Valid
-AT91C_PIO_PB18            EQU (1:SHL:18) ;- Pin Controlled by PB18
-AT91C_PB18_RI1            EQU (AT91C_PIO_PB18) ;-  USART 1 Ring Indicator
-AT91C_PB18_ECOL           EQU (AT91C_PIO_PB18) ;-  Ethernet MAC Collision Detected
-AT91C_PIO_PB19            EQU (1:SHL:19) ;- Pin Controlled by PB19
-AT91C_PB19_DTR1           EQU (AT91C_PIO_PB19) ;-  USART 1 Data Terminal ready
-AT91C_PB19_ERXCK          EQU (AT91C_PIO_PB19) ;-  Ethernet MAC Receive Clock
-AT91C_PIO_PB2             EQU (1:SHL:2) ;- Pin Controlled by PB2
-AT91C_PB2_TD0             EQU (AT91C_PIO_PB2) ;-  SSC Transmit data
-AT91C_PB2_SCK3            EQU (AT91C_PIO_PB2) ;-  USART 3 Serial Clock
-AT91C_PIO_PB20            EQU (1:SHL:20) ;- Pin Controlled by PB20
-AT91C_PB20_TXD1           EQU (AT91C_PIO_PB20) ;-  USART 1 Transmit Data
-AT91C_PIO_PB21            EQU (1:SHL:21) ;- Pin Controlled by PB21
-AT91C_PB21_RXD1           EQU (AT91C_PIO_PB21) ;-  USART 1 Receive Data
-AT91C_PIO_PB22            EQU (1:SHL:22) ;- Pin Controlled by PB22
-AT91C_PB22_SCK1           EQU (AT91C_PIO_PB22) ;-  USART1 Serial Clock
-AT91C_PIO_PB23            EQU (1:SHL:23) ;- Pin Controlled by PB23
-AT91C_PB23_DCD1           EQU (AT91C_PIO_PB23) ;-  USART 1 Data Carrier Detect
-AT91C_PIO_PB24            EQU (1:SHL:24) ;- Pin Controlled by PB24
-AT91C_PB24_CTS1           EQU (AT91C_PIO_PB24) ;-  USART 1 Clear To Send
-AT91C_PIO_PB25            EQU (1:SHL:25) ;- Pin Controlled by PB25
-AT91C_PB25_DSR1           EQU (AT91C_PIO_PB25) ;-  USART 1 Data Set ready
-AT91C_PB25_EF100          EQU (AT91C_PIO_PB25) ;-  Ethernet MAC Force 100 Mbits/sec
-AT91C_PIO_PB26            EQU (1:SHL:26) ;- Pin Controlled by PB26
-AT91C_PB26_RTS1           EQU (AT91C_PIO_PB26) ;-  Usart 0 Ready To Send
-AT91C_PIO_PB27            EQU (1:SHL:27) ;- Pin Controlled by PB27
-AT91C_PB27_PCK0           EQU (AT91C_PIO_PB27) ;-  PMC Programmable Clock Output 0
-AT91C_PIO_PB28            EQU (1:SHL:28) ;- Pin Controlled by PB28
-AT91C_PB28_FIQ            EQU (AT91C_PIO_PB28) ;-  AIC Fast Interrupt Input
-AT91C_PIO_PB29            EQU (1:SHL:29) ;- Pin Controlled by PB29
-AT91C_PB29_IRQ0           EQU (AT91C_PIO_PB29) ;-  Interrupt input 0
-AT91C_PIO_PB3             EQU (1:SHL:3) ;- Pin Controlled by PB3
-AT91C_PB3_RD0             EQU (AT91C_PIO_PB3) ;-  SSC Receive Data
-AT91C_PB3_MCDA1           EQU (AT91C_PIO_PB3) ;-  Multimedia Card A Data 1
-AT91C_PIO_PB4             EQU (1:SHL:4) ;- Pin Controlled by PB4
-AT91C_PB4_RK0             EQU (AT91C_PIO_PB4) ;-  SSC Receive Clock
-AT91C_PB4_MCDA2           EQU (AT91C_PIO_PB4) ;-  Multimedia Card A Data 2
-AT91C_PIO_PB5             EQU (1:SHL:5) ;- Pin Controlled by PB5
-AT91C_PB5_RF0             EQU (AT91C_PIO_PB5) ;-  SSC Receive Frame Sync 0
-AT91C_PB5_MCDA3           EQU (AT91C_PIO_PB5) ;-  Multimedia Card A Data 3
-AT91C_PIO_PB6             EQU (1:SHL:6) ;- Pin Controlled by PB6
-AT91C_PB6_TF1             EQU (AT91C_PIO_PB6) ;-  SSC Transmit Frame Sync 1
-AT91C_PB6_TIOA3           EQU (AT91C_PIO_PB6) ;-  Timer Counter 4 Multipurpose Timer I/O Pin A
-AT91C_PIO_PB7             EQU (1:SHL:7) ;- Pin Controlled by PB7
-AT91C_PB7_TK1             EQU (AT91C_PIO_PB7) ;-  SSC Transmit Clock 1
-AT91C_PB7_TIOB3           EQU (AT91C_PIO_PB7) ;-  Timer Counter 3 Multipurpose Timer I/O Pin B
-AT91C_PIO_PB8             EQU (1:SHL:8) ;- Pin Controlled by PB8
-AT91C_PB8_TD1             EQU (AT91C_PIO_PB8) ;-  SSC Transmit Data 1
-AT91C_PB8_TIOA4           EQU (AT91C_PIO_PB8) ;-  Timer Counter 4 Multipurpose Timer I/O Pin A
-AT91C_PIO_PB9             EQU (1:SHL:9) ;- Pin Controlled by PB9
-AT91C_PB9_RD1             EQU (AT91C_PIO_PB9) ;-  SSC Receive Data 1
-AT91C_PB9_TIOB4           EQU (AT91C_PIO_PB9) ;-  Timer Counter 4 Multipurpose Timer I/O Pin B
-AT91C_PIO_PC0             EQU (1:SHL:0) ;- Pin Controlled by PC0
-AT91C_PC0_BFCK            EQU (AT91C_PIO_PC0) ;-  Burst Flash Clock
-AT91C_PIO_PC1             EQU (1:SHL:1) ;- Pin Controlled by PC1
-AT91C_PC1_BFRDY_SMOE      EQU (AT91C_PIO_PC1) ;-  Burst Flash Ready
-AT91C_PIO_PC10            EQU (1:SHL:10) ;- Pin Controlled by PC10
-AT91C_PC10_NCS4_CFCS      EQU (AT91C_PIO_PC10) ;-  Compact Flash Chip Select
-AT91C_PIO_PC11            EQU (1:SHL:11) ;- Pin Controlled by PC11
-AT91C_PC11_NCS5_CFCE1     EQU (AT91C_PIO_PC11) ;-  Chip Select 5 / Compact Flash Chip Enable 1
-AT91C_PIO_PC12            EQU (1:SHL:12) ;- Pin Controlled by PC12
-AT91C_PC12_NCS6_CFCE2     EQU (AT91C_PIO_PC12) ;-  Chip Select 6 / Compact Flash Chip Enable 2
-AT91C_PIO_PC13            EQU (1:SHL:13) ;- Pin Controlled by PC13
-AT91C_PC13_NCS7           EQU (AT91C_PIO_PC13) ;-  Chip Select 7
-AT91C_PIO_PC14            EQU (1:SHL:14) ;- Pin Controlled by PC14
-AT91C_PIO_PC15            EQU (1:SHL:15) ;- Pin Controlled by PC15
-AT91C_PIO_PC16            EQU (1:SHL:16) ;- Pin Controlled by PC16
-AT91C_PC16_D16            EQU (AT91C_PIO_PC16) ;-  Data Bus [16]
-AT91C_PIO_PC17            EQU (1:SHL:17) ;- Pin Controlled by PC17
-AT91C_PC17_D17            EQU (AT91C_PIO_PC17) ;-  Data Bus [17]
-AT91C_PIO_PC18            EQU (1:SHL:18) ;- Pin Controlled by PC18
-AT91C_PC18_D18            EQU (AT91C_PIO_PC18) ;-  Data Bus [18]
-AT91C_PIO_PC19            EQU (1:SHL:19) ;- Pin Controlled by PC19
-AT91C_PC19_D19            EQU (AT91C_PIO_PC19) ;-  Data Bus [19]
-AT91C_PIO_PC2             EQU (1:SHL:2) ;- Pin Controlled by PC2
-AT91C_PC2_BFAVD           EQU (AT91C_PIO_PC2) ;-  Burst Flash Address Valid
-AT91C_PIO_PC20            EQU (1:SHL:20) ;- Pin Controlled by PC20
-AT91C_PC20_D20            EQU (AT91C_PIO_PC20) ;-  Data Bus [20]
-AT91C_PIO_PC21            EQU (1:SHL:21) ;- Pin Controlled by PC21
-AT91C_PC21_D21            EQU (AT91C_PIO_PC21) ;-  Data Bus [21]
-AT91C_PIO_PC22            EQU (1:SHL:22) ;- Pin Controlled by PC22
-AT91C_PC22_D22            EQU (AT91C_PIO_PC22) ;-  Data Bus [22]
-AT91C_PIO_PC23            EQU (1:SHL:23) ;- Pin Controlled by PC23
-AT91C_PC23_D23            EQU (AT91C_PIO_PC23) ;-  Data Bus [23]
-AT91C_PIO_PC24            EQU (1:SHL:24) ;- Pin Controlled by PC24
-AT91C_PC24_D24            EQU (AT91C_PIO_PC24) ;-  Data Bus [24]
-AT91C_PIO_PC25            EQU (1:SHL:25) ;- Pin Controlled by PC25
-AT91C_PC25_D25            EQU (AT91C_PIO_PC25) ;-  Data Bus [25]
-AT91C_PIO_PC26            EQU (1:SHL:26) ;- Pin Controlled by PC26
-AT91C_PC26_D26            EQU (AT91C_PIO_PC26) ;-  Data Bus [26]
-AT91C_PIO_PC27            EQU (1:SHL:27) ;- Pin Controlled by PC27
-AT91C_PC27_D27            EQU (AT91C_PIO_PC27) ;-  Data Bus [27]
-AT91C_PIO_PC28            EQU (1:SHL:28) ;- Pin Controlled by PC28
-AT91C_PC28_D28            EQU (AT91C_PIO_PC28) ;-  Data Bus [28]
-AT91C_PIO_PC29            EQU (1:SHL:29) ;- Pin Controlled by PC29
-AT91C_PC29_D29            EQU (AT91C_PIO_PC29) ;-  Data Bus [29]
-AT91C_PIO_PC3             EQU (1:SHL:3) ;- Pin Controlled by PC3
-AT91C_PC3_BFBAA_SMWE      EQU (AT91C_PIO_PC3) ;-  Burst Flash Address Advance / SmartMedia Write Enable
-AT91C_PIO_PC30            EQU (1:SHL:30) ;- Pin Controlled by PC30
-AT91C_PC30_D30            EQU (AT91C_PIO_PC30) ;-  Data Bus [30]
-AT91C_PIO_PC31            EQU (1:SHL:31) ;- Pin Controlled by PC31
-AT91C_PC31_D31            EQU (AT91C_PIO_PC31) ;-  Data Bus [31]
-AT91C_PIO_PC4             EQU (1:SHL:4) ;- Pin Controlled by PC4
-AT91C_PC4_BFOE            EQU (AT91C_PIO_PC4) ;-  Burst Flash Output Enable
-AT91C_PIO_PC5             EQU (1:SHL:5) ;- Pin Controlled by PC5
-AT91C_PC5_BFWE            EQU (AT91C_PIO_PC5) ;-  Burst Flash Write Enable
-AT91C_PIO_PC6             EQU (1:SHL:6) ;- Pin Controlled by PC6
-AT91C_PC6_NWAIT           EQU (AT91C_PIO_PC6) ;-  NWAIT
-AT91C_PIO_PC7             EQU (1:SHL:7) ;- Pin Controlled by PC7
-AT91C_PC7_A23             EQU (AT91C_PIO_PC7) ;-  Address Bus[23]
-AT91C_PIO_PC8             EQU (1:SHL:8) ;- Pin Controlled by PC8
-AT91C_PC8_A24             EQU (AT91C_PIO_PC8) ;-  Address Bus[24]
-AT91C_PIO_PC9             EQU (1:SHL:9) ;- Pin Controlled by PC9
-AT91C_PC9_A25_CFRNW       EQU (AT91C_PIO_PC9) ;-  Address Bus[25] /  Compact Flash Read Not Write
-AT91C_PIO_PD0             EQU (1:SHL:0) ;- Pin Controlled by PD0
-AT91C_PD0_ETX0            EQU (AT91C_PIO_PD0) ;-  Ethernet MAC Transmit Data 0
-AT91C_PIO_PD1             EQU (1:SHL:1) ;- Pin Controlled by PD1
-AT91C_PD1_ETX1            EQU (AT91C_PIO_PD1) ;-  Ethernet MAC Transmit Data 1
-AT91C_PIO_PD10            EQU (1:SHL:10) ;- Pin Controlled by PD10
-AT91C_PD10_PCK3           EQU (AT91C_PIO_PD10) ;-  PMC Programmable Clock Output 3
-AT91C_PD10_TPS1           EQU (AT91C_PIO_PD10) ;-  ETM ARM9 pipeline status 1
-AT91C_PIO_PD11            EQU (1:SHL:11) ;- Pin Controlled by PD11
-AT91C_PD11_               EQU (AT91C_PIO_PD11) ;-  
-AT91C_PD11_TPS2           EQU (AT91C_PIO_PD11) ;-  ETM ARM9 pipeline status 2
-AT91C_PIO_PD12            EQU (1:SHL:12) ;- Pin Controlled by PD12
-AT91C_PD12_               EQU (AT91C_PIO_PD12) ;-  
-AT91C_PD12_TPK0           EQU (AT91C_PIO_PD12) ;-  ETM Trace Packet 0
-AT91C_PIO_PD13            EQU (1:SHL:13) ;- Pin Controlled by PD13
-AT91C_PD13_               EQU (AT91C_PIO_PD13) ;-  
-AT91C_PD13_TPK1           EQU (AT91C_PIO_PD13) ;-  ETM Trace Packet 1
-AT91C_PIO_PD14            EQU (1:SHL:14) ;- Pin Controlled by PD14
-AT91C_PD14_               EQU (AT91C_PIO_PD14) ;-  
-AT91C_PD14_TPK2           EQU (AT91C_PIO_PD14) ;-  ETM Trace Packet 2
-AT91C_PIO_PD15            EQU (1:SHL:15) ;- Pin Controlled by PD15
-AT91C_PD15_TD0            EQU (AT91C_PIO_PD15) ;-  SSC Transmit data
-AT91C_PD15_TPK3           EQU (AT91C_PIO_PD15) ;-  ETM Trace Packet 3
-AT91C_PIO_PD16            EQU (1:SHL:16) ;- Pin Controlled by PD16
-AT91C_PD16_TD1            EQU (AT91C_PIO_PD16) ;-  SSC Transmit Data 1
-AT91C_PD16_TPK4           EQU (AT91C_PIO_PD16) ;-  ETM Trace Packet 4
-AT91C_PIO_PD17            EQU (1:SHL:17) ;- Pin Controlled by PD17
-AT91C_PD17_TD2            EQU (AT91C_PIO_PD17) ;-  SSC Transmit Data 2
-AT91C_PD17_TPK5           EQU (AT91C_PIO_PD17) ;-  ETM Trace Packet 5
-AT91C_PIO_PD18            EQU (1:SHL:18) ;- Pin Controlled by PD18
-AT91C_PD18_NPCS1          EQU (AT91C_PIO_PD18) ;-  SPI Peripheral Chip Select 1
-AT91C_PD18_TPK6           EQU (AT91C_PIO_PD18) ;-  ETM Trace Packet 6
-AT91C_PIO_PD19            EQU (1:SHL:19) ;- Pin Controlled by PD19
-AT91C_PD19_NPCS2          EQU (AT91C_PIO_PD19) ;-  SPI Peripheral Chip Select 2
-AT91C_PD19_TPK7           EQU (AT91C_PIO_PD19) ;-  ETM Trace Packet 7
-AT91C_PIO_PD2             EQU (1:SHL:2) ;- Pin Controlled by PD2
-AT91C_PD2_ETX2            EQU (AT91C_PIO_PD2) ;-  Ethernet MAC Transmit Data 2
-AT91C_PIO_PD20            EQU (1:SHL:20) ;- Pin Controlled by PD20
-AT91C_PD20_NPCS3          EQU (AT91C_PIO_PD20) ;-  SPI Peripheral Chip Select 3
-AT91C_PD20_TPK8           EQU (AT91C_PIO_PD20) ;-  ETM Trace Packet 8
-AT91C_PIO_PD21            EQU (1:SHL:21) ;- Pin Controlled by PD21
-AT91C_PD21_RTS0           EQU (AT91C_PIO_PD21) ;-  Usart 0 Ready To Send
-AT91C_PD21_TPK9           EQU (AT91C_PIO_PD21) ;-  ETM Trace Packet 9
-AT91C_PIO_PD22            EQU (1:SHL:22) ;- Pin Controlled by PD22
-AT91C_PD22_RTS1           EQU (AT91C_PIO_PD22) ;-  Usart 0 Ready To Send
-AT91C_PD22_TPK10          EQU (AT91C_PIO_PD22) ;-  ETM Trace Packet 10
-AT91C_PIO_PD23            EQU (1:SHL:23) ;- Pin Controlled by PD23
-AT91C_PD23_RTS2           EQU (AT91C_PIO_PD23) ;-  USART 2 Ready To Send
-AT91C_PD23_TPK11          EQU (AT91C_PIO_PD23) ;-  ETM Trace Packet 11
-AT91C_PIO_PD24            EQU (1:SHL:24) ;- Pin Controlled by PD24
-AT91C_PD24_RTS3           EQU (AT91C_PIO_PD24) ;-  USART 3 Ready To Send
-AT91C_PD24_TPK12          EQU (AT91C_PIO_PD24) ;-  ETM Trace Packet 12
-AT91C_PIO_PD25            EQU (1:SHL:25) ;- Pin Controlled by PD25
-AT91C_PD25_DTR1           EQU (AT91C_PIO_PD25) ;-  USART 1 Data Terminal ready
-AT91C_PD25_TPK13          EQU (AT91C_PIO_PD25) ;-  ETM Trace Packet 13
-AT91C_PIO_PD26            EQU (1:SHL:26) ;- Pin Controlled by PD26
-AT91C_PD26_TPK14          EQU (AT91C_PIO_PD26) ;-  ETM Trace Packet 14
-AT91C_PIO_PD27            EQU (1:SHL:27) ;- Pin Controlled by PD27
-AT91C_PD27_TPK15          EQU (AT91C_PIO_PD27) ;-  ETM Trace Packet 15
-AT91C_PIO_PD3             EQU (1:SHL:3) ;- Pin Controlled by PD3
-AT91C_PD3_ETX3            EQU (AT91C_PIO_PD3) ;-  Ethernet MAC Transmit Data 3
-AT91C_PIO_PD4             EQU (1:SHL:4) ;- Pin Controlled by PD4
-AT91C_PD4_ETXEN           EQU (AT91C_PIO_PD4) ;-  Ethernet MAC Transmit Enable
-AT91C_PIO_PD5             EQU (1:SHL:5) ;- Pin Controlled by PD5
-AT91C_PD5_ETXER           EQU (AT91C_PIO_PD5) ;-  Ethernet MAC Transmikt Coding Error
-AT91C_PIO_PD6             EQU (1:SHL:6) ;- Pin Controlled by PD6
-AT91C_PD6_DTXD            EQU (AT91C_PIO_PD6) ;-  DBGU Debug Transmit Data
-AT91C_PIO_PD7             EQU (1:SHL:7) ;- Pin Controlled by PD7
-AT91C_PD7_PCK0            EQU (AT91C_PIO_PD7) ;-  PMC Programmable Clock Output 0
-AT91C_PD7_TSYNC           EQU (AT91C_PIO_PD7) ;-  ETM Synchronization signal
-AT91C_PIO_PD8             EQU (1:SHL:8) ;- Pin Controlled by PD8
-AT91C_PD8_PCK1            EQU (AT91C_PIO_PD8) ;-  PMC Programmable Clock Output 1
-AT91C_PD8_TCLK            EQU (AT91C_PIO_PD8) ;-  ETM Trace Clock signal
-AT91C_PIO_PD9             EQU (1:SHL:9) ;- Pin Controlled by PD9
-AT91C_PD9_PCK2            EQU (AT91C_PIO_PD9) ;-  PMC Programmable Clock 2
-AT91C_PD9_TPS0            EQU (AT91C_PIO_PD9) ;-  ETM ARM9 pipeline status 0
-
-;- *****************************************************************************
-;-               PERIPHERAL ID DEFINITIONS FOR AT91RM9200
-;- *****************************************************************************
-AT91C_ID_FIQ              EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
-AT91C_ID_SYS              EQU ( 1) ;- System Peripheral
-AT91C_ID_PIOA             EQU ( 2) ;- Parallel IO Controller A 
-AT91C_ID_PIOB             EQU ( 3) ;- Parallel IO Controller B
-AT91C_ID_PIOC             EQU ( 4) ;- Parallel IO Controller C
-AT91C_ID_PIOD             EQU ( 5) ;- Parallel IO Controller D
-AT91C_ID_US0              EQU ( 6) ;- USART 0
-AT91C_ID_US1              EQU ( 7) ;- USART 1
-AT91C_ID_US2              EQU ( 8) ;- USART 2
-AT91C_ID_US3              EQU ( 9) ;- USART 3
-AT91C_ID_MCI              EQU (10) ;- Multimedia Card Interface
-AT91C_ID_UDP              EQU (11) ;- USB Device Port
-AT91C_ID_TWI              EQU (12) ;- Two-Wire Interface
-AT91C_ID_SPI              EQU (13) ;- Serial Peripheral Interface
-AT91C_ID_SSC0             EQU (14) ;- Serial Synchronous Controller 0
-AT91C_ID_SSC1             EQU (15) ;- Serial Synchronous Controller 1
-AT91C_ID_SSC2             EQU (16) ;- Serial Synchronous Controller 2
-AT91C_ID_TC0              EQU (17) ;- Timer Counter 0
-AT91C_ID_TC1              EQU (18) ;- Timer Counter 1
-AT91C_ID_TC2              EQU (19) ;- Timer Counter 2
-AT91C_ID_TC3              EQU (20) ;- Timer Counter 3
-AT91C_ID_TC4              EQU (21) ;- Timer Counter 4
-AT91C_ID_TC5              EQU (22) ;- Timer Counter 5
-AT91C_ID_UHP              EQU (23) ;- USB Host port
-AT91C_ID_EMAC             EQU (24) ;- Ethernet MAC
-AT91C_ID_IRQ0             EQU (25) ;- Advanced Interrupt Controller (IRQ0)
-AT91C_ID_IRQ1             EQU (26) ;- Advanced Interrupt Controller (IRQ1)
-AT91C_ID_IRQ2             EQU (27) ;- Advanced Interrupt Controller (IRQ2)
-AT91C_ID_IRQ3             EQU (28) ;- Advanced Interrupt Controller (IRQ3)
-AT91C_ID_IRQ4             EQU (29) ;- Advanced Interrupt Controller (IRQ4)
-AT91C_ID_IRQ5             EQU (30) ;- Advanced Interrupt Controller (IRQ5)
-AT91C_ID_IRQ6             EQU (31) ;- Advanced Interrupt Controller (IRQ6)
-
-;- *****************************************************************************
-;-               BASE ADDRESS DEFINITIONS FOR AT91RM9200
-;- *****************************************************************************
-AT91C_BASE_SYS            EQU (0xFFFFF000) ;- (SYS) Base Address
-AT91C_BASE_MC             EQU (0xFFFFFF00) ;- (MC) Base Address
-AT91C_BASE_RTC            EQU (0xFFFFFE00) ;- (RTC) Base Address
-AT91C_BASE_ST             EQU (0xFFFFFD00) ;- (ST) Base Address
-AT91C_BASE_PMC            EQU (0xFFFFFC00) ;- (PMC) Base Address
-AT91C_BASE_CKGR           EQU (0xFFFFFC20) ;- (CKGR) Base Address
-AT91C_BASE_PIOD           EQU (0xFFFFFA00) ;- (PIOD) Base Address
-AT91C_BASE_PIOC           EQU (0xFFFFF800) ;- (PIOC) Base Address
-AT91C_BASE_PIOB           EQU (0xFFFFF600) ;- (PIOB) Base Address
-AT91C_BASE_PIOA           EQU (0xFFFFF400) ;- (PIOA) Base Address
-AT91C_BASE_DBGU           EQU (0xFFFFF200) ;- (DBGU) Base Address
-AT91C_BASE_PDC_DBGU       EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
-AT91C_BASE_AIC            EQU (0xFFFFF000) ;- (AIC) Base Address
-AT91C_BASE_PDC_SPI        EQU (0xFFFE0100) ;- (PDC_SPI) Base Address
-AT91C_BASE_SPI            EQU (0xFFFE0000) ;- (SPI) Base Address
-AT91C_BASE_PDC_SSC2       EQU (0xFFFD8100) ;- (PDC_SSC2) Base Address
-AT91C_BASE_SSC2           EQU (0xFFFD8000) ;- (SSC2) Base Address
-AT91C_BASE_PDC_SSC1       EQU (0xFFFD4100) ;- (PDC_SSC1) Base Address
-AT91C_BASE_SSC1           EQU (0xFFFD4000) ;- (SSC1) Base Address
-AT91C_BASE_PDC_SSC0       EQU (0xFFFD0100) ;- (PDC_SSC0) Base Address
-AT91C_BASE_SSC0           EQU (0xFFFD0000) ;- (SSC0) Base Address
-AT91C_BASE_PDC_US3        EQU (0xFFFCC100) ;- (PDC_US3) Base Address
-AT91C_BASE_US3            EQU (0xFFFCC000) ;- (US3) Base Address
-AT91C_BASE_PDC_US2        EQU (0xFFFC8100) ;- (PDC_US2) Base Address
-AT91C_BASE_US2            EQU (0xFFFC8000) ;- (US2) Base Address
-AT91C_BASE_PDC_US1        EQU (0xFFFC4100) ;- (PDC_US1) Base Address
-AT91C_BASE_US1            EQU (0xFFFC4000) ;- (US1) Base Address
-AT91C_BASE_PDC_US0        EQU (0xFFFC0100) ;- (PDC_US0) Base Address
-AT91C_BASE_US0            EQU (0xFFFC0000) ;- (US0) Base Address
-AT91C_BASE_TWI            EQU (0xFFFB8000) ;- (TWI) Base Address
-AT91C_BASE_PDC_MCI        EQU (0xFFFB4100) ;- (PDC_MCI) Base Address
-AT91C_BASE_MCI            EQU (0xFFFB4000) ;- (MCI) Base Address
-AT91C_BASE_UDP            EQU (0xFFFB0000) ;- (UDP) Base Address
-AT91C_BASE_TC5            EQU (0xFFFA4080) ;- (TC5) Base Address
-AT91C_BASE_TC4            EQU (0xFFFA4040) ;- (TC4) Base Address
-AT91C_BASE_TC3            EQU (0xFFFA4000) ;- (TC3) Base Address
-AT91C_BASE_TCB1           EQU (0xFFFA4080) ;- (TCB1) Base Address
-AT91C_BASE_TC2            EQU (0xFFFA0080) ;- (TC2) Base Address
-AT91C_BASE_TC1            EQU (0xFFFA0040) ;- (TC1) Base Address
-AT91C_BASE_TC0            EQU (0xFFFA0000) ;- (TC0) Base Address
-AT91C_BASE_TCB0           EQU (0xFFFA0000) ;- (TCB0) Base Address
-AT91C_BASE_UHP            EQU (0x00300000) ;- (UHP) Base Address
-AT91C_BASE_EMAC           EQU (0xFFFBC000) ;- (EMAC) Base Address
-AT91C_BASE_EBI            EQU (0xFFFFFF60) ;- (EBI) Base Address
-AT91C_BASE_SMC2           EQU (0xFFFFFF70) ;- (SMC2) Base Address
-AT91C_BASE_SDRC           EQU (0xFFFFFF90) ;- (SDRC) Base Address
-AT91C_BASE_BFC            EQU (0xFFFFFFC0) ;- (BFC) Base Address
-
-;- *****************************************************************************
-;-               MEMORY MAPPING DEFINITIONS FOR AT91RM9200
-;- *****************************************************************************
-AT91C_ISRAM               EQU (0x00200000) ;- Internal SRAM base address
-AT91C_ISRAM_SIZE          EQU (0x00004000) ;- Internal SRAM size in byte (16 Kbyte)
-AT91C_IROM                EQU (0x00100000) ;- Internal ROM base address
-AT91C_IROM_SIZE           EQU (0x00020000) ;- Internal ROM size in byte (128 Kbyte)
-
-
-	END
diff --git a/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200_inc.h b/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200_inc.h
deleted file mode 100644
index dabab01..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/include/AT91RM9200_inc.h
+++ /dev/null
@@ -1,2401 +0,0 @@
-// ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-// ----------------------------------------------------------------------------
-//  The software is delivered "AS IS" without warranty or condition of any
-//  kind, either express, implied or statutory. This includes without
-//  limitation any warranty or condition with respect to merchantability or
-//  fitness for any particular purpose, or against the infringements of
-//  intellectual property rights of others.
-// ----------------------------------------------------------------------------
-// File Name           : AT91RM9200.h
-// Object              : AT91RM9200 definitions
-// Generated           : AT91 SW Application Group  11/19/2003 (17:20:51)
-// 
-// CVS Reference       : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003//
-// CVS Reference       : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003//
-// CVS Reference       : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002//
-// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//
-// CVS Reference       : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
-// CVS Reference       : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002//
-// CVS Reference       : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003//
-// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//
-// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
-// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002//
-// CVS Reference       : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002//
-// CVS Reference       : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002//
-// CVS Reference       : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002//
-// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002//
-// CVS Reference       : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003//
-// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003//
-// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002//
-// CVS Reference       : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002//
-// CVS Reference       : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003//
-// CVS Reference       : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003//
-// CVS Reference       : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002//
-// CVS Reference       : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002//
-// CVS Reference       : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002//
-// ----------------------------------------------------------------------------
-
-// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_MC structure ***
-#define MC_RCR          ( 0) // MC Remap Control Register
-#define MC_ASR          ( 4) // MC Abort Status Register
-#define MC_AASR         ( 8) // MC Abort Address Status Register
-#define MC_PUIA         (16) // MC Protection Unit Area
-#define MC_PUP          (80) // MC Protection Unit Peripherals
-#define MC_PUER         (84) // MC Protection Unit Enable Register
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_MPU              (0x1 <<  2) // (MC) Memory protection Unit Abort Status
-#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- 
-#define AT91C_MC_PROT             (0x3 <<  0) // (MC) Protection
-#define 	AT91C_MC_PROT_PNAUNA               (0x0) // (MC) Privilege: No Access, User: No Access
-#define 	AT91C_MC_PROT_PRWUNA               (0x1) // (MC) Privilege: Read/Write, User: No Access
-#define 	AT91C_MC_PROT_PRWURO               (0x2) // (MC) Privilege: Read/Write, User: Read Only
-#define 	AT91C_MC_PROT_PRWURW               (0x3) // (MC) Privilege: Read/Write, User: Read/Write
-#define AT91C_MC_SIZE             (0xF <<  4) // (MC) Internal Area Size
-#define 	AT91C_MC_SIZE_1KB                  (0x0 <<  4) // (MC) Area size 1KByte
-#define 	AT91C_MC_SIZE_2KB                  (0x1 <<  4) // (MC) Area size 2KByte
-#define 	AT91C_MC_SIZE_4KB                  (0x2 <<  4) // (MC) Area size 4KByte
-#define 	AT91C_MC_SIZE_8KB                  (0x3 <<  4) // (MC) Area size 8KByte
-#define 	AT91C_MC_SIZE_16KB                 (0x4 <<  4) // (MC) Area size 16KByte
-#define 	AT91C_MC_SIZE_32KB                 (0x5 <<  4) // (MC) Area size 32KByte
-#define 	AT91C_MC_SIZE_64KB                 (0x6 <<  4) // (MC) Area size 64KByte
-#define 	AT91C_MC_SIZE_128KB                (0x7 <<  4) // (MC) Area size 128KByte
-#define 	AT91C_MC_SIZE_256KB                (0x8 <<  4) // (MC) Area size 256KByte
-#define 	AT91C_MC_SIZE_512KB                (0x9 <<  4) // (MC) Area size 512KByte
-#define 	AT91C_MC_SIZE_1MB                  (0xA <<  4) // (MC) Area size 1MByte
-#define 	AT91C_MC_SIZE_2MB                  (0xB <<  4) // (MC) Area size 2MByte
-#define 	AT91C_MC_SIZE_4MB                  (0xC <<  4) // (MC) Area size 4MByte
-#define 	AT91C_MC_SIZE_8MB                  (0xD <<  4) // (MC) Area size 8MByte
-#define 	AT91C_MC_SIZE_16MB                 (0xE <<  4) // (MC) Area size 16MByte
-#define 	AT91C_MC_SIZE_64MB                 (0xF <<  4) // (MC) Area size 64MByte
-#define AT91C_MC_BA               (0x3FFFF << 10) // (MC) Internal Area Base Address
-// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- 
-// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- 
-#define AT91C_MC_PUEB             (0x1 <<  0) // (MC) Protection Unit enable Bit
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm and Parallel Load Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RTC structure ***
-#define RTC_CR          ( 0) // Control Register
-#define RTC_MR          ( 4) // Mode Register
-#define RTC_TIMR        ( 8) // Time Register
-#define RTC_CALR        (12) // Calendar Register
-#define RTC_TIMALR      (16) // Time Alarm Register
-#define RTC_CALALR      (20) // Calendar Alarm Register
-#define RTC_SR          (24) // Status Register
-#define RTC_SCCR        (28) // Status Clear Command Register
-#define RTC_IER         (32) // Interrupt Enable Register
-#define RTC_IDR         (36) // Interrupt Disable Register
-#define RTC_IMR         (40) // Interrupt Mask Register
-#define RTC_VER         (44) // Valid Entry Register
-// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- 
-#define AT91C_RTC_UPDTIM          (0x1 <<  0) // (RTC) Update Request Time Register
-#define AT91C_RTC_UPDCAL          (0x1 <<  1) // (RTC) Update Request Calendar Register
-#define AT91C_RTC_TIMEVSEL        (0x3 <<  8) // (RTC) Time Event Selection
-#define 	AT91C_RTC_TIMEVSEL_MINUTE               (0x0 <<  8) // (RTC) Minute change.
-#define 	AT91C_RTC_TIMEVSEL_HOUR                 (0x1 <<  8) // (RTC) Hour change.
-#define 	AT91C_RTC_TIMEVSEL_DAY24                (0x2 <<  8) // (RTC) Every day at midnight.
-#define 	AT91C_RTC_TIMEVSEL_DAY12                (0x3 <<  8) // (RTC) Every day at noon.
-#define AT91C_RTC_CALEVSEL        (0x3 << 16) // (RTC) Calendar Event Selection
-#define 	AT91C_RTC_CALEVSEL_WEEK                 (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).
-#define 	AT91C_RTC_CALEVSEL_MONTH                (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).
-#define 	AT91C_RTC_CALEVSEL_YEAR                 (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).
-// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- 
-#define AT91C_RTC_HRMOD           (0x1 <<  0) // (RTC) 12-24 hour Mode
-// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- 
-#define AT91C_RTC_SEC             (0x7F <<  0) // (RTC) Current Second
-#define AT91C_RTC_MIN             (0x7F <<  8) // (RTC) Current Minute
-#define AT91C_RTC_HOUR            (0x1F << 16) // (RTC) Current Hour
-#define AT91C_RTC_AMPM            (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator
-// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- 
-#define AT91C_RTC_CENT            (0x3F <<  0) // (RTC) Current Century
-#define AT91C_RTC_YEAR            (0xFF <<  8) // (RTC) Current Year
-#define AT91C_RTC_MONTH           (0x1F << 16) // (RTC) Current Month
-#define AT91C_RTC_DAY             (0x7 << 21) // (RTC) Current Day
-#define AT91C_RTC_DATE            (0x3F << 24) // (RTC) Current Date
-// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- 
-#define AT91C_RTC_SECEN           (0x1 <<  7) // (RTC) Second Alarm Enable
-#define AT91C_RTC_MINEN           (0x1 << 15) // (RTC) Minute Alarm
-#define AT91C_RTC_HOUREN          (0x1 << 23) // (RTC) Current Hour
-// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- 
-#define AT91C_RTC_MONTHEN         (0x1 << 23) // (RTC) Month Alarm Enable
-#define AT91C_RTC_DATEEN          (0x1 << 31) // (RTC) Date Alarm Enable
-// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- 
-#define AT91C_RTC_ACKUPD          (0x1 <<  0) // (RTC) Acknowledge for Update
-#define AT91C_RTC_ALARM           (0x1 <<  1) // (RTC) Alarm Flag
-#define AT91C_RTC_SECEV           (0x1 <<  2) // (RTC) Second Event
-#define AT91C_RTC_TIMEV           (0x1 <<  3) // (RTC) Time Event
-#define AT91C_RTC_CALEV           (0x1 <<  4) // (RTC) Calendar event
-// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- 
-// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- 
-// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- 
-// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- 
-// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- 
-#define AT91C_RTC_NVTIM           (0x1 <<  0) // (RTC) Non valid Time
-#define AT91C_RTC_NVCAL           (0x1 <<  1) // (RTC) Non valid Calendar
-#define AT91C_RTC_NVTIMALR        (0x1 <<  2) // (RTC) Non valid time Alarm
-#define AT91C_RTC_NVCALALR        (0x1 <<  3) // (RTC) Nonvalid Calendar Alarm
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Timer Interface
-// *****************************************************************************
-// *** Register offset in AT91S_ST structure ***
-#define ST_CR           ( 0) // Control Register
-#define ST_PIMR         ( 4) // Period Interval Mode Register
-#define ST_WDMR         ( 8) // Watchdog Mode Register
-#define ST_RTMR         (12) // Real-time Mode Register
-#define ST_SR           (16) // Status Register
-#define ST_IER          (20) // Interrupt Enable Register
-#define ST_IDR          (24) // Interrupt Disable Register
-#define ST_IMR          (28) // Interrupt Mask Register
-#define ST_RTAR         (32) // Real-time Alarm Register
-#define ST_CRTR         (36) // Current Real-time Register
-// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- 
-#define AT91C_ST_WDRST            (0x1 <<  0) // (ST) Watchdog Timer Restart
-// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- 
-#define AT91C_ST_PIV              (0xFFFF <<  0) // (ST) Watchdog Timer Restart
-// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- 
-#define AT91C_ST_WDV              (0xFFFF <<  0) // (ST) Watchdog Timer Restart
-#define AT91C_ST_RSTEN            (0x1 << 16) // (ST) Reset Enable
-#define AT91C_ST_EXTEN            (0x1 << 17) // (ST) External Signal Assertion Enable
-// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- 
-#define AT91C_ST_RTPRES           (0xFFFF <<  0) // (ST) Real-time Timer Prescaler Value
-// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- 
-#define AT91C_ST_PITS             (0x1 <<  0) // (ST) Period Interval Timer Interrupt
-#define AT91C_ST_WDOVF            (0x1 <<  1) // (ST) Watchdog Overflow
-#define AT91C_ST_RTTINC           (0x1 <<  2) // (ST) Real-time Timer Increment
-#define AT91C_ST_ALMS             (0x1 <<  3) // (ST) Alarm Status
-// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- 
-// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- 
-// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- 
-// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- 
-#define AT91C_ST_ALMV             (0xFFFFF <<  0) // (ST) Alarm Value Value
-// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- 
-#define AT91C_ST_CRTV             (0xFFFFF <<  0) // (ST) Current Real-time Value
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PMC structure ***
-#define PMC_SCER        ( 0) // System Clock Enable Register
-#define PMC_SCDR        ( 4) // System Clock Disable Register
-#define PMC_SCSR        ( 8) // System Clock Status Register
-#define PMC_PCER        (16) // Peripheral Clock Enable Register
-#define PMC_PCDR        (20) // Peripheral Clock Disable Register
-#define PMC_PCSR        (24) // Peripheral Clock Status Register
-#define PMC_MCKR        (48) // Master Clock Register
-#define PMC_PCKR        (64) // Programmable Clock Register
-#define PMC_IER         (96) // Interrupt Enable Register
-#define PMC_IDR         (100) // Interrupt Disable Register
-#define PMC_SR          (104) // Status Register
-#define PMC_IMR         (108) // Interrupt Mask Register
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP             (0x1 <<  1) // (PMC) USB Device Port Clock
-#define AT91C_PMC_MCKUDP          (0x1 <<  2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend
-#define AT91C_PMC_UHP             (0x1 <<  4) // (PMC) USB Host Port Clock
-#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK4            (0x1 << 12) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK5            (0x1 << 13) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK6            (0x1 << 14) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK7            (0x1 << 15) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLLA_CLK             (0x2) // (PMC) Clock from PLL A is selected
-#define 	AT91C_PMC_CSS_PLLB_CLK             (0x3) // (PMC) Clock from PLL B is selected
-#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-#define AT91C_PMC_MDIV            (0x3 <<  8) // (PMC) Master Clock Division
-#define 	AT91C_PMC_MDIV_1                    (0x0 <<  8) // (PMC) The master clock and the processor clock are the same
-#define 	AT91C_PMC_MDIV_2                    (0x1 <<  8) // (PMC) The processor clock is twice as fast as the master clock
-#define 	AT91C_PMC_MDIV_3                    (0x2 <<  8) // (PMC) The processor clock is three times faster than the master clock
-#define 	AT91C_PMC_MDIV_4                    (0x3 <<  8) // (PMC) The processor clock is four times faster than the master clock
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCKA           (0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCKB           (0x1 <<  2) // (PMC) PLL B Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK4RDY         (0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK5RDY         (0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK6RDY         (0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK7RDY         (0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-// *** Register offset in AT91S_CKGR structure ***
-#define CKGR_MOR        ( 0) // Main Oscillator Register
-#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
-#define CKGR_PLLAR      ( 8) // PLL A Register
-#define CKGR_PLLBR      (12) // PLL B Register
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCTEST        (0x1 <<  1) // (CKGR) Oscillator Test
-#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- 
-#define AT91C_CKGR_DIVA           (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIVA_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIVA_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLACOUNT      (0x3F <<  8) // (CKGR) PLL A Counter
-#define AT91C_CKGR_OUTA           (0x3 << 14) // (CKGR) PLL A Output Frequency Range
-#define 	AT91C_CKGR_OUTA_0                    (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
-#define 	AT91C_CKGR_OUTA_1                    (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
-#define 	AT91C_CKGR_OUTA_2                    (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
-#define 	AT91C_CKGR_OUTA_3                    (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
-#define AT91C_CKGR_MULA           (0x7FF << 16) // (CKGR) PLL A Multiplier
-#define AT91C_CKGR_SRCA           (0x1 << 29) // (CKGR) PLL A Source
-// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIVB           (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIVB_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIVB_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLBCOUNT      (0x3F <<  8) // (CKGR) PLL B Counter
-#define AT91C_CKGR_OUTB           (0x3 << 14) // (CKGR) PLL B Output Frequency Range
-#define 	AT91C_CKGR_OUTB_0                    (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
-#define 	AT91C_CKGR_OUTB_1                    (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
-#define 	AT91C_CKGR_OUTB_2                    (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
-#define 	AT91C_CKGR_OUTB_3                    (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
-#define AT91C_CKGR_MULB           (0x7FF << 16) // (CKGR) PLL B Multiplier
-#define AT91C_CKGR_USB_96M        (0x1 << 28) // (CKGR) Divider for USB Ports
-#define AT91C_CKGR_USB_PLL        (0x1 << 29) // (CKGR) PLL Use
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PIO structure ***
-#define PIO_PER         ( 0) // PIO Enable Register
-#define PIO_PDR         ( 4) // PIO Disable Register
-#define PIO_PSR         ( 8) // PIO Status Register
-#define PIO_OER         (16) // Output Enable Register
-#define PIO_ODR         (20) // Output Disable Registerr
-#define PIO_OSR         (24) // Output Status Register
-#define PIO_IFER        (32) // Input Filter Enable Register
-#define PIO_IFDR        (36) // Input Filter Disable Register
-#define PIO_IFSR        (40) // Input Filter Status Register
-#define PIO_SODR        (48) // Set Output Data Register
-#define PIO_CODR        (52) // Clear Output Data Register
-#define PIO_ODSR        (56) // Output Data Status Register
-#define PIO_PDSR        (60) // Pin Data Status Register
-#define PIO_IER         (64) // Interrupt Enable Register
-#define PIO_IDR         (68) // Interrupt Disable Register
-#define PIO_IMR         (72) // Interrupt Mask Register
-#define PIO_ISR         (76) // Interrupt Status Register
-#define PIO_MDER        (80) // Multi-driver Enable Register
-#define PIO_MDDR        (84) // Multi-driver Disable Register
-#define PIO_MDSR        (88) // Multi-driver Status Register
-#define PIO_PPUDR       (96) // Pull-up Disable Register
-#define PIO_PPUER       (100) // Pull-up Enable Register
-#define PIO_PPUSR       (104) // Pad Pull-up Status Register
-#define PIO_ASR         (112) // Select A Register
-#define PIO_BSR         (116) // Select B Register
-#define PIO_ABSR        (120) // AB Select Status Register
-#define PIO_OWER        (160) // Output Write Enable Register
-#define PIO_OWDR        (164) // Output Write Disable Register
-#define PIO_OWSR        (168) // Output Write Status Register
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-// *** Register offset in AT91S_DBGU structure ***
-#define DBGU_CR         ( 0) // Control Register
-#define DBGU_MR         ( 4) // Mode Register
-#define DBGU_IER        ( 8) // Interrupt Enable Register
-#define DBGU_IDR        (12) // Interrupt Disable Register
-#define DBGU_IMR        (16) // Interrupt Mask Register
-#define DBGU_CSR        (20) // Channel Status Register
-#define DBGU_RHR        (24) // Receiver Holding Register
-#define DBGU_THR        (28) // Transmitter Holding Register
-#define DBGU_BRGR       (32) // Baud Rate Generator Register
-#define DBGU_C1R        (64) // Chip ID1 Register
-#define DBGU_C2R        (68) // Chip ID2 Register
-#define DBGU_FNTR       (72) // Force NTRST Register
-#define DBGU_RPR        (256) // Receive Pointer Register
-#define DBGU_RCR        (260) // Receive Counter Register
-#define DBGU_TPR        (264) // Transmit Pointer Register
-#define DBGU_TCR        (268) // Transmit Counter Register
-#define DBGU_RNPR       (272) // Receive Next Pointer Register
-#define DBGU_RNCR       (276) // Receive Next Counter Register
-#define DBGU_TNPR       (280) // Transmit Next Pointer Register
-#define DBGU_TNCR       (284) // Transmit Next Counter Register
-#define DBGU_PTCR       (288) // PDC Transfer Control Register
-#define DBGU_PTSR       (292) // PDC Transfer Status Register
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
-// *****************************************************************************
-// *** Register offset in AT91S_PDC structure ***
-#define PDC_RPR         ( 0) // Receive Pointer Register
-#define PDC_RCR         ( 4) // Receive Counter Register
-#define PDC_TPR         ( 8) // Transmit Pointer Register
-#define PDC_TCR         (12) // Transmit Counter Register
-#define PDC_RNPR        (16) // Receive Next Pointer Register
-#define PDC_RNCR        (20) // Receive Next Counter Register
-#define PDC_TNPR        (24) // Transmit Next Pointer Register
-#define PDC_TNCR        (28) // Transmit Next Counter Register
-#define PDC_PTCR        (32) // PDC Transfer Control Register
-#define PDC_PTSR        (36) // PDC Transfer Status Register
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-// *** Register offset in AT91S_AIC structure ***
-#define AIC_SMR         ( 0) // Source Mode Register
-#define AIC_SVR         (128) // Source Vector Register
-#define AIC_IVR         (256) // IRQ Vector Register
-#define AIC_FVR         (260) // FIQ Vector Register
-#define AIC_ISR         (264) // Interrupt Status Register
-#define AIC_IPR         (268) // Interrupt Pending Register
-#define AIC_IMR         (272) // Interrupt Mask Register
-#define AIC_CISR        (276) // Core Interrupt Status Register
-#define AIC_IECR        (288) // Interrupt Enable Command Register
-#define AIC_IDCR        (292) // Interrupt Disable Command Register
-#define AIC_ICCR        (296) // Interrupt Clear Command Register
-#define AIC_ISCR        (300) // Interrupt Set Command Register
-#define AIC_EOICR       (304) // End of Interrupt Command Register
-#define AIC_SPU         (308) // Spurious Vector Register
-#define AIC_DCR         (312) // Debug Control Register (Protect)
-#define AIC_FFER        (320) // Fast Forcing Enable Register
-#define AIC_FFDR        (324) // Fast Forcing Disable Register
-#define AIC_FFSR        (328) // Fast Forcing Status Register
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SPI structure ***
-#define SPI_CR          ( 0) // Control Register
-#define SPI_MR          ( 4) // Mode Register
-#define SPI_RDR         ( 8) // Receive Data Register
-#define SPI_TDR         (12) // Transmit Data Register
-#define SPI_SR          (16) // Status Register
-#define SPI_IER         (20) // Interrupt Enable Register
-#define SPI_IDR         (24) // Interrupt Disable Register
-#define SPI_IMR         (28) // Interrupt Mask Register
-#define SPI_CSR         (48) // Chip Select Register
-#define SPI_RPR         (256) // Receive Pointer Register
-#define SPI_RCR         (260) // Receive Counter Register
-#define SPI_TPR         (264) // Transmit Pointer Register
-#define SPI_TCR         (268) // Transmit Counter Register
-#define SPI_RNPR        (272) // Receive Next Pointer Register
-#define SPI_RNCR        (276) // Receive Next Counter Register
-#define SPI_TNPR        (280) // Transmit Next Pointer Register
-#define SPI_TNCR        (284) // Transmit Next Counter Register
-#define SPI_PTCR        (288) // PDC Transfer Control Register
-#define SPI_PTSR        (292) // PDC Transfer Status Register
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_DIV32           (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_SPENDRX         (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_SPENDTX         (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SSC structure ***
-#define SSC_CR          ( 0) // Control Register
-#define SSC_CMR         ( 4) // Clock Mode Register
-#define SSC_RCMR        (16) // Receive Clock ModeRegister
-#define SSC_RFMR        (20) // Receive Frame Mode Register
-#define SSC_TCMR        (24) // Transmit Clock Mode Register
-#define SSC_TFMR        (28) // Transmit Frame Mode Register
-#define SSC_RHR         (32) // Receive Holding Register
-#define SSC_THR         (36) // Transmit Holding Register
-#define SSC_RSHR        (48) // Receive Sync Holding Register
-#define SSC_TSHR        (52) // Transmit Sync Holding Register
-#define SSC_RC0R        (56) // Receive Compare 0 Register
-#define SSC_RC1R        (60) // Receive Compare 1 Register
-#define SSC_SR          (64) // Status Register
-#define SSC_IER         (68) // Interrupt Enable Register
-#define SSC_IDR         (72) // Interrupt Disable Register
-#define SSC_IMR         (76) // Interrupt Mask Register
-#define SSC_RPR         (256) // Receive Pointer Register
-#define SSC_RCR         (260) // Receive Counter Register
-#define SSC_TPR         (264) // Transmit Pointer Register
-#define SSC_TCR         (268) // Transmit Counter Register
-#define SSC_RNPR        (272) // Receive Next Pointer Register
-#define SSC_RNCR        (276) // Receive Next Counter Register
-#define SSC_TNPR        (280) // Transmit Next Pointer Register
-#define SSC_TNCR        (284) // Transmit Next Counter Register
-#define SSC_PTCR        (288) // PDC Transfer Control Register
-#define SSC_PTSR        (292) // PDC Transfer Status Register
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG             (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
-#define 	AT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define 	AT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define 	AT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STOP            (0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTOUT          (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
-#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0             (0x1 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_CP1             (0x1 <<  9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-// *** Register offset in AT91S_USART structure ***
-#define US_CR           ( 0) // Control Register
-#define US_MR           ( 4) // Mode Register
-#define US_IER          ( 8) // Interrupt Enable Register
-#define US_IDR          (12) // Interrupt Disable Register
-#define US_IMR          (16) // Interrupt Mask Register
-#define US_CSR          (20) // Channel Status Register
-#define US_RHR          (24) // Receiver Holding Register
-#define US_THR          (28) // Transmitter Holding Register
-#define US_BRGR         (32) // Baud Rate Generator Register
-#define US_RTOR         (36) // Receiver Time-out Register
-#define US_TTGR         (40) // Transmitter Time-guard Register
-#define US_FIDI         (64) // FI_DI_Ratio Register
-#define US_NER          (68) // Nb Errors Register
-#define US_XXR          (72) // XON_XOFF Register
-#define US_IF           (76) // IRDA_FILTER Register
-#define US_RPR          (256) // Receive Pointer Register
-#define US_RCR          (260) // Receive Counter Register
-#define US_TPR          (264) // Transmit Pointer Register
-#define US_TCR          (268) // Transmit Counter Register
-#define US_RNPR         (272) // Receive Next Pointer Register
-#define US_RNCR         (276) // Receive Next Counter Register
-#define US_TNPR         (280) // Transmit Next Pointer Register
-#define US_TNCR         (284) // Transmit Next Counter Register
-#define US_PTCR         (288) // PDC Transfer Control Register
-#define US_PTSR         (292) // PDC Transfer Status Register
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTSTA           (0x1 <<  8) // (USART) Reset Status Bits
-#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TWI structure ***
-#define TWI_CR          ( 0) // Control Register
-#define TWI_MMR         ( 4) // Master Mode Register
-#define TWI_SMR         ( 8) // Slave Mode Register
-#define TWI_IADR        (12) // Internal Address Register
-#define TWI_CWGR        (16) // Clock Waveform Generator Register
-#define TWI_SR          (32) // Status Register
-#define TWI_IER         (36) // Interrupt Enable Register
-#define TWI_IDR         (40) // Interrupt Disable Register
-#define TWI_IMR         (44) // Interrupt Mask Register
-#define TWI_RHR         (48) // Receive Holding Register
-#define TWI_THR         (52) // Transmit Holding Register
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SVEN            (0x1 <<  4) // (TWI) TWI Slave Transfer Enabled
-#define AT91C_TWI_SVDIS           (0x1 <<  5) // (TWI) TWI Slave Transfer Disabled
-#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
-// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
-#define AT91C_TWI_SADR            (0x7F << 16) // (TWI) Slave Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_SVREAD          (0x1 <<  3) // (TWI) Slave Read
-#define AT91C_TWI_SVACC           (0x1 <<  4) // (TWI) Slave Access
-#define AT91C_TWI_GCACC           (0x1 <<  5) // (TWI) General Call Access
-#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ARBLST          (0x1 <<  9) // (TWI) Arbitration Lost
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface
-// *****************************************************************************
-// *** Register offset in AT91S_MCI structure ***
-#define MCI_CR          ( 0) // MCI Control Register
-#define MCI_MR          ( 4) // MCI Mode Register
-#define MCI_DTOR        ( 8) // MCI Data Timeout Register
-#define MCI_SDCR        (12) // MCI SD Card Register
-#define MCI_ARGR        (16) // MCI Argument Register
-#define MCI_CMDR        (20) // MCI Command Register
-#define MCI_RSPR        (32) // MCI Response Register
-#define MCI_RDR         (48) // MCI Receive Data Register
-#define MCI_TDR         (52) // MCI Transmit Data Register
-#define MCI_SR          (64) // MCI Status Register
-#define MCI_IER         (68) // MCI Interrupt Enable Register
-#define MCI_IDR         (72) // MCI Interrupt Disable Register
-#define MCI_IMR         (76) // MCI Interrupt Mask Register
-#define MCI_RPR         (256) // Receive Pointer Register
-#define MCI_RCR         (260) // Receive Counter Register
-#define MCI_TPR         (264) // Transmit Pointer Register
-#define MCI_TCR         (268) // Transmit Counter Register
-#define MCI_RNPR        (272) // Receive Next Pointer Register
-#define MCI_RNCR        (276) // Receive Next Counter Register
-#define MCI_TNPR        (280) // Transmit Next Pointer Register
-#define MCI_TNCR        (284) // Transmit Next Counter Register
-#define MCI_PTCR        (288) // PDC Transfer Control Register
-#define MCI_PTSR        (292) // PDC Transfer Status Register
-// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- 
-#define AT91C_MCI_MCIEN           (0x1 <<  0) // (MCI) Multimedia Interface Enable
-#define AT91C_MCI_MCIDIS          (0x1 <<  1) // (MCI) Multimedia Interface Disable
-#define AT91C_MCI_PWSEN           (0x1 <<  2) // (MCI) Power Save Mode Enable
-#define AT91C_MCI_PWSDIS          (0x1 <<  3) // (MCI) Power Save Mode Disable
-// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- 
-#define AT91C_MCI_CLKDIV          (0x1 <<  0) // (MCI) Clock Divider
-#define AT91C_MCI_PWSDIV          (0x1 <<  8) // (MCI) Power Saving Divider
-#define AT91C_MCI_PDCPADV         (0x1 << 14) // (MCI) PDC Padding Value
-#define AT91C_MCI_PDCMODE         (0x1 << 15) // (MCI) PDC Oriented Mode
-#define AT91C_MCI_BLKLEN          (0x1 << 18) // (MCI) Data Block Length
-// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- 
-#define AT91C_MCI_DTOCYC          (0x1 <<  0) // (MCI) Data Timeout Cycle Number
-#define AT91C_MCI_DTOMUL          (0x7 <<  4) // (MCI) Data Timeout Multiplier
-#define 	AT91C_MCI_DTOMUL_1                    (0x0 <<  4) // (MCI) DTOCYC x 1
-#define 	AT91C_MCI_DTOMUL_16                   (0x1 <<  4) // (MCI) DTOCYC x 16
-#define 	AT91C_MCI_DTOMUL_128                  (0x2 <<  4) // (MCI) DTOCYC x 128
-#define 	AT91C_MCI_DTOMUL_256                  (0x3 <<  4) // (MCI) DTOCYC x 256
-#define 	AT91C_MCI_DTOMUL_1024                 (0x4 <<  4) // (MCI) DTOCYC x 1024
-#define 	AT91C_MCI_DTOMUL_4096                 (0x5 <<  4) // (MCI) DTOCYC x 4096
-#define 	AT91C_MCI_DTOMUL_65536                (0x6 <<  4) // (MCI) DTOCYC x 65536
-#define 	AT91C_MCI_DTOMUL_1048576              (0x7 <<  4) // (MCI) DTOCYC x 1048576
-// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- 
-#define AT91C_MCI_SCDSEL          (0x1 <<  0) // (MCI) SD Card Selector
-#define AT91C_MCI_SCDBUS          (0x1 <<  7) // (MCI) SD Card Bus Width
-// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- 
-#define AT91C_MCI_CMDNB           (0x1F <<  0) // (MCI) Command Number
-#define AT91C_MCI_RSPTYP          (0x3 <<  6) // (MCI) Response Type
-#define 	AT91C_MCI_RSPTYP_NO                   (0x0 <<  6) // (MCI) No response
-#define 	AT91C_MCI_RSPTYP_48                   (0x1 <<  6) // (MCI) 48-bit response
-#define 	AT91C_MCI_RSPTYP_136                  (0x2 <<  6) // (MCI) 136-bit response
-#define AT91C_MCI_SPCMD           (0x7 <<  8) // (MCI) Special CMD
-#define 	AT91C_MCI_SPCMD_NONE                 (0x0 <<  8) // (MCI) Not a special CMD
-#define 	AT91C_MCI_SPCMD_INIT                 (0x1 <<  8) // (MCI) Initialization CMD
-#define 	AT91C_MCI_SPCMD_SYNC                 (0x2 <<  8) // (MCI) Synchronized CMD
-#define 	AT91C_MCI_SPCMD_IT_CMD               (0x4 <<  8) // (MCI) Interrupt command
-#define 	AT91C_MCI_SPCMD_IT_REP               (0x5 <<  8) // (MCI) Interrupt response
-#define AT91C_MCI_OPDCMD          (0x1 << 11) // (MCI) Open Drain Command
-#define AT91C_MCI_MAXLAT          (0x1 << 12) // (MCI) Maximum Latency for Command to respond
-#define AT91C_MCI_TRCMD           (0x3 << 16) // (MCI) Transfer CMD
-#define 	AT91C_MCI_TRCMD_NO                   (0x0 << 16) // (MCI) No transfer
-#define 	AT91C_MCI_TRCMD_START                (0x1 << 16) // (MCI) Start transfer
-#define 	AT91C_MCI_TRCMD_STOP                 (0x2 << 16) // (MCI) Stop transfer
-#define AT91C_MCI_TRDIR           (0x1 << 18) // (MCI) Transfer Direction
-#define AT91C_MCI_TRTYP           (0x3 << 19) // (MCI) Transfer Type
-#define 	AT91C_MCI_TRTYP_BLOCK                (0x0 << 19) // (MCI) Block Transfer type
-#define 	AT91C_MCI_TRTYP_MULTIPLE             (0x1 << 19) // (MCI) Multiple Block transfer type
-#define 	AT91C_MCI_TRTYP_STREAM               (0x2 << 19) // (MCI) Stream transfer type
-// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- 
-#define AT91C_MCI_CMDRDY          (0x1 <<  0) // (MCI) Command Ready flag
-#define AT91C_MCI_RXRDY           (0x1 <<  1) // (MCI) RX Ready flag
-#define AT91C_MCI_TXRDY           (0x1 <<  2) // (MCI) TX Ready flag
-#define AT91C_MCI_BLKE            (0x1 <<  3) // (MCI) Data Block Transfer Ended flag
-#define AT91C_MCI_DTIP            (0x1 <<  4) // (MCI) Data Transfer in Progress flag
-#define AT91C_MCI_NOTBUSY         (0x1 <<  5) // (MCI) Data Line Not Busy flag
-#define AT91C_MCI_ENDRX           (0x1 <<  6) // (MCI) End of RX Buffer flag
-#define AT91C_MCI_ENDTX           (0x1 <<  7) // (MCI) End of TX Buffer flag
-#define AT91C_MCI_RXBUFF          (0x1 << 14) // (MCI) RX Buffer Full flag
-#define AT91C_MCI_TXBUFE          (0x1 << 15) // (MCI) TX Buffer Empty flag
-#define AT91C_MCI_RINDE           (0x1 << 16) // (MCI) Response Index Error flag
-#define AT91C_MCI_RDIRE           (0x1 << 17) // (MCI) Response Direction Error flag
-#define AT91C_MCI_RCRCE           (0x1 << 18) // (MCI) Response CRC Error flag
-#define AT91C_MCI_RENDE           (0x1 << 19) // (MCI) Response End Bit Error flag
-#define AT91C_MCI_RTOE            (0x1 << 20) // (MCI) Response Time-out Error flag
-#define AT91C_MCI_DCRCE           (0x1 << 21) // (MCI) data CRC Error flag
-#define AT91C_MCI_DTOE            (0x1 << 22) // (MCI) Data timeout Error flag
-#define AT91C_MCI_OVRE            (0x1 << 30) // (MCI) Overrun flag
-#define AT91C_MCI_UNRE            (0x1 << 31) // (MCI) Underrun flag
-// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- 
-// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- 
-// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-// *** Register offset in AT91S_UDP structure ***
-#define UDP_NUM         ( 0) // Frame Number Register
-#define UDP_GLBSTATE    ( 4) // Global State Register
-#define UDP_FADDR       ( 8) // Function Address Register
-#define UDP_IER         (16) // Interrupt Enable Register
-#define UDP_IDR         (20) // Interrupt Disable Register
-#define UDP_IMR         (24) // Interrupt Mask Register
-#define UDP_ISR         (28) // Interrupt Status Register
-#define UDP_ICR         (32) // Interrupt Clear Register
-#define UDP_RSTEP       (40) // Reset Endpoint Register
-#define UDP_CSR         (48) // Endpoint Control and Status Register
-#define UDP_FDR         (80) // Endpoint FIFO Data Register
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_RMWUPE          (0x1 <<  2) // (UDP) Remote Wake Up Enable
-#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_EPINT6          (0x1 <<  6) // (UDP) Endpoint 6 Interrupt
-#define AT91C_UDP_EPINT7          (0x1 <<  7) // (UDP) Endpoint 7 Interrupt
-#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
-#define AT91C_UDP_EP6             (0x1 <<  6) // (UDP) Reset Endpoint 6
-#define AT91C_UDP_EP7             (0x1 <<  7) // (UDP) Reset Endpoint 7
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TC structure ***
-#define TC_CCR          ( 0) // Channel Control Register
-#define TC_CMR          ( 4) // Channel Mode Register
-#define TC_CV           (16) // Counter Value
-#define TC_RA           (20) // Register A
-#define TC_RB           (24) // Register B
-#define TC_RC           (28) // Register C
-#define TC_SR           (32) // Status Register
-#define TC_IER          (36) // Interrupt Enable Register
-#define TC_IDR          (40) // Interrupt Disable Register
-#define TC_IMR          (44) // Interrupt Mask Register
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_NONE                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_RISING               (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_FALLING              (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_BOTH                 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE             (0x1 << 15) // (TC) 
-#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRCS            (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_ETRGS            (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TCB structure ***
-#define TCB_TC0         ( 0) // TC Channel 0
-#define TCB_TC1         (64) // TC Channel 1
-#define TCB_TC2         (128) // TC Channel 2
-#define TCB_BCR         (192) // TC Block Control Register
-#define TCB_BMR         (196) // TC Block Mode Register
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S         (0x1 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S         (0x1 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S         (0x1 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA2                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Host Interface
-// *****************************************************************************
-// *** Register offset in AT91S_UHP structure ***
-#define UHP_HcRevision  ( 0) // Revision
-#define UHP_HcControl   ( 4) // Operating modes for the Host Controller
-#define UHP_HcCommandStatus ( 8) // Command & status Register
-#define UHP_HcInterruptStatus (12) // Interrupt Status Register
-#define UHP_HcInterruptEnable (16) // Interrupt Enable Register
-#define UHP_HcInterruptDisable (20) // Interrupt Disable Register
-#define UHP_HcHCCA      (24) // Pointer to the Host Controller Communication Area
-#define UHP_HcPeriodCurrentED (28) // Current Isochronous or Interrupt Endpoint Descriptor
-#define UHP_HcControlHeadED (32) // First Endpoint Descriptor of the Control list
-#define UHP_HcControlCurrentED (36) // Endpoint Control and Status Register
-#define UHP_HcBulkHeadED (40) // First endpoint register of the Bulk list
-#define UHP_HcBulkCurrentED (44) // Current endpoint of the Bulk list
-#define UHP_HcBulkDoneHead (48) // Last completed transfer descriptor
-#define UHP_HcFmInterval (52) // Bit time between 2 consecutive SOFs
-#define UHP_HcFmRemaining (56) // Bit time remaining in the current Frame
-#define UHP_HcFmNumber  (60) // Frame number
-#define UHP_HcPeriodicStart (64) // Periodic Start
-#define UHP_HcLSThreshold (68) // LS Threshold
-#define UHP_HcRhDescriptorA (72) // Root Hub characteristics A
-#define UHP_HcRhDescriptorB (76) // Root Hub characteristics B
-#define UHP_HcRhStatus  (80) // Root Hub Status register
-#define UHP_HcRhPortStatus (84) // Root Hub Port Status Register
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC
-// *****************************************************************************
-// *** Register offset in AT91S_EMAC structure ***
-#define EMAC_CTL        ( 0) // Network Control Register
-#define EMAC_CFG        ( 4) // Network Configuration Register
-#define EMAC_SR         ( 8) // Network Status Register
-#define EMAC_TAR        (12) // Transmit Address Register
-#define EMAC_TCR        (16) // Transmit Control Register
-#define EMAC_TSR        (20) // Transmit Status Register
-#define EMAC_RBQP       (24) // Receive Buffer Queue Pointer
-#define EMAC_RSR        (32) // Receive Status Register
-#define EMAC_ISR        (36) // Interrupt Status Register
-#define EMAC_IER        (40) // Interrupt Enable Register
-#define EMAC_IDR        (44) // Interrupt Disable Register
-#define EMAC_IMR        (48) // Interrupt Mask Register
-#define EMAC_MAN        (52) // PHY Maintenance Register
-#define EMAC_FRA        (64) // Frames Transmitted OK Register
-#define EMAC_SCOL       (68) // Single Collision Frame Register
-#define EMAC_MCOL       (72) // Multiple Collision Frame Register
-#define EMAC_OK         (76) // Frames Received OK Register
-#define EMAC_SEQE       (80) // Frame Check Sequence Error Register
-#define EMAC_ALE        (84) // Alignment Error Register
-#define EMAC_DTE        (88) // Deferred Transmission Frame Register
-#define EMAC_LCOL       (92) // Late Collision Register
-#define EMAC_ECOL       (96) // Excessive Collision Register
-#define EMAC_CSE        (100) // Carrier Sense Error Register
-#define EMAC_TUE        (104) // Transmit Underrun Error Register
-#define EMAC_CDE        (108) // Code Error Register
-#define EMAC_ELR        (112) // Excessive Length Error Register
-#define EMAC_RJB        (116) // Receive Jabber Register
-#define EMAC_USF        (120) // Undersize Frame Register
-#define EMAC_SQEE       (124) // SQE Test Error Register
-#define EMAC_DRFC       (128) // Discarded RX Frame Register
-#define EMAC_HSH        (144) // Hash Address High[63:32]
-#define EMAC_HSL        (148) // Hash Address Low[31:0]
-#define EMAC_SA1L       (152) // Specific Address 1 Low, First 4 bytes
-#define EMAC_SA1H       (156) // Specific Address 1 High, Last 2 bytes
-#define EMAC_SA2L       (160) // Specific Address 2 Low, First 4 bytes
-#define EMAC_SA2H       (164) // Specific Address 2 High, Last 2 bytes
-#define EMAC_SA3L       (168) // Specific Address 3 Low, First 4 bytes
-#define EMAC_SA3H       (172) // Specific Address 3 High, Last 2 bytes
-#define EMAC_SA4L       (176) // Specific Address 4 Low, First 4 bytes
-#define EMAC_SA4H       (180) // Specific Address 4 High, Last 2 bytesr
-// -------- EMAC_CTL : (EMAC Offset: 0x0)  -------- 
-#define AT91C_EMAC_LB             (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LBL            (0x1 <<  1) // (EMAC) Loopback local. 
-#define AT91C_EMAC_RE             (0x1 <<  2) // (EMAC) Receive enable. 
-#define AT91C_EMAC_TE             (0x1 <<  3) // (EMAC) Transmit enable. 
-#define AT91C_EMAC_MPE            (0x1 <<  4) // (EMAC) Management port enable. 
-#define AT91C_EMAC_CSR            (0x1 <<  5) // (EMAC) Clear statistics registers. 
-#define AT91C_EMAC_ISR            (0x1 <<  6) // (EMAC) Increment statistics registers. 
-#define AT91C_EMAC_WES            (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
-#define AT91C_EMAC_BP             (0x1 <<  8) // (EMAC) Back pressure. 
-// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- 
-#define AT91C_EMAC_SPD            (0x1 <<  0) // (EMAC) Speed. 
-#define AT91C_EMAC_FD             (0x1 <<  1) // (EMAC) Full duplex. 
-#define AT91C_EMAC_BR             (0x1 <<  2) // (EMAC) Bit rate. 
-#define AT91C_EMAC_CAF            (0x1 <<  4) // (EMAC) Copy all frames. 
-#define AT91C_EMAC_NBC            (0x1 <<  5) // (EMAC) No broadcast. 
-#define AT91C_EMAC_MTI            (0x1 <<  6) // (EMAC) Multicast hash enable
-#define AT91C_EMAC_UNI            (0x1 <<  7) // (EMAC) Unicast hash enable. 
-#define AT91C_EMAC_BIG            (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
-#define AT91C_EMAC_EAE            (0x1 <<  9) // (EMAC) External address match enable. 
-#define AT91C_EMAC_CLK            (0x3 << 10) // (EMAC) 
-#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY            (0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_RMII           (0x1 << 13) // (EMAC) 
-// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- 
-#define AT91C_EMAC_MDIO           (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_IDLE           (0x1 <<  2) // (EMAC) 
-// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- 
-#define AT91C_EMAC_LEN            (0x7FF <<  0) // (EMAC) 
-#define AT91C_EMAC_NCRC           (0x1 << 15) // (EMAC) 
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- 
-#define AT91C_EMAC_OVR            (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_COL            (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RLE            (0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TXIDLE         (0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_BNQ            (0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_COMP           (0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_UND            (0x1 <<  6) // (EMAC) 
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-#define AT91C_EMAC_BNA            (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_REC            (0x1 <<  1) // (EMAC) 
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-#define AT91C_EMAC_DONE           (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_RCOM           (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RBNA           (0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TOVR           (0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_TUND           (0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_RTRY           (0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_TBRE           (0x1 <<  6) // (EMAC) 
-#define AT91C_EMAC_TCOM           (0x1 <<  7) // (EMAC) 
-#define AT91C_EMAC_TIDLE          (0x1 <<  8) // (EMAC) 
-#define AT91C_EMAC_LINK           (0x1 <<  9) // (EMAC) 
-#define AT91C_EMAC_ROVR           (0x1 << 10) // (EMAC) 
-#define AT91C_EMAC_HRESP          (0x1 << 11) // (EMAC) 
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-#define AT91C_EMAC_DATA           (0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_CODE           (0x3 << 16) // (EMAC) 
-#define AT91C_EMAC_REGA           (0x1F << 18) // (EMAC) 
-#define AT91C_EMAC_PHYA           (0x1F << 23) // (EMAC) 
-#define AT91C_EMAC_RW             (0x3 << 28) // (EMAC) 
-#define AT91C_EMAC_HIGH           (0x1 << 30) // (EMAC) 
-#define AT91C_EMAC_LOW            (0x1 << 31) // (EMAC) 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR External Bus Interface
-// *****************************************************************************
-// *** Register offset in AT91S_EBI structure ***
-#define EBI_CSA         ( 0) // Chip Select Assignment Register
-#define EBI_CFGR        ( 4) // Configuration Register
-// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- 
-#define AT91C_EBI_CS0A            (0x1 <<  0) // (EBI) Chip Select 0 Assignment
-#define 	AT91C_EBI_CS0A_SMC                  (0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller.
-#define 	AT91C_EBI_CS0A_BFC                  (0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller.
-#define AT91C_EBI_CS1A            (0x1 <<  1) // (EBI) Chip Select 1 Assignment
-#define 	AT91C_EBI_CS1A_SMC                  (0x0 <<  1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller.
-#define 	AT91C_EBI_CS1A_SDRAMC               (0x1 <<  1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller.
-#define AT91C_EBI_CS3A            (0x1 <<  3) // (EBI) Chip Select 3 Assignment
-#define 	AT91C_EBI_CS3A_SMC                  (0x0 <<  3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2.
-#define 	AT91C_EBI_CS3A_SMC_SmartMedia       (0x1 <<  3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
-#define AT91C_EBI_CS4A            (0x1 <<  4) // (EBI) Chip Select 4 Assignment
-#define 	AT91C_EBI_CS4A_SMC                  (0x0 <<  4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2.
-#define 	AT91C_EBI_CS4A_SMC_CompactFlash     (0x1 <<  4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.
-// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- 
-#define AT91C_EBI_DBPUC           (0x1 <<  0) // (EBI) Data Bus Pull-Up Configuration
-#define AT91C_EBI_EBSEN           (0x1 <<  1) // (EBI) Bus Sharing Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SMC2 structure ***
-#define SMC2_CSR        ( 0) // SMC2 Chip Select Register
-// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- 
-#define AT91C_SMC2_NWS            (0x7F <<  0) // (SMC2) Number of Wait States
-#define AT91C_SMC2_WSEN           (0x1 <<  7) // (SMC2) Wait State Enable
-#define AT91C_SMC2_TDF            (0xF <<  8) // (SMC2) Data Float Time
-#define AT91C_SMC2_BAT            (0x1 << 12) // (SMC2) Byte Access Type
-#define AT91C_SMC2_DBW            (0x1 << 13) // (SMC2) Data Bus Width
-#define 	AT91C_SMC2_DBW_16                   (0x1 << 13) // (SMC2) 16-bit.
-#define 	AT91C_SMC2_DBW_8                    (0x2 << 13) // (SMC2) 8-bit.
-#define AT91C_SMC2_DRP            (0x1 << 15) // (SMC2) Data Read Protocol
-#define AT91C_SMC2_ACSS           (0x3 << 16) // (SMC2) Address to Chip Select Setup
-#define 	AT91C_SMC2_ACSS_STANDARD             (0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end.
-#define 	AT91C_SMC2_ACSS_1_CYCLE              (0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access.
-#define 	AT91C_SMC2_ACSS_2_CYCLES             (0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access.
-#define 	AT91C_SMC2_ACSS_3_CYCLES             (0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access.
-#define AT91C_SMC2_RWSETUP        (0x7 << 24) // (SMC2) Read and Write Signal Setup Time
-#define AT91C_SMC2_RWHOLD         (0x7 << 29) // (SMC2) Read and Write Signal Hold Time
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SDRC structure ***
-#define SDRC_MR         ( 0) // SDRAM Controller Mode Register
-#define SDRC_TR         ( 4) // SDRAM Controller Refresh Timer Register
-#define SDRC_CR         ( 8) // SDRAM Controller Configuration Register
-#define SDRC_SRR        (12) // SDRAM Controller Self Refresh Register
-#define SDRC_LPR        (16) // SDRAM Controller Low Power Register
-#define SDRC_IER        (20) // SDRAM Controller Interrupt Enable Register
-#define SDRC_IDR        (24) // SDRAM Controller Interrupt Disable Register
-#define SDRC_IMR        (28) // SDRAM Controller Interrupt Mask Register
-#define SDRC_ISR        (32) // SDRAM Controller Interrupt Mask Register
-// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- 
-#define AT91C_SDRC_MODE           (0xF <<  0) // (SDRC) Mode
-#define 	AT91C_SDRC_MODE_NORMAL_CMD           (0x0) // (SDRC) Normal Mode
-#define 	AT91C_SDRC_MODE_NOP_CMD              (0x1) // (SDRC) NOP Command
-#define 	AT91C_SDRC_MODE_PRCGALL_CMD          (0x2) // (SDRC) All Banks Precharge Command
-#define 	AT91C_SDRC_MODE_LMR_CMD              (0x3) // (SDRC) Load Mode Register Command
-#define 	AT91C_SDRC_MODE_RFSH_CMD             (0x4) // (SDRC) Refresh Command
-#define AT91C_SDRC_DBW            (0x1 <<  4) // (SDRC) Data Bus Width
-#define 	AT91C_SDRC_DBW_32_BITS              (0x0 <<  4) // (SDRC) 32 Bits datas bus
-#define 	AT91C_SDRC_DBW_16_BITS              (0x1 <<  4) // (SDRC) 16 Bits datas bus
-// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- 
-#define AT91C_SDRC_COUNT          (0xFFF <<  0) // (SDRC) Refresh Counter
-// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- 
-#define AT91C_SDRC_NC             (0x3 <<  0) // (SDRC) Number of Column Bits
-#define 	AT91C_SDRC_NC_8                    (0x0) // (SDRC) 8 Bits
-#define 	AT91C_SDRC_NC_9                    (0x1) // (SDRC) 9 Bits
-#define 	AT91C_SDRC_NC_10                   (0x2) // (SDRC) 10 Bits
-#define 	AT91C_SDRC_NC_11                   (0x3) // (SDRC) 11 Bits
-#define AT91C_SDRC_NR             (0x3 <<  2) // (SDRC) Number of Row Bits
-#define 	AT91C_SDRC_NR_11                   (0x0 <<  2) // (SDRC) 11 Bits
-#define 	AT91C_SDRC_NR_12                   (0x1 <<  2) // (SDRC) 12 Bits
-#define 	AT91C_SDRC_NR_13                   (0x2 <<  2) // (SDRC) 13 Bits
-#define AT91C_SDRC_NB             (0x1 <<  4) // (SDRC) Number of Banks
-#define 	AT91C_SDRC_NB_2_BANKS              (0x0 <<  4) // (SDRC) 2 banks
-#define 	AT91C_SDRC_NB_4_BANKS              (0x1 <<  4) // (SDRC) 4 banks
-#define AT91C_SDRC_CAS            (0x3 <<  5) // (SDRC) CAS Latency
-#define 	AT91C_SDRC_CAS_2                    (0x2 <<  5) // (SDRC) 2 cycles
-#define AT91C_SDRC_TWR            (0xF <<  7) // (SDRC) Number of Write Recovery Time Cycles
-#define AT91C_SDRC_TRC            (0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles
-#define AT91C_SDRC_TRP            (0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles
-#define AT91C_SDRC_TRCD           (0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles
-#define AT91C_SDRC_TRAS           (0xF << 23) // (SDRC) Number of RAS Active Time Cycles
-#define AT91C_SDRC_TXSR           (0xF << 27) // (SDRC) Number of Command Recovery Time Cycles
-// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- 
-#define AT91C_SDRC_SRCB           (0x1 <<  0) // (SDRC) Self-refresh Command Bit
-// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- 
-#define AT91C_SDRC_LPCB           (0x1 <<  0) // (SDRC) Low-power Command Bit
-// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- 
-#define AT91C_SDRC_RES            (0x1 <<  0) // (SDRC) Refresh Error Status
-// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- 
-// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- 
-// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Burst Flash Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_BFC structure ***
-#define BFC_MR          ( 0) // BFC Mode Register
-// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- 
-#define AT91C_BFC_BFCOM           (0x3 <<  0) // (BFC) Burst Flash Controller Operating Mode
-#define 	AT91C_BFC_BFCOM_DISABLED             (0x0) // (BFC) NPCS0 is driven by the SMC or remains high.
-#define 	AT91C_BFC_BFCOM_ASYNC                (0x1) // (BFC) Asynchronous
-#define 	AT91C_BFC_BFCOM_BURST_READ           (0x2) // (BFC) Burst Read
-#define AT91C_BFC_BFCC            (0x3 <<  2) // (BFC) Burst Flash Controller Operating Mode
-#define 	AT91C_BFC_BFCC_MCK                  (0x1 <<  2) // (BFC) Master Clock.
-#define 	AT91C_BFC_BFCC_MCK_DIV_2            (0x2 <<  2) // (BFC) Master Clock divided by 2.
-#define 	AT91C_BFC_BFCC_MCK_DIV_4            (0x3 <<  2) // (BFC) Master Clock divided by 4.
-#define AT91C_BFC_AVL             (0xF <<  4) // (BFC) Address Valid Latency
-#define AT91C_BFC_PAGES           (0x7 <<  8) // (BFC) Page Size
-#define 	AT91C_BFC_PAGES_NO_PAGE              (0x0 <<  8) // (BFC) No page handling.
-#define 	AT91C_BFC_PAGES_16                   (0x1 <<  8) // (BFC) 16 bytes page size.
-#define 	AT91C_BFC_PAGES_32                   (0x2 <<  8) // (BFC) 32 bytes page size.
-#define 	AT91C_BFC_PAGES_64                   (0x3 <<  8) // (BFC) 64 bytes page size.
-#define 	AT91C_BFC_PAGES_128                  (0x4 <<  8) // (BFC) 128 bytes page size.
-#define 	AT91C_BFC_PAGES_256                  (0x5 <<  8) // (BFC) 256 bytes page size.
-#define 	AT91C_BFC_PAGES_512                  (0x6 <<  8) // (BFC) 512 bytes page size.
-#define 	AT91C_BFC_PAGES_1024                 (0x7 <<  8) // (BFC) 1024 bytes page size.
-#define AT91C_BFC_OEL             (0x3 << 12) // (BFC) Output Enable Latency
-#define AT91C_BFC_BAAEN           (0x1 << 16) // (BFC) Burst Address Advance Enable
-#define AT91C_BFC_BFOEH           (0x1 << 17) // (BFC) Burst Flash Output Enable Handling
-#define AT91C_BFC_MUXEN           (0x1 << 18) // (BFC) Multiplexed Bus Enable
-#define AT91C_BFC_RDYEN           (0x1 << 19) // (BFC) Ready Enable Mode
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91RM9200
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ========== 
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_PUER             (0xFFFFFF54) // (MC) MC Protection Unit Enable Register
-#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_PUP              (0xFFFFFF50) // (MC) MC Protection Unit Peripherals
-#define AT91C_MC_PUIA             (0xFFFFFF10) // (MC) MC Protection Unit Area
-#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
-// ========== Register definition for RTC peripheral ========== 
-#define AT91C_RTC_IMR             (0xFFFFFE28) // (RTC) Interrupt Mask Register
-#define AT91C_RTC_IER             (0xFFFFFE20) // (RTC) Interrupt Enable Register
-#define AT91C_RTC_SR              (0xFFFFFE18) // (RTC) Status Register
-#define AT91C_RTC_TIMALR          (0xFFFFFE10) // (RTC) Time Alarm Register
-#define AT91C_RTC_TIMR            (0xFFFFFE08) // (RTC) Time Register
-#define AT91C_RTC_CR              (0xFFFFFE00) // (RTC) Control Register
-#define AT91C_RTC_VER             (0xFFFFFE2C) // (RTC) Valid Entry Register
-#define AT91C_RTC_IDR             (0xFFFFFE24) // (RTC) Interrupt Disable Register
-#define AT91C_RTC_SCCR            (0xFFFFFE1C) // (RTC) Status Clear Command Register
-#define AT91C_RTC_CALALR          (0xFFFFFE14) // (RTC) Calendar Alarm Register
-#define AT91C_RTC_CALR            (0xFFFFFE0C) // (RTC) Calendar Register
-#define AT91C_RTC_MR              (0xFFFFFE04) // (RTC) Mode Register
-// ========== Register definition for ST peripheral ========== 
-#define AT91C_ST_CRTR             (0xFFFFFD24) // (ST) Current Real-time Register
-#define AT91C_ST_IMR              (0xFFFFFD1C) // (ST) Interrupt Mask Register
-#define AT91C_ST_IER              (0xFFFFFD14) // (ST) Interrupt Enable Register
-#define AT91C_ST_RTMR             (0xFFFFFD0C) // (ST) Real-time Mode Register
-#define AT91C_ST_PIMR             (0xFFFFFD04) // (ST) Period Interval Mode Register
-#define AT91C_ST_RTAR             (0xFFFFFD20) // (ST) Real-time Alarm Register
-#define AT91C_ST_IDR              (0xFFFFFD18) // (ST) Interrupt Disable Register
-#define AT91C_ST_SR               (0xFFFFFD10) // (ST) Status Register
-#define AT91C_ST_WDMR             (0xFFFFFD08) // (ST) Watchdog Mode Register
-#define AT91C_ST_CR               (0xFFFFFD00) // (ST) Control Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
-#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_PLLBR          (0xFFFFFC2C) // (CKGR) PLL B Register
-#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-#define AT91C_CKGR_PLLAR          (0xFFFFFC28) // (CKGR) PLL A Register
-#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
-// ========== Register definition for PIOD peripheral ========== 
-#define AT91C_PIOD_PDSR           (0xFFFFFA3C) // (PIOD) Pin Data Status Register
-#define AT91C_PIOD_CODR           (0xFFFFFA34) // (PIOD) Clear Output Data Register
-#define AT91C_PIOD_OWER           (0xFFFFFAA0) // (PIOD) Output Write Enable Register
-#define AT91C_PIOD_MDER           (0xFFFFFA50) // (PIOD) Multi-driver Enable Register
-#define AT91C_PIOD_IMR            (0xFFFFFA48) // (PIOD) Interrupt Mask Register
-#define AT91C_PIOD_IER            (0xFFFFFA40) // (PIOD) Interrupt Enable Register
-#define AT91C_PIOD_ODSR           (0xFFFFFA38) // (PIOD) Output Data Status Register
-#define AT91C_PIOD_SODR           (0xFFFFFA30) // (PIOD) Set Output Data Register
-#define AT91C_PIOD_PER            (0xFFFFFA00) // (PIOD) PIO Enable Register
-#define AT91C_PIOD_OWDR           (0xFFFFFAA4) // (PIOD) Output Write Disable Register
-#define AT91C_PIOD_PPUER          (0xFFFFFA64) // (PIOD) Pull-up Enable Register
-#define AT91C_PIOD_MDDR           (0xFFFFFA54) // (PIOD) Multi-driver Disable Register
-#define AT91C_PIOD_ISR            (0xFFFFFA4C) // (PIOD) Interrupt Status Register
-#define AT91C_PIOD_IDR            (0xFFFFFA44) // (PIOD) Interrupt Disable Register
-#define AT91C_PIOD_PDR            (0xFFFFFA04) // (PIOD) PIO Disable Register
-#define AT91C_PIOD_ODR            (0xFFFFFA14) // (PIOD) Output Disable Registerr
-#define AT91C_PIOD_OWSR           (0xFFFFFAA8) // (PIOD) Output Write Status Register
-#define AT91C_PIOD_ABSR           (0xFFFFFA78) // (PIOD) AB Select Status Register
-#define AT91C_PIOD_ASR            (0xFFFFFA70) // (PIOD) Select A Register
-#define AT91C_PIOD_PPUSR          (0xFFFFFA68) // (PIOD) Pad Pull-up Status Register
-#define AT91C_PIOD_PPUDR          (0xFFFFFA60) // (PIOD) Pull-up Disable Register
-#define AT91C_PIOD_MDSR           (0xFFFFFA58) // (PIOD) Multi-driver Status Register
-#define AT91C_PIOD_PSR            (0xFFFFFA08) // (PIOD) PIO Status Register
-#define AT91C_PIOD_OER            (0xFFFFFA10) // (PIOD) Output Enable Register
-#define AT91C_PIOD_OSR            (0xFFFFFA18) // (PIOD) Output Status Register
-#define AT91C_PIOD_IFER           (0xFFFFFA20) // (PIOD) Input Filter Enable Register
-#define AT91C_PIOD_BSR            (0xFFFFFA74) // (PIOD) Select B Register
-#define AT91C_PIOD_IFDR           (0xFFFFFA24) // (PIOD) Input Filter Disable Register
-#define AT91C_PIOD_IFSR           (0xFFFFFA28) // (PIOD) Input Filter Status Register
-// ========== Register definition for PIOC peripheral ========== 
-#define AT91C_PIOC_IFDR           (0xFFFFF824) // (PIOC) Input Filter Disable Register
-#define AT91C_PIOC_ODR            (0xFFFFF814) // (PIOC) Output Disable Registerr
-#define AT91C_PIOC_ABSR           (0xFFFFF878) // (PIOC) AB Select Status Register
-#define AT91C_PIOC_SODR           (0xFFFFF830) // (PIOC) Set Output Data Register
-#define AT91C_PIOC_IFSR           (0xFFFFF828) // (PIOC) Input Filter Status Register
-#define AT91C_PIOC_CODR           (0xFFFFF834) // (PIOC) Clear Output Data Register
-#define AT91C_PIOC_ODSR           (0xFFFFF838) // (PIOC) Output Data Status Register
-#define AT91C_PIOC_IER            (0xFFFFF840) // (PIOC) Interrupt Enable Register
-#define AT91C_PIOC_IMR            (0xFFFFF848) // (PIOC) Interrupt Mask Register
-#define AT91C_PIOC_OWDR           (0xFFFFF8A4) // (PIOC) Output Write Disable Register
-#define AT91C_PIOC_MDDR           (0xFFFFF854) // (PIOC) Multi-driver Disable Register
-#define AT91C_PIOC_PDSR           (0xFFFFF83C) // (PIOC) Pin Data Status Register
-#define AT91C_PIOC_IDR            (0xFFFFF844) // (PIOC) Interrupt Disable Register
-#define AT91C_PIOC_ISR            (0xFFFFF84C) // (PIOC) Interrupt Status Register
-#define AT91C_PIOC_PDR            (0xFFFFF804) // (PIOC) PIO Disable Register
-#define AT91C_PIOC_OWSR           (0xFFFFF8A8) // (PIOC) Output Write Status Register
-#define AT91C_PIOC_OWER           (0xFFFFF8A0) // (PIOC) Output Write Enable Register
-#define AT91C_PIOC_ASR            (0xFFFFF870) // (PIOC) Select A Register
-#define AT91C_PIOC_PPUSR          (0xFFFFF868) // (PIOC) Pad Pull-up Status Register
-#define AT91C_PIOC_PPUDR          (0xFFFFF860) // (PIOC) Pull-up Disable Register
-#define AT91C_PIOC_MDSR           (0xFFFFF858) // (PIOC) Multi-driver Status Register
-#define AT91C_PIOC_MDER           (0xFFFFF850) // (PIOC) Multi-driver Enable Register
-#define AT91C_PIOC_IFER           (0xFFFFF820) // (PIOC) Input Filter Enable Register
-#define AT91C_PIOC_OSR            (0xFFFFF818) // (PIOC) Output Status Register
-#define AT91C_PIOC_OER            (0xFFFFF810) // (PIOC) Output Enable Register
-#define AT91C_PIOC_PSR            (0xFFFFF808) // (PIOC) PIO Status Register
-#define AT91C_PIOC_PER            (0xFFFFF800) // (PIOC) PIO Enable Register
-#define AT91C_PIOC_BSR            (0xFFFFF874) // (PIOC) Select B Register
-#define AT91C_PIOC_PPUER          (0xFFFFF864) // (PIOC) Pull-up Enable Register
-// ========== Register definition for PIOB peripheral ========== 
-#define AT91C_PIOB_OWSR           (0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PPUSR          (0xFFFFF668) // (PIOB) Pad Pull-up Status Register
-#define AT91C_PIOB_PPUDR          (0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_MDSR           (0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_MDER           (0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_IMR            (0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_OSR            (0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_OER            (0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PSR            (0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_PER            (0xFFFFF600) // (PIOB) PIO Enable Register
-#define AT91C_PIOB_BSR            (0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_PPUER          (0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_IFDR           (0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_ODR            (0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_ABSR           (0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_ASR            (0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_IFER           (0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_IFSR           (0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_SODR           (0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ODSR           (0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_CODR           (0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_PDSR           (0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_OWER           (0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_IER            (0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_OWDR           (0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDDR           (0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_ISR            (0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_IDR            (0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_PDR            (0xFFFFF604) // (PIOB) PIO Disable Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
-#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pad Pull-up Status Register
-#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_C2R            (0xFFFFF244) // (DBGU) Chip ID2 Register
-#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_C1R            (0xFFFFF240) // (DBGU) Chip ID1 Register
-#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
-#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
-#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
-// ========== Register definition for PDC_SPI peripheral ========== 
-#define AT91C_SPI_PTCR            (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TNPR            (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-#define AT91C_SPI_RNPR            (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_TPR             (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_RPR             (0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_PTSR            (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_TNCR            (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR            (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TCR             (0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR             (0xFFFE0104) // (PDC_SPI) Receive Counter Register
-// ========== Register definition for SPI peripheral ========== 
-#define AT91C_SPI_CSR             (0xFFFE0030) // (SPI) Chip Select Register
-#define AT91C_SPI_IDR             (0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_SR              (0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_RDR             (0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CR              (0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_IMR             (0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_IER             (0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_TDR             (0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_MR              (0xFFFE0004) // (SPI) Mode Register
-// ========== Register definition for PDC_SSC2 peripheral ========== 
-#define AT91C_SSC2_PTCR           (0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register
-#define AT91C_SSC2_TNPR           (0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register
-#define AT91C_SSC2_RNPR           (0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register
-#define AT91C_SSC2_TPR            (0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register
-#define AT91C_SSC2_RPR            (0xFFFD8100) // (PDC_SSC2) Receive Pointer Register
-#define AT91C_SSC2_PTSR           (0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register
-#define AT91C_SSC2_TNCR           (0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register
-#define AT91C_SSC2_RNCR           (0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register
-#define AT91C_SSC2_TCR            (0xFFFD810C) // (PDC_SSC2) Transmit Counter Register
-#define AT91C_SSC2_RCR            (0xFFFD8104) // (PDC_SSC2) Receive Counter Register
-// ========== Register definition for SSC2 peripheral ========== 
-#define AT91C_SSC2_IMR            (0xFFFD804C) // (SSC2) Interrupt Mask Register
-#define AT91C_SSC2_IER            (0xFFFD8044) // (SSC2) Interrupt Enable Register
-#define AT91C_SSC2_RC1R           (0xFFFD803C) // (SSC2) Receive Compare 1 Register
-#define AT91C_SSC2_TSHR           (0xFFFD8034) // (SSC2) Transmit Sync Holding Register
-#define AT91C_SSC2_CMR            (0xFFFD8004) // (SSC2) Clock Mode Register
-#define AT91C_SSC2_IDR            (0xFFFD8048) // (SSC2) Interrupt Disable Register
-#define AT91C_SSC2_TCMR           (0xFFFD8018) // (SSC2) Transmit Clock Mode Register
-#define AT91C_SSC2_RCMR           (0xFFFD8010) // (SSC2) Receive Clock ModeRegister
-#define AT91C_SSC2_CR             (0xFFFD8000) // (SSC2) Control Register
-#define AT91C_SSC2_RFMR           (0xFFFD8014) // (SSC2) Receive Frame Mode Register
-#define AT91C_SSC2_TFMR           (0xFFFD801C) // (SSC2) Transmit Frame Mode Register
-#define AT91C_SSC2_THR            (0xFFFD8024) // (SSC2) Transmit Holding Register
-#define AT91C_SSC2_SR             (0xFFFD8040) // (SSC2) Status Register
-#define AT91C_SSC2_RC0R           (0xFFFD8038) // (SSC2) Receive Compare 0 Register
-#define AT91C_SSC2_RSHR           (0xFFFD8030) // (SSC2) Receive Sync Holding Register
-#define AT91C_SSC2_RHR            (0xFFFD8020) // (SSC2) Receive Holding Register
-// ========== Register definition for PDC_SSC1 peripheral ========== 
-#define AT91C_SSC1_PTCR           (0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register
-#define AT91C_SSC1_TNPR           (0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register
-#define AT91C_SSC1_RNPR           (0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register
-#define AT91C_SSC1_TPR            (0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register
-#define AT91C_SSC1_RPR            (0xFFFD4100) // (PDC_SSC1) Receive Pointer Register
-#define AT91C_SSC1_PTSR           (0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register
-#define AT91C_SSC1_TNCR           (0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register
-#define AT91C_SSC1_RNCR           (0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register
-#define AT91C_SSC1_TCR            (0xFFFD410C) // (PDC_SSC1) Transmit Counter Register
-#define AT91C_SSC1_RCR            (0xFFFD4104) // (PDC_SSC1) Receive Counter Register
-// ========== Register definition for SSC1 peripheral ========== 
-#define AT91C_SSC1_RFMR           (0xFFFD4014) // (SSC1) Receive Frame Mode Register
-#define AT91C_SSC1_CMR            (0xFFFD4004) // (SSC1) Clock Mode Register
-#define AT91C_SSC1_IDR            (0xFFFD4048) // (SSC1) Interrupt Disable Register
-#define AT91C_SSC1_SR             (0xFFFD4040) // (SSC1) Status Register
-#define AT91C_SSC1_RC0R           (0xFFFD4038) // (SSC1) Receive Compare 0 Register
-#define AT91C_SSC1_RSHR           (0xFFFD4030) // (SSC1) Receive Sync Holding Register
-#define AT91C_SSC1_RHR            (0xFFFD4020) // (SSC1) Receive Holding Register
-#define AT91C_SSC1_TCMR           (0xFFFD4018) // (SSC1) Transmit Clock Mode Register
-#define AT91C_SSC1_RCMR           (0xFFFD4010) // (SSC1) Receive Clock ModeRegister
-#define AT91C_SSC1_CR             (0xFFFD4000) // (SSC1) Control Register
-#define AT91C_SSC1_IMR            (0xFFFD404C) // (SSC1) Interrupt Mask Register
-#define AT91C_SSC1_IER            (0xFFFD4044) // (SSC1) Interrupt Enable Register
-#define AT91C_SSC1_RC1R           (0xFFFD403C) // (SSC1) Receive Compare 1 Register
-#define AT91C_SSC1_TSHR           (0xFFFD4034) // (SSC1) Transmit Sync Holding Register
-#define AT91C_SSC1_THR            (0xFFFD4024) // (SSC1) Transmit Holding Register
-#define AT91C_SSC1_TFMR           (0xFFFD401C) // (SSC1) Transmit Frame Mode Register
-// ========== Register definition for PDC_SSC0 peripheral ========== 
-#define AT91C_SSC0_PTCR           (0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register
-#define AT91C_SSC0_TNPR           (0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register
-#define AT91C_SSC0_RNPR           (0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register
-#define AT91C_SSC0_TPR            (0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register
-#define AT91C_SSC0_RPR            (0xFFFD0100) // (PDC_SSC0) Receive Pointer Register
-#define AT91C_SSC0_PTSR           (0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register
-#define AT91C_SSC0_TNCR           (0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register
-#define AT91C_SSC0_RNCR           (0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register
-#define AT91C_SSC0_TCR            (0xFFFD010C) // (PDC_SSC0) Transmit Counter Register
-#define AT91C_SSC0_RCR            (0xFFFD0104) // (PDC_SSC0) Receive Counter Register
-// ========== Register definition for SSC0 peripheral ========== 
-#define AT91C_SSC0_IMR            (0xFFFD004C) // (SSC0) Interrupt Mask Register
-#define AT91C_SSC0_IER            (0xFFFD0044) // (SSC0) Interrupt Enable Register
-#define AT91C_SSC0_RC1R           (0xFFFD003C) // (SSC0) Receive Compare 1 Register
-#define AT91C_SSC0_TSHR           (0xFFFD0034) // (SSC0) Transmit Sync Holding Register
-#define AT91C_SSC0_THR            (0xFFFD0024) // (SSC0) Transmit Holding Register
-#define AT91C_SSC0_TFMR           (0xFFFD001C) // (SSC0) Transmit Frame Mode Register
-#define AT91C_SSC0_RFMR           (0xFFFD0014) // (SSC0) Receive Frame Mode Register
-#define AT91C_SSC0_CMR            (0xFFFD0004) // (SSC0) Clock Mode Register
-#define AT91C_SSC0_IDR            (0xFFFD0048) // (SSC0) Interrupt Disable Register
-#define AT91C_SSC0_SR             (0xFFFD0040) // (SSC0) Status Register
-#define AT91C_SSC0_RC0R           (0xFFFD0038) // (SSC0) Receive Compare 0 Register
-#define AT91C_SSC0_RSHR           (0xFFFD0030) // (SSC0) Receive Sync Holding Register
-#define AT91C_SSC0_RHR            (0xFFFD0020) // (SSC0) Receive Holding Register
-#define AT91C_SSC0_TCMR           (0xFFFD0018) // (SSC0) Transmit Clock Mode Register
-#define AT91C_SSC0_RCMR           (0xFFFD0010) // (SSC0) Receive Clock ModeRegister
-#define AT91C_SSC0_CR             (0xFFFD0000) // (SSC0) Control Register
-// ========== Register definition for PDC_US3 peripheral ========== 
-#define AT91C_US3_PTSR            (0xFFFCC124) // (PDC_US3) PDC Transfer Status Register
-#define AT91C_US3_TNCR            (0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register
-#define AT91C_US3_RNCR            (0xFFFCC114) // (PDC_US3) Receive Next Counter Register
-#define AT91C_US3_TCR             (0xFFFCC10C) // (PDC_US3) Transmit Counter Register
-#define AT91C_US3_RCR             (0xFFFCC104) // (PDC_US3) Receive Counter Register
-#define AT91C_US3_PTCR            (0xFFFCC120) // (PDC_US3) PDC Transfer Control Register
-#define AT91C_US3_TNPR            (0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register
-#define AT91C_US3_RNPR            (0xFFFCC110) // (PDC_US3) Receive Next Pointer Register
-#define AT91C_US3_TPR             (0xFFFCC108) // (PDC_US3) Transmit Pointer Register
-#define AT91C_US3_RPR             (0xFFFCC100) // (PDC_US3) Receive Pointer Register
-// ========== Register definition for US3 peripheral ========== 
-#define AT91C_US3_IF              (0xFFFCC04C) // (US3) IRDA_FILTER Register
-#define AT91C_US3_NER             (0xFFFCC044) // (US3) Nb Errors Register
-#define AT91C_US3_RTOR            (0xFFFCC024) // (US3) Receiver Time-out Register
-#define AT91C_US3_THR             (0xFFFCC01C) // (US3) Transmitter Holding Register
-#define AT91C_US3_CSR             (0xFFFCC014) // (US3) Channel Status Register
-#define AT91C_US3_IDR             (0xFFFCC00C) // (US3) Interrupt Disable Register
-#define AT91C_US3_MR              (0xFFFCC004) // (US3) Mode Register
-#define AT91C_US3_XXR             (0xFFFCC048) // (US3) XON_XOFF Register
-#define AT91C_US3_FIDI            (0xFFFCC040) // (US3) FI_DI_Ratio Register
-#define AT91C_US3_TTGR            (0xFFFCC028) // (US3) Transmitter Time-guard Register
-#define AT91C_US3_BRGR            (0xFFFCC020) // (US3) Baud Rate Generator Register
-#define AT91C_US3_RHR             (0xFFFCC018) // (US3) Receiver Holding Register
-#define AT91C_US3_IMR             (0xFFFCC010) // (US3) Interrupt Mask Register
-#define AT91C_US3_IER             (0xFFFCC008) // (US3) Interrupt Enable Register
-#define AT91C_US3_CR              (0xFFFCC000) // (US3) Control Register
-// ========== Register definition for PDC_US2 peripheral ========== 
-#define AT91C_US2_PTSR            (0xFFFC8124) // (PDC_US2) PDC Transfer Status Register
-#define AT91C_US2_TNCR            (0xFFFC811C) // (PDC_US2) Transmit Next Counter Register
-#define AT91C_US2_RNCR            (0xFFFC8114) // (PDC_US2) Receive Next Counter Register
-#define AT91C_US2_TCR             (0xFFFC810C) // (PDC_US2) Transmit Counter Register
-#define AT91C_US2_PTCR            (0xFFFC8120) // (PDC_US2) PDC Transfer Control Register
-#define AT91C_US2_RCR             (0xFFFC8104) // (PDC_US2) Receive Counter Register
-#define AT91C_US2_TNPR            (0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register
-#define AT91C_US2_RPR             (0xFFFC8100) // (PDC_US2) Receive Pointer Register
-#define AT91C_US2_TPR             (0xFFFC8108) // (PDC_US2) Transmit Pointer Register
-#define AT91C_US2_RNPR            (0xFFFC8110) // (PDC_US2) Receive Next Pointer Register
-// ========== Register definition for US2 peripheral ========== 
-#define AT91C_US2_XXR             (0xFFFC8048) // (US2) XON_XOFF Register
-#define AT91C_US2_FIDI            (0xFFFC8040) // (US2) FI_DI_Ratio Register
-#define AT91C_US2_TTGR            (0xFFFC8028) // (US2) Transmitter Time-guard Register
-#define AT91C_US2_BRGR            (0xFFFC8020) // (US2) Baud Rate Generator Register
-#define AT91C_US2_RHR             (0xFFFC8018) // (US2) Receiver Holding Register
-#define AT91C_US2_IMR             (0xFFFC8010) // (US2) Interrupt Mask Register
-#define AT91C_US2_IER             (0xFFFC8008) // (US2) Interrupt Enable Register
-#define AT91C_US2_CR              (0xFFFC8000) // (US2) Control Register
-#define AT91C_US2_IF              (0xFFFC804C) // (US2) IRDA_FILTER Register
-#define AT91C_US2_NER             (0xFFFC8044) // (US2) Nb Errors Register
-#define AT91C_US2_RTOR            (0xFFFC8024) // (US2) Receiver Time-out Register
-#define AT91C_US2_THR             (0xFFFC801C) // (US2) Transmitter Holding Register
-#define AT91C_US2_CSR             (0xFFFC8014) // (US2) Channel Status Register
-#define AT91C_US2_IDR             (0xFFFC800C) // (US2) Interrupt Disable Register
-#define AT91C_US2_MR              (0xFFFC8004) // (US2) Mode Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_XXR             (0xFFFC4048) // (US1) XON_XOFF Register
-#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_XXR             (0xFFFC0048) // (US0) XON_XOFF Register
-#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
-#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
-#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_SMR             (0xFFFB8008) // (TWI) Slave Mode Register
-#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
-// ========== Register definition for PDC_MCI peripheral ========== 
-#define AT91C_MCI_PTCR            (0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register
-#define AT91C_MCI_TNPR            (0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register
-#define AT91C_MCI_RNPR            (0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register
-#define AT91C_MCI_TPR             (0xFFFB4108) // (PDC_MCI) Transmit Pointer Register
-#define AT91C_MCI_RPR             (0xFFFB4100) // (PDC_MCI) Receive Pointer Register
-#define AT91C_MCI_PTSR            (0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register
-#define AT91C_MCI_TNCR            (0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register
-#define AT91C_MCI_RNCR            (0xFFFB4114) // (PDC_MCI) Receive Next Counter Register
-#define AT91C_MCI_TCR             (0xFFFB410C) // (PDC_MCI) Transmit Counter Register
-#define AT91C_MCI_RCR             (0xFFFB4104) // (PDC_MCI) Receive Counter Register
-// ========== Register definition for MCI peripheral ========== 
-#define AT91C_MCI_IDR             (0xFFFB4048) // (MCI) MCI Interrupt Disable Register
-#define AT91C_MCI_SR              (0xFFFB4040) // (MCI) MCI Status Register
-#define AT91C_MCI_RDR             (0xFFFB4030) // (MCI) MCI Receive Data Register
-#define AT91C_MCI_RSPR            (0xFFFB4020) // (MCI) MCI Response Register
-#define AT91C_MCI_ARGR            (0xFFFB4010) // (MCI) MCI Argument Register
-#define AT91C_MCI_DTOR            (0xFFFB4008) // (MCI) MCI Data Timeout Register
-#define AT91C_MCI_CR              (0xFFFB4000) // (MCI) MCI Control Register
-#define AT91C_MCI_IMR             (0xFFFB404C) // (MCI) MCI Interrupt Mask Register
-#define AT91C_MCI_IER             (0xFFFB4044) // (MCI) MCI Interrupt Enable Register
-#define AT91C_MCI_TDR             (0xFFFB4034) // (MCI) MCI Transmit Data Register
-#define AT91C_MCI_CMDR            (0xFFFB4014) // (MCI) MCI Command Register
-#define AT91C_MCI_SDCR            (0xFFFB400C) // (MCI) MCI SD Card Register
-#define AT91C_MCI_MR              (0xFFFB4004) // (MCI) MCI Mode Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
-#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
-// ========== Register definition for TC5 peripheral ========== 
-#define AT91C_TC5_CMR             (0xFFFA4084) // (TC5) Channel Mode Register
-#define AT91C_TC5_IDR             (0xFFFA40A8) // (TC5) Interrupt Disable Register
-#define AT91C_TC5_SR              (0xFFFA40A0) // (TC5) Status Register
-#define AT91C_TC5_RB              (0xFFFA4098) // (TC5) Register B
-#define AT91C_TC5_CV              (0xFFFA4090) // (TC5) Counter Value
-#define AT91C_TC5_CCR             (0xFFFA4080) // (TC5) Channel Control Register
-#define AT91C_TC5_IMR             (0xFFFA40AC) // (TC5) Interrupt Mask Register
-#define AT91C_TC5_IER             (0xFFFA40A4) // (TC5) Interrupt Enable Register
-#define AT91C_TC5_RC              (0xFFFA409C) // (TC5) Register C
-#define AT91C_TC5_RA              (0xFFFA4094) // (TC5) Register A
-// ========== Register definition for TC4 peripheral ========== 
-#define AT91C_TC4_IMR             (0xFFFA406C) // (TC4) Interrupt Mask Register
-#define AT91C_TC4_IER             (0xFFFA4064) // (TC4) Interrupt Enable Register
-#define AT91C_TC4_RC              (0xFFFA405C) // (TC4) Register C
-#define AT91C_TC4_RA              (0xFFFA4054) // (TC4) Register A
-#define AT91C_TC4_CMR             (0xFFFA4044) // (TC4) Channel Mode Register
-#define AT91C_TC4_IDR             (0xFFFA4068) // (TC4) Interrupt Disable Register
-#define AT91C_TC4_SR              (0xFFFA4060) // (TC4) Status Register
-#define AT91C_TC4_RB              (0xFFFA4058) // (TC4) Register B
-#define AT91C_TC4_CV              (0xFFFA4050) // (TC4) Counter Value
-#define AT91C_TC4_CCR             (0xFFFA4040) // (TC4) Channel Control Register
-// ========== Register definition for TC3 peripheral ========== 
-#define AT91C_TC3_IMR             (0xFFFA402C) // (TC3) Interrupt Mask Register
-#define AT91C_TC3_CV              (0xFFFA4010) // (TC3) Counter Value
-#define AT91C_TC3_CCR             (0xFFFA4000) // (TC3) Channel Control Register
-#define AT91C_TC3_IER             (0xFFFA4024) // (TC3) Interrupt Enable Register
-#define AT91C_TC3_CMR             (0xFFFA4004) // (TC3) Channel Mode Register
-#define AT91C_TC3_RA              (0xFFFA4014) // (TC3) Register A
-#define AT91C_TC3_RC              (0xFFFA401C) // (TC3) Register C
-#define AT91C_TC3_IDR             (0xFFFA4028) // (TC3) Interrupt Disable Register
-#define AT91C_TC3_RB              (0xFFFA4018) // (TC3) Register B
-#define AT91C_TC3_SR              (0xFFFA4020) // (TC3) Status Register
-// ========== Register definition for TCB1 peripheral ========== 
-#define AT91C_TCB1_BCR            (0xFFFA4140) // (TCB1) TC Block Control Register
-#define AT91C_TCB1_BMR            (0xFFFA4144) // (TCB1) TC Block Mode Register
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register
-#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
-#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register
-#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
-#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
-#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register
-#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
-// ========== Register definition for TCB0 peripheral ========== 
-#define AT91C_TCB0_BMR            (0xFFFA00C4) // (TCB0) TC Block Mode Register
-#define AT91C_TCB0_BCR            (0xFFFA00C0) // (TCB0) TC Block Control Register
-// ========== Register definition for UHP peripheral ========== 
-#define AT91C_UHP_HcRhDescriptorA (0x00300048) // (UHP) Root Hub characteristics A
-#define AT91C_UHP_HcRhPortStatus  (0x00300054) // (UHP) Root Hub Port Status Register
-#define AT91C_UHP_HcRhDescriptorB (0x0030004C) // (UHP) Root Hub characteristics B
-#define AT91C_UHP_HcControl       (0x00300004) // (UHP) Operating modes for the Host Controller
-#define AT91C_UHP_HcInterruptStatus (0x0030000C) // (UHP) Interrupt Status Register
-#define AT91C_UHP_HcRhStatus      (0x00300050) // (UHP) Root Hub Status register
-#define AT91C_UHP_HcRevision      (0x00300000) // (UHP) Revision
-#define AT91C_UHP_HcCommandStatus (0x00300008) // (UHP) Command & status Register
-#define AT91C_UHP_HcInterruptEnable (0x00300010) // (UHP) Interrupt Enable Register
-#define AT91C_UHP_HcHCCA          (0x00300018) // (UHP) Pointer to the Host Controller Communication Area
-#define AT91C_UHP_HcControlHeadED (0x00300020) // (UHP) First Endpoint Descriptor of the Control list
-#define AT91C_UHP_HcInterruptDisable (0x00300014) // (UHP) Interrupt Disable Register
-#define AT91C_UHP_HcPeriodCurrentED (0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
-#define AT91C_UHP_HcControlCurrentED (0x00300024) // (UHP) Endpoint Control and Status Register
-#define AT91C_UHP_HcBulkCurrentED (0x0030002C) // (UHP) Current endpoint of the Bulk list
-#define AT91C_UHP_HcFmInterval    (0x00300034) // (UHP) Bit time between 2 consecutive SOFs
-#define AT91C_UHP_HcBulkHeadED    (0x00300028) // (UHP) First endpoint register of the Bulk list
-#define AT91C_UHP_HcBulkDoneHead  (0x00300030) // (UHP) Last completed transfer descriptor
-#define AT91C_UHP_HcFmRemaining   (0x00300038) // (UHP) Bit time remaining in the current Frame
-#define AT91C_UHP_HcPeriodicStart (0x00300040) // (UHP) Periodic Start
-#define AT91C_UHP_HcLSThreshold   (0x00300044) // (UHP) LS Threshold
-#define AT91C_UHP_HcFmNumber      (0x0030003C) // (UHP) Frame number
-// ========== Register definition for EMAC peripheral ========== 
-#define AT91C_EMAC_RSR            (0xFFFBC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_MAN            (0xFFFBC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_HSH            (0xFFFBC090) // (EMAC) Hash Address High[63:32]
-#define AT91C_EMAC_MCOL           (0xFFFBC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_IER            (0xFFFBC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA2H           (0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes
-#define AT91C_EMAC_HSL            (0xFFFBC094) // (EMAC) Hash Address Low[31:0]
-#define AT91C_EMAC_LCOL           (0xFFFBC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_OK             (0xFFFBC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_CFG            (0xFFFBC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_SA3L           (0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes
-#define AT91C_EMAC_SEQE           (0xFFFBC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_ECOL           (0xFFFBC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_ELR            (0xFFFBC070) // (EMAC) Excessive Length Error Register
-#define AT91C_EMAC_SR             (0xFFFBC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_RBQP           (0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_CSE            (0xFFFBC064) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_RJB            (0xFFFBC074) // (EMAC) Receive Jabber Register
-#define AT91C_EMAC_USF            (0xFFFBC078) // (EMAC) Undersize Frame Register
-#define AT91C_EMAC_IDR            (0xFFFBC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_SA1L           (0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes
-#define AT91C_EMAC_IMR            (0xFFFBC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_FRA            (0xFFFBC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_SA3H           (0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes
-#define AT91C_EMAC_SA1H           (0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes
-#define AT91C_EMAC_SCOL           (0xFFFBC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_ALE            (0xFFFBC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_TAR            (0xFFFBC00C) // (EMAC) Transmit Address Register
-#define AT91C_EMAC_SA4L           (0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes
-#define AT91C_EMAC_SA2L           (0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes
-#define AT91C_EMAC_TUE            (0xFFFBC068) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_DTE            (0xFFFBC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TCR            (0xFFFBC010) // (EMAC) Transmit Control Register
-#define AT91C_EMAC_CTL            (0xFFFBC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4H           (0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr
-#define AT91C_EMAC_CDE            (0xFFFBC06C) // (EMAC) Code Error Register
-#define AT91C_EMAC_SQEE           (0xFFFBC07C) // (EMAC) SQE Test Error Register
-#define AT91C_EMAC_TSR            (0xFFFBC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_DRFC           (0xFFFBC080) // (EMAC) Discarded RX Frame Register
-// ========== Register definition for EBI peripheral ========== 
-#define AT91C_EBI_CFGR            (0xFFFFFF64) // (EBI) Configuration Register
-#define AT91C_EBI_CSA             (0xFFFFFF60) // (EBI) Chip Select Assignment Register
-// ========== Register definition for SMC2 peripheral ========== 
-#define AT91C_SMC2_CSR            (0xFFFFFF70) // (SMC2) SMC2 Chip Select Register
-// ========== Register definition for SDRC peripheral ========== 
-#define AT91C_SDRC_IMR            (0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register
-#define AT91C_SDRC_IER            (0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register
-#define AT91C_SDRC_SRR            (0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register
-#define AT91C_SDRC_TR             (0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register
-#define AT91C_SDRC_ISR            (0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register
-#define AT91C_SDRC_IDR            (0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register
-#define AT91C_SDRC_LPR            (0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register
-#define AT91C_SDRC_CR             (0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register
-#define AT91C_SDRC_MR             (0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register
-// ========== Register definition for BFC peripheral ========== 
-#define AT91C_BFC_MR              (0xFFFFFFC0) // (BFC) BFC Mode Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91RM9200
-// *****************************************************************************
-#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_MISO            (AT91C_PIO_PA0) //  SPI Master In Slave
-#define AT91C_PA0_PCK3            (AT91C_PIO_PA0) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_MOSI            (AT91C_PIO_PA1) //  SPI Master Out Slave
-#define AT91C_PA1_PCK0            (AT91C_PIO_PA1) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_ETX1           (AT91C_PIO_PA10) //  Ethernet MAC Transmit Data 1
-#define AT91C_PA10_MCDB1          (AT91C_PIO_PA10) //  Multimedia Card B Data 1
-#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_ECRS_ECRSDV    (AT91C_PIO_PA11) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PA11_MCDB2          (AT91C_PIO_PA11) //  Multimedia Card B Data 2
-#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_ERX0           (AT91C_PIO_PA12) //  Ethernet MAC Receive Data 0
-#define AT91C_PA12_MCDB3          (AT91C_PIO_PA12) //  Multimedia Card B Data 3
-#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_ERX1           (AT91C_PIO_PA13) //  Ethernet MAC Receive Data 1
-#define AT91C_PA13_TCLK0          (AT91C_PIO_PA13) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_ERXER          (AT91C_PIO_PA14) //  Ethernet MAC Receive Error
-#define AT91C_PA14_TCLK1          (AT91C_PIO_PA14) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_EMDC           (AT91C_PIO_PA15) //  Ethernet MAC Management Data Clock
-#define AT91C_PA15_TCLK2          (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_EMDIO          (AT91C_PIO_PA16) //  Ethernet MAC Management Data Input/Output
-#define AT91C_PA16_IRQ6           (AT91C_PIO_PA16) //  AIC Interrupt input 6
-#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TXD0           (AT91C_PIO_PA17) //  USART 0 Transmit Data
-#define AT91C_PA17_TIOA0          (AT91C_PIO_PA17) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RXD0           (AT91C_PIO_PA18) //  USART 0 Receive Data
-#define AT91C_PA18_TIOB0          (AT91C_PIO_PA18) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_SCK0           (AT91C_PIO_PA19) //  USART 0 Serial Clock
-#define AT91C_PA19_TIOA1          (AT91C_PIO_PA19) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SPCK            (AT91C_PIO_PA2) //  SPI Serial Clock
-#define AT91C_PA2_IRQ4            (AT91C_PIO_PA2) //  AIC Interrupt Input 4
-#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CTS0           (AT91C_PIO_PA20) //  USART 0 Clear To Send
-#define AT91C_PA20_TIOB1          (AT91C_PIO_PA20) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RTS0           (AT91C_PIO_PA21) //  Usart 0 Ready To Send
-#define AT91C_PA21_TIOA2          (AT91C_PIO_PA21) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_RXD2           (AT91C_PIO_PA22) //  USART 2 Receive Data
-#define AT91C_PA22_TIOB2          (AT91C_PIO_PA22) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TXD2           (AT91C_PIO_PA23) //  USART 2 Transmit Data
-#define AT91C_PA23_IRQ3           (AT91C_PIO_PA23) //  Interrupt input 3
-#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_SCK2           (AT91C_PIO_PA24) //  USART2 Serial Clock
-#define AT91C_PA24_PCK1           (AT91C_PIO_PA24) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_TWD            (AT91C_PIO_PA25) //  TWI Two-wire Serial Data
-#define AT91C_PA25_IRQ2           (AT91C_PIO_PA25) //  Interrupt input 2
-#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_TWCK           (AT91C_PIO_PA26) //  TWI Two-wire Serial Clock
-#define AT91C_PA26_IRQ1           (AT91C_PIO_PA26) //  Interrupt input 1
-#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_MCCK           (AT91C_PIO_PA27) //  Multimedia Card Clock
-#define AT91C_PA27_TCLK3          (AT91C_PIO_PA27) //  Timer Counter 3 External Clock Input
-#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_MCCDA          (AT91C_PIO_PA28) //  Multimedia Card A Command
-#define AT91C_PA28_TCLK4          (AT91C_PIO_PA28) //  Timer Counter 4 external Clock Input
-#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_MCDA0          (AT91C_PIO_PA29) //  Multimedia Card A Data 0
-#define AT91C_PA29_TCLK5          (AT91C_PIO_PA29) //  Timer Counter 5 external clock input
-#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_NPCS0           (AT91C_PIO_PA3) //  SPI Peripheral Chip Select 0
-#define AT91C_PA3_IRQ5            (AT91C_PIO_PA3) //  AIC Interrupt Input 5
-#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_DRXD           (AT91C_PIO_PA30) //  DBGU Debug Receive Data
-#define AT91C_PA30_CTS2           (AT91C_PIO_PA30) //  Usart 2 Clear To Send
-#define AT91C_PIO_PA31            (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_DTXD           (AT91C_PIO_PA31) //  DBGU Debug Transmit Data
-#define AT91C_PA31_RTS2           (AT91C_PIO_PA31) //  USART 2 Ready To Send
-#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_NPCS1           (AT91C_PIO_PA4) //  SPI Peripheral Chip Select 1
-#define AT91C_PA4_PCK1            (AT91C_PIO_PA4) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_NPCS2           (AT91C_PIO_PA5) //  SPI Peripheral Chip Select 2
-#define AT91C_PA5_TXD3            (AT91C_PIO_PA5) //  USART 3 Transmit Data
-#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_NPCS3           (AT91C_PIO_PA6) //  SPI Peripheral Chip Select 3
-#define AT91C_PA6_RXD3            (AT91C_PIO_PA6) //  USART 3 Receive Data
-#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_ETXCK_EREFCK    (AT91C_PIO_PA7) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PA7_PCK2            (AT91C_PIO_PA7) //  PMC Programmable Clock 2
-#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_ETXEN           (AT91C_PIO_PA8) //  Ethernet MAC Transmit Enable
-#define AT91C_PA8_MCCDB           (AT91C_PIO_PA8) //  Multimedia Card B Command
-#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_ETX0            (AT91C_PIO_PA9) //  Ethernet MAC Transmit Data 0
-#define AT91C_PA9_MCDB0           (AT91C_PIO_PA9) //  Multimedia Card B Data 0
-#define AT91C_PIO_PB0             (1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_TF0             (AT91C_PIO_PB0) //  SSC Transmit Frame Sync 0
-#define AT91C_PB0_TIOB3           (AT91C_PIO_PB0) //  Timer Counter 3 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PB1             (1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_TK0             (AT91C_PIO_PB1) //  SSC Transmit Clock 0
-#define AT91C_PB1_CTS3            (AT91C_PIO_PB1) //  USART 3 Clear To Send
-#define AT91C_PIO_PB10            (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_RK1            (AT91C_PIO_PB10) //  SSC Receive Clock 1
-#define AT91C_PB10_TIOA5          (AT91C_PIO_PB10) //  Timer Counter 5 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PB11            (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_RF1            (AT91C_PIO_PB11) //  SSC Receive Frame Sync 1
-#define AT91C_PB11_TIOB5          (AT91C_PIO_PB11) //  Timer Counter 5 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PB12            (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_TF2            (AT91C_PIO_PB12) //  SSC Transmit Frame Sync 2
-#define AT91C_PB12_ETX2           (AT91C_PIO_PB12) //  Ethernet MAC Transmit Data 2
-#define AT91C_PIO_PB13            (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_TK2            (AT91C_PIO_PB13) //  SSC Transmit Clock 2
-#define AT91C_PB13_ETX3           (AT91C_PIO_PB13) //  Ethernet MAC Transmit Data 3
-#define AT91C_PIO_PB14            (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_TD2            (AT91C_PIO_PB14) //  SSC Transmit Data 2
-#define AT91C_PB14_ETXER          (AT91C_PIO_PB14) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PIO_PB15            (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_RD2            (AT91C_PIO_PB15) //  SSC Receive Data 2
-#define AT91C_PB15_ERX2           (AT91C_PIO_PB15) //  Ethernet MAC Receive Data 2
-#define AT91C_PIO_PB16            (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_RK2            (AT91C_PIO_PB16) //  SSC Receive Clock 2
-#define AT91C_PB16_ERX3           (AT91C_PIO_PB16) //  Ethernet MAC Receive Data 3
-#define AT91C_PIO_PB17            (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_RF2            (AT91C_PIO_PB17) //  SSC Receive Frame Sync 2
-#define AT91C_PB17_ERXDV          (AT91C_PIO_PB17) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB18            (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_RI1            (AT91C_PIO_PB18) //  USART 1 Ring Indicator
-#define AT91C_PB18_ECOL           (AT91C_PIO_PB18) //  Ethernet MAC Collision Detected
-#define AT91C_PIO_PB19            (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_DTR1           (AT91C_PIO_PB19) //  USART 1 Data Terminal ready
-#define AT91C_PB19_ERXCK          (AT91C_PIO_PB19) //  Ethernet MAC Receive Clock
-#define AT91C_PIO_PB2             (1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_TD0             (AT91C_PIO_PB2) //  SSC Transmit data
-#define AT91C_PB2_SCK3            (AT91C_PIO_PB2) //  USART 3 Serial Clock
-#define AT91C_PIO_PB20            (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_TXD1           (AT91C_PIO_PB20) //  USART 1 Transmit Data
-#define AT91C_PIO_PB21            (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_RXD1           (AT91C_PIO_PB21) //  USART 1 Receive Data
-#define AT91C_PIO_PB22            (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_SCK1           (AT91C_PIO_PB22) //  USART1 Serial Clock
-#define AT91C_PIO_PB23            (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_DCD1           (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24            (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_CTS1           (AT91C_PIO_PB24) //  USART 1 Clear To Send
-#define AT91C_PIO_PB25            (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_DSR1           (AT91C_PIO_PB25) //  USART 1 Data Set ready
-#define AT91C_PB25_EF100          (AT91C_PIO_PB25) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PIO_PB26            (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_RTS1           (AT91C_PIO_PB26) //  Usart 0 Ready To Send
-#define AT91C_PIO_PB27            (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_PCK0           (AT91C_PIO_PB27) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB28            (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_FIQ            (AT91C_PIO_PB28) //  AIC Fast Interrupt Input
-#define AT91C_PIO_PB29            (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_IRQ0           (AT91C_PIO_PB29) //  Interrupt input 0
-#define AT91C_PIO_PB3             (1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_RD0             (AT91C_PIO_PB3) //  SSC Receive Data
-#define AT91C_PB3_MCDA1           (AT91C_PIO_PB3) //  Multimedia Card A Data 1
-#define AT91C_PIO_PB4             (1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_RK0             (AT91C_PIO_PB4) //  SSC Receive Clock
-#define AT91C_PB4_MCDA2           (AT91C_PIO_PB4) //  Multimedia Card A Data 2
-#define AT91C_PIO_PB5             (1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_RF0             (AT91C_PIO_PB5) //  SSC Receive Frame Sync 0
-#define AT91C_PB5_MCDA3           (AT91C_PIO_PB5) //  Multimedia Card A Data 3
-#define AT91C_PIO_PB6             (1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_TF1             (AT91C_PIO_PB6) //  SSC Transmit Frame Sync 1
-#define AT91C_PB6_TIOA3           (AT91C_PIO_PB6) //  Timer Counter 4 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PB7             (1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_TK1             (AT91C_PIO_PB7) //  SSC Transmit Clock 1
-#define AT91C_PB7_TIOB3           (AT91C_PIO_PB7) //  Timer Counter 3 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PB8             (1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_TD1             (AT91C_PIO_PB8) //  SSC Transmit Data 1
-#define AT91C_PB8_TIOA4           (AT91C_PIO_PB8) //  Timer Counter 4 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PB9             (1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_RD1             (AT91C_PIO_PB9) //  SSC Receive Data 1
-#define AT91C_PB9_TIOB4           (AT91C_PIO_PB9) //  Timer Counter 4 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PC0             (1 <<  0) // Pin Controlled by PC0
-#define AT91C_PC0_BFCK            (AT91C_PIO_PC0) //  Burst Flash Clock
-#define AT91C_PIO_PC1             (1 <<  1) // Pin Controlled by PC1
-#define AT91C_PC1_BFRDY_SMOE      (AT91C_PIO_PC1) //  Burst Flash Ready
-#define AT91C_PIO_PC10            (1 << 10) // Pin Controlled by PC10
-#define AT91C_PC10_NCS4_CFCS      (AT91C_PIO_PC10) //  Compact Flash Chip Select
-#define AT91C_PIO_PC11            (1 << 11) // Pin Controlled by PC11
-#define AT91C_PC11_NCS5_CFCE1     (AT91C_PIO_PC11) //  Chip Select 5 / Compact Flash Chip Enable 1
-#define AT91C_PIO_PC12            (1 << 12) // Pin Controlled by PC12
-#define AT91C_PC12_NCS6_CFCE2     (AT91C_PIO_PC12) //  Chip Select 6 / Compact Flash Chip Enable 2
-#define AT91C_PIO_PC13            (1 << 13) // Pin Controlled by PC13
-#define AT91C_PC13_NCS7           (AT91C_PIO_PC13) //  Chip Select 7
-#define AT91C_PIO_PC14            (1 << 14) // Pin Controlled by PC14
-#define AT91C_PIO_PC15            (1 << 15) // Pin Controlled by PC15
-#define AT91C_PIO_PC16            (1 << 16) // Pin Controlled by PC16
-#define AT91C_PC16_D16            (AT91C_PIO_PC16) //  Data Bus [16]
-#define AT91C_PIO_PC17            (1 << 17) // Pin Controlled by PC17
-#define AT91C_PC17_D17            (AT91C_PIO_PC17) //  Data Bus [17]
-#define AT91C_PIO_PC18            (1 << 18) // Pin Controlled by PC18
-#define AT91C_PC18_D18            (AT91C_PIO_PC18) //  Data Bus [18]
-#define AT91C_PIO_PC19            (1 << 19) // Pin Controlled by PC19
-#define AT91C_PC19_D19            (AT91C_PIO_PC19) //  Data Bus [19]
-#define AT91C_PIO_PC2             (1 <<  2) // Pin Controlled by PC2
-#define AT91C_PC2_BFAVD           (AT91C_PIO_PC2) //  Burst Flash Address Valid
-#define AT91C_PIO_PC20            (1 << 20) // Pin Controlled by PC20
-#define AT91C_PC20_D20            (AT91C_PIO_PC20) //  Data Bus [20]
-#define AT91C_PIO_PC21            (1 << 21) // Pin Controlled by PC21
-#define AT91C_PC21_D21            (AT91C_PIO_PC21) //  Data Bus [21]
-#define AT91C_PIO_PC22            (1 << 22) // Pin Controlled by PC22
-#define AT91C_PC22_D22            (AT91C_PIO_PC22) //  Data Bus [22]
-#define AT91C_PIO_PC23            (1 << 23) // Pin Controlled by PC23
-#define AT91C_PC23_D23            (AT91C_PIO_PC23) //  Data Bus [23]
-#define AT91C_PIO_PC24            (1 << 24) // Pin Controlled by PC24
-#define AT91C_PC24_D24            (AT91C_PIO_PC24) //  Data Bus [24]
-#define AT91C_PIO_PC25            (1 << 25) // Pin Controlled by PC25
-#define AT91C_PC25_D25            (AT91C_PIO_PC25) //  Data Bus [25]
-#define AT91C_PIO_PC26            (1 << 26) // Pin Controlled by PC26
-#define AT91C_PC26_D26            (AT91C_PIO_PC26) //  Data Bus [26]
-#define AT91C_PIO_PC27            (1 << 27) // Pin Controlled by PC27
-#define AT91C_PC27_D27            (AT91C_PIO_PC27) //  Data Bus [27]
-#define AT91C_PIO_PC28            (1 << 28) // Pin Controlled by PC28
-#define AT91C_PC28_D28            (AT91C_PIO_PC28) //  Data Bus [28]
-#define AT91C_PIO_PC29            (1 << 29) // Pin Controlled by PC29
-#define AT91C_PC29_D29            (AT91C_PIO_PC29) //  Data Bus [29]
-#define AT91C_PIO_PC3             (1 <<  3) // Pin Controlled by PC3
-#define AT91C_PC3_BFBAA_SMWE      (AT91C_PIO_PC3) //  Burst Flash Address Advance / SmartMedia Write Enable
-#define AT91C_PIO_PC30            (1 << 30) // Pin Controlled by PC30
-#define AT91C_PC30_D30            (AT91C_PIO_PC30) //  Data Bus [30]
-#define AT91C_PIO_PC31            (1 << 31) // Pin Controlled by PC31
-#define AT91C_PC31_D31            (AT91C_PIO_PC31) //  Data Bus [31]
-#define AT91C_PIO_PC4             (1 <<  4) // Pin Controlled by PC4
-#define AT91C_PC4_BFOE            (AT91C_PIO_PC4) //  Burst Flash Output Enable
-#define AT91C_PIO_PC5             (1 <<  5) // Pin Controlled by PC5
-#define AT91C_PC5_BFWE            (AT91C_PIO_PC5) //  Burst Flash Write Enable
-#define AT91C_PIO_PC6             (1 <<  6) // Pin Controlled by PC6
-#define AT91C_PC6_NWAIT           (AT91C_PIO_PC6) //  NWAIT
-#define AT91C_PIO_PC7             (1 <<  7) // Pin Controlled by PC7
-#define AT91C_PC7_A23             (AT91C_PIO_PC7) //  Address Bus[23]
-#define AT91C_PIO_PC8             (1 <<  8) // Pin Controlled by PC8
-#define AT91C_PC8_A24             (AT91C_PIO_PC8) //  Address Bus[24]
-#define AT91C_PIO_PC9             (1 <<  9) // Pin Controlled by PC9
-#define AT91C_PC9_A25_CFRNW       (AT91C_PIO_PC9) //  Address Bus[25] /  Compact Flash Read Not Write
-#define AT91C_PIO_PD0             (1 <<  0) // Pin Controlled by PD0
-#define AT91C_PD0_ETX0            (AT91C_PIO_PD0) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PD1             (1 <<  1) // Pin Controlled by PD1
-#define AT91C_PD1_ETX1            (AT91C_PIO_PD1) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PD10            (1 << 10) // Pin Controlled by PD10
-#define AT91C_PD10_PCK3           (AT91C_PIO_PD10) //  PMC Programmable Clock Output 3
-#define AT91C_PD10_TPS1           (AT91C_PIO_PD10) //  ETM ARM9 pipeline status 1
-#define AT91C_PIO_PD11            (1 << 11) // Pin Controlled by PD11
-#define AT91C_PD11_               (AT91C_PIO_PD11) //  
-#define AT91C_PD11_TPS2           (AT91C_PIO_PD11) //  ETM ARM9 pipeline status 2
-#define AT91C_PIO_PD12            (1 << 12) // Pin Controlled by PD12
-#define AT91C_PD12_               (AT91C_PIO_PD12) //  
-#define AT91C_PD12_TPK0           (AT91C_PIO_PD12) //  ETM Trace Packet 0
-#define AT91C_PIO_PD13            (1 << 13) // Pin Controlled by PD13
-#define AT91C_PD13_               (AT91C_PIO_PD13) //  
-#define AT91C_PD13_TPK1           (AT91C_PIO_PD13) //  ETM Trace Packet 1
-#define AT91C_PIO_PD14            (1 << 14) // Pin Controlled by PD14
-#define AT91C_PD14_               (AT91C_PIO_PD14) //  
-#define AT91C_PD14_TPK2           (AT91C_PIO_PD14) //  ETM Trace Packet 2
-#define AT91C_PIO_PD15            (1 << 15) // Pin Controlled by PD15
-#define AT91C_PD15_TD0            (AT91C_PIO_PD15) //  SSC Transmit data
-#define AT91C_PD15_TPK3           (AT91C_PIO_PD15) //  ETM Trace Packet 3
-#define AT91C_PIO_PD16            (1 << 16) // Pin Controlled by PD16
-#define AT91C_PD16_TD1            (AT91C_PIO_PD16) //  SSC Transmit Data 1
-#define AT91C_PD16_TPK4           (AT91C_PIO_PD16) //  ETM Trace Packet 4
-#define AT91C_PIO_PD17            (1 << 17) // Pin Controlled by PD17
-#define AT91C_PD17_TD2            (AT91C_PIO_PD17) //  SSC Transmit Data 2
-#define AT91C_PD17_TPK5           (AT91C_PIO_PD17) //  ETM Trace Packet 5
-#define AT91C_PIO_PD18            (1 << 18) // Pin Controlled by PD18
-#define AT91C_PD18_NPCS1          (AT91C_PIO_PD18) //  SPI Peripheral Chip Select 1
-#define AT91C_PD18_TPK6           (AT91C_PIO_PD18) //  ETM Trace Packet 6
-#define AT91C_PIO_PD19            (1 << 19) // Pin Controlled by PD19
-#define AT91C_PD19_NPCS2          (AT91C_PIO_PD19) //  SPI Peripheral Chip Select 2
-#define AT91C_PD19_TPK7           (AT91C_PIO_PD19) //  ETM Trace Packet 7
-#define AT91C_PIO_PD2             (1 <<  2) // Pin Controlled by PD2
-#define AT91C_PD2_ETX2            (AT91C_PIO_PD2) //  Ethernet MAC Transmit Data 2
-#define AT91C_PIO_PD20            (1 << 20) // Pin Controlled by PD20
-#define AT91C_PD20_NPCS3          (AT91C_PIO_PD20) //  SPI Peripheral Chip Select 3
-#define AT91C_PD20_TPK8           (AT91C_PIO_PD20) //  ETM Trace Packet 8
-#define AT91C_PIO_PD21            (1 << 21) // Pin Controlled by PD21
-#define AT91C_PD21_RTS0           (AT91C_PIO_PD21) //  Usart 0 Ready To Send
-#define AT91C_PD21_TPK9           (AT91C_PIO_PD21) //  ETM Trace Packet 9
-#define AT91C_PIO_PD22            (1 << 22) // Pin Controlled by PD22
-#define AT91C_PD22_RTS1           (AT91C_PIO_PD22) //  Usart 0 Ready To Send
-#define AT91C_PD22_TPK10          (AT91C_PIO_PD22) //  ETM Trace Packet 10
-#define AT91C_PIO_PD23            (1 << 23) // Pin Controlled by PD23
-#define AT91C_PD23_RTS2           (AT91C_PIO_PD23) //  USART 2 Ready To Send
-#define AT91C_PD23_TPK11          (AT91C_PIO_PD23) //  ETM Trace Packet 11
-#define AT91C_PIO_PD24            (1 << 24) // Pin Controlled by PD24
-#define AT91C_PD24_RTS3           (AT91C_PIO_PD24) //  USART 3 Ready To Send
-#define AT91C_PD24_TPK12          (AT91C_PIO_PD24) //  ETM Trace Packet 12
-#define AT91C_PIO_PD25            (1 << 25) // Pin Controlled by PD25
-#define AT91C_PD25_DTR1           (AT91C_PIO_PD25) //  USART 1 Data Terminal ready
-#define AT91C_PD25_TPK13          (AT91C_PIO_PD25) //  ETM Trace Packet 13
-#define AT91C_PIO_PD26            (1 << 26) // Pin Controlled by PD26
-#define AT91C_PD26_TPK14          (AT91C_PIO_PD26) //  ETM Trace Packet 14
-#define AT91C_PIO_PD27            (1 << 27) // Pin Controlled by PD27
-#define AT91C_PD27_TPK15          (AT91C_PIO_PD27) //  ETM Trace Packet 15
-#define AT91C_PIO_PD3             (1 <<  3) // Pin Controlled by PD3
-#define AT91C_PD3_ETX3            (AT91C_PIO_PD3) //  Ethernet MAC Transmit Data 3
-#define AT91C_PIO_PD4             (1 <<  4) // Pin Controlled by PD4
-#define AT91C_PD4_ETXEN           (AT91C_PIO_PD4) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PD5             (1 <<  5) // Pin Controlled by PD5
-#define AT91C_PD5_ETXER           (AT91C_PIO_PD5) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PIO_PD6             (1 <<  6) // Pin Controlled by PD6
-#define AT91C_PD6_DTXD            (AT91C_PIO_PD6) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PD7             (1 <<  7) // Pin Controlled by PD7
-#define AT91C_PD7_PCK0            (AT91C_PIO_PD7) //  PMC Programmable Clock Output 0
-#define AT91C_PD7_TSYNC           (AT91C_PIO_PD7) //  ETM Synchronization signal
-#define AT91C_PIO_PD8             (1 <<  8) // Pin Controlled by PD8
-#define AT91C_PD8_PCK1            (AT91C_PIO_PD8) //  PMC Programmable Clock Output 1
-#define AT91C_PD8_TCLK            (AT91C_PIO_PD8) //  ETM Trace Clock signal
-#define AT91C_PIO_PD9             (1 <<  9) // Pin Controlled by PD9
-#define AT91C_PD9_PCK2            (AT91C_PIO_PD9) //  PMC Programmable Clock 2
-#define AT91C_PD9_TPS0            (AT91C_PIO_PD9) //  ETM ARM9 pipeline status 0
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91RM9200
-// *****************************************************************************
-#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS              ( 1) // System Peripheral
-#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller A 
-#define AT91C_ID_PIOB             ( 3) // Parallel IO Controller B
-#define AT91C_ID_PIOC             ( 4) // Parallel IO Controller C
-#define AT91C_ID_PIOD             ( 5) // Parallel IO Controller D
-#define AT91C_ID_US0              ( 6) // USART 0
-#define AT91C_ID_US1              ( 7) // USART 1
-#define AT91C_ID_US2              ( 8) // USART 2
-#define AT91C_ID_US3              ( 9) // USART 3
-#define AT91C_ID_MCI              (10) // Multimedia Card Interface
-#define AT91C_ID_UDP              (11) // USB Device Port
-#define AT91C_ID_TWI              (12) // Two-Wire Interface
-#define AT91C_ID_SPI              (13) // Serial Peripheral Interface
-#define AT91C_ID_SSC0             (14) // Serial Synchronous Controller 0
-#define AT91C_ID_SSC1             (15) // Serial Synchronous Controller 1
-#define AT91C_ID_SSC2             (16) // Serial Synchronous Controller 2
-#define AT91C_ID_TC0              (17) // Timer Counter 0
-#define AT91C_ID_TC1              (18) // Timer Counter 1
-#define AT91C_ID_TC2              (19) // Timer Counter 2
-#define AT91C_ID_TC3              (20) // Timer Counter 3
-#define AT91C_ID_TC4              (21) // Timer Counter 4
-#define AT91C_ID_TC5              (22) // Timer Counter 5
-#define AT91C_ID_UHP              (23) // USB Host port
-#define AT91C_ID_EMAC             (24) // Ethernet MAC
-#define AT91C_ID_IRQ0             (25) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1             (26) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ID_IRQ2             (27) // Advanced Interrupt Controller (IRQ2)
-#define AT91C_ID_IRQ3             (28) // Advanced Interrupt Controller (IRQ3)
-#define AT91C_ID_IRQ4             (29) // Advanced Interrupt Controller (IRQ4)
-#define AT91C_ID_IRQ5             (30) // Advanced Interrupt Controller (IRQ5)
-#define AT91C_ID_IRQ6             (31) // Advanced Interrupt Controller (IRQ6)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91RM9200
-// *****************************************************************************
-#define AT91C_BASE_SYS            (0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_RTC            (0xFFFFFE00) // (RTC) Base Address
-#define AT91C_BASE_ST             (0xFFFFFD00) // (ST) Base Address
-#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PIOD           (0xFFFFFA00) // (PIOD) Base Address
-#define AT91C_BASE_PIOC           (0xFFFFF800) // (PIOC) Base Address
-#define AT91C_BASE_PIOB           (0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_SPI        (0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI            (0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_SSC2       (0xFFFD8100) // (PDC_SSC2) Base Address
-#define AT91C_BASE_SSC2           (0xFFFD8000) // (SSC2) Base Address
-#define AT91C_BASE_PDC_SSC1       (0xFFFD4100) // (PDC_SSC1) Base Address
-#define AT91C_BASE_SSC1           (0xFFFD4000) // (SSC1) Base Address
-#define AT91C_BASE_PDC_SSC0       (0xFFFD0100) // (PDC_SSC0) Base Address
-#define AT91C_BASE_SSC0           (0xFFFD0000) // (SSC0) Base Address
-#define AT91C_BASE_PDC_US3        (0xFFFCC100) // (PDC_US3) Base Address
-#define AT91C_BASE_US3            (0xFFFCC000) // (US3) Base Address
-#define AT91C_BASE_PDC_US2        (0xFFFC8100) // (PDC_US2) Base Address
-#define AT91C_BASE_US2            (0xFFFC8000) // (US2) Base Address
-#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PDC_MCI        (0xFFFB4100) // (PDC_MCI) Base Address
-#define AT91C_BASE_MCI            (0xFFFB4000) // (MCI) Base Address
-#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC5            (0xFFFA4080) // (TC5) Base Address
-#define AT91C_BASE_TC4            (0xFFFA4040) // (TC4) Base Address
-#define AT91C_BASE_TC3            (0xFFFA4000) // (TC3) Base Address
-#define AT91C_BASE_TCB1           (0xFFFA4080) // (TCB1) Base Address
-#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TCB0           (0xFFFA0000) // (TCB0) Base Address
-#define AT91C_BASE_UHP            (0x00300000) // (UHP) Base Address
-#define AT91C_BASE_EMAC           (0xFFFBC000) // (EMAC) Base Address
-#define AT91C_BASE_EBI            (0xFFFFFF60) // (EBI) Base Address
-#define AT91C_BASE_SMC2           (0xFFFFFF70) // (SMC2) Base Address
-#define AT91C_BASE_SDRC           (0xFFFFFF90) // (SDRC) Base Address
-#define AT91C_BASE_BFC            (0xFFFFFFC0) // (BFC) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91RM9200
-// *****************************************************************************
-#define AT91C_ISRAM	              (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	         (0x00004000) // Internal SRAM size in byte (16 Kbyte)
-#define AT91C_IROM 	              (0x00100000) // Internal ROM base address
-#define AT91C_IROM_SIZE	          (0x00020000) // Internal ROM size in byte (128 Kbyte)
-
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/include/led.h b/target/linux/at91-2.6/image/dfboot/src/include/led.h
deleted file mode 100644
index 9bebd9c..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/include/led.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (C) Copyright 2006
- * Atmel Nordic AB <www.atmel.com>
- * Ulf Samuelsson <ulf@atmel.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
- 
- #ifndef __LED_H
-#define __LED_H
-
-#ifndef	__ASSEMBLY__
-extern void	LED_init (void);
-extern void	LED_set(unsigned int led);
-extern void	red_LED_on(void);
-extern void	red_LED_off(void);
-extern void	green_LED_on(void);
-extern void	green_LED_off(void);
-extern void	yellow_LED_on(void);
-extern void	yellow_LED_off(void);
-extern void	LED_blink(unsigned int led);
-#else
-	.extern LED_init
-	.extern LED_set
-	.extern LED_blink
-	.extern red_LED_on
-	.extern red_LED_off
-	.extern yellow_LED_on
-	.extern yellow_LED_off
-	.extern green_LED_on
-	.extern green_LED_off
-#endif
-#endif
diff --git a/target/linux/at91-2.6/image/dfboot/src/include/lib_AT91RM9200.h b/target/linux/at91-2.6/image/dfboot/src/include/lib_AT91RM9200.h
deleted file mode 100644
index c322b32..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/include/lib_AT91RM9200.h
+++ /dev/null
@@ -1,2978 +0,0 @@
-//*----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : lib_AT91RM9200.h
-//* Object              : AT91RM9200 inlined functions
-//* Generated           : AT91 SW Application Group  11/19/2003 (17:20:51)
-//*
-//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul 02 12:29:40 2002//
-//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference       : /lib_rtc_1245d.h/1.1/Fri Jan 31 12:19:12 2003//
-//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference       : /lib_spi_AT91RMxxxx.h/1.2/Fri Jan 31 12:19:31 2003//
-//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference       : /lib_pmc.h/1.3/Thu Nov 14 07:40:45 2002//
-//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference       : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003//
-//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:53 2002//
-//* CVS Reference       : /lib_mci.h/1.2/Wed Nov 20 14:18:55 2002//
-//* CVS Reference       : /lib_aic.h/1.3/Fri Jul 12 07:46:11 2002//
-//* CVS Reference       : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003//
-//* CVS Reference       : /lib_st.h/1.4/Fri Jan 31 12:20:13 2003//
-//*----------------------------------------------------------------------------
-
-#ifndef lib_AT91RM9200_H
-#define lib_AT91RM9200_H
-
-/* *****************************************************************************
-                SOFTWARE API FOR PDC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextRx
-//* \brief Set the next receive transfer descriptor
-//*----------------------------------------------------------------------------
-static inline void AT91F_PDC_SetNextRx (
-	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
-	char *address,       // \arg address to the next bloc to be received
-	unsigned int bytes)  // \arg number of bytes to be received
-{
-	pPDC->PDC_RNPR = (unsigned int) address;
-	pPDC->PDC_RNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextTx
-//* \brief Set the next transmit transfer descriptor
-//*----------------------------------------------------------------------------
-static inline void AT91F_PDC_SetNextTx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be transmitted
-	unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-	pPDC->PDC_TNPR = (unsigned int) address;
-	pPDC->PDC_TNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetRx
-//* \brief Set the receive transfer descriptor
-//*----------------------------------------------------------------------------
-static inline void AT91F_PDC_SetRx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be received
-	unsigned int bytes)    // \arg number of bytes to be received
-{
-	pPDC->PDC_RPR = (unsigned int) address;
-	pPDC->PDC_RCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetTx
-//* \brief Set the transmit transfer descriptor
-//*----------------------------------------------------------------------------
-static inline void AT91F_PDC_SetTx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be transmitted
-	unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-	pPDC->PDC_TPR = (unsigned int) address;
-	pPDC->PDC_TCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableTx
-//* \brief Enable transmit
-//*----------------------------------------------------------------------------
-static inline void AT91F_PDC_EnableTx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableRx
-//* \brief Enable receive
-//*----------------------------------------------------------------------------
-static inline void AT91F_PDC_EnableRx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableTx
-//* \brief Disable transmit
-//*----------------------------------------------------------------------------
-static inline void AT91F_PDC_DisableTx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableRx
-//* \brief Disable receive
-//*----------------------------------------------------------------------------
-static inline void AT91F_PDC_DisableRx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsTxEmpty
-//* \brief Test if the current transfer descriptor has been sent
-//*----------------------------------------------------------------------------
-static inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_TCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextTxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-static inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_TNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsRxEmpty
-//* \brief Test if the current transfer descriptor has been filled
-//*----------------------------------------------------------------------------
-static inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_RCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextRxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-static inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_RNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Open
-//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
-//*----------------------------------------------------------------------------
-static inline void AT91F_PDC_Open (
-	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-	AT91F_PDC_DisableRx(pPDC);
-	AT91F_PDC_DisableTx(pPDC);
-
-	//* Reset all Counter register Next buffer first
-	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-    //* Enable the RX and TX PDC transfer requests
-	AT91F_PDC_EnableRx(pPDC);
-	AT91F_PDC_EnableTx(pPDC);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Close
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-static inline void AT91F_PDC_Close (
-	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-	AT91F_PDC_DisableRx(pPDC);
-	AT91F_PDC_DisableTx(pPDC);
-
-	//* Reset all Counter register Next buffer first
-	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SendFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PDC_SendFrame(
-	AT91PS_PDC pPDC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	if (AT91F_PDC_IsTxEmpty(pPDC)) {
-		//* Buffer and next buffer can be initialized
-		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
-		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
-		return 2;
-	}
-	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
-		//* Only one buffer can be initialized
-		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
-		return 1;
-	}
-	else {
-		//* All buffer are in use...
-		return 0;
-	}
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_ReceiveFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PDC_ReceiveFrame (
-	AT91PS_PDC pPDC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	if (AT91F_PDC_IsRxEmpty(pPDC)) {
-		//* Buffer and next buffer can be initialized
-		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
-		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
-		return 2;
-	}
-	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
-		//* Only one buffer can be initialized
-		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
-		return 1;
-	}
-	else {
-		//* All buffer are in use...
-		return 0;
-	}
-}
-/* *****************************************************************************
-                SOFTWARE API FOR DBGU
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptEnable
-//* \brief Enable DBGU Interrupt
-//*----------------------------------------------------------------------------
-static inline void AT91F_DBGU_InterruptEnable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be enabled
-{
-        pDbgu->DBGU_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptDisable
-//* \brief Disable DBGU Interrupt
-//*----------------------------------------------------------------------------
-static inline void AT91F_DBGU_InterruptDisable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be disabled
-{
-        pDbgu->DBGU_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_GetInterruptMaskStatus
-//* \brief Return DBGU Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
-        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
-{
-        return pDbgu->DBGU_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_IsInterruptMasked
-//* \brief Test if DBGU Interrupt is Masked 
-//*----------------------------------------------------------------------------
-static inline int AT91F_DBGU_IsInterruptMasked(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR RTC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RTC_InterruptEnable
-//* \brief Enable RTC Interrupt
-//*----------------------------------------------------------------------------
-static inline void AT91F_RTC_InterruptEnable(
-        AT91PS_RTC pRtc,   // \arg  pointer to a RTC controller
-        unsigned int flag) // \arg  RTC interrupt to be enabled
-{
-        pRtc->RTC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RTC_InterruptDisable
-//* \brief Disable RTC Interrupt
-//*----------------------------------------------------------------------------
-static inline void AT91F_RTC_InterruptDisable(
-        AT91PS_RTC pRtc,   // \arg  pointer to a RTC controller
-        unsigned int flag) // \arg  RTC interrupt to be disabled
-{
-        pRtc->RTC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RTC_GetInterruptMaskStatus
-//* \brief Return RTC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_RTC_GetInterruptMaskStatus( // \return RTC Interrupt Mask Status
-        AT91PS_RTC pRtc) // \arg  pointer to a RTC controller
-{
-        return pRtc->RTC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RTC_IsInterruptMasked
-//* \brief Test if RTC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-static inline int AT91F_RTC_IsInterruptMasked(
-        AT91PS_RTC pRtc,   // \arg  pointer to a RTC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_RTC_GetInterruptMaskStatus(pRtc) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR SSC
-   ***************************************************************************** */
-//* Define the standard I2S mode configuration
-
-//* Configuration to set in the SSC Transmit Clock Mode Register
-//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
-//* 			  nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
-									   AT91C_SSC_CKS_DIV   +\
-                            		   AT91C_SSC_CKO_CONTINOUS      +\
-                            		   AT91C_SSC_CKG_NONE    +\
-                                       AT91C_SSC_START_FALL_RF +\
-                           			   AT91C_SSC_STTOUT  +\
-                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
-                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
-
-
-//* Configuration to set in the SSC Transmit Frame Mode Register
-//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
-//* 			 nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
-									(nb_bit_by_slot-1)  +\
-                            		AT91C_SSC_MSBF   +\
-                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
-                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
-                            		AT91C_SSC_FSOS_NEGATIVE)
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC_SetBaudrate (
-        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
-        unsigned int mainClock, // \arg peripheral clock
-        unsigned int speed)     // \arg SSC baudrate
-{
-        unsigned int baud_value;
-        //* Define the baud rate divisor register
-        if (speed == 0)
-           baud_value = 0;
-        else
-        {
-           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
-           if ((baud_value % 10) >= 5)
-                  baud_value = (baud_value / 10) + 1;
-           else
-                  baud_value /= 10;
-        }
-
-        pSSC->SSC_CMR = baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_Configure
-//* \brief Configure SSC
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC_Configure (
-             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
-             unsigned int syst_clock,  // \arg System Clock Frequency
-             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
-             unsigned int clock_rx,    // \arg Receiver Clock Parameters
-             unsigned int mode_rx,     // \arg mode Register to be programmed
-             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
-             unsigned int mode_tx)     // \arg mode Register to be programmed
-{
-    //* Disable interrupts
-	pSSC->SSC_IDR = (unsigned int) -1;
-
-    //* Reset receiver and transmitter
-	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
-
-    //* Define the Clock Mode Register
-	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
-
-     //* Write the Receive Clock Mode Register
-	pSSC->SSC_RCMR =  clock_rx;
-
-     //* Write the Transmit Clock Mode Register
-	pSSC->SSC_TCMR =  clock_tx;
-
-     //* Write the Receive Frame Mode Register
-	pSSC->SSC_RFMR =  mode_rx;
-
-     //* Write the Transmit Frame Mode Register
-	pSSC->SSC_TFMR =  mode_tx;
-
-    //* Clear Transmit and Receive Counters
-	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
-
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableRx
-//* \brief Enable receiving datas
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC_EnableRx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Enable receiver
-    pSSC->SSC_CR = AT91C_SSC_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableRx
-//* \brief Disable receiving datas
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC_DisableRx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Disable receiver
-    pSSC->SSC_CR = AT91C_SSC_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableTx
-//* \brief Enable sending datas
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC_EnableTx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Enable  transmitter
-    pSSC->SSC_CR = AT91C_SSC_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableTx
-//* \brief Disable sending datas
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC_DisableTx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Disable  transmitter
-    pSSC->SSC_CR = AT91C_SSC_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableIt
-//* \brief Enable SSC IT
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC_EnableIt (
-	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pSSC->SSC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableIt
-//* \brief Disable SSC IT
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC_DisableIt (
-	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pSSC->SSC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_SSC_ReceiveFrame (
-	AT91PS_SSC pSSC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pSSC->SSC_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_SSC_SendFrame(
-	AT91PS_SSC pSSC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pSSC->SSC_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_GetInterruptMaskStatus
-//* \brief Return SSC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
-        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
-{
-        return pSsc->SSC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_IsInterruptMasked
-//* \brief Test if SSC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-static inline int AT91F_SSC_IsInterruptMasked(
-        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR SPI
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Open
-//* \brief Open a SPI Port
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_SPI_Open (
-        const unsigned int null)  // \arg
-{
-        /* NOT DEFINED AT THIS MOMENT */
-        return ( 0 );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgCs
-//* \brief Configure SPI chip select register
-//*----------------------------------------------------------------------------
-static inline void AT91F_SPI_CfgCs (
-	int cs,     // SPI cs number (0 to 3)
- 	int val)   //  chip select register
-{
-	//* Write to the CSR register
-	*(AT91C_SPI_CSR + cs) = val;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_EnableIt
-//* \brief Enable SPI interrupt
-//*----------------------------------------------------------------------------
-static inline void AT91F_SPI_EnableIt (
-	AT91PS_SPI pSPI,     // pointer to a SPI controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pSPI->SPI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_DisableIt
-//* \brief Disable SPI interrupt
-//*----------------------------------------------------------------------------
-static inline void AT91F_SPI_DisableIt (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pSPI->SPI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Reset
-//* \brief Reset the SPI controller
-//*----------------------------------------------------------------------------
-static inline void AT91F_SPI_Reset (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SWRST;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Enable
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-static inline void AT91F_SPI_Enable (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Disable
-//* \brief Disable the SPI controller
-//*----------------------------------------------------------------------------
-static inline void AT91F_SPI_Disable (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgMode
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-static inline void AT91F_SPI_CfgMode (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	int mode)        // mode register 
-{
-	//* Write to the MR register
-	pSPI->SPI_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgPCS
-//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
-//*----------------------------------------------------------------------------
-static inline void AT91F_SPI_CfgPCS (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	char PCS_Device) // PCS of the Device
-{	
- 	//* Write to the MR register
-	pSPI->SPI_MR &= 0xFFF0FFFF;
-	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_SPI_ReceiveFrame (
-	AT91PS_SPI pSPI,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pSPI->SPI_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_SPI_SendFrame(
-	AT91PS_SPI pSPI,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pSPI->SPI_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Close
-//* \brief Close SPI: disable IT disable transfert, close PDC
-//*----------------------------------------------------------------------------
-static inline void AT91F_SPI_Close (
-	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
-{
-    //* Reset all the Chip Select register
-    pSPI->SPI_CSR[0] = 0 ;
-    pSPI->SPI_CSR[1] = 0 ;
-    pSPI->SPI_CSR[2] = 0 ;
-    pSPI->SPI_CSR[3] = 0 ;
-
-    //* Reset the SPI mode
-    pSPI->SPI_MR = 0  ;
-
-    //* Disable all interrupts
-    pSPI->SPI_IDR = 0xFFFFFFFF ;
-
-    //* Abort the Peripheral Data Transfers
-    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
-
-    //* Disable receiver and transmitter and stop any activity immediately
-    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-static inline void AT91F_SPI_PutChar (
-	AT91PS_SPI pSPI,
-	unsigned int character,
-             unsigned int cs_number )
-{
-    unsigned int value_for_cs;
-    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
-    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-static inline int AT91F_SPI_GetChar (
-	const AT91PS_SPI pSPI)
-{
-    return((pSPI->SPI_RDR) & 0xFFFF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_GetInterruptMaskStatus
-//* \brief Return SPI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
-        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
-{
-        return pSpi->SPI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_IsInterruptMasked
-//* \brief Test if SPI Interrupt is Masked 
-//*----------------------------------------------------------------------------
-static inline int AT91F_SPI_IsInterruptMasked(
-        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_InterruptEnable
-//* \brief Enable TC Interrupt
-//*----------------------------------------------------------------------------
-static inline void AT91F_TC_InterruptEnable(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  TC interrupt to be enabled
-{
-        pTc->TC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_InterruptDisable
-//* \brief Disable TC Interrupt
-//*----------------------------------------------------------------------------
-static inline void AT91F_TC_InterruptDisable(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  TC interrupt to be disabled
-{
-        pTc->TC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_GetInterruptMaskStatus
-//* \brief Return TC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
-        AT91PS_TC pTc) // \arg  pointer to a TC controller
-{
-        return pTc->TC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_IsInterruptMasked
-//* \brief Test if TC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-static inline int AT91F_TC_IsInterruptMasked(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClock
-//* \brief Return Main clock in Hz
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_CKGR_GetMainClock (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetProcessorClock
-//* \brief Return processor clock in Hz (for AT91RM3400 and AT91RM9200)
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PMC_GetProcessorClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	unsigned int reg = pPMC->PMC_MCKR;
-	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
-	unsigned int pllDivider, pllMultiplier;
-
-	switch (reg & AT91C_PMC_CSS) {
-		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
-			return slowClock / prescaler;
-		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
-			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
-		case AT91C_PMC_CSS_PLLA_CLK: // PLLA clock is selected
-			reg = pCKGR->CKGR_PLLAR;
-			pllDivider    = (reg  & AT91C_CKGR_DIVA);
-			pllMultiplier = ((reg  & AT91C_CKGR_MULA) >> 16) + 1;
-			if (reg & AT91C_CKGR_SRCA) // Source is Main clock
-				return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
-			else                       // Source is Slow clock
-				return slowClock / pllDivider * pllMultiplier / prescaler;
-		case AT91C_PMC_CSS_PLLB_CLK: // PLLB clock is selected
-			reg = pCKGR->CKGR_PLLBR;
-			pllDivider    = (reg  & AT91C_CKGR_DIVB);
-			pllMultiplier = ((reg  & AT91C_CKGR_MULB) >> 16) + 1;
-			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
-	}
-	return 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMasterClock
-//* \brief Return master clock in Hz (just for AT91RM9200)
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PMC_GetMasterClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	return AT91F_PMC_GetProcessorClock(pPMC, pCKGR, slowClock) /
-		(((pPMC->PMC_MCKR & AT91C_PMC_MDIV) >> 8)+1);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePeriphClock
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-static inline void AT91F_PMC_EnablePeriphClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-	pPMC->PMC_PCER = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePeriphClock
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-static inline void AT91F_PMC_DisablePeriphClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-	pPMC->PMC_PCDR = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-static inline void AT91F_PMC_EnablePCK (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
-	unsigned int ccs,  // \arg clock selection: AT91C_PMC_CSS_SLOW_CLK, AT91C_PMC_CSS_MAIN_CLK, AT91C_PMC_CSS_PLLA_CLK, AT91C_PMC_CSS_PLLB_CLK
-	unsigned int pres) // \arg Programmable clock prescalar AT91C_PMC_PRES_CLK, AT91C_PMC_PRES_CLK_2, ..., AT91C_PMC_PRES_CLK_64
-{
-	pPMC->PMC_PCKR[pck] = ccs | pres;
-	pPMC->PMC_SCER = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-static inline void AT91F_PMC_DisablePCK (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
-{
-	pPMC->PMC_SCDR = (1 << pck) << 8;
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PIO
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPeriph
-//* \brief Enable pins to be drived by peripheral
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_CfgPeriph(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int periphAEnable,  // \arg PERIPH A to enable
-	unsigned int periphBEnable)  // \arg PERIPH B to enable
-
-{
-	pPio->PIO_ASR = periphAEnable;
-	pPio->PIO_BSR = periphBEnable;
-	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOutput
-//* \brief Enable PIO in output mode
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_CfgOutput(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int pioEnable)      // \arg PIO to be enabled
-{
-	pPio->PIO_PER = pioEnable; // Set in PIO mode
-	pPio->PIO_OER = pioEnable; // Configure in Output
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInput
-//* \brief Enable PIO in input mode
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_CfgInput(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int inputEnable)      // \arg PIO to be enabled
-{
-	// Disable output
-	pPio->PIO_ODR  = inputEnable;
-	pPio->PIO_PER  = inputEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOpendrain
-//* \brief Configure PIO in open drain
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_CfgOpendrain(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
-{
-	// Configure the multi-drive option
-	pPio->PIO_MDDR = ~multiDrvEnable;
-	pPio->PIO_MDER = multiDrvEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPullup
-//* \brief Enable pullup on PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_CfgPullup(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int pullupEnable)   // \arg enable pullup on PIO
-{
-		// Connect or not Pullup
-	pPio->PIO_PPUDR = ~pullupEnable;
-	pPio->PIO_PPUER = pullupEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgDirectDrive
-//* \brief Enable direct drive on PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_CfgDirectDrive(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int directDrive)    // \arg PIO to be configured with direct drive
-
-{
-	// Configure the Direct Drive
-	pPio->PIO_OWDR  = ~directDrive;
-	pPio->PIO_OWER  = directDrive;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInputFilter
-//* \brief Enable input filter on input PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_CfgInputFilter(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int inputFilter)    // \arg PIO to be configured with input filter
-
-{
-	// Configure the Direct Drive
-	pPio->PIO_IFDR  = ~inputFilter;
-	pPio->PIO_IFER  = inputFilter;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInput
-//* \brief Return PIO input value
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PIO_GetInput( // \return PIO input
-	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-	return pPio->PIO_PDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputSet
-//* \brief Test if PIO is input flag is active
-//*----------------------------------------------------------------------------
-static inline int AT91F_PIO_IsInputSet(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PIO_GetInput(pPio) & flag);
-}
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_SetOutput
-//* \brief Set to 1 output PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_SetOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be set
-{
-	pPio->PIO_SODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ClearOutput
-//* \brief Set to 0 output PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_ClearOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be cleared
-{
-	pPio->PIO_CODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ForceOutput
-//* \brief Force output when Direct drive option is enabled
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_ForceOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be forced
-{
-	pPio->PIO_ODSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Enable
-//* \brief Enable PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_Enable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled 
-{
-        pPio->PIO_PER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Disable
-//* \brief Disable PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_Disable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled 
-{
-        pPio->PIO_PDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetStatus
-//* \brief Return PIO Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsSet
-//* \brief Test if PIO is Set
-//*----------------------------------------------------------------------------
-static inline int AT91F_PIO_IsSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputEnable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_OutputEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be enabled
-{
-        pPio->PIO_OER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputDisable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_OutputDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be disabled
-{
-        pPio->PIO_ODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputStatus
-//* \brief Return PIO Output Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOuputSet
-//* \brief Test if PIO Output is Set
-//*----------------------------------------------------------------------------
-static inline int AT91F_PIO_IsOutputSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterEnable
-//* \brief Input Filter Enable PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_InputFilterEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be enabled
-{
-        pPio->PIO_IFER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterDisable
-//* \brief Input Filter Disable PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_InputFilterDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be disabled
-{
-        pPio->PIO_IFDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInputFilterStatus
-//* \brief Return PIO Input Filter Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IFSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputFilterSet
-//* \brief Test if PIO Input filter is Set
-//*----------------------------------------------------------------------------
-static inline int AT91F_PIO_IsInputFilterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputDataStatus
-//* \brief Return PIO Output Data Status 
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status 
-	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ODSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptEnable
-//* \brief Enable PIO Interrupt
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_InterruptEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be enabled
-{
-        pPio->PIO_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptDisable
-//* \brief Disable PIO Interrupt
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_InterruptDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be disabled
-{
-        pPio->PIO_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptMaskStatus
-//* \brief Return PIO Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptMasked
-//* \brief Test if PIO Interrupt is Masked 
-//*----------------------------------------------------------------------------
-static inline int AT91F_PIO_IsInterruptMasked(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptSet
-//* \brief Test if PIO Interrupt is Set
-//*----------------------------------------------------------------------------
-static inline int AT91F_PIO_IsInterruptSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverEnable
-//* \brief Multi Driver Enable PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_MultiDriverEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
-{
-        pPio->PIO_MDER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverDisable
-//* \brief Multi Driver Disable PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_MultiDriverDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
-{
-        pPio->PIO_MDDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetMultiDriverStatus
-//* \brief Return PIO Multi Driver Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_MDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsMultiDriverSet
-//* \brief Test if PIO MultiDriver is Set
-//*----------------------------------------------------------------------------
-static inline int AT91F_PIO_IsMultiDriverSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_A_RegisterSelection
-//* \brief PIO A Register Selection 
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_A_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio A register selection
-{
-        pPio->PIO_ASR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_B_RegisterSelection
-//* \brief PIO B Register Selection 
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_B_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio B register selection 
-{
-        pPio->PIO_BSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Get_AB_RegisterStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ABSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsAB_RegisterSet
-//* \brief Test if PIO AB Register is Set
-//*----------------------------------------------------------------------------
-static inline int AT91F_PIO_IsAB_RegisterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteEnable
-//* \brief Output Write Enable PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_OutputWriteEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be enabled
-{
-        pPio->PIO_OWER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteDisable
-//* \brief Output Write Disable PIO
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIO_OutputWriteDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be disabled
-{
-        pPio->PIO_OWDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputWriteStatus
-//* \brief Return PIO Output Write Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OWSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputWriteSet
-//* \brief Test if PIO OutputWrite is Set
-//*----------------------------------------------------------------------------
-static inline int AT91F_PIO_IsOutputWriteSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetCfgPullup
-//* \brief Return PIO Configuration Pullup
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup 
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PPUSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputDataStatusSet
-//* \brief Test if PIO Output Data Status is Set 
-//*----------------------------------------------------------------------------
-static inline int AT91F_PIO_IsOutputDataStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsCfgPullupStatusSet
-//* \brief Test if PIO Configuration Pullup Status is Set
-//*----------------------------------------------------------------------------
-static inline int AT91F_PIO_IsCfgPullupStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TWI
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_EnableIt
-//* \brief Enable TWI IT
-//*----------------------------------------------------------------------------
-static inline void AT91F_TWI_EnableIt (
-	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pTWI->TWI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_DisableIt
-//* \brief Disable TWI IT
-//*----------------------------------------------------------------------------
-static inline void AT91F_TWI_DisableIt (
-	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pTWI->TWI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_Configure
-//* \brief Configure TWI in master mode
-//*----------------------------------------------------------------------------
-static inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
-{
-    //* Disable interrupts
-	pTWI->TWI_IDR = (unsigned int) -1;
-
-    //* Reset peripheral
-	pTWI->TWI_CR = AT91C_TWI_SWRST;
-
-	//* Set Master mode
-	pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_GetInterruptMaskStatus
-//* \brief Return TWI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
-        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
-{
-        return pTwi->TWI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_IsInterruptMasked
-//* \brief Test if TWI Interrupt is Masked 
-//*----------------------------------------------------------------------------
-static inline int AT91F_TWI_IsInterruptMasked(
-        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR USART
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Baudrate
-//* \brief Calculate the baudrate
-//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
-                        AT91C_US_NBSTOP_1_BIT + \
-                        AT91C_US_PAR_NONE + \
-                        AT91C_US_CHRL_8_BITS + \
-                        AT91C_US_CLKS_CLOCK )
-
-//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
-                            AT91C_US_NBSTOP_1_BIT + \
-                            AT91C_US_PAR_NONE + \
-                            AT91C_US_CHRL_8_BITS + \
-                            AT91C_US_CLKS_EXT )
-
-//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
-                       AT91C_US_USMODE_NORMAL + \
-                       AT91C_US_NBSTOP_1_BIT + \
-                       AT91C_US_PAR_NONE + \
-                       AT91C_US_CHRL_8_BITS + \
-                       AT91C_US_CLKS_CLOCK )
-
-//* SCK used Label
-#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
-
-//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
-#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
-					   		 AT91C_US_CLKS_CLOCK +\
-                       		 AT91C_US_NBSTOP_1_BIT + \
-                       		 AT91C_US_PAR_EVEN + \
-                       		 AT91C_US_CHRL_8_BITS + \
-                       		 AT91C_US_CKLO +\
-                       		 AT91C_US_OVER)
-
-//* Standard IRDA mode
-#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
-                            AT91C_US_NBSTOP_1_BIT + \
-                            AT91C_US_PAR_NONE + \
-                            AT91C_US_CHRL_8_BITS + \
-                            AT91C_US_CLKS_CLOCK )
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Baudrate
-//* \brief Caluculate baud_value according to the main clock and the baud rate
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_US_Baudrate (
-	const unsigned int main_clock, // \arg peripheral clock
-	const unsigned int baud_rate)  // \arg UART baudrate
-{
-	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
-	if ((baud_value % 10) >= 5)
-		baud_value = (baud_value / 10) + 1;
-	else
-		baud_value /= 10;
-	return baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_SetBaudrate (
-	AT91PS_USART pUSART,    // \arg pointer to a USART controller
-	unsigned int mainClock, // \arg peripheral clock
-	unsigned int speed)     // \arg UART baudrate
-{
-	//* Define the baud rate divisor register
-	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetTimeguard
-//* \brief Set USART timeguard
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_SetTimeguard (
-	AT91PS_USART pUSART,    // \arg pointer to a USART controller
-	unsigned int timeguard) // \arg timeguard value
-{
-	//* Write the Timeguard Register
-	pUSART->US_TTGR = timeguard ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableIt
-//* \brief Enable USART IT
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_EnableIt (
-	AT91PS_USART pUSART, // \arg pointer to a USART controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pUSART->US_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableIt
-//* \brief Disable USART IT
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_DisableIt (
-	AT91PS_USART pUSART, // \arg pointer to a USART controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IER register
-	pUSART->US_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Configure
-//* \brief Configure USART
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_Configure (
-	AT91PS_USART pUSART,     // \arg pointer to a USART controller
-	unsigned int mainClock,  // \arg peripheral clock
-	unsigned int mode ,      // \arg mode Register to be programmed
-	unsigned int baudRate ,  // \arg baudrate to be programmed
-	unsigned int timeguard ) // \arg timeguard to be programmed
-{
-    //* Disable interrupts
-    pUSART->US_IDR = (unsigned int) -1;
-
-    //* Reset receiver and transmitter
-    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
-
-	//* Define the baud rate divisor register
-	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
-
-	//* Write the Timeguard Register
-	AT91F_US_SetTimeguard(pUSART, timeguard);
-
-    //* Clear Transmit and Receive Counters
-    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
-
-    //* Define the USART mode
-    pUSART->US_MR = mode  ;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableRx
-//* \brief Enable receiving characters
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_EnableRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Enable receiver
-    pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableTx
-//* \brief Enable sending characters
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_EnableTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Enable  transmitter
-    pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ResetRx
-//* \brief Reset Receiver and re-enable it
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_ResetRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-	//* Reset receiver
-	pUSART->US_CR = AT91C_US_RSTRX;
-    //* Re-Enable receiver
-    pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ResetTx
-//* \brief Reset Transmitter and re-enable it
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_ResetTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-	//* Reset transmitter
-	pUSART->US_CR = AT91C_US_RSTTX;
-    //* Enable transmitter
-    pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableRx
-//* \brief Disable Receiver
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_DisableRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Disable receiver
-    pUSART->US_CR = AT91C_US_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableTx
-//* \brief Disable Transmitter
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_DisableTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Disable transmitter
-    pUSART->US_CR = AT91C_US_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Close
-//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_Close (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Reset the baud rate divisor register
-    pUSART->US_BRGR = 0 ;
-
-    //* Reset the USART mode
-    pUSART->US_MR = 0  ;
-
-    //* Reset the Timeguard Register
-    pUSART->US_TTGR = 0;
-
-    //* Disable all interrupts
-    pUSART->US_IDR = 0xFFFFFFFF ;
-
-    //* Abort the Peripheral Data Transfers
-    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
-
-    //* Disable receiver and transmitter and stop any activity immediately
-    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_TxReady
-//* \brief Return 1 if a character can be written in US_THR
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_US_TxReady (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR & AT91C_US_TXRDY);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_RxReady
-//* \brief Return 1 if a character can be read in US_RHR
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_US_RxReady (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR & AT91C_US_RXRDY);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Error
-//* \brief Return the error flag
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_US_Error (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR &
-    	(AT91C_US_OVRE |  // Overrun error
-    	 AT91C_US_FRAME | // Framing error
-    	 AT91C_US_PARE));  // Parity error
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_PutChar (
-	AT91PS_USART pUSART,
-	int character )
-{
-    pUSART->US_THR = (character & 0x1FF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-static inline int AT91F_US_GetChar (
-	const AT91PS_USART pUSART)
-{
-    return((pUSART->US_RHR) & 0x1FF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_US_SendFrame(
-	AT91PS_USART pUSART,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pUSART->US_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_US_ReceiveFrame (
-	AT91PS_USART pUSART,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pUSART->US_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetIrdaFilter
-//* \brief Set the value of IrDa filter tregister
-//*----------------------------------------------------------------------------
-static inline void AT91F_US_SetIrdaFilter (
-	AT91PS_USART pUSART,
-	unsigned char value
-)
-{
-	pUSART->US_IF = value;
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR MCI
-   ***************************************************************************** */
-//* Classic MCI Mode Register Configuration with PDC mode enabled and MCK = MCI Clock
-#define AT91C_MCI_MR_PDCMODE	(AT91C_MCI_CLKDIV |\
-                                AT91C_MCI_PWSDIV |\
-                                (AT91C_MCI_PWSDIV<<1) |\
-                                AT91C_MCI_PDCMODE)
-
-//* Classic MCI Data Timeout Register Configuration with 1048576 MCK cycles between 2 data transfer
-#define AT91C_MCI_DTOR_1MEGA_CYCLES	(AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL)
-
-//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot A
-#define AT91C_MCI_MMC_SLOTA	(AT91C_MCI_SCDSEL & 0x0)
-
-//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot B
-#define AT91C_MCI_MMC_SLOTB	(AT91C_MCI_SCDSEL)
-
-//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot A
-#define AT91C_MCI_SDCARD_4BITS_SLOTA	( (AT91C_MCI_SCDSEL & 0x0) | AT91C_MCI_SCDBUS )
-
-//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot B
-#define AT91C_MCI_SDCARD_4BITS_SLOTB	(AT91C_MCI_SCDSEL | AT91C_MCI_SCDBUS)
-
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_Configure
-//* \brief Configure the MCI
-//*----------------------------------------------------------------------------
-static inline void AT91F_MCI_Configure (
-        AT91PS_MCI pMCI,  			 // \arg pointer to a MCI controller
-        unsigned int DTOR_register,  // \arg Data Timeout Register to be programmed
-        unsigned int MR_register,  	 // \arg Mode Register to be programmed
-        unsigned int SDCR_register)  // \arg SDCard Register to be programmed
-{
-    //* Reset the MCI
-    pMCI->MCI_CR = AT91C_MCI_MCIEN | AT91C_MCI_PWSEN;
-
-    //* Disable all the interrupts
-    pMCI->MCI_IDR = 0xFFFFFFFF;
-
-    //* Set the Data Timeout Register
-    pMCI->MCI_DTOR = DTOR_register;
-
-    //* Set the Mode Register
-    pMCI->MCI_MR = MR_register;
-
-    //* Set the SDCard Register
-    pMCI->MCI_SDCR = SDCR_register;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_EnableIt
-//* \brief Enable MCI IT
-//*----------------------------------------------------------------------------
-static inline void AT91F_MCI_EnableIt (
-        AT91PS_MCI pMCI, // \arg pointer to a MCI controller
-        unsigned int flag)   // \arg IT to be enabled
-{
-    //* Write to the IER register
-    pMCI->MCI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_DisableIt
-//* \brief Disable MCI IT
-//*----------------------------------------------------------------------------
-static inline void AT91F_MCI_DisableIt (
-        AT91PS_MCI pMCI, // \arg pointer to a MCI controller
-        unsigned int flag)   // \arg IT to be disabled
-{
-    //* Write to the IDR register
-    pMCI->MCI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_Enable_Interface
-//* \brief Enable the MCI Interface
-//*----------------------------------------------------------------------------
-static inline void AT91F_MCI_Enable_Interface (
-        AT91PS_MCI pMCI)     // \arg pointer to a MCI controller
-{
-    //* Enable the MCI
-    pMCI->MCI_CR = AT91C_MCI_MCIEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_Disable_Interface
-//* \brief Disable the MCI Interface
-//*----------------------------------------------------------------------------
-static inline void AT91F_MCI_Disable_Interface (
-        AT91PS_MCI pMCI)     // \arg pointer to a MCI controller
-{
-    //* Disable the MCI
-    pMCI->MCI_CR = AT91C_MCI_MCIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_Cfg_ModeRegister
-//* \brief Configure the MCI Mode Register
-//*----------------------------------------------------------------------------
-static inline void AT91F_MCI_Cfg_ModeRegister (
-        AT91PS_MCI pMCI, // \arg pointer to a MCI controller
-        unsigned int mode_register)   // \arg value to set in the mode register
-{
-    //* Configure the MCI MR
-    pMCI->MCI_MR = mode_register;
-}
-/* *****************************************************************************
-                SOFTWARE API FOR AIC
-   ***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_AIC_ConfigureIt (
-	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
-	unsigned int irq_id,     // \arg interrupt number to initialize
-	unsigned int priority,   // \arg priority to give to the interrupt
-	unsigned int src_type,   // \arg activation and sense of activation
-	void (*newHandler) (void) ) // \arg address of the interrupt handler
-{
-	unsigned int oldHandler;
-    unsigned int mask ;
-
-    oldHandler = pAic->AIC_SVR[irq_id];
-
-    mask = 0x1 << irq_id ;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Save the interrupt handler routine pointer and the interrupt priority
-    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
-    //* Store the Source Mode Register
-    pAic->AIC_SMR[irq_id] = src_type | priority  ;
-    //* Clear the interrupt on the interrupt controller
-    pAic->AIC_ICCR = mask ;
-
-	return oldHandler;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_EnableIt
-//* \brief Enable corresponding IT number
-//*----------------------------------------------------------------------------
-static inline void AT91F_AIC_EnableIt (
-	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-	unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    //* Enable the interrupt on the interrupt controller
-    pAic->AIC_IECR = 0x1 << irq_id ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_DisableIt
-//* \brief Disable corresponding IT number
-//*----------------------------------------------------------------------------
-static inline void AT91F_AIC_DisableIt (
-	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-	unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    unsigned int mask = 0x1 << irq_id;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = mask ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ClearIt
-//* \brief Clear corresponding IT number
-//*----------------------------------------------------------------------------
-static inline void AT91F_AIC_ClearIt (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg interrupt number to initialize
-{
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = (0x1 << irq_id);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_AcknowledgeIt
-//* \brief Acknowledge corresponding IT number
-//*----------------------------------------------------------------------------
-static inline void AT91F_AIC_AcknowledgeIt (
-	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
-{
-    pAic->AIC_EOICR = pAic->AIC_EOICR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_SetExceptionVector
-//* \brief Configure vector handler
-//*----------------------------------------------------------------------------
-static inline unsigned int  AT91F_AIC_SetExceptionVector (
-	unsigned int *pVector, // \arg pointer to the AIC registers
-	void (*Handler) () )   // \arg Interrupt Handler
-{
-	unsigned int oldVector = *pVector;
-
-	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
-		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
-	else
-		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
-
-	return oldVector;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Trig
-//* \brief Trig an IT
-//*----------------------------------------------------------------------------
-static inline void  AT91F_AIC_Trig (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg interrupt number
-{
-	pAic->AIC_ISCR = (0x1 << irq_id) ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsActive
-//* \brief Test if an IT is active
-//*----------------------------------------------------------------------------
-static inline unsigned int  AT91F_AIC_IsActive (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg Interrupt Number
-{
-	return (pAic->AIC_ISR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsPending
-//* \brief Test if an IT is pending
-//*----------------------------------------------------------------------------
-static inline unsigned int  AT91F_AIC_IsPending (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg Interrupt Number
-{
-	return (pAic->AIC_IPR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Open
-//* \brief Set exception vectors and AIC registers to default values
-//*----------------------------------------------------------------------------
-static inline void AT91F_AIC_Open(
-	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
-	void (*IrqHandler) (),  // \arg Default IRQ vector exception
-	void (*FiqHandler) (),  // \arg Default FIQ vector exception
-	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
-	void (*SpuriousHandler) (), // \arg Default Spurious Handler
-	unsigned int protectMode)   // \arg Debug Control Register
-{
-	int i;
-
-	// Disable all interrupts and set IVR to the default handler
-	for (i = 0; i < 32; ++i) {
-		AT91F_AIC_DisableIt(pAic, i);
-		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler);
-	}
-
-	// Set the IRQ exception vector
-	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
-	// Set the Fast Interrupt exception vector
-	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
-
-	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
-	pAic->AIC_DCR = protectMode;
-}
-/* *****************************************************************************
-                SOFTWARE API FOR UDP
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EnableIt
-//* \brief Enable UDP IT
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_EnableIt (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pUDP->UDP_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_DisableIt
-//* \brief Disable UDP IT
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_DisableIt (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pUDP->UDP_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_SetAddress
-//* \brief Set UDP functional address
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_SetAddress (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char address)   // \arg new UDP address
-{
-	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EnableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_EnableEp (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg endpoints to be enabled
-{
-	pUDP->UDP_GLBSTATE  |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_DisableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_DisableEp (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg endpoints to be enabled
-{
-	pUDP->UDP_GLBSTATE  &= ~(flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_SetState
-//* \brief Set UDP Device state
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_SetState (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg new UDP address
-{
-	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
-	pUDP->UDP_GLBSTATE  |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_GetState
-//* \brief return UDP Device state
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
-	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
-{
-	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_ResetEp
-//* \brief Reset UDP endpoint
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_ResetEp ( // \return the UDP device state
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg Endpoints to be reset
-{
-	pUDP->UDP_RSTEP = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpStall
-//* \brief Endpoint will STALL requests
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_EpStall(
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char endpoint)   // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpWrite
-//* \brief Write value in the DPR
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_EpWrite(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned char value)     // \arg value to be written in the DPR
-{
-	pUDP->UDP_FDR[endpoint] = value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpRead
-//* \brief Return value from the DPR
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_UDP_EpRead(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	return pUDP->UDP_FDR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpEndOfWr
-//* \brief Notify the UDP that values in DPR are ready to be sent
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_EpEndOfWr(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpClear
-//* \brief Clear flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_EpClear(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned int flag)       // \arg flag to be cleared
-{
-	pUDP->UDP_CSR[endpoint] &= ~(flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpSet
-//* \brief Set flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_EpSet(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned int flag)       // \arg flag to be cleared
-{
-	pUDP->UDP_CSR[endpoint] |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpStatus
-//* \brief Return the endpoint CSR register
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_UDP_EpStatus(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	return pUDP->UDP_CSR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_GetInterruptMaskStatus
-//* \brief Return UDP Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
-        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
-{
-        return pUdp->UDP_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_IsInterruptMasked
-//* \brief Test if UDP Interrupt is Masked 
-//*----------------------------------------------------------------------------
-static inline int AT91F_UDP_IsInterruptMasked(
-        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR ST
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ST_SetPeriodInterval
-//* \brief Set Periodic Interval Interrupt (period in ms)
-//*----------------------------------------------------------------------------
-static inline void AT91F_ST_SetPeriodInterval(
-	AT91PS_ST pSt,
-	unsigned int period)
-{
-	volatile int status;
-	pSt->ST_IDR = AT91C_ST_PITS;			/* Interrupt disable Register */
-
-	status = pSt->ST_SR;
-    pSt->ST_PIMR = period << 5;   			/* Period Interval Mode Register == timer interval = 1ms*/
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ST_EnableIt
-//* \brief Enable system timer interrupt
-//*----------------------------------------------------------------------------
-static inline void AT91F_ST_EnableIt(
-	AT91PS_ST pSt,
-	unsigned int flag)
-{
-	pSt->ST_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ST_DisableIt
-//* \brief Disable system timer interrupt
-//*----------------------------------------------------------------------------
-static inline void AT91F_ST_DisableIt(
-	AT91PS_ST pSt,
-	unsigned int flag)
-{
-	pSt->ST_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ST_GetInterruptMaskStatus
-//* \brief Return ST Interrupt Mask Status
-//*----------------------------------------------------------------------------
-static inline unsigned int AT91F_ST_GetInterruptMaskStatus( // \return ST Interrupt Mask Status
-        AT91PS_ST pSt) // \arg  pointer to a ST controller
-{
-        return pSt->ST_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ST_IsInterruptMasked
-//* \brief Test if ST Interrupt is Masked 
-//*----------------------------------------------------------------------------
-static inline int AT91F_ST_IsInterruptMasked(
-        AT91PS_ST pSt,   // \arg  pointer to a ST controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_ST_GetInterruptMaskStatus(pSt) & flag);
-}
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_EBI_CfgPIO
-//* \brief Configure PIO controllers to drive EBI signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_EBI_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOC, // PIO controller base address
-		((unsigned int) AT91C_PC8_A24     ) |
-		((unsigned int) AT91C_PC7_A23     ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  DBGU
-//*----------------------------------------------------------------------------
-static inline void AT91F_DBGU_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_CfgPIO
-//* \brief Configure PIO controllers to drive DBGU signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_DBGU_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA31_DTXD    ) |
-		((unsigned int) AT91C_PA30_DRXD    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SYS_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SYS
-//*----------------------------------------------------------------------------
-static inline void AT91F_SYS_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UHP_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  UHP
-//*----------------------------------------------------------------------------
-static inline void AT91F_UHP_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_UHP));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SDRC_CfgPIO
-//* \brief Configure PIO controllers to drive SDRC signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_SDRC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOC, // PIO controller base address
-		((unsigned int) AT91C_PC20_D20     ) |
-		((unsigned int) AT91C_PC21_D21     ) |
-		((unsigned int) AT91C_PC30_D30     ) |
-		((unsigned int) AT91C_PC22_D22     ) |
-		((unsigned int) AT91C_PC31_D31     ) |
-		((unsigned int) AT91C_PC23_D23     ) |
-		((unsigned int) AT91C_PC16_D16     ) |
-		((unsigned int) AT91C_PC24_D24     ) |
-		((unsigned int) AT91C_PC17_D17     ) |
-		((unsigned int) AT91C_PC25_D25     ) |
-		((unsigned int) AT91C_PC18_D18     ) |
-		((unsigned int) AT91C_PC26_D26     ) |
-		((unsigned int) AT91C_PC19_D19     ) |
-		((unsigned int) AT91C_PC27_D27     ) |
-		((unsigned int) AT91C_PC28_D28     ) |
-		((unsigned int) AT91C_PC29_D29     ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_EMAC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  EMAC
-//*----------------------------------------------------------------------------
-static inline void AT91F_EMAC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_EMAC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_EMAC_CfgPIO
-//* \brief Configure PIO controllers to drive EMAC signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_EMAC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA14_ERXER   ) |
-		((unsigned int) AT91C_PA12_ERX0    ) |
-		((unsigned int) AT91C_PA13_ERX1    ) |
-		((unsigned int) AT91C_PA8_ETXEN   ) |
-		((unsigned int) AT91C_PA16_EMDIO   ) |
-		((unsigned int) AT91C_PA9_ETX0    ) |
-		((unsigned int) AT91C_PA10_ETX1    ) |
-		((unsigned int) AT91C_PA11_ECRS_ECRSDV) |
-		((unsigned int) AT91C_PA15_EMDC    ) |
-		((unsigned int) AT91C_PA7_ETXCK_EREFCK), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  RTC
-//*----------------------------------------------------------------------------
-static inline void AT91F_RTC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC2_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SSC2
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC2_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SSC2));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC2_CfgPIO
-//* \brief Configure PIO controllers to drive SSC2 signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC2_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB12_TF2     ) |
-		((unsigned int) AT91C_PB17_RF2     ) |
-		((unsigned int) AT91C_PB13_TK2     ) |
-		((unsigned int) AT91C_PB16_RK2     ) |
-		((unsigned int) AT91C_PB14_TD2     ) |
-		((unsigned int) AT91C_PB15_RD2     ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SSC1
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SSC1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC1_CfgPIO
-//* \brief Configure PIO controllers to drive SSC1 signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB11_RF1     ) |
-		((unsigned int) AT91C_PB10_RK1     ) |
-		((unsigned int) AT91C_PB8_TD1     ) |
-		((unsigned int) AT91C_PB9_RD1     ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SSC0
-//*----------------------------------------------------------------------------
-static inline void AT91F_SSC0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SSC0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SPI
-//*----------------------------------------------------------------------------
-static inline void AT91F_SPI_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SPI));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgPIO
-//* \brief Configure PIO controllers to drive SPI signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_SPI_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA3_NPCS0   ) |
-		((unsigned int) AT91C_PA4_NPCS1   ) |
-		((unsigned int) AT91C_PA1_MOSI    ) |
-		((unsigned int) AT91C_PA5_NPCS2   ) |
-		((unsigned int) AT91C_PA6_NPCS3   ) |
-		((unsigned int) AT91C_PA0_MISO    ) |
-		((unsigned int) AT91C_PA2_SPCK    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC5_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC5
-//*----------------------------------------------------------------------------
-static inline void AT91F_TC5_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC5));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC4_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC4
-//*----------------------------------------------------------------------------
-static inline void AT91F_TC4_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC4));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC3_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC3
-//*----------------------------------------------------------------------------
-static inline void AT91F_TC3_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC3));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC2_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC2
-//*----------------------------------------------------------------------------
-static inline void AT91F_TC2_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC2));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC1
-//*----------------------------------------------------------------------------
-static inline void AT91F_TC1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC0
-//*----------------------------------------------------------------------------
-static inline void AT91F_TC0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SMC2_CfgPIO
-//* \brief Configure PIO controllers to drive SMC2 signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_SMC2_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOC, // PIO controller base address
-		((unsigned int) AT91C_PC10_NCS4_CFCS) |
-		((unsigned int) AT91C_PC9_A25_CFRNW) |
-		((unsigned int) AT91C_PC12_NCS6_CFCE2) |
-		((unsigned int) AT91C_PC11_NCS5_CFCE1), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PMC
-//*----------------------------------------------------------------------------
-static inline void AT91F_PMC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgPIO
-//* \brief Configure PIO controllers to drive PMC signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_PMC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA24_PCK1    )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB27_PCK0    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIOD_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PIOD
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIOD_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PIOD));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIOC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PIOC
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIOC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PIOC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIOB_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PIOB
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIOB_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PIOB));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIOA_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PIOA
-//*----------------------------------------------------------------------------
-static inline void AT91F_PIOA_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PIOA));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TWI
-//*----------------------------------------------------------------------------
-static inline void AT91F_TWI_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TWI));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_CfgPIO
-//* \brief Configure PIO controllers to drive TWI signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_TWI_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA25_TWD     ) |
-		((unsigned int) AT91C_PA26_TWCK    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US3_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US3
-//*----------------------------------------------------------------------------
-static inline void AT91F_US3_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_US3));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US2_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US2
-//*----------------------------------------------------------------------------
-static inline void AT91F_US2_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_US2));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US2_CfgPIO
-//* \brief Configure PIO controllers to drive US2 signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_US2_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA23_TXD2    ) |
-		((unsigned int) AT91C_PA22_RXD2    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US1
-//*----------------------------------------------------------------------------
-static inline void AT91F_US1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_US1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US1_CfgPIO
-//* \brief Configure PIO controllers to drive US1 signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_US1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB21_RXD1    ) |
-		((unsigned int) AT91C_PB26_RTS1    ) |
-		((unsigned int) AT91C_PB25_DSR1    ) |
-		((unsigned int) AT91C_PB24_CTS1    ) |
-		((unsigned int) AT91C_PB19_DTR1    ) |
-		((unsigned int) AT91C_PB23_DCD1    ) |
-		((unsigned int) AT91C_PB20_TXD1    ) |
-		((unsigned int) AT91C_PB18_RI1     ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US0
-//*----------------------------------------------------------------------------
-static inline void AT91F_US0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_US0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US0_CfgPIO
-//* \brief Configure PIO controllers to drive US0 signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_US0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA17_TXD0    ) |
-		((unsigned int) AT91C_PA21_RTS0    ) |
-		((unsigned int) AT91C_PA19_SCK0    ) |
-		((unsigned int) AT91C_PA20_CTS0    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  MCI
-//*----------------------------------------------------------------------------
-static inline void AT91F_MCI_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_MCI));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_CfgPIO
-//* \brief Configure PIO controllers to drive MCI signals
-//*----------------------------------------------------------------------------
-static inline void AT91F_MCI_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA28_MCCDA   ) |
-		((unsigned int) AT91C_PA29_MCDA0   ) |
-		((unsigned int) AT91C_PA27_MCCK    ), // Peripheral A
-		0); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB5_MCDA3   ) |
-		((unsigned int) AT91C_PB3_MCDA1   ) |
-		((unsigned int) AT91C_PB4_MCDA2   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  AIC
-//*----------------------------------------------------------------------------
-static inline void AT91F_AIC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_IRQ4) |
-		((unsigned int) 1 << AT91C_ID_FIQ) |
-		((unsigned int) 1 << AT91C_ID_IRQ5) |
-		((unsigned int) 1 << AT91C_ID_IRQ6) |
-		((unsigned int) 1 << AT91C_ID_IRQ0) |
-		((unsigned int) 1 << AT91C_ID_IRQ1) |
-		((unsigned int) 1 << AT91C_ID_IRQ2) |
-		((unsigned int) 1 << AT91C_ID_IRQ3));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  UDP
-//*----------------------------------------------------------------------------
-static inline void AT91F_UDP_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_UDP));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ST_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  ST
-//*----------------------------------------------------------------------------
-static inline void AT91F_ST_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-#endif // lib_AT91RM9200_H
diff --git a/target/linux/at91-2.6/image/dfboot/src/init.c b/target/linux/at91-2.6/image/dfboot/src/init.c
deleted file mode 100644
index 4088973..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/init.c
+++ /dev/null
@@ -1,165 +0,0 @@
-//*----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : init.c
-//* Object              : Low level initialisations written in C
-//* Creation            : HIi   10/10/2003
-//*
-//*----------------------------------------------------------------------------
-#include "config.h"
-#include "AT91RM9200.h"
-#include "lib_AT91RM9200.h"
-#include "stdio.h"
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DataAbort
-//* \brief This function reports an Abort
-//*----------------------------------------------------------------------------
-static void AT91F_SpuriousHandler() 
-{
-	puts("ISI");
-	while (1);
-}
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DataAbort
-//* \brief This function reports an Abort
-//*----------------------------------------------------------------------------
-static void AT91F_DataAbort() 
-{
-	puts("IDA");
-	while (1);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_FetchAbort
-//* \brief This function reports an Abort
-//*----------------------------------------------------------------------------
-static void AT91F_FetchAbort()
-{
-	puts("IFA");
-	while (1);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UndefHandler
-//* \brief This function reports that no handler have been set for current IT
-//*----------------------------------------------------------------------------
-static void AT91F_UndefHandler() 
-{
-	puts("IUD");
-	while (1);
-}
-
-
-//*--------------------------------------------------------------------------------------
-//* Function Name       : AT91F_InitSdram
-//* Object              : Initialize the SDRAM
-//* Input Parameters    :
-//* Output Parameters   :
-//*--------------------------------------------------------------------------------------
-static void AT91F_InitSdram()
-{
-	int *pRegister;
-	
-	//* Configure PIOC as peripheral (D16/D31)
-	
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOC, // PIO controller base address
-		0xFFFF0030,
-		0
-	);
-	
-	//*Init SDRAM
-	pRegister = (int *)0xFFFFFF98;
-	*pRegister = 0x2188c155; 
-	pRegister = (int *)0xFFFFFF90;
-	*pRegister = 0x2; 
-	pRegister = (int *)0x20000000;
-	*pRegister = 0; 
-	pRegister = (int *)0xFFFFFF90;
-	*pRegister = 0x4; 
-	pRegister = (int *)0x20000000;
-	*pRegister = 0; 
-	*pRegister = 0; 
-	*pRegister = 0; 
-	*pRegister = 0; 
-	*pRegister = 0; 
-	*pRegister = 0; 
-	*pRegister = 0; 
-	*pRegister = 0; 
-	pRegister = (int *)0xFFFFFF90;
-	*pRegister = 0x3; 
-	pRegister = (int *)0x20000080;
-	*pRegister = 0; 
-
-	pRegister = (int *)0xFFFFFF94;
-	*pRegister = 0x2e0; 
-	pRegister = (int *)0x20000000;
-	*pRegister = 0; 
-
-	pRegister = (int *)0xFFFFFF90;
-	*pRegister = 0x00; 
-	pRegister = (int *)0x20000000;
-	*pRegister = 0; 
-}
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_InitFlash
-//* \brief This function performs low level HW initialization
-//*----------------------------------------------------------------------------
-static void AT91F_InitMemories()
-{
-	int *pEbi = (int *)0xFFFFFF60;
-
-	//* Setup MEMC to support all connected memories (CS0 = FLASH; CS1=SDRAM)
-	pEbi  = (int *)0xFFFFFF60;
-	*pEbi = 0x00000002;
-
-	//* CS0 cs for flash
-	pEbi  = (int *)0xFFFFFF70;
-	*pEbi = 0x00003284;
-	
-	AT91F_InitSdram();
-}
-
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_LowLevelInit
-//* \brief This function performs very low level HW initialization
-//*----------------------------------------------------------------------------
-void AT91F_LowLevelInit(void)
-{
-	int i;
-
-	// Init Interrupt Controller
-	AT91F_AIC_Open(
-		AT91C_BASE_AIC,          // pointer to the AIC registers
-		AT91C_AIC_BRANCH_OPCODE, // IRQ exception vector
-		AT91F_UndefHandler,      // FIQ exception vector
-		AT91F_UndefHandler,      // AIC default handler
-		AT91F_SpuriousHandler,   // AIC spurious handler
-		0);                      // Protect mode
-
-	// Perform 8 End Of Interrupt Command to make sýre AIC will not Lock out nIRQ 
-	for(i=0; i<8; i++)
-		AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
-
-	AT91F_AIC_SetExceptionVector((unsigned int *)0x0C, AT91F_FetchAbort);
-	AT91F_AIC_SetExceptionVector((unsigned int *)0x10, AT91F_DataAbort);
-	AT91F_AIC_SetExceptionVector((unsigned int *)0x4, AT91F_UndefHandler);
-
-	//Initialize SDRAM and Flash
-	AT91F_InitMemories();
-
-}
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/jump.S b/target/linux/at91-2.6/image/dfboot/src/jump.S
deleted file mode 100644
index cc69311..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/jump.S
+++ /dev/null
@@ -1,4 +0,0 @@
-.global		Jump
-	
-Jump:		mov pc, r0				
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/led.c b/target/linux/at91-2.6/image/dfboot/src/led.c
deleted file mode 100644
index 40d4911..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/led.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2006
- * Atmel Nordic AB <www.atmel.com>
- * Ulf Samuelsson <ulf@atmel.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <AT91RM9200.h>
-
-#define	GREEN_LED	AT91C_PIO_PB0
-#define	YELLOW_LED	AT91C_PIO_PB1
-#define	RED_LED	AT91C_PIO_PB2
-
-void	LED_set(unsigned int led)
-{
-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
-	PIOB->PIO_SODR		= (led ^ 0x7) & 0x7;		// All 0's => Set PIO high => OFF
-	PIOB->PIO_CODR		=  led & 0x7;			// All 1's => Set PIO low   => ON
-}
-
-void	green_LED_on(void)
-{
-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
-//	PIOB->PIO_CODR		= GREEN_LED;
-	PIOB->PIO_CODR		= (1 << 0);
-}
-
-void	 yellow_LED_on(void)
-{
-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
-//	PIOB->PIO_CODR		= YELLOW_LED;
-	PIOB->PIO_CODR		= (1 << 1);
-}
-
-void	 red_LED_on(void)
-{
-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
-//	PIOB->PIO_CODR		= RED_LED;
-	PIOB->PIO_CODR		= (1 << 2);
-}
-
-void	green_LED_off(void)
-{
-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
-//	PIOB->PIO_SODR		= GREEN_LED;
-	PIOB->PIO_SODR		= (1 << 0);
-}
-
-void	yellow_LED_off(void)
-{
-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
-//	PIOB->PIO_SODR		= YELLOW_LED;
-	PIOB->PIO_SODR		= (1 << 1);
-}
-
-void	red_LED_off(void)
-{
-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
-//	PIOB->PIO_SODR		= RED_LED;
-	PIOB->PIO_SODR		= (1 << 2);
-}
-
-void	LED_blink(unsigned int led)
-{
-	volatile int i,j;
-	for(i = 0; i < 5; i++) {
-		LED_set((1 << led)&0x7);
-		for(j= 0; j < 200000; j++);
-		LED_set(0);
-		for(j= 0; j < 200000; j++);
-	}		
-}
-
-
-void LED_init (void)
-{
-	AT91PS_PIO	PIOB	= AT91C_BASE_PIOB;
-	AT91PS_PMC	PMC	= AT91C_BASE_PMC;
-	PMC->PMC_PCER		= (1 << AT91C_ID_PIOB);	// Enable PIOB clock
-	// Disable peripherals on LEDs
-	PIOB->PIO_PER		= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
-	// Enable pins as outputs
-	PIOB->PIO_OER		= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
-	// Turn all LEDs OFF
-	PIOB->PIO_SODR		= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
-}
diff --git a/target/linux/at91-2.6/image/dfboot/src/main.c b/target/linux/at91-2.6/image/dfboot/src/main.c
deleted file mode 100644
index c0705de..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/main.c
+++ /dev/null
@@ -1,811 +0,0 @@
-/*----------------------------------------------------------------------------
- *         ATMEL Microcontroller Software Support  -  ROUSSET  -
- *----------------------------------------------------------------------------
- * The software is delivered "AS IS" without warranty or condition of any
- * kind, either express, implied or statutory. This includes without
- * limitation any warranty or condition with respect to merchantability or
- * fitness for any particular purpose, or against the infringements of
- * intellectual property rights of others.
- *----------------------------------------------------------------------------
- * File Name		: main.c
- * Object		: 
- * Creation		: HIi	10/10/2003
- * Modif		: HIi	15/06/2004 :	add crc32 to verify the download
- *                                          	from dataflash
- *			: HIi	21/09/2004 :	Set first PLLA to 180Mhz and MCK to
- *						60Mhz to speed up dataflash boot (15Mhz)
- *			: MLC	12/04/2005 :	Modify SetPLL() to avoid errata
- *			: USA	30/12/2005 :	Change to page Size 1056
- *						Change startaddress to C0008400
- *						Change SPI Speed to ~4 Mhz
- *						Add retry on CRC Error
- *----------------------------------------------------------------------------
- */
-#include "config.h"
-#include "stdio.h"
-#include "AT91RM9200.h"
-#include "lib_AT91RM9200.h"
-#include "com.h"
-#include "main.h"
-#include "dataflash.h"
-#include "AT91C_MCI_Device.h"
-
-#define	DEBUGOUT
-#define XMODEM
-#define MEMDISP
-
-#ifdef	PAGESZ_1056
-#define	PAGESIZE	1056
-#else
-#define	PAGESIZE	1024
-#endif
-
-#define AT91C_SDRAM_START 0x20000000
-#define AT91C_BOOT_ADDR 0x21F00000
-#define AT91C_BOOT_SIZE 128*PAGESIZE
-#ifdef	PAGESZ_1056
-#define AT91C_BOOT_DATAFLASH_ADDR 0xC0008400
-#else
-#define AT91C_BOOT_DATAFLASH_ADDR 0xC0008000
-#endif
-#define AT91C_PLLA_VALUE 0x237A3E5A  // crystal= 18.432MHz - fixes BRG error at 115kbps
-//#define AT91C_PLLA_VALUE 0x2026BE04	// crystal= 18.432MHz
-//#define AT91C_PLLA_VALUE 0x202CBE01	// crystal= 4MHz
-
-
-
-#define DISP_LINE_LEN 16
-
-// Reason for boot failure
-#define	IMAGE_BAD_SIZE			0
-#define	IMAGE_READ_FAILURE	1
-#define	IMAGE_CRC_ERROR		2
-#define	IMAGE_ERROR			3
-#define	SUCCESS				-1
-
-/* prototypes*/
-extern void AT91F_ST_ASM_HANDLER(void);
-extern void Jump(unsigned int addr);
-
-const char *menu_dataflash[] = {
-#ifdef XMODEM
-	"1: P DFboot\n",
-	"2: P U-Boot\n",
-#endif
-	"3: P SDCard\n",
-#ifdef	PAGESZ_1056
-	"4: R UBOOT\n",
-#else
-	"4: R UBOOT\n",
-#endif
-#ifdef XMODEM
-	"5: P DF [addr]\n",
-#endif
-	"6: RD DF [addr]\n",
-	"7: E DF\n"
-};
-#ifdef XMODEM
-#define	MAXMENU 7
-#else
-#define MAXMENU 4
-#endif
-
-char message[20];
-#ifdef XMODEM
-volatile char XmodemComplete = 0;
-#endif
-unsigned int StTick = 0;
-
-AT91S_RomBoot const *pAT91;
-#ifdef XMODEM
-AT91S_SBuffer sXmBuffer;
-AT91S_SvcXmodem svcXmodem;
-AT91S_Pipe xmodemPipe;
-#endif
-AT91S_CtlTempo ctlTempo;
-
-
-//*--------------------------------------------------------------------------------------
-//* Function Name       : GetTickCount()
-//* Object              : Return the number of systimer tick 
-//* Input Parameters    :
-//* Output Parameters   :
-//*--------------------------------------------------------------------------------------
-unsigned int GetTickCount(void)
-{
-	return StTick;
-}
-
-#ifdef XMODEM
-//*--------------------------------------------------------------------------------------
-//* Function Name       : AT91_XmodemComplete()
-//* Object              : Perform the remap and jump to appli in RAM
-//* Input Parameters    :
-//* Output Parameters   :
-//*--------------------------------------------------------------------------------------
-static void AT91_XmodemComplete(AT91S_PipeStatus status, void *pVoid)
-{
-	/* stop the Xmodem tempo */
-	svcXmodem.tempo.Stop(&(svcXmodem.tempo));
-	XmodemComplete = 1;
-}
-
-
-//*--------------------------------------------------------------------------------------
-//* Function Name       : AT91F_XmodemProtocol(AT91S_PipeStatus status, void *pVoid)
-//* Object              : Xmodem dispatcher
-//* Input Parameters    :
-//* Output Parameters   :
-//*--------------------------------------------------------------------------------------
-static void XmodemProtocol(AT91S_PipeStatus status, void *pVoid)
-{
-	AT91PS_SBuffer pSBuffer = (AT91PS_SBuffer) xmodemPipe.pBuffer->pChild;
-	AT91PS_USART   pUsart     = svcXmodem.pUsart;
-			
-	if (pSBuffer->szRdBuffer == 0) {
-		/* Start a tempo to wait the Xmodem protocol complete */
-		svcXmodem.tempo.Start(&(svcXmodem.tempo), 10, 0, AT91_XmodemComplete, pUsart);								
-	}
-}
-#endif
-
-//*--------------------------------------------------------------------------------------
-//* Function Name       : irq1_c_handler()
-//* Object              : C Interrupt handler for Interrutp source 1
-//* Input Parameters    : none
-//* Output Parameters   : none
-//*--------------------------------------------------------------------------------------
-void AT91F_ST_HANDLER(void)
-{
-	volatile unsigned int csr = *AT91C_DBGU_CSR;
-#ifdef XMODEM
-	unsigned int error;
-#endif
-	
-	if (AT91C_BASE_ST->ST_SR & 0x01) {
-		StTick++;
-		ctlTempo.CtlTempoTick(&ctlTempo);
-		return;
-	}
-
-#ifdef XMODEM
-	error = AT91F_US_Error((AT91PS_USART)AT91C_BASE_DBGU);
-	if (csr & error) {
-		/* Stop previous Xmodem transmition*/
-		*(AT91C_DBGU_CR) = AT91C_US_RSTSTA;
-		AT91F_US_DisableIt((AT91PS_USART)AT91C_BASE_DBGU, AT91C_US_ENDRX);
-		AT91F_US_EnableIt((AT91PS_USART)AT91C_BASE_DBGU, AT91C_US_RXRDY);
-
-	}
-	
-	else if (csr & (AT91C_US_TXRDY | AT91C_US_ENDTX | AT91C_US_TXEMPTY | 
-	                AT91C_US_RXRDY | AT91C_US_ENDRX | AT91C_US_TIMEOUT | 
-	                AT91C_US_RXBUFF)) {
-		if ( !(svcXmodem.eot) )
-			svcXmodem.Handler(&svcXmodem, csr);
-	}
-#endif
-}
-
-
-//*-----------------------------------------------------------------------------
-//* Function Name       : AT91F_DisplayMenu()
-//* Object              : 
-//* Input Parameters    : 
-//* Return value		: 
-//*-----------------------------------------------------------------------------
-static int AT91F_DisplayMenu(void)
-{
-	int i, mci_present = 0;
-	printf("\nDF LOADER %s %s %s\n",AT91C_VERSION,__DATE__,__TIME__);
-	AT91F_DataflashPrintInfo();
-	mci_present = AT91F_MCI_Init();
-	for(i = 0; i < MAXMENU; i++) {
-		puts(menu_dataflash[i]);
-	}
-	return mci_present;
-}	
-
-
-//*-----------------------------------------------------------------------------
-//* Function Name       : AsciiToHex()
-//* Object              : ascii to hexa conversion
-//* Input Parameters    : 
-//* Return value		: 
-//*-----------------------------------------------------------------------------
-static unsigned int AsciiToHex(char *s, unsigned int *val)
-{
-	int n;
-
-	*val=0;
-	
-	if(s[0] == '0' && ((s[1] == 'x') || (s[1] == 'X')))
-		s+=2;
-	n = 0;	
-	while((n < 8) && (s[n] !=0))
-	{
-		*val <<= 4;
-		if ( (s[n] >= '0') && (s[n] <='9'))
-			*val += (s[n] - '0');
-		else	
-			if ((s[n] >= 'a') && (s[n] <='f'))
-				*val += (s[n] - 0x57);
-			else
-				if ((s[n] >= 'A') && (s[n] <='F'))
-					*val += (s[n] - 0x37);
-			else
-				return 0;
-		n++;
-	}
-
-	return 1;				
-}
-
-
-#ifdef MEMDISP
-//*-----------------------------------------------------------------------------
-//* Function Name       : AT91F_MemoryDisplay()
-//* Object              : Display the content of the dataflash
-//* Input Parameters    : 
-//* Return value		: 
-//*-----------------------------------------------------------------------------
-static int AT91F_MemoryDisplay(unsigned int addr, unsigned int length)
-{
-	unsigned long	i, nbytes, linebytes;
-	char	*cp;
-//	unsigned int 	*uip;
-//	unsigned short 	*usp;
-	unsigned char 	*ucp;
-	char linebuf[DISP_LINE_LEN];
-
-//	nbytes = length * size;
-	nbytes = length;
-   	do
-   	{
-//   		uip = (unsigned int *)linebuf;
-//   		usp = (unsigned short *)linebuf;
-		ucp = (unsigned char *)linebuf;
-		
-		printf("%08x:", addr);
-		linebytes = (nbytes > DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
-                if((addr & 0xF0000000) == 0x20000000) {
-			for(i = 0; i < linebytes; i ++) {
-				linebuf[i] =  *(char *)(addr+i);
-			}
-		} else {
-			read_dataflash(addr, linebytes, linebuf);
-		}
-		for (i=0; i<linebytes; i++)
-		{
-/*			if (size == 4) 
-				printf(" %08x", *uip++);
-			else if (size == 2)
-				printf(" %04x", *usp++);
-			else
-*/
-				printf(" %02x", *ucp++);
-//			addr += size;
-			addr++;
-		}
-		printf("    ");
-		cp = linebuf;
-		for (i=0; i<linebytes; i++) {
-			if ((*cp < 0x20) || (*cp > 0x7e))
-				printf(".");
-			else
-				printf("%c", *cp);
-			cp++;
-		}
-		printf("\n");
-		nbytes -= linebytes;
-	} while (nbytes > 0);
-	return 0;
-}
-#endif
-
-//*--------------------------------------------------------------------------------------
-//* Function Name       : AT91F_SetPLL
-//* Object              : Set the PLLA to 180Mhz and Master clock to 60 Mhz
-//* Input Parameters    :
-//* Output Parameters   :
-//*--------------------------------------------------------------------------------------
-static unsigned int AT91F_SetPLL(void)
-{
-	AT91_REG tmp;
-	AT91PS_PMC pPmc = AT91C_BASE_PMC;
-	AT91PS_CKGR pCkgr = AT91C_BASE_CKGR;
-
-	pPmc->PMC_IDR = 0xFFFFFFFF;
-
-	/* -Setup the PLL A */
-	pCkgr->CKGR_PLLAR = AT91C_PLLA_VALUE;
-
-	while (!(*AT91C_PMC_SR & AT91C_PMC_LOCKA));
-	
-	/* - Switch Master Clock from PLLB to PLLA/3 */
-	tmp = pPmc->PMC_MCKR;
-	/* See Atmel Errata #27 and #28 */
-	if (tmp & 0x0000001C) {
-		tmp = (tmp & ~0x0000001C);
-		pPmc->PMC_MCKR = tmp;
-		while (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY));
-	}
-	if (tmp != 0x00000202) {
-		pPmc->PMC_MCKR = 0x00000202;
-		if ((tmp & 0x00000003) != 0x00000002)
-			while (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY));
-	}
-
-	return 1;	
-}
-
-
-//*--------------------------------------------------------------------------------------
-//* Function Name       : AT91F_ResetRegisters
-//* Object              : Restore the initial state to registers
-//* Input Parameters    :
-//* Output Parameters   :
-//*--------------------------------------------------------------------------------------
-static unsigned int AT91F_ResetRegisters(void)
-{
-	volatile int i = 0;
-
-	/* set the PIOs in input*/
-	/* This disables the UART output, so dont execute for now*/
-
-#ifndef	DEBUGOUT
-	*AT91C_PIOA_ODR = 0xFFFFFFFF;	/* Disables all the output pins */
-	*AT91C_PIOA_PER = 0xFFFFFFFF;	/* Enables the PIO to control all the pins */
-#endif
-
-	AT91F_AIC_DisableIt (AT91C_BASE_AIC, AT91C_ID_SYS);
-	/* close all peripheral clocks */
-
-#ifndef	DEBUGOUT
-	AT91C_BASE_PMC->PMC_PCDR = 0xFFFFFFFC;
-#endif
-	/* Disable core interrupts and set supervisor mode */
-	__asm__ ("msr CPSR_c, #0xDF"); //* ARM_MODE_SYS(0x1F) | I_BIT(0x80) | F_BIT(0x40)
-	/* Clear all the interrupts */
-	*AT91C_AIC_ICCR = 0xffffffff;
-
-	/* read the AIC_IVR and AIC_FVR */
-	i = *AT91C_AIC_IVR;
-	i = *AT91C_AIC_FVR;
-
-	/* write the end of interrupt control register */
-	*AT91C_AIC_EOICR	= 0;
-
-	return 1;
-}
-
-
-static int AT91F_LoadBoot(void)
-{
-//	volatile unsigned int crc1 = 0, crc2 = 0;
-	volatile unsigned int SizeToDownload = 0x21400;
-	volatile unsigned int AddressToDownload = AT91C_BOOT_ADDR;
-
-#if 0
-	/* Read vector 6 to extract size to load */	
-	if (read_dataflash(AT91C_BOOT_DATAFLASH_ADDR, 32,
-	                   (char *)AddressToDownload) != AT91C_DATAFLASH_OK)
-	{
-		printf("Bad Code Size\n");
-		return IMAGE_BAD_SIZE;
-	}
-	/* calculate the size to download */
-	SizeToDownload = *(int *)(AddressToDownload + AT91C_OFFSET_VECT6);
-#endif
-	
-//	printf("\nLoad UBOOT from dataflash[%x] to SDRAM[%x]\n",
-//	       AT91C_BOOT_DATAFLASH_ADDR, AT91C_BOOT_ADDR);
-	if (read_dataflash(AT91C_BOOT_DATAFLASH_ADDR, SizeToDownload + 8,
-	                   (char *)AddressToDownload) != AT91C_DATAFLASH_OK)
-	{
-		printf("F DF RD\n");
-		return IMAGE_READ_FAILURE;
-	}
-#if 0
-	pAT91->CRC32((const unsigned char *)AT91C_BOOT_ADDR,
-	             (unsigned int)SizeToDownload , (unsigned int *)&crc2);
-	crc1 = (int)(*(char *)(AddressToDownload + SizeToDownload)) +
-	       (int)(*(char *)(AddressToDownload + SizeToDownload + 1) << 8) +
-	       (int)(*(char *)(AddressToDownload + SizeToDownload + 2) << 16) +
-	       (int)(*(char *)(AddressToDownload + SizeToDownload + 3) << 24);
-
-	/* Restore the value of Vector 6 */
-	*(int *)(AddressToDownload + AT91C_OFFSET_VECT6) =
-		*(int *)(AddressToDownload + SizeToDownload + 4);
-	
-	if (crc1 != crc2) {
-		printf("DF CRC bad %x != %x\n",crc1,crc2);
-	 	return	IMAGE_CRC_ERROR;
-	}
-#endif
-	return SUCCESS;
-}
-
-static int AT91F_StartBoot(void)
-{
-	int	sts;
-	if((sts = AT91F_LoadBoot()) != SUCCESS) return sts;
-//	printf("\n");
-//	printf("PLLA[180MHz], MCK[60Mhz] ==> Start UBOOT\n");
-	if (AT91F_ResetRegisters())
-	{
-		printf("Jump");
-		Jump(AT91C_BOOT_ADDR);
-//		LED_blink(0);
-	}
-	return	IMAGE_ERROR;
-}
-
-#if 0
-static void	AT91F_RepeatedStartBoot(void)
-{
-	int	i;
-	for(i = 0; i < CRC_RETRIES; i++) {
-		if(AT91F_StartBoot() != IMAGE_CRC_ERROR){
-//			LED_blink(1);
-			return;
-		}
-	}
-	return;
-}
-#endif
-
-#define TRUE 1
-#define FALSE 0
-#define TRX_MAGIC 0x30524448  /* "HDR0" */
-#define TRX_VERSION 1
-
-struct trx_header {
-	unsigned int magic;
-	unsigned int len;
-	unsigned int crc32;
-	unsigned int flag_version;
-	unsigned int offsets[3];
-};
-
-#define AT91C_MCI_TIMEOUT 1000000
-
-extern AT91S_MciDevice MCI_Device;
-extern void AT91F_MCIDeviceWaitReady(unsigned int);
-extern int AT91F_MCI_ReadBlockSwab(AT91PS_MciDevice, int, unsigned int *, int);
-
-int Program_From_MCI(void)
-{
-  int i;
-  unsigned int Max_Read_DataBlock_Length;
-  int block = 0;
-  int buffer = AT91C_DOWNLOAD_BASE_ADDRESS;
-  int bufpos = AT91C_DOWNLOAD_BASE_ADDRESS;
-  int NbPage = 0;
-  struct trx_header *p;
-
-	p = (struct trx_header *)bufpos;
-
-	Max_Read_DataBlock_Length = MCI_Device.pMCI_DeviceFeatures->Max_Read_DataBlock_Length;
-
-	AT91F_MCIDeviceWaitReady(AT91C_MCI_TIMEOUT);
-
-  AT91F_MCI_ReadBlockSwab(&MCI_Device, block*Max_Read_DataBlock_Length, (unsigned int *)bufpos, Max_Read_DataBlock_Length);
-
-  if (p->magic != TRX_MAGIC) {
-		printf("Inv IMG 0x%08x\n", p->magic);
-		return FALSE;
-		}
-
-	printf("RDSD");
-	AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15 | AT91C_PIO_PC8 | AT91C_PIO_PC14;
-	for (i=0; i<(p->len/512); i++) {
-		AT91F_MCI_ReadBlockSwab(&MCI_Device, block*Max_Read_DataBlock_Length, (unsigned int *)bufpos, Max_Read_DataBlock_Length);
-		block++;
-		bufpos += Max_Read_DataBlock_Length;
-		}
-
-	NbPage = 0;
-	i = dataflash_info[0].Device.pages_number;
-	while(i >>= 1)
-		NbPage++;
-	i = ((p->offsets[1] - p->offsets[0])/ 512) + 1 + (NbPage << 13) + (dataflash_info[0].Device.pages_size << 17);
-	*(int *)(buffer + p->offsets[0] + AT91C_OFFSET_VECT6) = i;
-
-	printf(" WDFB");
-	AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15 | AT91C_PIO_PC14;
-	AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC8;
-	write_dataflash(0xc0000000, buffer + p->offsets[0], p->offsets[1] - p->offsets[0]);
-	printf(" WUB");
-	AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15;
-	AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC8 | AT91C_PIO_PC14;
-	write_dataflash(0xc0008000, buffer + p->offsets[1], p->offsets[2] - p->offsets[1]);
-	printf(" WKRFS");
-	AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC8 | AT91C_PIO_PC15;
-	AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC7 | AT91C_PIO_PC14;
-	write_dataflash(0xc0042000, buffer + p->offsets[2], p->len - p->offsets[2]);
-	AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC8 | AT91C_PIO_PC14;
-	AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC7 | AT91C_PIO_PC15;
-	return TRUE;
-}
-
-//*----------------------------------------------------------------------------
-//* Function Name       : main
-//* Object              : Main function
-//* Input Parameters    : none
-//* Output Parameters   : True
-//*----------------------------------------------------------------------------
-int main(void)
-{
-#ifdef XMODEM
-	AT91PS_Buffer  		pXmBuffer;
-	AT91PS_SvcComm 		pSvcXmodem;
-#endif
-	AT91S_SvcTempo 		svcBootTempo; 	 // Link to a AT91S_Tempo object
-	unsigned int		ix;
-	volatile unsigned int AddressToDownload, SizeToDownload;	
- 	unsigned int DeviceAddress = 0;
-	char command = 0;
-#ifdef XMODEM
-	volatile int i = 0;	
-	unsigned int crc1 = 0, crc2 = 0;
-	volatile int device;
-	int NbPage;
-#endif
-	volatile int Nb_Device = 0;
-	int mci_present = 0;
-
-	pAT91 = AT91C_ROM_BOOT_ADDRESS;
-
-	if (!AT91F_SetPLL())
-	{
-		printf("F SetPLL");
-		while(1);
-	}
-
-	at91_init_uarts();
-
-	/* Tempo Initialisation */
-	pAT91->OpenCtlTempo(&ctlTempo, (void *) &(pAT91->SYSTIMER_DESC));
-	ctlTempo.CtlTempoStart((void *) &(pAT91->SYSTIMER_DESC));
-	
-	// Attach the tempo to a tempo controler
-	ctlTempo.CtlTempoCreate(&ctlTempo, &svcBootTempo);
-//	LED_init();
-//	LED_blink(2);
-
-#ifdef XMODEM
-	/* Xmodem Initialisation */
-	pXmBuffer = pAT91->OpenSBuffer(&sXmBuffer);
-	pSvcXmodem = pAT91->OpenSvcXmodem(&svcXmodem,
-	             (AT91PS_USART)AT91C_BASE_DBGU, &ctlTempo);
-	pAT91->OpenPipe(&xmodemPipe, pSvcXmodem, pXmBuffer);
-#endif
-
-	/* System Timer initialization */
-	AT91F_AIC_ConfigureIt(
-		AT91C_BASE_AIC,                        // AIC base address
-		AT91C_ID_SYS,                          // System peripheral ID
-		AT91C_AIC_PRIOR_HIGHEST,               // Max priority
-		AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, // Level sensitive
-		AT91F_ST_ASM_HANDLER
-	);
-	/* Enable ST interrupt */
-	AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS);
-
-#ifndef PRODTEST
-	/* Start tempo to start Boot in a delay of
-	 * AT91C_DELAY_TO_BOOT sec if no key pressed */
-	svcBootTempo.Start(&svcBootTempo, AT91C_DELAY_TO_BOOT,
-	                   0, AT91F_StartBoot, NULL);
-#endif
-
-	while(1)
-	{
-		while(command == 0)
-		{
-			AddressToDownload = AT91C_DOWNLOAD_BASE_ADDRESS;
-			SizeToDownload = AT91C_DOWNLOAD_MAX_SIZE;
-			DeviceAddress = 0;
-			
-			/* try to detect Dataflash */
-			if (!Nb_Device)
-				Nb_Device = AT91F_DataflashInit();				
-							
-			mci_present = AT91F_DisplayMenu();
-
-#ifdef PRODTEST
-			if (mci_present) {
-				if (Program_From_MCI())
-					AT91F_StartBoot();
-			}
-#endif
-
-			message[0] = 0;
-			AT91F_ReadLine ("Enter: ", message);
-
-#ifndef PRODTEST
-			/* stop tempo ==> stop autoboot */
-			svcBootTempo.Stop(&svcBootTempo);
-#endif
-
-			command = message[0];
-			for(ix = 1; (message[ix] == ' ') && (ix < 12); ix++);	// Skip some whitespace
-				
-			if(!AsciiToHex(&message[ix], &DeviceAddress) )
-				DeviceAddress = 0;			// Illegal DeviceAddress
-				
-			switch(command)
-			{
-#ifdef XMODEM
-				case '1':
-				case '2':
-				case '5':
-					if(command == '1') {
-						DeviceAddress = 0xC0000000;
-//						printf("Download DataflashBoot.bin to [0x%x]\n", DeviceAddress);
-					} else if(command == '2') {
-						DeviceAddress = AT91C_BOOT_DATAFLASH_ADDR;
-//						printf("Download u-boot.bin to [0x%x]\n", DeviceAddress);
-					} else {
-//						printf("Download Dataflash to [0x%x]\n", DeviceAddress);
-					}
-					switch(DeviceAddress & 0xFF000000)
-					{
-						case CFG_DATAFLASH_LOGIC_ADDR_CS0:
-							if (dataflash_info[0].id == 0){
-								printf("No DF");
-								AT91F_WaitKeyPressed();
-								command = 0;
-							}
-
-							device = 0;
-						break;
-					
-						case CFG_DATAFLASH_LOGIC_ADDR_CS3:
-							if (dataflash_info[1].id == 0){
-								printf("No DF");
-								AT91F_WaitKeyPressed();
-								command = 0;
-							}
-							device = 1;
-						break;
-					
-						default:
-							command = 0;
-						break;
-					}
-				break;
-#endif
-
-				case '3':
-					if (mci_present)
-						Program_From_MCI();
-					command = 0;
-					break;
-
-				case '4':
-					AT91F_StartBoot();
-					command = 0;
-				break;
-
-#ifdef MEMDISP
-				case '6':
-					do 
-					{
-						AT91F_MemoryDisplay(DeviceAddress, 256);
-						AT91F_ReadLine (NULL, message);
-						DeviceAddress += 0x100;
-					}
-					while(message[0] == '\0');
-					command = 0;
-				break;
-#endif
-
-				case '7':
-					switch(DeviceAddress & 0xFF000000)
-					{
-						case CFG_DATAFLASH_LOGIC_ADDR_CS0:
-							break;
-						case CFG_DATAFLASH_LOGIC_ADDR_CS3:
-							break;
-						default:
-							command = 0;
-							break;
-					}
-
-					if (command != 0) {
-						AT91F_ReadLine ("RDY ERA\nSure?",
-								message);
-						if(message[0] == 'Y' || message[0] == 'y') {
-							erase_dataflash(DeviceAddress & 0xFF000000);
-//							printf("Erase complete\n\n");
-						}
-//						else
-//							printf("Erase aborted\n");
-					}
-					command = 0;
-
-				break;
-
-				default:
-					command = 0;
-				break;
-			}
-		}
-#ifdef XMODEM
-		for(i = 0; i <= AT91C_DOWNLOAD_MAX_SIZE; i++)
-			*(unsigned char *)(AddressToDownload + i) = 0;
-	
-		xmodemPipe.Read(&xmodemPipe, (char *)AddressToDownload,
-		                SizeToDownload, XmodemProtocol, 0);	
-		while(XmodemComplete !=1);
-		SizeToDownload = (unsigned int)((svcXmodem.pData) -
-		                 (unsigned int)AddressToDownload);
-
-		/* Modification of vector 6 */
-		if ((DeviceAddress == CFG_DATAFLASH_LOGIC_ADDR_CS0)) {
-			// Vector 6 must be compliant to the BootRom description (ref Datasheet)
-	   		NbPage = 0;
-	    	i = dataflash_info[device].Device.pages_number;
-	    	while(i >>= 1)
-	    		NbPage++;
-			i = (SizeToDownload / 512)+1 + (NbPage << 13) +
-			    (dataflash_info[device].Device.pages_size << 17); //+4 to add crc32
-		    SizeToDownload = 512 * (i &0xFF);
-		}	
-		else
-		{
-			/* Save the contents of vector 6 ==> will be restored 
-			 * at boot time (AT91F_StartBoot) */
-			*(int *)(AddressToDownload + SizeToDownload + 4) =
-				*(int *)(AddressToDownload + AT91C_OFFSET_VECT6);
-			/* Modify Vector 6 to contain the size of the
-			 * file to copy (Dataflash -> SDRAM)*/
-			i = SizeToDownload;	
-		}		
-
-		*(int *)(AddressToDownload + AT91C_OFFSET_VECT6) = i;
-//		printf("\nModification of Arm Vector 6 :%x\n", i);
-			    
-//		printf("\nWrite %d bytes in DataFlash [0x%x]\n",SizeToDownload, DeviceAddress);
-		crc1 = 0;
-		pAT91->CRC32((const unsigned char *)AddressToDownload, SizeToDownload , &crc1);
-
-		/* Add the crc32 at the end of the code */
-		*(char *)(AddressToDownload + SizeToDownload)     = (char)(crc1 & 0x000000FF);
-		*(char *)(AddressToDownload + SizeToDownload + 1) = (char)((crc1 & 0x0000FF00) >> 8);
-		*(char *)(AddressToDownload + SizeToDownload + 2) = (char)((crc1 & 0x00FF0000) >> 16);
-		*(char *)(AddressToDownload + SizeToDownload + 3) = (char)((crc1 & 0xFF000000) >> 24);
-
-		/* write dataflash */
-		write_dataflash (DeviceAddress, AddressToDownload, (SizeToDownload + 8));
-
-		/* clear the buffer before read */
-		for(i=0; i <= SizeToDownload; i++)
-			*(unsigned char *)(AddressToDownload + i) = 0;
-					
-		/* Read dataflash to check the validity of the data */
-		read_dataflash (DeviceAddress, (SizeToDownload + 4), (char *)(AddressToDownload));
-
-		printf("VFY: ");	
-		crc2 = 0;
-				
-		pAT91->CRC32((const unsigned char *)AddressToDownload, SizeToDownload , &crc2);
- 		crc1 = (int)(*(char *)(AddressToDownload + SizeToDownload))          +
-			   (int)(*(char *)(AddressToDownload + SizeToDownload + 1) << 8) +
-			   (int)(*(char *)(AddressToDownload + SizeToDownload + 2) << 16) +
-			   (int)(*(char *)(AddressToDownload + SizeToDownload + 3) << 24);
-
-		if (crc1 != crc2)
-		 	printf("ERR");
-		else
-		 	printf("OK");
-		 	
- 		command = 0;
- 		XmodemComplete = 0;
-		AT91F_WaitKeyPressed();
-#endif
- 	}
-}
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/main.h b/target/linux/at91-2.6/image/dfboot/src/main.h
deleted file mode 100644
index a8cd325..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/main.h
+++ /dev/null
@@ -1,43 +0,0 @@
-//*----------------------------------------------------------------------------
-//*      ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : main.h
-//* Object              :
-//*
-//* 1.0 27/03/03 HIi    : Creation
-//* 1.01 03/05/04 HIi   : AT9C_VERSION incremented to 1.01
-//* 1.02 15/06/04 HIi   : AT9C_VERSION incremented to 1.02 ==> 
-//*                       Add crc32 to verify dataflash download
-//* 1.03 18/04/05 MLC   : AT91C_VERSION incremented to 1.03g
-//*			  Repeat boot on CRC Failure
-//*			  Change Page Size to 1056
-//*			  Reduce SPI speed to 4 Mbit
-//*			  Change U-Boot boot address to a 1056 byte page boundary
-//* 1.04 30/04/05 USA	: AT91C_VERSION incremented to 1.04
-//* 1.05 07/08/06 USA	: AT91C_VERSION incremented to 1.05
-//*			  Will only support loading Dataflashboot.bin and U-Boot
-//*----------------------------------------------------------------------------
-
-#ifndef main_h
-#define main_h
-
-#include    "embedded_services.h"
-
-#define AT91C_DOWNLOAD_BASE_ADDRESS     0x20000000
-#define AT91C_DOWNLOAD_MAX_SIZE         0x00040000
-
-#define AT91C_OFFSET_VECT6              0x14        //* Offset for ARM vector 6
-
-#define AT91C_VERSION   "VER 1.05"
-
-
-// Global variables and functions definition
-extern unsigned int GetTickCount(void);
-#endif
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/mci_device.c b/target/linux/at91-2.6/image/dfboot/src/mci_device.c
deleted file mode 100644
index cce74a3..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/mci_device.c
+++ /dev/null
@@ -1,743 +0,0 @@
-//*----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : mci_device.c
-//* Object              : TEST DataFlash Functions
-//* Creation            : FB   26/11/2002
-//*
-//*----------------------------------------------------------------------------
-
-#include <AT91C_MCI_Device.h>
-#include "stdio.h"
-
-#define AT91C_MCI_TIMEOUT			1000000   /* For AT91F_MCIDeviceWaitReady */
-#define BUFFER_SIZE_MCI_DEVICE		512
-#define MASTER_CLOCK				60000000
-#define FALSE						0
-#define TRUE						1
-
-//* External Functions
-extern void AT91F_ASM_MCI_Handler(void);
-//* Global Variables
-AT91S_MciDeviceFeatures			MCI_Device_Features;
-AT91S_MciDeviceDesc				MCI_Device_Desc;
-AT91S_MciDevice					MCI_Device;
-
-#undef ENABLE_WRITE
-#undef MMC
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_SendCommand
-//* \brief Generic function to send a command to the MMC or SDCard
-//*----------------------------------------------------------------------------
-int AT91F_MCI_SendCommand (
-	AT91PS_MciDevice pMCI_Device,
-	unsigned int Cmd,
-	unsigned int Arg)
-{
-	unsigned int	error,status;
-	//unsigned int	tick=0;
-
-    // Send the command
-    AT91C_BASE_MCI->MCI_ARGR = Arg;
-    AT91C_BASE_MCI->MCI_CMDR = Cmd;
-
-	// wait for CMDRDY Status flag to read the response
-	do
-	{
-		status = AT91C_BASE_MCI->MCI_SR;
-		//tick++;
-	}
-	while( !(status & AT91C_MCI_CMDRDY) );//&& (tick<100) );
-
-    // Test error  ==> if crc error and response R3 ==> don't check error
-    error = (AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR;
-	if(error != 0 )
-	{
-		// if the command is SEND_OP_COND the CRC error flag is always present (cf : R3 response)
-		if ( (Cmd != AT91C_SDCARD_APP_OP_COND_CMD) && (Cmd != AT91C_MMC_SEND_OP_COND_CMD) )
-			return ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR);
-		else
-		{
-			if (error != AT91C_MCI_RCRCE)
-				return ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR);
-		}
-	}
-    return AT91C_CMD_SEND_OK;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_SDCard_SendAppCommand
-//* \brief Specific function to send a specific command to the SDCard
-//*----------------------------------------------------------------------------
-int AT91F_MCI_SDCard_SendAppCommand (
-	AT91PS_MciDevice pMCI_Device,
-	unsigned int Cmd_App,
-	unsigned int Arg	)
-{
-	unsigned int status;
-	//unsigned int	tick=0;
-
-	// Send the CMD55 for application specific command
-    AT91C_BASE_MCI->MCI_ARGR = (pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address << 16 );
-    AT91C_BASE_MCI->MCI_CMDR = AT91C_APP_CMD;
-
-	// wait for CMDRDY Status flag to read the response
-	do
-	{
-		status = AT91C_BASE_MCI->MCI_SR;
-		//tick++;
-	}
-	while( !(status & AT91C_MCI_CMDRDY) );//&& (tick<100) );	
-
-    // if an error occurs
-    if (((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR) != 0 )
-		return ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR);
-
-    // check if it is a specific command and then send the command
-	if ( (Cmd_App && AT91C_SDCARD_APP_ALL_CMD) == 0)
-		return AT91C_CMD_SEND_ERROR;
-
-   return( AT91F_MCI_SendCommand(pMCI_Device,Cmd_App,Arg) );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_GetStatus
-//* \brief Addressed card sends its status register
-//*----------------------------------------------------------------------------
-int AT91F_MCI_GetStatus(AT91PS_MciDevice pMCI_Device,unsigned int relative_card_address)
-{
-	if (AT91F_MCI_SendCommand(pMCI_Device,
-								AT91C_SEND_STATUS_CMD,
-								relative_card_address <<16) == AT91C_CMD_SEND_OK)
-    	return (AT91C_BASE_MCI->MCI_RSPR[0]);
-
-    return AT91C_CMD_SEND_ERROR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_Device_Handler
-//* \brief MCI C interrupt handler
-//*----------------------------------------------------------------------------
-void AT91F_MCI_Device_Handler(
-	AT91PS_MciDevice pMCI_Device,
-	unsigned int status)
-{
-	// If End of Tx Buffer Empty interrupt occurred
-	if ( status & AT91C_MCI_TXBUFE )
-    {
-		AT91C_BASE_MCI->MCI_IDR = AT91C_MCI_TXBUFE;
- 		AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTDIS;
-        	
-		pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_IDLE;
-	}	// End of if AT91C_MCI_TXBUFF		
-	
-    // If End of Rx Buffer Full interrupt occurred
-    if ( status & AT91C_MCI_RXBUFF )
-    {        
-       	AT91C_BASE_MCI->MCI_IDR = AT91C_MCI_RXBUFF;
- 		AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTDIS;
-	
-		pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_IDLE;
-	}	// End of if AT91C_MCI_RXBUFF
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_Handler
-//* \brief MCI Handler
-//*----------------------------------------------------------------------------
-void AT91F_MCI_Handler(void)
-{
-	int status;
-
-	status = ( AT91C_BASE_MCI->MCI_SR & AT91C_BASE_MCI->MCI_IMR );
-
-	AT91F_MCI_Device_Handler(&MCI_Device,status);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_ReadBlock
-//* \brief Read an ENTIRE block or PARTIAL block
-//*----------------------------------------------------------------------------
-int AT91F_MCI_ReadBlock(
-	AT91PS_MciDevice pMCI_Device,
-	int src,
-	unsigned int *dataBuffer,
-	int sizeToRead )
-{
-    ////////////////////////////////////////////////////////////////////////////////////////////
-    if(pMCI_Device->pMCI_DeviceDesc->state != AT91C_MCI_IDLE)
-    	return AT91C_READ_ERROR;
-    
-    if( (AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address) & AT91C_SR_READY_FOR_DATA) != AT91C_SR_READY_FOR_DATA)
-    	return AT91C_READ_ERROR;
-    	
-    if ( (src + sizeToRead) > pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity )
-		return AT91C_READ_ERROR;
-
-    // If source does not fit a begin of a block
-	if ( (src % pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) != 0 )
-		return AT91C_READ_ERROR;
-   
-     // Test if the MMC supports Partial Read Block
-     // ALWAYS SUPPORTED IN SD Memory Card
-     if( (sizeToRead < pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) 
-    	&& (pMCI_Device->pMCI_DeviceFeatures->Read_Partial == 0x00) )
-   		return AT91C_READ_ERROR;
-   		
-    if( sizeToRead > pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length)
-   		return AT91C_READ_ERROR;
-    ////////////////////////////////////////////////////////////////////////////////////////////
-      
-    // Init Mode Register
-	AT91C_BASE_MCI->MCI_MR |= ((pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length << 16) | AT91C_MCI_PDCMODE);
-	 
-    if (sizeToRead %4)
-		sizeToRead = (sizeToRead /4)+1;
-	else
-		sizeToRead = sizeToRead/4;
-
-	AT91C_BASE_PDC_MCI->PDC_PTCR = (AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS);
-    AT91C_BASE_PDC_MCI->PDC_RPR  = (unsigned int)dataBuffer;
-    AT91C_BASE_PDC_MCI->PDC_RCR  = sizeToRead;
-
-	// Send the Read single block command
-    if ( AT91F_MCI_SendCommand(pMCI_Device, AT91C_READ_SINGLE_BLOCK_CMD, src) != AT91C_CMD_SEND_OK )
-    	return AT91C_READ_ERROR;
-
-	pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_RX_SINGLE_BLOCK;
-
-	// Enable AT91C_MCI_RXBUFF Interrupt
-    AT91C_BASE_MCI->MCI_IER = AT91C_MCI_RXBUFF;
-
-	// (PDC) Receiver Transfer Enable
-	AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTEN;
-	
-	return AT91C_READ_OK;
-}
-
-
-#ifdef ENABLE_WRITE
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_WriteBlock
-//* \brief  Write an ENTIRE block but not always PARTIAL block !!!
-//*----------------------------------------------------------------------------
-int AT91F_MCI_WriteBlock(
-	AT91PS_MciDevice pMCI_Device,
-	int dest,
-	unsigned int *dataBuffer,
-	int sizeToWrite )
-{
-    ////////////////////////////////////////////////////////////////////////////////////////////
-	if( pMCI_Device->pMCI_DeviceDesc->state != AT91C_MCI_IDLE)
-    	return AT91C_WRITE_ERROR;
-    
-    if( (AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address) & AT91C_SR_READY_FOR_DATA) != AT91C_SR_READY_FOR_DATA)
-    	return AT91C_WRITE_ERROR;
-    	
-    if ( (dest + sizeToWrite) > pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity )
-		return AT91C_WRITE_ERROR;
-
-    // If source does not fit a begin of a block
-	if ( (dest % pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) != 0 )
-		return AT91C_WRITE_ERROR;
-   
-    // Test if the MMC supports Partial Write Block 
-    if( (sizeToWrite < pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length) 
-    	&& (pMCI_Device->pMCI_DeviceFeatures->Write_Partial == 0x00) )
-   		return AT91C_WRITE_ERROR;
-   		
-   	if( sizeToWrite > pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length )
-   		return AT91C_WRITE_ERROR;
-    ////////////////////////////////////////////////////////////////////////////////////////////
-  
-    // Init Mode Register
-	AT91C_BASE_MCI->MCI_MR |= ((pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length << 16) | AT91C_MCI_PDCMODE);
-	
-	if (sizeToWrite %4)
-		sizeToWrite = (sizeToWrite /4)+1;
-	else
-		sizeToWrite = sizeToWrite/4;
-
-	// Init PDC for write sequence
-    AT91C_BASE_PDC_MCI->PDC_PTCR = (AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS);
-    AT91C_BASE_PDC_MCI->PDC_TPR = (unsigned int) dataBuffer;
-    AT91C_BASE_PDC_MCI->PDC_TCR = sizeToWrite;
-
-	// Send the write single block command
-    if ( AT91F_MCI_SendCommand(pMCI_Device, AT91C_WRITE_BLOCK_CMD, dest) != AT91C_CMD_SEND_OK)
-    	return AT91C_WRITE_ERROR;
-
-	pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_TX_SINGLE_BLOCK;
-
-	// Enable AT91C_MCI_TXBUFE Interrupt
-    AT91C_BASE_MCI->MCI_IER = AT91C_MCI_TXBUFE;
-  
-  	// Enables TX for PDC transfert requests
-    AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTEN;
-  
-	return AT91C_WRITE_OK;
-}
-#endif
-
-#ifdef MMC
-//*------------------------------------------------------------------------------------------------------------
-//* \fn    AT91F_MCI_MMC_SelectCard
-//* \brief Toggles a card between the Stand_by and Transfer states or between Programming and Disconnect states
-//*------------------------------------------------------------------------------------------------------------
-int AT91F_MCI_MMC_SelectCard(AT91PS_MciDevice pMCI_Device, unsigned int relative_card_address)
-{
-    int status;
-	
-	//* Check if the MMC card chosen is already the selected one
-	status = AT91F_MCI_GetStatus(pMCI_Device,relative_card_address);
-
-	if (status < 0)
-		return AT91C_CARD_SELECTED_ERROR;
-
-	if ((status & AT91C_SR_CARD_SELECTED) == AT91C_SR_CARD_SELECTED)
-		return AT91C_CARD_SELECTED_OK;
-
-	//* Search for the MMC Card to be selected, status = the Corresponding Device Number
-	status = 0;
-	while( (pMCI_Device->pMCI_DeviceFeatures[status].Relative_Card_Address != relative_card_address)
-		   && (status < AT91C_MAX_MCI_CARDS) )
-		status++;
-
-	if (status > AT91C_MAX_MCI_CARDS)
-    	return AT91C_CARD_SELECTED_ERROR;
-
-    if (AT91F_MCI_SendCommand( pMCI_Device,
-    								   AT91C_SEL_DESEL_CARD_CMD,
-    								   pMCI_Device->pMCI_DeviceFeatures[status].Relative_Card_Address << 16) == AT91C_CMD_SEND_OK)
-    	return AT91C_CARD_SELECTED_OK;
-    return AT91C_CARD_SELECTED_ERROR;
-}
-#endif
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_GetCSD
-//* \brief Asks to the specified card to send its CSD
-//*----------------------------------------------------------------------------
-int AT91F_MCI_GetCSD (AT91PS_MciDevice pMCI_Device, unsigned int relative_card_address , unsigned int * response)
-{
- 	
- 	if(AT91F_MCI_SendCommand(pMCI_Device,
-								  AT91C_SEND_CSD_CMD,
-								  (relative_card_address << 16)) != AT91C_CMD_SEND_OK)
-		return AT91C_CMD_SEND_ERROR;
-	
-    response[0] = AT91C_BASE_MCI->MCI_RSPR[0];
-   	response[1] = AT91C_BASE_MCI->MCI_RSPR[1];
-    response[2] = AT91C_BASE_MCI->MCI_RSPR[2];
-    response[3] = AT91C_BASE_MCI->MCI_RSPR[3];
-    
-    return AT91C_CMD_SEND_OK;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_SetBlocklength
-//* \brief Select a block length for all following block commands (R/W)
-//*----------------------------------------------------------------------------
-int AT91F_MCI_SetBlocklength(AT91PS_MciDevice pMCI_Device,unsigned int length)
-{
-    return( AT91F_MCI_SendCommand(pMCI_Device, AT91C_SET_BLOCKLEN_CMD, length) );
-}
-
-#ifdef MMC
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_MMC_GetAllOCR
-//* \brief Asks to all cards to send their operations conditions
-//*----------------------------------------------------------------------------
-int AT91F_MCI_MMC_GetAllOCR (AT91PS_MciDevice pMCI_Device)
-{
-	unsigned int	response =0x0;
- 	
- 	while(1)
-    {
-    	response = AT91F_MCI_SendCommand(pMCI_Device,
-  										AT91C_MMC_SEND_OP_COND_CMD,
-  										AT91C_MMC_HOST_VOLTAGE_RANGE);
-		if (response != AT91C_CMD_SEND_OK)
-			return AT91C_INIT_ERROR;
-		
-		response = AT91C_BASE_MCI->MCI_RSPR[0];
-		
-		if ( (response & AT91C_CARD_POWER_UP_BUSY) == AT91C_CARD_POWER_UP_BUSY)
-			return(response);	
-	}
-}
-#endif
-
-#ifdef MMC
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_MMC_GetAllCID
-//* \brief Asks to the MMC on the chosen slot to send its CID
-//*----------------------------------------------------------------------------
-int AT91F_MCI_MMC_GetAllCID (AT91PS_MciDevice pMCI_Device, unsigned int *response)
-{
-	int Nb_Cards_Found=-1;
-  
-	while(1)
-	{
-	 	if(AT91F_MCI_SendCommand(pMCI_Device,
-								AT91C_MMC_ALL_SEND_CID_CMD,
-								AT91C_NO_ARGUMENT) != AT91C_CMD_SEND_OK)
-			return Nb_Cards_Found;
-		else
-		{		
-			Nb_Cards_Found = 0;
-			//* Assignation of the relative address to the MMC CARD
-			pMCI_Device->pMCI_DeviceFeatures[Nb_Cards_Found].Relative_Card_Address = Nb_Cards_Found + AT91C_FIRST_RCA;
-			//* Set the insert flag
-			pMCI_Device->pMCI_DeviceFeatures[Nb_Cards_Found].Card_Inserted = AT91C_MMC_CARD_INSERTED;
-	
-			if (AT91F_MCI_SendCommand(pMCI_Device,
-									 AT91C_MMC_SET_RELATIVE_ADDR_CMD,
-									 (Nb_Cards_Found + AT91C_FIRST_RCA) << 16) != AT91C_CMD_SEND_OK)
-				return AT91C_CMD_SEND_ERROR;
-				 
-			//* If no error during assignation address ==> Increment Nb_cards_Found
-			Nb_Cards_Found++ ;
-		}
-	}
-}
-#endif
-#ifdef MMC
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_MMC_Init
-//* \brief Return the MMC initialisation status
-//*----------------------------------------------------------------------------
-int AT91F_MCI_MMC_Init (AT91PS_MciDevice pMCI_Device)
-{
-    unsigned int	tab_response[4];
-	unsigned int	mult,blocknr;
-	unsigned int 	i,Nb_Cards_Found=0;
-
-	//* Resets all MMC Cards in Idle state
-	AT91F_MCI_SendCommand(pMCI_Device, AT91C_MMC_GO_IDLE_STATE_CMD, AT91C_NO_ARGUMENT);
-
-    if(AT91F_MCI_MMC_GetAllOCR(pMCI_Device) == AT91C_INIT_ERROR)
-    	return AT91C_INIT_ERROR;
-
-	Nb_Cards_Found = AT91F_MCI_MMC_GetAllCID(pMCI_Device,tab_response);
-	if (Nb_Cards_Found != AT91C_CMD_SEND_ERROR)
-	{
-	    //* Set the Mode Register
-    	AT91C_BASE_MCI->MCI_MR = AT91C_MCI_MR_PDCMODE;
-
-		for(i = 0; i < Nb_Cards_Found; i++)
-		{
-			if (AT91F_MCI_GetCSD(pMCI_Device,
-									  pMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address,
-									  tab_response) != AT91C_CMD_SEND_OK)
-				pMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address = 0;					  
-			else
-			{
-				pMCI_Device->pMCI_DeviceFeatures[i].Max_Read_DataBlock_Length = 1 << ((tab_response[1] >> AT91C_CSD_RD_B_LEN_S) & AT91C_CSD_RD_B_LEN_M );
-	 			pMCI_Device->pMCI_DeviceFeatures[i].Max_Write_DataBlock_Length =	1 << ((tab_response[3] >> AT91C_CSD_WBLEN_S) & AT91C_CSD_WBLEN_M );
-				pMCI_Device->pMCI_DeviceFeatures[i].Sector_Size = 1 + ((tab_response[2] >> AT91C_CSD_v22_SECT_SIZE_S) & AT91C_CSD_v22_SECT_SIZE_M );
-		  		pMCI_Device->pMCI_DeviceFeatures[i].Read_Partial = (tab_response[1] >> AT91C_CSD_RD_B_PAR_S) & AT91C_CSD_RD_B_PAR_M;
-				pMCI_Device->pMCI_DeviceFeatures[i].Write_Partial = (tab_response[3] >> AT91C_CSD_WBLOCK_P_S) & AT91C_CSD_WBLOCK_P_M;
-				
-				// None in MMC specification version 2.2
-				pMCI_Device->pMCI_DeviceFeatures[i].Erase_Block_Enable = 0;
-				
-				pMCI_Device->pMCI_DeviceFeatures[i].Read_Block_Misalignment = (tab_response[1] >> AT91C_CSD_RD_B_MIS_S) & AT91C_CSD_RD_B_MIS_M;
-				pMCI_Device->pMCI_DeviceFeatures[i].Write_Block_Misalignment = (tab_response[1] >> AT91C_CSD_WR_B_MIS_S) & AT91C_CSD_WR_B_MIS_M;
-
-				//// Compute Memory Capacity
-				// compute MULT
-				mult = 1 << ( ((tab_response[2] >> AT91C_CSD_C_SIZE_M_S) & AT91C_CSD_C_SIZE_M_M) + 2 );
-				// compute MSB of C_SIZE
-				blocknr = ((tab_response[1] >> AT91C_CSD_CSIZE_H_S) & AT91C_CSD_CSIZE_H_M) << 2;
-				// compute MULT * (LSB of C-SIZE + MSB already computed + 1) = BLOCKNR
-				blocknr = mult * ( ( blocknr + ( (tab_response[2] >> AT91C_CSD_CSIZE_L_S) & AT91C_CSD_CSIZE_L_M) ) + 1 );
-
-				pMCI_Device->pMCI_DeviceFeatures[i].Memory_Capacity =  pMCI_Device->pMCI_DeviceFeatures[i].Max_Read_DataBlock_Length * blocknr;
-		  		//// End of Compute Memory Capacity
-		  		
-			}	// end of else			  
-		}	// end of for
-		
-		return AT91C_INIT_OK;
-	}	// end of if
-
-    return AT91C_INIT_ERROR;
-}
-#endif
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_SDCard_GetOCR
-//* \brief Asks to all cards to send their operations conditions
-//*----------------------------------------------------------------------------
-int AT91F_MCI_SDCard_GetOCR (AT91PS_MciDevice pMCI_Device)
-{
-	unsigned int	response =0x0;
-
-	// The RCA to be used for CMD55 in Idle state shall be the card's default RCA=0x0000.
-	pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address = 0x0;
- 	
- 	while( (response & AT91C_CARD_POWER_UP_BUSY) != AT91C_CARD_POWER_UP_BUSY )
-    {
-    	response = AT91F_MCI_SDCard_SendAppCommand(pMCI_Device,
-  										AT91C_SDCARD_APP_OP_COND_CMD,
-  										AT91C_MMC_HOST_VOLTAGE_RANGE);
-		if (response != AT91C_CMD_SEND_OK)
-			return AT91C_INIT_ERROR;
-		
-		response = AT91C_BASE_MCI->MCI_RSPR[0];
-	}
-	
-	return(AT91C_BASE_MCI->MCI_RSPR[0]);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_SDCard_GetCID
-//* \brief Asks to the SDCard on the chosen slot to send its CID
-//*----------------------------------------------------------------------------
-int AT91F_MCI_SDCard_GetCID (AT91PS_MciDevice pMCI_Device, unsigned int *response)
-{
- 	if(AT91F_MCI_SendCommand(pMCI_Device,
-							AT91C_ALL_SEND_CID_CMD,
-							AT91C_NO_ARGUMENT) != AT91C_CMD_SEND_OK)
-		return AT91C_CMD_SEND_ERROR;
-	
-    response[0] = AT91C_BASE_MCI->MCI_RSPR[0];
-   	response[1] = AT91C_BASE_MCI->MCI_RSPR[1];
-    response[2] = AT91C_BASE_MCI->MCI_RSPR[2];
-    response[3] = AT91C_BASE_MCI->MCI_RSPR[3];
-    
-    return AT91C_CMD_SEND_OK;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_SDCard_SetBusWidth
-//* \brief  Set bus width for SDCard
-//*----------------------------------------------------------------------------
-int AT91F_MCI_SDCard_SetBusWidth(AT91PS_MciDevice pMCI_Device)
-{
-	volatile int	ret_value;
-	char			bus_width;
-
-	do
-	{
-		ret_value =AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address);
-	}
-	while((ret_value > 0) && ((ret_value & AT91C_SR_READY_FOR_DATA) == 0));
-
-	// Select Card
-    AT91F_MCI_SendCommand(pMCI_Device,
-    						AT91C_SEL_DESEL_CARD_CMD,
-    						(pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address)<<16);
-
-	// Set bus width for Sdcard
-	if(pMCI_Device->pMCI_DeviceDesc->SDCard_bus_width == AT91C_MCI_SCDBUS)
-		 	bus_width = AT91C_BUS_WIDTH_4BITS;
-	else	bus_width = AT91C_BUS_WIDTH_1BIT;
-
-	if (AT91F_MCI_SDCard_SendAppCommand(pMCI_Device,AT91C_SDCARD_SET_BUS_WIDTH_CMD,bus_width) != AT91C_CMD_SEND_OK)
-		return AT91C_CMD_SEND_ERROR;
-
-	return AT91C_CMD_SEND_OK;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_SDCard_Init
-//* \brief Return the SDCard initialisation status
-//*----------------------------------------------------------------------------
-int AT91F_MCI_SDCard_Init (AT91PS_MciDevice pMCI_Device)
-{
-    unsigned int	tab_response[4];
-	unsigned int	mult,blocknr;
-
-	AT91F_MCI_SendCommand(pMCI_Device, AT91C_GO_IDLE_STATE_CMD, AT91C_NO_ARGUMENT);
-
-    if(AT91F_MCI_SDCard_GetOCR(pMCI_Device) == AT91C_INIT_ERROR)
-    	return AT91C_INIT_ERROR;
-
-	if (AT91F_MCI_SDCard_GetCID(pMCI_Device,tab_response) == AT91C_CMD_SEND_OK)
-	{
-	    pMCI_Device->pMCI_DeviceFeatures->Card_Inserted = AT91C_SD_CARD_INSERTED;
-
-	    if (AT91F_MCI_SendCommand(pMCI_Device, AT91C_SET_RELATIVE_ADDR_CMD, 0) == AT91C_CMD_SEND_OK)
-		{
-			pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address = (AT91C_BASE_MCI->MCI_RSPR[0] >> 16);
-			if (AT91F_MCI_GetCSD(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address,tab_response) == AT91C_CMD_SEND_OK)
-			{
-		  		pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length = 1 << ((tab_response[1] >> AT91C_CSD_RD_B_LEN_S) & AT91C_CSD_RD_B_LEN_M );
-	 			pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length =	1 << ((tab_response[3] >> AT91C_CSD_WBLEN_S) & AT91C_CSD_WBLEN_M );
-				pMCI_Device->pMCI_DeviceFeatures->Sector_Size = 1 + ((tab_response[2] >> AT91C_CSD_v21_SECT_SIZE_S) & AT91C_CSD_v21_SECT_SIZE_M );
-		  		pMCI_Device->pMCI_DeviceFeatures->Read_Partial = (tab_response[1] >> AT91C_CSD_RD_B_PAR_S) & AT91C_CSD_RD_B_PAR_M;
-				pMCI_Device->pMCI_DeviceFeatures->Write_Partial = (tab_response[3] >> AT91C_CSD_WBLOCK_P_S) & AT91C_CSD_WBLOCK_P_M;
-				pMCI_Device->pMCI_DeviceFeatures->Erase_Block_Enable = (tab_response[3] >> AT91C_CSD_v21_ER_BLEN_EN_S) & AT91C_CSD_v21_ER_BLEN_EN_M;
-				pMCI_Device->pMCI_DeviceFeatures->Read_Block_Misalignment = (tab_response[1] >> AT91C_CSD_RD_B_MIS_S) & AT91C_CSD_RD_B_MIS_M;
-				pMCI_Device->pMCI_DeviceFeatures->Write_Block_Misalignment = (tab_response[1] >> AT91C_CSD_WR_B_MIS_S) & AT91C_CSD_WR_B_MIS_M;
-
-				//// Compute Memory Capacity
-					// compute MULT
-					mult = 1 << ( ((tab_response[2] >> AT91C_CSD_C_SIZE_M_S) & AT91C_CSD_C_SIZE_M_M) + 2 );
-					// compute MSB of C_SIZE
-					blocknr = ((tab_response[1] >> AT91C_CSD_CSIZE_H_S) & AT91C_CSD_CSIZE_H_M) << 2;
-					// compute MULT * (LSB of C-SIZE + MSB already computed + 1) = BLOCKNR
-					blocknr = mult * ( ( blocknr + ( (tab_response[2] >> AT91C_CSD_CSIZE_L_S) & AT91C_CSD_CSIZE_L_M) ) + 1 );
-
-					pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity =  pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length * blocknr;
-			  	//// End of Compute Memory Capacity
-					printf("SD-Card: %d Bytes\n\r", pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity);
-
-		  		if( AT91F_MCI_SDCard_SetBusWidth(pMCI_Device) == AT91C_CMD_SEND_OK )
-				{	
-					 if (AT91F_MCI_SetBlocklength(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) == AT91C_CMD_SEND_OK)
-					return AT91C_INIT_OK;
-				}
-			}
-		}
-	}
-    return AT91C_INIT_ERROR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CfgDevice
-//* \brief This function is used to initialise MMC or SDCard Features
-//*----------------------------------------------------------------------------
-void AT91F_CfgDevice(void)
-{
-	// Init Device Structure
-
-	MCI_Device_Features.Relative_Card_Address 		= 0;
-	MCI_Device_Features.Card_Inserted 				= AT91C_CARD_REMOVED;
-	MCI_Device_Features.Max_Read_DataBlock_Length	= 0;
-	MCI_Device_Features.Max_Write_DataBlock_Length 	= 0;
-	MCI_Device_Features.Read_Partial 				= 0;
-	MCI_Device_Features.Write_Partial 				= 0;
-	MCI_Device_Features.Erase_Block_Enable 			= 0;
-	MCI_Device_Features.Sector_Size 				= 0;
-	MCI_Device_Features.Memory_Capacity 			= 0;
-	
-	MCI_Device_Desc.state							= AT91C_MCI_IDLE;
-	MCI_Device_Desc.SDCard_bus_width				= AT91C_MCI_SCDBUS;
-	
-	// Init AT91S_DataFlash Global Structure, by default AT45DB choosen !!!
-	MCI_Device.pMCI_DeviceDesc 		= &MCI_Device_Desc;
-	MCI_Device.pMCI_DeviceFeatures 	= &MCI_Device_Features;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCI_Init
-//* \brief Initialsise Card
-//*----------------------------------------------------------------------------
-int AT91F_MCI_Init(void)
-{
-
-///////////////////////////////////////////////////////////////////////////////////////////
-//  MCI Init : common to MMC and SDCard
-///////////////////////////////////////////////////////////////////////////////////////////
-
-    // Set up PIO SDC_TYPE to switch on MMC/SDCard and not DataFlash Card
-	AT91F_PIO_CfgOutput(AT91C_BASE_PIOB,AT91C_PIO_PB7);
-	AT91F_PIO_SetOutput(AT91C_BASE_PIOB,AT91C_PIO_PB7);
-	
-	// Init MCI for MMC and SDCard interface
-	AT91F_MCI_CfgPIO();	
-	AT91F_MCI_CfgPMC();
-	AT91F_PDC_Open(AT91C_BASE_PDC_MCI);
-
-    // Disable all the interrupts
-    AT91C_BASE_MCI->MCI_IDR = 0xFFFFFFFF;
-
-	// Init MCI Device Structures
-	AT91F_CfgDevice();
-
-	// Configure MCI interrupt 
-	AT91F_AIC_ConfigureIt(AT91C_BASE_AIC,
-						 AT91C_ID_MCI,
-						 AT91C_AIC_PRIOR_HIGHEST,
-						 AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE,
-						 AT91F_ASM_MCI_Handler);
-
-	// Enable MCI interrupt
-	AT91F_AIC_EnableIt(AT91C_BASE_AIC,AT91C_ID_MCI);
-
-	// Enable Receiver
-	AT91F_US_EnableRx((AT91PS_USART) AT91C_BASE_DBGU);
-
-	AT91F_MCI_Configure(AT91C_BASE_MCI,
-						AT91C_MCI_DTOR_1MEGA_CYCLES,
-						AT91C_MCI_MR_PDCMODE,			// 15MHz for MCK = 60MHz (CLKDIV = 1)
-						AT91C_MCI_SDCARD_4BITS_SLOTA);
-	
-	if(AT91F_MCI_SDCard_Init(&MCI_Device) != AT91C_INIT_OK)
-		return FALSE;
-	else
-		return TRUE;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MCIDeviceWaitReady
-//* \brief Wait for MCI Device ready
-//*----------------------------------------------------------------------------
-void AT91F_MCIDeviceWaitReady(unsigned int timeout)
-{
-	volatile int status;
-	
-	do
-	{
-		status = AT91C_BASE_MCI->MCI_SR;
-		timeout--;
-	}
-	while( !(status & AT91C_MCI_NOTBUSY)  && (timeout>0) );	
-}
-
-unsigned int swab32(unsigned int data)
-{
-	unsigned int res = 0;
-
-	res = (data & 0x000000ff) << 24 |
-				(data & 0x0000ff00) << 8  |
-				(data & 0x00ff0000) >> 8  |
-				(data & 0xff000000) >> 24;
-
-	return res;
-}
-
-//*--------------------------------------------------------------------
-//* \fn    AT91F_MCI_ReadBlockSwab
-//* \brief Read Block and swap byte order
-//*--------------------------------------------------------------------
-int AT91F_MCI_ReadBlockSwab(
-	AT91PS_MciDevice pMCI_Device,
-	int src,
-	unsigned int *databuffer,
-	int sizeToRead)
-{
-	int i;
-	unsigned char *buf = (unsigned char *)databuffer;
-
-	//* Read Block 1
-	for(i=0;i<BUFFER_SIZE_MCI_DEVICE;i++)
-		*buf++ = 0x00;	
-	AT91F_MCI_ReadBlock(&MCI_Device,src,databuffer,sizeToRead);
-
-	//* Wait end of Read
-	AT91F_MCIDeviceWaitReady(AT91C_MCI_TIMEOUT);
-
-	{
-		int index;
-		unsigned int *uiBuffer = databuffer;
-
-		for(index = 0; index < 512/4; index++)
-			uiBuffer[index] = swab32(uiBuffer[index]);
-	}
-	return(1);
-}
-
diff --git a/target/linux/at91-2.6/image/dfboot/src/stdio.h b/target/linux/at91-2.6/image/dfboot/src/stdio.h
deleted file mode 100644
index e4e35ec..0000000
--- a/target/linux/at91-2.6/image/dfboot/src/stdio.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#include <stdarg.h>
-#include <stdbool.h>
-
-#ifndef NULL
-#define NULL ((void *)0)
-#endif
-
-void at91_init_uarts(void);
-int puts(const char *str);
-int putc(int c);
-int putchar(int c);
-int getc();
-
-int strlen(const char *str);
-
-int hvfprintf(const char *fmt, va_list ap);
-
-int printf(const char *fmt, ...);