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| author | Hamish Guthrie <hcg@openwrt.org> | 2008-07-08 06:13:54 +0000 |
|---|---|---|
| committer | Hamish Guthrie <hcg@openwrt.org> | 2008-07-08 06:13:54 +0000 |
| commit | 40e85a7d5dd9ae5facba0fc0a0208500a4619dfa (patch) | |
| tree | b65d0132af51e2aae959748a9a72ed5ff5328f6f /target/linux/at91/patches-2.6.22/009-fdl-uartinit.patch | |
| parent | 22754b63e7ac756b14d753fc61c6795004f79690 (diff) | |
| download | mtk-20170518-40e85a7d5dd9ae5facba0fc0a0208500a4619dfa.zip mtk-20170518-40e85a7d5dd9ae5facba0fc0a0208500a4619dfa.tar.gz mtk-20170518-40e85a7d5dd9ae5facba0fc0a0208500a4619dfa.tar.bz2 | |
Removed patches and config for non-functional 2.6.22 kernel
SVN-Revision: 11746
Diffstat (limited to 'target/linux/at91/patches-2.6.22/009-fdl-uartinit.patch')
| -rw-r--r-- | target/linux/at91/patches-2.6.22/009-fdl-uartinit.patch | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/target/linux/at91/patches-2.6.22/009-fdl-uartinit.patch b/target/linux/at91/patches-2.6.22/009-fdl-uartinit.patch deleted file mode 100644 index b9ceb72..0000000 --- a/target/linux/at91/patches-2.6.22/009-fdl-uartinit.patch +++ /dev/null @@ -1,28 +0,0 @@ -Index: linux-2.6.22.19/arch/arm/mach-at91/at91rm9200_devices.c -=================================================================== ---- linux-2.6.22.19.orig/arch/arm/mach-at91/at91rm9200_devices.c -+++ linux-2.6.22.19/arch/arm/mach-at91/at91rm9200_devices.c -@@ -721,6 +721,10 @@ static inline void configure_usart0_pins - * We need to drive the pin manually. Default is off (RTS is active low). - */ - at91_set_gpio_output(AT91_PIN_PA21, 1); -+ at91_set_gpio_output(AT91_PIN_PB6, 1); /* DTR0 */ -+ at91_set_gpio_output(AT91_PIN_PB7, 1); /* RI0 */ -+ at91_set_gpio_input(AT91_PIN_PA19, 1); /* DCD0 */ -+ at91_set_deglitch(AT91_PIN_PA19, 1); - } - - static struct resource uart1_resources[] = { -@@ -832,6 +836,12 @@ static inline void configure_usart3_pins - { - at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */ - at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */ -+ at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */ -+ at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */ -+ at91_set_gpio_output(AT91_PIN_PB29, 1); /* DTR0 */ -+ at91_set_gpio_output(AT91_PIN_PB2, 1); /* RI0 */ -+ at91_set_gpio_input(AT91_PIN_PA24, 1); /* DCD0 */ -+ at91_set_deglitch(AT91_PIN_PA24, 1); - } - - struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ |