diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2007-02-16 09:23:15 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2007-02-16 09:23:15 +0000 |
| commit | 3d60d69334f43e0da151208dffee850b26d34c3c (patch) | |
| tree | c3e70ccc5a93810bfa7b3e5cb7363823a4b0209d /target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h | |
| parent | 312aeaf1bee32e524f4ab12796e3fba46f36e8aa (diff) | |
| download | mtk-20170518-3d60d69334f43e0da151208dffee850b26d34c3c.zip mtk-20170518-3d60d69334f43e0da151208dffee850b26d34c3c.tar.gz mtk-20170518-3d60d69334f43e0da151208dffee850b26d34c3c.tar.bz2 | |
major cleanup of the ar531x code, improved hardware detection and support for multiple ethernet interfaces
SVN-Revision: 6307
Diffstat (limited to 'target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h')
| -rw-r--r-- | target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h index ef2df87..c3eeed1 100644 --- a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h +++ b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h @@ -121,11 +121,11 @@ */ #define AR5315_SREV (AR5315_DSLBASE + 0x0014) -#define REV_MAJ 0x00f0 -#define REV_MAJ_S 4 -#define REV_MIN 0x000f -#define REV_MIN_S 0 -#define REV_CHIP (REV_MAJ|REV_MIN) +#define AR5315_REV_MAJ 0x00f0 +#define AR5315_REV_MAJ_S 4 +#define AR5315_REV_MIN 0x000f +#define AR5315_REV_MIN_S 0 +#define AR5315_REV_CHIP (AR5315_REV_MAJ|AR5315_REV_MIN) /* * Interface Enable @@ -359,21 +359,21 @@ #define AR5315_PCICLK (AR5315_DSLBASE + 0x00a4) -#define PCICLK_INPUT_M 0x3 -#define PCICLK_INPUT_S 0 +#define AR5315_PCICLK_INPUT_M 0x3 +#define AR5315_PCICLK_INPUT_S 0 -#define PCICLK_PLLC_CLKM 0 -#define PCICLK_PLLC_CLKM1 1 -#define PCICLK_PLLC_CLKC 2 -#define PCICLK_REF_CLK 3 +#define AR5315_PCICLK_PLLC_CLKM 0 +#define AR5315_PCICLK_PLLC_CLKM1 1 +#define AR5315_PCICLK_PLLC_CLKC 2 +#define AR5315_PCICLK_REF_CLK 3 -#define PCICLK_DIV_M 0xc -#define PCICLK_DIV_S 2 +#define AR5315_PCICLK_DIV_M 0xc +#define AR5315_PCICLK_DIV_S 2 -#define PCICLK_IN_FREQ 0 -#define PCICLK_IN_FREQ_DIV_6 1 -#define PCICLK_IN_FREQ_DIV_8 2 -#define PCICLK_IN_FREQ_DIV_10 3 +#define AR5315_PCICLK_IN_FREQ 0 +#define AR5315_PCICLK_IN_FREQ_DIV_6 1 +#define AR5315_PCICLK_IN_FREQ_DIV_8 2 +#define AR5315_PCICLK_IN_FREQ_DIV_10 3 /* * Observation Control Register |