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author | Florian Fainelli <florian@openwrt.org> | 2010-07-01 19:07:27 +0000 |
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committer | Florian Fainelli <florian@openwrt.org> | 2010-07-01 19:07:27 +0000 |
commit | 48b8c5e945f123e2284d0cf6de450cbd03d249a8 (patch) | |
tree | 8966d42d0d8ac1ca554b932a1b4fee34e97d5c55 /target/linux/au1000/patches-2.6.32/005-mtx1_fix_pci.patch | |
parent | 25602743d16580389f3140b6227620edc583a456 (diff) | |
download | mtk-20170518-48b8c5e945f123e2284d0cf6de450cbd03d249a8.zip mtk-20170518-48b8c5e945f123e2284d0cf6de450cbd03d249a8.tar.gz mtk-20170518-48b8c5e945f123e2284d0cf6de450cbd03d249a8.tar.bz2 |
fix PCI, thanks br1, put back 2.6.32.14 support by default
SVN-Revision: 22033
Diffstat (limited to 'target/linux/au1000/patches-2.6.32/005-mtx1_fix_pci.patch')
-rw-r--r-- | target/linux/au1000/patches-2.6.32/005-mtx1_fix_pci.patch | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/target/linux/au1000/patches-2.6.32/005-mtx1_fix_pci.patch b/target/linux/au1000/patches-2.6.32/005-mtx1_fix_pci.patch new file mode 100644 index 0000000..c2d7473 --- /dev/null +++ b/target/linux/au1000/patches-2.6.32/005-mtx1_fix_pci.patch @@ -0,0 +1,38 @@ + + +diff --git a/arch/mips/alchemy/mtx-1/board_setup.c +b/arch/mips/alchemy/mtx-1/board_setup.c +index 45b61c9..17140ac 100644 +--- a/arch/mips/alchemy/mtx-1/board_setup.c ++++ b/arch/mips/alchemy/mtx-1/board_setup.c +@@ -56,8 +56,6 @@ void __init board_setup(void) + } + #endif + +- alchemy_gpio2_enable(); +- + #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) + /* Enable USB power switch */ + alchemy_gpio_direction_output(204, 0); +@@ -92,20 +90,12 @@ void __init board_setup(void) + int + mtx1_pci_idsel(unsigned int devsel, int assert) + { +-#define MTX_IDSEL_ONLY_0_AND_3 0 +-#if MTX_IDSEL_ONLY_0_AND_3 +- if (devsel != 0 && devsel != 3) { +- printk(KERN_ERR "*** not 0 or 3\n"); +- return 0; +- } +-#endif +- + if (assert && devsel != 0) + /* Suppress signal to Cardbus */ + gpio_set_value(1, 0); /* set EXT_IO3 OFF */ + else + gpio_set_value(1, 1); /* set EXT_IO3 ON */ + +- au_sync_udelay(1); ++ udelay(1); + return 1; + } |