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authorFlorian Fainelli <florian@openwrt.org>2007-12-09 15:51:45 +0000
committerFlorian Fainelli <florian@openwrt.org>2007-12-09 15:51:45 +0000
commitdc36fccfdcb916f7c2dd1cfe69bdc492dca86cba (patch)
treedaac8debec7a921178799b5719ceef457925fca4 /target/linux/brcm-2.4/patches
parentab883d42a1f0a5a79587161a4e6af7cdb34370da (diff)
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Add bcm5354 patch from #2754
SVN-Revision: 9684
Diffstat (limited to 'target/linux/brcm-2.4/patches')
-rw-r--r--target/linux/brcm-2.4/patches/014-bcm5354.patch155
1 files changed, 155 insertions, 0 deletions
diff --git a/target/linux/brcm-2.4/patches/014-bcm5354.patch b/target/linux/brcm-2.4/patches/014-bcm5354.patch
new file mode 100644
index 0000000..fed89ca
--- /dev/null
+++ b/target/linux/brcm-2.4/patches/014-bcm5354.patch
@@ -0,0 +1,155 @@
+--- a/arch/mips/bcm947xx/include/sbchipc.h 2007-11-23 12:12:01.000000000 -0500
++++ b/arch/mips/bcm947xx/include/sbchipc.h 2007-11-25 06:16:42.000000000 -0500
+@@ -188,6 +188,7 @@
+ #define CAP_JTAGP 0x00400000 /* JTAG Master Present */
+ #define CAP_ROM 0x00800000 /* Internal boot rom active */
+ #define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
++#define CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
+
+ /* PLL type */
+ #define PLL_NONE 0x00000000
+@@ -199,6 +200,9 @@
+ #define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
+ #define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
+
++/* watchdog clock */
++#define WATCHDOG_CLOCK_5354 32000 /* Hz */
++
+ /* corecontrol */
+ #define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
+ #define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
+--- a/arch/mips/bcm947xx/include/bcmdevs.h 2007-11-23 12:12:01.000000000 -0500
++++ b/arch/mips/bcm947xx/include/bcmdevs.h 2007-11-25 05:58:20.000000000 -0500
+@@ -121,6 +121,7 @@
+ #define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
+ #define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
+ #define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
++#define BCM5354_CHIP_ID 0x5354 /* bcm5354 chipcommon chipid */
+
+ #define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
+
+--- a/arch/mips/bcm947xx/sbmips.c 2007-11-23 12:12:02.000000000 -0500
++++ b/arch/mips/bcm947xx/sbmips.c 2007-11-25 05:40:40.000000000 -0500
+@@ -290,6 +290,12 @@
+ n = R_REG(osh, &eir->clockcontrol_n);
+ m = R_REG(osh, &eir->clockcontrol_sb);
+ } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
++ /* 5354 chip uses a non programmable PLL of frequency 240MHz */
++ if (sb_chip(sbh) == BCM5354_CHIP_ID) {
++ rate = 240000000;
++ goto out;
++ }
++
+ pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
+ n = R_REG(osh, &cc->clockcontrol_n);
+ if ((pll_type == PLL_TYPE2) ||
+@@ -612,6 +618,15 @@
+ clockcontrol_pci = &eir->clockcontrol_pci;
+ clockcontrol_m2 = &cc->clockcontrol_m2;
+ } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
++
++ /* 5354 chipcommon pll setting can't be changed.
++ * The PMU on power up comes up with the default clk frequency
++ * of 240MHz
++ */
++ if (sb_chip(sbh) == BCM5354_CHIP_ID) {
++ ret = TRUE;
++ goto done;
++ }
+ pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
+ if (pll_type == PLL_TYPE6) {
+ clockcontrol_n = NULL;
+--- a/arch/mips/bcm947xx/sbutils.c 2007-11-23 12:12:02.000000000 -0500
++++ b/arch/mips/bcm947xx/sbutils.c 2007-11-25 06:22:43.000000000 -0500
+@@ -791,8 +791,14 @@
+ /* readback */
+ if (regoff >= SBCONFIGOFF)
+ w = R_SBREG(si, r);
+- else
++ else {
++ if ((si->sb.chip == BCM5354_CHIP_ID) &&
++ (coreidx == SB_CC_IDX) &&
++ (regoff == OFFSETOF(chipcregs_t, watchdog))) {
++ w = val;
++ } else
+ w = R_REG(si->osh, r);
++ }
+
+ if (!fast) {
+ /* restore core index */
+@@ -1902,6 +1908,15 @@
+ n = R_REG(si->osh, &eir->clockcontrol_n);
+ m = R_REG(si->osh, &eir->clockcontrol_sb);
+ } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
++
++ if (R_REG(si->osh, &cc->capabilities) & CAP_PMU) {
++ if (sb_chip(sbh) == BCM5354_CHIP_ID) {
++ /* 5354 has a constant sb clock of 120MHz */
++ rate = 120000000;
++ goto end;
++ } else
++ ASSERT(0);
++ }
+ pll_type = R_REG(si->osh, &cc->capabilities) & CAP_PLL_MASK;
+ if (pll_type == PLL_NONE) {
+ INTR_RESTORE(si, intr_val);
+@@ -1929,6 +1944,7 @@
+ rate = rate / 2;
+ }
+
++end:
+ /* switch back to previous core */
+ sb_setcoreidx(sbh, idx);
+
+--- a/arch/mips/bcm947xx/hndchipc.c 2007-11-23 12:12:02.000000000 -0500
++++ b/arch/mips/bcm947xx/hndchipc.c 2007-11-25 06:31:15.000000000 -0500
+@@ -93,6 +93,9 @@
+ chipcregs_t *cc = (chipcregs_t *) regs;
+ uint32 rev, cap, pll, baud_base, div;
+
++ /* Default value */
++ div = 48;
++
+ /* Determine core revision and capabilities */
+ rev = sb_corerev(sbh);
+ cap = R_REG(osh, &cc->capabilities);
+@@ -108,22 +111,29 @@
+ R_REG(osh, &cc->clockcontrol_m2));
+ div = 1;
+ } else {
+- /* Fixed ALP clock */
+- if (rev >= 11 && rev != 15) {
+- baud_base = 20000000;
++/* 5354 chip common uart uses a constant clock
++ * frequency of 25MHz */
++ if (sb_corerev(sbh) == 20) {
++ /* Set the override bit so we don't divide it */
++ W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
++ baud_base = 25000000;
++ } else if (rev >= 11 && rev != 15) {
++ /* Fixed ALP clock */
++// baud_base = sb_alp_clock(sbh);
++ baud_base = 20000000;
+ div = 1;
+ /* Set the override bit so we don't divide it */
+ W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
+- }
++
+ /* Internal backplane clock */
+- else if (rev >= 3) {
+- baud_base = sb_clock(sbh);
+- div = 2; /* Minimum divisor */
+- W_REG(osh, &cc->clkdiv,
++ } else if (rev >= 3) {
++ baud_base = sb_clock(sbh);
++ div = 2; /* Minimum divisor */
++ W_REG(osh, &cc->clkdiv,
+ ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
+- }
++
+ /* Fixed internal backplane clock */
+- else {
++ } else {
+ baud_base = 88000000;
+ div = 48;
+ }