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| author | Jonas Gorski <jogo@openwrt.org> | 2014-06-21 19:23:28 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2014-06-21 19:23:28 +0000 |
| commit | 21d65bb185225a3a5369756fc44acbbbfbc2f651 (patch) | |
| tree | 4c18455910033e540eeb1d15eb98131bcc7ccf7c /target/linux/brcm63xx/patches-3.14/332-MIPS-BCM63XX-detect-BCM6328-variants.patch | |
| parent | f695fa358aafe1a96825977dd7d598354b1828f6 (diff) | |
| download | mtk-20170518-21d65bb185225a3a5369756fc44acbbbfbc2f651.zip mtk-20170518-21d65bb185225a3a5369756fc44acbbbfbc2f651.tar.gz mtk-20170518-21d65bb185225a3a5369756fc44acbbbfbc2f651.tar.bz2 | |
brcm63xx: update variant detection patches and fix VARID shift
The variant id field shift was wrong, causing the variant detection
to fail.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 41295
Diffstat (limited to 'target/linux/brcm63xx/patches-3.14/332-MIPS-BCM63XX-detect-BCM6328-variants.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.14/332-MIPS-BCM63XX-detect-BCM6328-variants.patch | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.14/332-MIPS-BCM63XX-detect-BCM6328-variants.patch b/target/linux/brcm63xx/patches-3.14/332-MIPS-BCM63XX-detect-BCM6328-variants.patch new file mode 100644 index 0000000..dc7fbfc --- /dev/null +++ b/target/linux/brcm63xx/patches-3.14/332-MIPS-BCM63XX-detect-BCM6328-variants.patch @@ -0,0 +1,68 @@ +From d59120f23279ef62a48d9f94847254b061d0a8b6 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 7 Dec 2013 14:30:59 +0100 +Subject: [PATCH 22/45] MIPS: BCM63XX: detect BCM6328 variants + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/cpu.c | 10 ++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++++-- + 2 files changed, 16 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -306,6 +306,7 @@ void __init bcm63xx_cpu_init(void) + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int cpu = smp_processor_id(); + u32 chipid_reg; ++ u8 __maybe_unused varid = 0; + + /* soc registers location depends on cpu type */ + chipid_reg = 0; +@@ -345,6 +346,7 @@ void __init bcm63xx_cpu_init(void) + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; + bcm63xx_cpu_variant = bcm63xx_cpu_id; + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; ++ varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; + + switch (bcm63xx_cpu_id) { + case BCM3368_CPU_ID: +@@ -354,6 +356,14 @@ void __init bcm63xx_cpu_init(void) + case BCM6328_CPU_ID: + bcm63xx_regs_base = bcm6328_regs_base; + bcm63xx_irqs = bcm6328_irqs; ++ ++ if (varid == 1) ++ bcm63xx_cpu_variant = BCM63281_CPU_ID; ++ else if (varid == 3) ++ bcm63xx_cpu_variant = BCM63283_CPU_ID; ++ else ++ pr_warn("unknown BCM6328 variant: %x\n", varid); ++ + break; + case BCM6338_CPU_ID: + bcm63xx_regs_base = bcm6338_regs_base; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -11,6 +11,8 @@ + */ + #define BCM3368_CPU_ID 0x3368 + #define BCM6328_CPU_ID 0x6328 ++#define BCM63281_CPU_ID 0x63281 ++#define BCM63283_CPU_ID 0x63283 + #define BCM6338_CPU_ID 0x6338 + #define BCM6345_CPU_ID 0x6345 + #define BCM6348_CPU_ID 0x6348 +@@ -85,8 +87,10 @@ static inline u16 __pure bcm63xx_get_cpu + + #define BCMCPU_VARIANT_IS_3368() \ + (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) +-#define BCMCPU_VARIANT_IS_6328() \ +- (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID) ++#define BCMCPU_VARIANT_IS_63281() \ ++ (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID) ++#define BCMCPU_VARIANT_IS_63283() \ ++ (bcm63xx_get_cpu_variant() == BCM63283_CPU_ID) + #define BCMCPU_VARIANT_IS_6338() \ + (bcm63xx_get_cpu_variant() == BCM6338_CPU_ID) + #define BCMCPU_VARIANT_IS_6345() \ |