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authorGabor Juhos <juhosg@openwrt.org>2012-03-18 22:06:55 +0000
committerGabor Juhos <juhosg@openwrt.org>2012-03-18 22:06:55 +0000
commitfaf82f3e106a548c99e8eafb0e7957ba242bd03b (patch)
treedc59bacacee10754dad0757e4beca10e4f052edf /target/linux/generic/files/include
parentfa7a83df4b208f1f09d00af171fc8e49f2c3226e (diff)
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generic: ar8216: add support for the AR8327 chip
SVN-Revision: 31011
Diffstat (limited to 'target/linux/generic/files/include')
-rw-r--r--target/linux/generic/files/include/linux/ar8216_platform.h72
1 files changed, 72 insertions, 0 deletions
diff --git a/target/linux/generic/files/include/linux/ar8216_platform.h b/target/linux/generic/files/include/linux/ar8216_platform.h
new file mode 100644
index 0000000..1ecb6e5
--- /dev/null
+++ b/target/linux/generic/files/include/linux/ar8216_platform.h
@@ -0,0 +1,72 @@
+/*
+ * AR8216 switch driver platform data
+ *
+ * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef AR8216_PLATFORM_H
+#define AR8216_PLATFORM_H
+
+enum ar8327_pad_mode {
+ AR8327_PAD_NC = 0,
+ AR8327_PAD_MAC2MAC_MII,
+ AR8327_PAD_MAC2MAC_GMII,
+ AR8327_PAD_MAC_SGMII,
+ AR8327_PAD_MAC2PHY_MII,
+ AR8327_PAD_MAC2PHY_GMII,
+ AR8327_PAD_MAC_RGMII,
+ AR8327_PAD_PHY_GMII,
+ AR8327_PAD_PHY_RGMII,
+ AR8327_PAD_PHY_MII,
+};
+
+enum ar8327_clk_delay_sel {
+ AR8327_CLK_DELAY_SEL0 = 0,
+ AR8327_CLK_DELAY_SEL1,
+ AR8327_CLK_DELAY_SEL2,
+ AR8327_CLK_DELAY_SEL3,
+};
+
+struct ar8327_pad_cfg {
+ enum ar8327_pad_mode mode;
+ bool rxclk_sel;
+ bool txclk_sel;
+ bool pipe_rxclk_sel;
+ bool txclk_delay_en;
+ bool rxclk_delay_en;
+ enum ar8327_clk_delay_sel txclk_delay_sel;
+ enum ar8327_clk_delay_sel rxclk_delay_sel;
+};
+
+enum ar8327_port_speed {
+ AR8327_PORT_SPEED_10 = 0,
+ AR8327_PORT_SPEED_100,
+ AR8327_PORT_SPEED_1000,
+};
+
+struct ar8327_port_cfg {
+ int force_link:1;
+ enum ar8327_port_speed speed;
+ int txpause:1;
+ int rxpause:1;
+ int duplex:1;
+};
+
+struct ar8327_platform_data {
+ struct ar8327_pad_cfg *pad0_cfg;
+ struct ar8327_pad_cfg *pad5_cfg;
+ struct ar8327_pad_cfg *pad6_cfg;
+ struct ar8327_port_cfg cpuport_cfg;
+};
+
+#endif /* AR8216_PLATFORM_H */ \ No newline at end of file